Digital indicator to simplify setting of tuning systemastrojjki

PATENT DESCRIPTION

118 258

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URZAO

PATENT

PRL

Additional patent to patent no

Reported: 29.08.78 (P. 209268)

Priority: 29.08.77 United States

America

The application was announced: 16.07.79

Patent description published: 30.07.1983

CI Int.³H03J 5/0 · H04N 5/44 H03J 1/02

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Inventor: Billy Wesley Beyers, Jr

Patent holder: RCA Corporation,

New York (US)

Digital indicator for easy tuning wrap adjustment

The subject of the invention is a digital indicator that facilitates tuning of a television receiver comprising memory for storing binary signals representing tuning information.

Recently, electronic systems have been developed for television receivers containing memory for storing binary signals representing tuning voltages for controlling a local generator in order to select the various channels available to the user e.g. from U.S. Patent No. 4,123,713, a memory tuning control system is known. Although this type of tuning system with memory is more universal and less expensive than other types of electronic tuning systems, such as, for example, systems using frequency synthesizers, their disadvantage is that it is necessary to program the system by the manufacturer, and in some cases also by the user to enter the necessary tuning information into the system's memory.

In some known types of memory tuning systems, the amount of memory, i.e. the number of elements in which information can be stored, is limited due to the cost of the tuning system. As a result, tuning information can only store tuning information for a limited number of preferred channels, less than the total number of channels on the television band. For the United States, channels 2-83 on the television band are approved by the Federal Communications Commission (FCC). Since the preferred channels for a given use, both due to their content and reception conditions in the user's residence are known only to this user, in the case of memory control systems containing memory with a limited number of memory elements, programming must be carried out by the user himself. Programming the memory tuning system consists not only in selecting the appropriate channels, but also involves generating binary signals representing the tuning voltage and channel number imaging information for individual channels. For a user who is accustomed to the traditional mechanical tuning system with a mechanical rotary channel switch, the programming procedure of the memory tuning system can be very difficult and unnecessarily call for service assistance. Therefore, it is desirable that the tuning memory arrangement simplify the programming procedure as much as possible.

One of the difficulties of programming a tuning system with memory is the need to correlate the image on the screen with the channel number. This means that when setting the tuning voltage to obtain a readable image, if it is not accidentally just when the image is received, the station identification signal is transmitted or if the user does not know which channel the program currently being received on the screen is broadcast on,

118 258 it is not possible to check on which channel the receiver is currently tuned and cannot program the appropriate channel number indication information.

In order to remove this inconvenience, an electromechanical voltage meter reacting analogously to the tuning voltage can be used, which gives the user information about the relative position of the tuning (see, e.g., the tuning system described in the Magnavox Service Manual - 703777 Video Touch Tuning Units, Manual No. 7353, Volume 12, published by Magnavox Company, Fort Wayne, Indiana). Electromagnetic meters are not only relatively expensive and because of their size they do not harmonize with the receiver, but their indications are difficult to read by a user not familiar with electronic equipment. In addition, the resolution of electromagnetic meters between tuning positions where the preferred channels are tightly spaced may not be sufficient. For example, the user may not distinguish between the positions for channels 4, 5 or 6.

It is also possible to build an indicator that would display the scale marked with channel numbers (rather than tuning voltages) on the screen and would have a bar-shaped indicator changing its length along the scale during tuning voltage changes (see, for example, the indicator described in the General Instrument brochure " General Instrument AY-3-8330 Electronic Tuning Scale on the TV Screen). Although such an indicator on the TV screen is free from some of the disadvantages of the electromechanical meter, its use can be quite difficult, however, because, like the electromechanical meter, it provides information in an analog form. In addition, the pointing arrangement on the television screen increases the cost of the tuning arrangement and therefore cannot be used.

Thus, it is preferred that the tuning memory system includes an assembly that enables the tuning voltage to be indicated in readable form for average use, and which preferably would contain means to reduce the possibility of user confusion.

According to the invention, the digital indicator facilitating tuning of the television set is equipped with a memory for storing binary signals for various channels that can be selected by the user and a device controlling the input of binary signals into the memory during the programming phase of the tuning system and downloading binary signals from the memory during the normal operation phase tuning system, containing a work phase selector connected to a time and control unit, used for the selective generation of a normal signal introducing the system into the normal operation phase and a tuning signal introducing the system into the programming phase. The channel number register connected to the time and control unit, generating binary signals on the user's command, representing the channel numbers connected to the time and control unit, includes tuning voltage elements that generate binary signals on the user's command, corresponding to the tuning voltages in different channels, indicator elements for displaying specific symbols in response to appropriate code combinations of binary signals. The indicator is characterized in that it comprises a multiplexer for selectively introducing binary signals corresponding to channel numbers into indicator elements, such that the channel numbers are depicted in response to a normal signal, and for selectively introducing specific signals selected from binary signals representing tuning voltages to indicator elements so that the number of displays in response to the tuning signal depended on the tuning voltage values. Preferably, the numbers depicted in response to the tuning signal are linearly dependent on the value of the tuning voltages.

The channel number register includes a channel number counter for generating at least four binary signals representing at least one binary coded decimal number, the tuning elements include a tuning voltage meter generating binary signals in a simple binary format format, and elements containing at least one digital field for displaying decimal numbers 0 to 9, the multiplexer introduces four binary signals in binary coded decimal format to the indicator means so that in response to a normal signal the one-digit indicator field depicts decimal numbers 0 to 9, and the multiplexer introduces the three most significant binary signals of the octal notation to the indicator elements so that the tuning signal, said one-digit indicator field will display numbers between 0 and 7. The multiplexer contains elements for the selective feeding of binary signals representing the first non-digital symbol denoting the programming phase for the indicator device, where this symbol is imaged in response to the tuning signal.

The channel number register includes a channel number counter for generating binary signals representing two-digit decimal numbers corresponding to channel numbers, and the indicator elements have first and second indicator fields. The multiplexer supplies binary signals representing two-digit numbers corresponding to channel numbers to the indicator device, so that the digits of tens of digital numbers corresponding to the channel numbers are depicted in the first field and the digits of the two-digit number units are depicted in the second field of the indicator in response to the normal signal and supplies the signals binary, representing the first symbol and specific binary signals selected in the signals

118 258 representing tuning voltage to indicator elements so that the first symbol is depicted in one of the indicator fields, and the numbers associated with tuning voltages are depicted in the remaining field. The first symbol is the letter A. The multiplexer contains elements for entering a specific break in the display of the letter A.

The channel number register includes control elements for generating the "up" control signal to increase the tuning voltage meter and the "down" control signal to decrease the tuning voltage meter. The multiplexer includes elements for feeding * binary signals representing the letter J to the indicator elements, whereby the multiplexer supplies binary signals representing the letters A and J to the indicator elements so that the letter A is continuously depicted in the first field, and the letter J is continuously depicted in the second field in response to the lack of up and down signals and the presence of the tuning signal. The multiplexer contains elements for feeding binary signals representing the letter C and binary signals representing the letter H of the indicator elements so that the letter C is depicted in the first field and the letter H is depicted in the second field in the first part of the duration of the clock signal and elements for feeding the binary signals representing the two-digit numbers corresponding to the channel numbers are depicted in the first field, and the digits of the two-digit decimal number units are depicted in the second field in the second part of the clock signal duration in response to the channel signal.

The subject of the invention is illustrated in the embodiment in the drawing, in which Fig. I shows a block diagram of a television set with the tuning memory system according to the invention facilitating its setting by the user, Fig. 2 - a table of certain binary code combinations facilitating explanation of the operation of the tuning system according to Fig. I and Figures 3 and 4 show, in logic form, the respective parts of the tuning system shown in Figure 1.

As shown in the diagram of Fig. 1, the high frequency RF signal is received by an antenna 12 connected to a shaping unit, where the high frequency RF signal is filtered, amplified and otherwise shaped. The shaped high frequency RF signal is fed to the mixer 14 where it is mixed with the signal generated by the local generator 18 to produce an intermediate frequency 1F signal.

The frequency of the local generator is set by the voltage generated in the tuning system 28 according to the channel selected by the user, so that the signal of this frequency will be mixed with the high frequency signal, the intermediate frequency signal IF has video and audio carrier frequencies with predetermined frequencies. The intermediate frequency IF signal is fed to assembly 22, where it is filtered, amplified and shaped in another way. Part of the intermediate frequency signal is fed to an automatic fine-tuning discriminator that produces an automatic fine-tuning signal AFT representing the deviation of the image carrier frequency from the rated value (in the US 45 75 MHz), resulting from the aging of components or changes in operating conditions. AFT voltage is applied to the local geperator 18 to change the tuning voltage in a way that reduces the deviation of the video carrier frequency from the nominal value. The output of the shaping assembly 22 is fed to the signal processing assembly 24, it processes the individual components of the intermediate frequency signal so that the image is created on the screen of the picture tube 28 and the sound is reproduced by means of the speaker 38.

Tuning system 28 is a memory system adapted to store enough information to tune to several selected channels, but not all channels that are within the television band. Tuning system 28 can be programmed to tune only 14 channels, those which are preferred by the recipients because of the broadcast program or the reception properties at the user's confusion.

Tuning system 28 includes a tuning voltage memory for storing binary signals representing tuning voltages of each of the 16 channels preferred by the recipient. Each memory element has 12 memory cells for storing 12 binary signals or bits (binary digits) that have either a logical value "Γ corresponding to a relatively high voltage + V or a logical value" 0 corresponding to a ground signal. The binary signals stored in each memory element have a simple binary format. This means that each of the 12 binary signals represents the power of 2 from Odo 11 and are ordered in ascending order from right to left.

Each tuning voltage memory element 112 has its address. Information about the tuning voltage of selected channels is stored in successively addressed memory elements in the order of increasing channel numbers. The four-stage address register 114 coupled to the tuning voltage memory 112 generates four binary signals representing in binary form decimal numbers 0-15 for addressing any of the 14 tuning voltage memory elements 112. Address register 114 is a counting counter

118 2Μ up and down with the option of introducing binary signals into the 'block' inputs, e.g. with a CD 4029 RCA Corporation. The contents of the address register 114 (represented by four binary signals) can be increased by a decimal digit 1 or decreased by a decimal digit I by the appropriate control signal, which will be explained below.

When the tuning voltage memory element 12 is addressed, the content of the addressed element is "read *" and fed into the D / A converter 116, which converts it to the appropriate tuning voltage for the local generator 18.

The tuning voltage register 118 containing 12 degrees resolved as a counter up and down in a simple binary format coupled with the tuning voltage memory 112 generates during tuning setup 28 twelve binary signals storage in each memory element 112 tuning voltages representing the tuning voltages of each selected channels. When tuning system 28 is set, the contents of tuning voltage register 118 increase or decrease by further 1 in response to signals generated under user control and are converted by converter 116 to corresponding tuning voltages, which continues until the picture on the picture tube is no picture expected by the user. The selected binary signals generated by the tuning voltage register 118 are sent to the channel number monitor 128, where the digits corresponding to the tuning voltage are imaged, so that the user can check that the picture on the picture tube corresponds to the channel he wanted to select. At the user's command, the contents of tuning voltage register 118 are "entered into the currently addressed tuning voltage voltage element 112.

The channel number corresponding to the number selected by the user is displayed on the indicator 128 in response to binary signals generated by the channel number register 122. The channel number register 122 includes two 4-step up and down counters, with the option of introducing binary signals onto the blocking inputs, for example CD 4029 RCA Corporation integrated circuits. Each counter generates four binary signals in BCD decimal binary coding format (see the encoded notation of numbers 0-9 in the table on Figure 2 in the column designated binary representing decimal numbers 0-9). Binary signals generated by the first counter represent the least significant digit LSD of the decimal number, and bineme signals generated by the second counter represent the most significant MSD digit of the channel number. Both counters are cascaded and count between numbers 02 and 83 in ascending or descending order in response to a user signal.

To reduce the number of electronic components in the 12 · digital indicator, binary signals representing the LSD and MSD of the channel number are multiplexed and processed sequentially in the 12 · indicator of the channel number. Binary signals representing LSD are fed to monitor decoder 124 through the indicator multiplexer 124 during the unit clock signal and binary signals representing MSD are fed to the indicator decoder 124 via the multiplexer 124 during the tenth clock signal. The monitor decoder 124 converts four binary signals input into its input terminals into seven binary signals, each of which corresponds to a segment of the seven-digit indicator. The seven binary output signals of the decoder 124 enter the multiplexer 124, which in turn places them on the positions of the units of the seven-segment indicator 134A during the clock signal of the one unit and on the positions of the tens during the clock signal of the tens. The seven-segment indicator 130A and 134B, which can be an indicator based on emission diodes or liquid crystals, contains seven ag segments, which can be selectively displayed in appropriate logical values ​​("0" or "1") of input binary signals giving decimal digits 0 to 9. To create the number 9, for example, display the segments a, b, c, and f. The frequency and duration of the indicator clock signal are set so that the user does not observe flickering on the channel number indicator.

LSD and MSD binary signals generated by channel number register 122 are brought to memory 132. Memory 132 is a memory containing 82 memory elements each having a cell for storing one bit. The addresses of the 82 memory elements 132 correspond to the numbers of the 82 channels between 02 and 83. Thus, for example, when the channel number register 122 contains binary signals representing the channel number 13, the corresponding hopping memory element 132 is addressed. The task of memory 132 is to send, for example, the logical value "1" when the channel is to be omitted because it is not the user's preferred channel. In response to the presence of the .1 "signal in memory 132, the detector 134 generates a" hop "signal.

The LSD and MSD binary signals generated by the channel number register 122 are also fed to the band selector 134, which may e.g. include a read-only memory (ROM) circuit that determines the frequency band in which the selected channel lies based on the channel number and produces the signal band selection. Thus, in the United States, the band selector 134 produces lithium 251, the corresponding band select signals for channels 2-6, 7-13, and 14-83. The band select signals are fed to the generator 18, where they control with the frequency range of its oscillation. The local generator 18 includes a set of factor diodes which are incorporated into the generator circuit in response to the band select signal and determine the frequency range in which the generator 18 oscillates. The exact value of generator 18 vibrations is determined by the amount of tuning voltage.

Clock signals controlling the operating sequence of tuning system 28 are produced by the stationary time-limiting unit 138 by dividing the clock signal produced by the timing oscillator for various time periods. The signals controlling the transfer of information to and from the tuning voltage memory 112 and the hop memory 132 and controlling the operations of counting the address register 114, tuning voltage register 118 and channel number register 122 as described below are generated in response to timing signals and command signals generated by the detector 142 , keyboard 144, mode selector 144 and skip detector 134. Overvoltage detector 142 detects the moment when the supply voltage of tuning system 28 rises above a certain level, when, after switching off, the supply voltage is again applied to the receiver and in response produces a PUP overvoltage signal. The keyboard 144 includes buttons marked up G, down D. Memory and Delete, which when pressed by the user generate and lead to the control-timing unit 138 appropriate command signals. These command signals increase or decrease the contents of address register 114, tuning voltage register 118 and channel number register 122 and decide whether the information contained in tuning voltage memory 112 and hop memory 132 is to be stored or deleted. The mode selector 146 has Normabe, Channel and Tuning positions to generate the appropriate signals that are used to control the type of tuning system 28. The operation of the timing and control assembly 138 in controlling the tuning system 28 will be described below. The timing and control assembly 138 includes a logic performing the operations described below. Alternatively, the timer-control assembly 138 may be in the form of a microprocessor controlled according to a program implementing the operations described below stored in its associated memory. Connections between timer and control unit 138 and various parts of tuning system 28 have been omitted for the sake of clarity. Operation of these control connections will be explained in the following description of control system 28.

During the operation of the device, assuming that the mode selector 146 is set to Normabe position, after turning on the receiver, the binary signals representing the lowest channel number, i.e. number 02 (depicted on the indicator 128) are entered into the register 122 of the number from the set 123, and the binary signals representing the number 15 are entered into register 114 from the set 115, with the entries being made in response to the PUP surge signal. At this point, the hopping detector 134 checks the contents of the hopping memory element 132 corresponding to channel number 02. If the logical value "Γ is detected, the detector generates a SKIP signal indicating that channel 2, as non-preferred, is dropped. If '0^M it is the detector that generates and supplies timing and control unit 138 with a SKIP signal (logically complementary to the SKIP signal) meaning that channel 2 is the preferred channel and will not be abandoned.

In response to the SKIP signal, the contents of the channel number register 122 is increased by 1 and the content of the hop memory element 132 corresponding to the next channel is examined. This process repeats until the SKIP signal is generated. In response to the SKIP signal, the content of address register 114 is increased by 1, while the status of register 122 of the channel number does not increase further. At this point, the contents of the channel number register 122 (which is the first hop memory address 132 at which the detector read "0") is displayed on the channel number indicator and the contents of the first tuning voltage memory element 112 are read and converted to an analog value.

If the user wants to change the channel, he can do it by pressing the down button D or up button G on the keyboard 144. When the down button D is pressed, the content of the register 12 of the channel number is successively increased by 1 until the SKIP signal is generated by the detector 134. After creating the SKIP signal, the content of the address register 114 is increased by 1, while the further increase in the content of register 122 of the channel number is stopped. During this time the number of the second preferred channel is displayed and the corresponding tuning voltage generated. Operation of tuning system 28 after pressing the down button D to change the channel is the same as operation of tuning system 20 when the up button G has been pressed to change the channel, except that the contents of the channel number register 122 and address register 114 are increased by 1, not reduced by I.

As mentioned above, it is required that information about the tuning voltage of the user's preferred channels be stored in the subsequent tuning voltage memory elements 112 in the same order as the channel numbers. To accomplish this, the user first sets the selector switch 146

118 258 kind of work in channel position. In response to the generation of the channel signal, the contents of the channel number register 122 and the contents of the address register 114 are increased until the number of the first channel which has the logical value "0" in the hopped memory element 132 associated with it and the associated element is displayed memory 112 addressed in the same way as for the PUP surge signal when the supply voltage is first applied to the receiver. If none of the channels has been programmed, the number 02 will appear on the indicator 120, and on the screen of the picture tube 28 an illegible image will be created, because the hop bit 132 will not be entered in the hop memory 132, i.e. "Γ, and the tuning voltage memory 112 does not contain any significant information. Then the user should program the tuning system 20 so that it creates the appropriate tuning voltage as described below to improve image quality, or can by pressing the up G button of the keyboard 144 select the next channel to program if the obtained image is of insufficient quality, or to reprogramming if the resulting image is readable but the user wants to improve its quality.

After the user presses the up G button, the contents of the channel number register 122 is increased by 1 until the next SKIP signal is generated. Then the number of the next programmed or unprogrammed channel is displayed and the tuning voltage voltage element 112 associated with it is addressed. In order to program or reprogram the tuning voltage, the user should set the mode selector switch 146 to the tuning position, and then press the up and down D buttons of the keyboard 144 to change the tuning voltage by changing the contents of the tuning voltage register 118 that will give a good picture on the CRT screen 28.

In this programming phase, the user must make sure that the picture corresponds to the selected channel for which the tuning voltage information is intended, before this information is stored in memory 112. This is necessary because the picture may correspond to a different channel number than the number shown on the number 120 indicator channel when the mode selector switch 146 was in the channel position. This situation can arise, for example, when the user "passes through the correct tuning voltage for the selected channel in which the RF high-frequency carrier is insufficiently strong to produce a good screen image for the tuning voltage of the next channel. Of course, the user can check whether the picture corresponds to the selected channel while waiting for the broadcast of the recognition signal of the station. However, since this procedure would have to be repeated for each of the preferred channels that should be programmed, this would be an undesirable, large waste of time.

In the tuning system of the invention, the user can check if the image corresponds to the selected channel by checking the channel number indicator 120 after turning the mode selector switch 146 to the tuning position. When the mode selector switch 146 is set to the tuning position, then the indicator input multiplexer 126 disconnects the binary signals generated by channel number register 122 representing the LSD and NSD channel number from the channel number indicator input 120 and turns on the binary signals generated by the tuning voltage register 118 current tuning voltage at the input 120 channel number indicator. As a result, the channel number indicator 120 displays a decimal number approximately equal to the tuning voltage, which gives the user some orientation in the tuning position. The tuning voltage generated by register 118, the signals fed to the multiplexer 126 of the indicator input and the channel number indicator input are selected so that the number corresponding to the tuning voltage imaged in the tuning phase is linearly related to the tuning voltage bypassing fractional values ​​in the range that will be explained below, is illegible or confusing to the average user. Using the tuning voltage table, which links the tuning voltage numbers imaged by the channel number indicator 120 when tuning system 20 is switched to tuning mode with the corresponding actual tuning voltages, the user can check if the image received in the switch tuning position and the corresponding tuning voltage correspond to the programmed channel.

To enter binary signals representing tuning voltage, the user presses the memory button on the keyboard 144. In response to the memory signal, the contents of tuning voltage register 118 are transferred and "entered into the currently addressed tuning voltage memory element 112. At the same time, in response to the memory signal, the contents of tuning voltage register 118 are transferred and "written to the currently addressed tuning voltage memory element 112. At the same time, in response to the signal, the memory is brought in and entered into the currently addressed memory element 132 of the "0" logical hop (by supplying the ground signal).

If the image of the channel to be programmed is inappropriate for the user or corresponds to another channel determined by the tuning voltage displayed in the tuning position, the user should press the delete button. In response to the generation of the signal, the deletion is introduced and entered into the currently addressed memory element 132 of the hop "1 (through connection with a 4-V supply voltage source).

118258 7

After programming the channel, the user should switch mode selector 146 to channel so that the next channel can be programmed or reprogrammed.

In tuning system 20, to create a digital indication related to the linear relationship / tuning voltage generated in the tuning position, the three most significant bits corresponding to 2-2 \ marked on leagues. And through B11-B9, the tuning voltages generated by register 118 are fed through the digital indicator input multiplexer 126 to the indicator decoder 124 instead of the binary signals representing the most significant digit of the MSD of the channel number during the clock signal tens and the next three most significant bits, corresponding to 2 * - 2 \ marked B8-B6 in fig. 1, the tuning voltage generated by register 118 is supplied through the digital indicator input multiplexer 128 to the indicator decoder 124 instead of the binary signals representing the channel number LSD * during the Units clocking signal. In such a system, where the content of the tuning voltage register 118 changes from the first limit value corresponding to the smallest tuning voltage value to the second, largest tuning voltage limit value, the digits at the tens positions and indicator unity change between 0 and 7 according to the octal code described in the column marked with the octal table in Fig. 2 It should be remembered that in the three-bit octal record there are no more than 7 combinations of code characters. So for octal notation there is no character combination for which there would be no significant digital indication, as in the case of the simple binary and hexadecimal notation discussed above. This means that when using octal, the channel number indicator 128 changes the indication in a linear relationship to the tuning voltage between the numbers 00 and 77 without any break in which the digital indication is not linearly related to the tuning voltage.

This is not the case when a simple binary or hexadecimal code entry is used. Analysis of the column labeled "binary" table in Fig. 2 indicates that, however, each field of the 12 * indicator of the channel number can only display ten decimal digits, i.e. 8-9, if a four-bit prostv binary code is used, e.g. by providing 128 binary signals to the indicator B11-B8 is because the four bits on each of the indicator boxes can take combinations corresponding to numbers greater than 9, i.e. numbers 18-15, after displaying the digit 9 on each of the indicator fields, six more code combinations will be generated, whose image symbols do not significantly bind to the amount of tuning voltage, and there will be a pause during which the indications will not be linearly dependent on the tuning voltage. When the four-bit hexadecimal code described in the column designated hexadecimal table in Fig. 2 however, you can display the letters AF on the display for the next six code combinations after 9. this will be toll for the user.

Fig. 3 shows the logic circuit of the multiple input signal digital indicator 126 to enter the six most significant bits B11-B6 at the input of the channel number indicator 128 in octal notation to display two decimal digits connected linearly with the tuning voltage in the tuning position of the mode selector 28. digital indicator input 126 shown in Fig. 3 includes a 4X4 square matrix T 312 * 4, 314a4, 316n-d and 31la-d transit gates. Each T gate has an input terminal 381, an output terminal 382, ​​and terminal 383 that controls the flow of information between input terminal 381 and output terminal 382. As long as "0" is on the terminal control terminal 383, so long terminal 381 is cut off from terminal 382 through what no signal applied to input terminal 381 does not affect the signal level at output terminal 382. When "" appears on control terminal 383, each signal fed to input terminal 381 is passed to the output terminal. The output terminal 382 of each gate of one matrix column is connected to one of the four common output wires 328n 6. The output wires 328a4 of the digital input indicator multiplexer 126 according to Figure 3 are the four input wires of the indicator decoder 124 according to Figure 1. The control terminal of each gate in one row is connected to one of the four 322 * 328 control cables. The control signal in each of the 322-328 control wires is generated by one of four elements 338-336.

Note that there are four bits of the channel number indication associated with the tens and unity fields, while only three tuning voltage indication bits associated with the tens and unity fields. Therefore, the input terminals 381 of gates 316a and 318a of the bushing of the row associated with the fields of tens and unity of the tuning voltage indication are continuously fed a "ground" signal.

The output of element 1 338 will take the value "1 *" and binary signals representing the decimal field of the channel number, i.e. the signals MSD3-MSDO corresponding to bits 2³-2 ° will be sent to indicator decoder 124 when the Tens timing signal becomes "1 *" and the normal signal or channel input into the OR 338 element is "1 *". The output signal of element I 332 will be "1 *" and binary signals representing the unit field of the channel number, i.e. LSD3-LSDHO signals corresponding to bits 2 * -2 ° will be sent to the decoder 124, when the Units timing signal

118 258 will be "Γ", and such a normal signal or channel will be .1 "The output of I 334 will be" 1 ". The output of element I 336 will be "1" and binary signals B11-B9 representing the tens field in the octal notation of the number corresponding to the tuning voltage will be sent to the decoder 124 of the indicator when the Tens timing signal and the tuning signal have values ​​.1 ". The output of element 1336 will be, 1 "and the binary signals B8-B6 representing the quality fields of the tuning voltage numerical value will be sent to decoder 124 when the timing signal JsfoaatU and the tuning signal have values. Γ. The binary signals fed to the decoder 124 are decoded according to the column labeled DECODER in the table of Fig. 2.

In the logic array of the digital input indicator multiplexer 126 according to Fig. 3 as the content of the register lithium tuning voltage changes in order to change the tuning voltage from one extreme value to the other, the number corresponding to the tuning voltage will change linearly between a two-digit decimal number 00 and a two-digit number decimal 77. Because the channel number is also a two-digit decimal number, the user may not be sure whether the mode selector, system 20 is in the normal operating position or the channel selection position, or the tuning voltage correction position. To avoid this uncertainty, it is desirable for the tuning position to display only one decimal digit indicating the tuning voltage value, not two. To completely rule out a mistake, it is expedient to display one symbol indicating to the user that the tuning system 20 is in the channel position and another symbol indicating that the system is in the tuning position.

To display one rather than two decimal digits representing tuning voltage, only the three most significant binary signals B11-B9 (instead of the two groups of signals B11-B9 and B8-B6) are fed into the multiplexer 126. The multiplexer 126 feeds signals B11-B9 onto the decoder 124 and the seven bit image symbol formed therein is inserted into the position of the units in the indicator unit 130 during the duration of the Units timing signal. Since the binary signals change from the symbol corresponding to the decimal digit 0 to the symbol corresponding to the decimal digit 7 when the tuning voltage changes, there will be no code symbol that could not be clearly depicted using the indicator 130A assembly and as a result the tuning voltage digit will change linearly with the tuning voltage in the whole range of its changes.

So that the user can better distinguish between selector entries: channel selection and tuning voltage correction, tuning selector 146, as long as the user does not change the tuning voltage value using the up and down D buttons on the keyboard 144, in position 130B tens of the image indicator is the letter A corresponding to the code symbol entered on the multiplexer 126 from assembly 140, and in the position of units the letter J corresponding to the code symbol introduced on multiplexer 126 from assembly 156, that the letter AJ symbol for adjustment is visible. While the user is changing the tuning voltage using the up and down D buttons and is displayed in the 130A box changing units^rę a one-digit number corresponding to the tuning voltage, the letter A is displayed in the field of tens 130B. Since only the three most significant signals B11-B9 are connected to the channel number indicator unit 120, the tuning voltage will change very slowly, which may give the impression that the voltage tuning does not change at all. To avoid this inconvenience, the binary signals supplied by the assembly 150 by means of appropriate connections between the + V voltage source and the ground signal representing the symbol - (dash) are placed on the multiplexer 126 and alternately imaged in place of the letter A in the field of tens 130A, when the tuning voltage changes in the system tuning position. It is preferable to use a timing signal for alternate imaging of the letter A and the symbol - (dash) at a frequency corresponding to the rate of change in tuning voltage. Since the BC signal from register 118 changes at a speed equal to half the speed at which the least significant binary signal input on the channel number indicator 120, i.e. B9, changes, it has a rate of change equal to half the speed at which the number of tuning voltage changes, which is favorable speed for this purpose.

To distinguish between types of operation, tuning and binary signals are introduced on the multiplexer 126 representing the letter C from the set 152 and signals representing the letter R from the set 154. These signals are imaged in the field of tens 130B and unity 130A as the symbol CH (channel) alternating with two-digit keypad number when the selector switch 146 is in the channel position. To change the image of the CH symbol to a two-digit channel number and vice versa, a Variable timing signal having for example a period of about 3 seconds. is generated by control assembly 138 and fed to the indicator input multiplexer 126.

FIG. 4 presents the 4X 7 matrix T goals, which task is: 1) continuous imaging of the two-digit channel iuinener in the normal position of the mode selector and 2) alternative imaging of the two-digit channel number and CH symbol in the channel selector position and 3a) continuous imaging of the AJ symbol when the tuning voltage is not corrected with the up and down D buttons tuning position and 3b) display 118 258 non-single-digit number of tuning voltage at the position of the indicator unit 13®A and alternative display of symbols A and —in tens position 13ΦΒ indicator when the tuning voltage is corrected with the up and down buttons D in the selector tuning position. The logic shown in Fig. 4 is analogous to that shown in Fig. 3. Element OR 412, elements NIE-I 414, elements NIE 416i I 418, 420, 422 and 424 by controlling the flow of information to the decoder 124 they perform the functions I) and 2). Element NO — OR 434 and element I 436 and 438 by controlling the flow of information to the deco -der 124 perform the function 3a). Element NO — OR 440, element NO 426 and elements 1428,430 and 432 by controlling the flow of information to the decoder 124 implement the function 3b). The digital indicator decoder 124 decodes according to the diagram in the column designated "DECODER of the table in Fig. 2, a group of four binary signals to form the corresponding numbers and symbols.

To facilitate the tuning process adjustment process, it may be beneficial to display symbols representing the tuning band at tens position 130B next to the number of tuning voltages depicted at position 130A units. To accomplish this, assuming there are three tuning bands, binary signals representing the letters A, B and C corresponding to the tuning bands, first, second and third are fed to the input of indicator multiplexer 126. After generating the tuning voltage of the channel in the first band, binary signals representing the letter A are depicted in the tens of 13ΦΒ field and the corresponding single-digit number of tuning voltage is displayed in the 13ΦΑ units field. The same applies to the other two bands. For band determination, a modulo 3 counter up and down can be used (i.e. counter with three output states) whose content increases by 1 each time the contents of the tuning voltage register 118 correspond to the maximum tuning voltage value, e.g. each time the contents of tuning voltage register 118 change from all "1" to all "0" and whose content decreases by 1 each time the content of register 118 corresponds to the minimum tuning voltage, e.g. each time the contents of tuning voltage register 118 change from all "0" to all "". These and other modifications of the invention are within its scope.