Self-synchronizing scrambler.

Self-synchronizing scrambler for high bit rates with a number of parallel-operating Verwürflerstufen, each of the series circuit of a first (A1) and a second (A2) modulo-2-adder and at least one shift register stage (SR) group; for suppression of short periods may be inserted 1 to 2 modulo 2 adder, a third modulo-two adder is inverted by the occurrence of short periods in at least one bit of the passing signal. The application can alternatively be performed with previous scramblers, wherein the processing speed is reduced to a fraction of the previous and thereby a cheaper conducting half (CMOS) technology may be used.