Adaptive selecting method for memory access priority control in MPEG processor

Patent holder (s):

United Microelectronics Corp, of Hsin-Chu, Taiwan (TW).

(47) Date:

07.05.99 (© Published:

01.07.99 IE 99/07

Inventor (s):

Wen-Yi Wu at Hsin-Chu (TW) Jyh-Shin Pan at Hsin-Chu (TW) (74) Authorized representative:

Ir. HJG Lips cs at 2596 HG The Hague.

(54) Adaptive dialing method for controlling the memory access priority in an MPEG processor.

© Adaptive dialing method for controlling the memory access priority in an MPEG processor. The processor includes function modules consisting of an input interface, a CPU, a sound decoder, an image decoder, a sound processor, an image processor and a memory controller. Each of the modules gains control of the data bus through arbitration by the memory controller to access the memory. The CPU's access priority to the data bus is kept at a relatively lower level, except when the CPU has to perform a syntactic parsing on the MPEG compressed data and realizes the initial decoding of the sound compressed data. This balances the use of data bus bandwidth among all system resources, increasing overall system efficiency.

NL C 1007453

The contents of this patent correspond to the original filed description with claim (s) and any drawings.

Adaptive dialing method for controlling the memory access priority in an MPEG processor

BACKGROUND OF THE INVENTION Field of the invention

The present invention relates to controlling the memory access priority in MPEG (Motion Picture Experts Group) circuits, and in particular to an adaptive dialing method for controlling the memory access priority in an MPEG processor. Specifically, this invention relates to an adaptable dialing method for dynamically controlling memory access priority in an MPEG processor, to improve decompression by reducing unnecessary system resource takeover.

Description of the Related Art

Due to advancements in the areas that include digital signal processing technology, materials science, as well as laser technology, storing and retrieving audio and video signals in digital format, the industry of high fidelity sound and motion picture production has types selected. When broadcasting entertainment programs, the similar trend of switching to digital format can be seen, moving away from the aging analog format, the technological basis of which was laid for several decades.

Due to the sizeable installation base of consumer analog reception equipment, such as televisions and radio receivers, except that the last segment of subscriber signal transmission is still in analog form, there is an increasing trend of using digital format when the program signal is manipulated or edited, either in the save / recall process or during transmission. For example, satellites transmit digital signals to ground stations, which then convert the program signal and relay analogous to subscribers' homes over the cable network. In fact, several standards have been proposed for all-digital broadcasting systems such as those recorded with the ubiquitous High Definition TV (HDTV). The aforementioned trend of switching from analog to digital processing system is taking place because, based on what is currently available, the digital storage and recovery technology for audio and video signals, which is better than its analog counterpart, produces much better results. Digi10 language processing is virtually the only means for the superior quality of sound and image reproduction in a cost effective manner that physical human perceptions may require from both hearing and vision.

Of the various methods of compressing / decompressing digital signals, the MPEG standard, either MPEG-I or MPEG-II, is one of the most promising and widely accepted in the multimedia industry. When decompressing the signal, namely the playback end, the MPEG method, like many others, relies on the use of digital signal processing (DSP) circuit elements to realize lookup data for displaying programs from a source which provides signals that contain compressed sound and image data. The source of compressed data for the

For example, MPEG processor circuitry in a display device may be the newest members of the popular Compact Disc (CD) family of data storage formats, including the video CD (VCD) or the digital video disc (DVD). It is also possible that the MPEG processor circuit receives its compressed data signal source from a digital broadcasting station.

To achieve the sound and image reproduction using compressed data extracted from signal sources in a multimedia application using the MPEG standard, function-related digital electronic equipment circuits known as MPEG process07453 sensors must be used. These MPEG processors can be constructed using digital switching elements built around digital signal processors and microprocessors that perform an equipment method for accomplishing the MPEG decompression operation. Memory resources are also used in the process of performing the MPEG decompression. In fact, MPEG processors rely heavily on the use of a memory subsystem when the multimedia data is decompressed to display a program.

However, conventional equipment modules in the digital electronic circuit that use the MPEG standard of audio and video signal decompression use a fixed memory access priority in a small and self-supporting equipment system. In such conventional MPEG systems, the use of system resources cannot be optimized to fully utilize the supported bandwidth of the data bus connecting the CPU, the DSP (digital signal processor), the memory, and the supporting logic circuitry of the system . As is known to those skilled in the digital processing art, an unbalanced use of resources in a digital system can be directly translated into wasting system power. An increase in the performance of many of the components in the system will be required. Such an increase in performance is necessary to achieve the same level of system throughput that shows well-balanced use of resources. In other words, an MPEG system that realizes an unbalanced use of resources (including bus bandwidth) with all its modules 30 would require the application of either a more powerful CPU, DSP, or other circuitry when compared to a system that shows a well-balanced use of resources.

In particular, in an MPEG decompression operation, when the memory access priority in all

53 If active modules were fixed in the MPEG processor, there would be a phenomenal waste of memory bus bandwidth since the CPU is enclosed in an endless scanning equipment loop. On the other hand, when a module in the MPEG processor has to access resources via the system bus, the bus is often busy. In that case, the requesting module must be put on hold. As a result, the system spends a considerable amount of time controlling the CPU to query, because the DSP portion of the system crashes in the path in which it tries to access the bus to access data in memory subsystem.

SUMMARY OF THE INVENTION It is therefore an object of the invention to provide an adaptive dialing method for controlling memory access priority in an MPEG processor in order to achieve a more balanced use of the memory bus bandwidth.

It is another object of the invention to provide an adaptive dialing method for controlling memory access priority in an MPEG processor that realizes a more balanced use of the memory bus bandwidth to improve the overall degree of MPEG decompression performance.

It is yet another object of the invention to provide an adaptive dialing method for controlling memory access priority in an MPEG processor that realizes a more balanced use of the memory bus bandwidth by dynamically prioritizing access rights to the system bus for improvement to improve the overall degree of MPEG decompression performance.

The present invention achieves the objects described above by providing an adaptive dialing method for controlling memory access priority in an MPEG processor. The processor has function modules that

1007457 include a CPU, which serves to parse the compressed audio data and the compressed image data syntactically from the compressed data of the MPEG, and a memory control unit is used to arbitrate the access priority of each of the memory access modules via the data bus. The CPU's access priority to the data bus becomes at a relatively lower level, except when the CPU must perform a syntactic parsing on the MPEG compressed data and perform the initial decoding of the compressed audio data. Using the data bus bandwidth is therefore balanced between all system resources, improving the overall performance of the system.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, advantages and features of the invention will become apparent from the presentation of the following detailed description of the preferred, but not limiting, embodiments. The description is made with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram showing the internal configuration of an MPEG processor;

FIG. 2 is a flow chart showing the hardware routine of a conventional MPEG processor used to control the execution of the decompression operation in a fixed priority scheme; and fig. 3 is a flow chart showing the hardware routine according to the preferred embodiment of the present invention for a conventional MPEG processor used to control the execution of the decompression operation in an adaptive priority schedule.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to Fig. 1, a block diagram is shown showing the internal configuration of a typical MPEG processor. The structural configuration of equipment circuitry and the general operation of such an MPEG processor has been examined for the purpose of the description of the invention.

As shown in the block diagram, an MPEG processor, generally designated by reference numeral 100, has a number of function modules coupled together via a data bus and a network of several control signal lines. The MPEG processor 100 receives input compressed data conforming to the MPEG compression standard at one end, and produces decompressed audio and picture program signals at the other end after processing.

In the example shown, the MPEG processor 100 receives a series of compressed data from a CD-compatible device, which can be a VCD or a DVD, and generates a PCM signal as an audio output, and an NTSC signal as an image output. . As is known, input to the MPEG processor 100 can also come from a multimedia signal source, such as a broadcasting station that transmits digital signals conforming to the MPEG standard. On the other hand, the image output signal generated by the MPEG20 processor 100 may be a PAL signal, or it may also take the form of, for example, the standard VGA format popular in the personal computer industry. This image output signal can then be relayed to suitable circuits for further processing and display.

In the hardware configuration of Fig. 1, the MPEG processor 100 operates to decompress the received MPEG data in conjunction with a memory system, generally indicated by the reference numeral 400 in the drawing. In this described example, the memory blocks required in the memory system 400 to perform the MPEG decompression scheme are physically independent of the MPEG processor 100. The MPEG processor 100 accesses the memory 400 through the intermediate data bus. As those skilled in the art will realize, this use of the memory block arrangement physically outside of the MPEG1 00 7453 processor 100 is not absolutely necessary. Embedding working memory blocks in the MPEG processor is also possible. In the example shown in FIG. 1 in a specific situation, the MPEG processor 100 may be included in the VCD5 or DVD drive subsystem mounted on the extension bus of a personal computer system. This particular arrangement can take an allocated memory segment of the addressable memory space in the host computer system as the working memory area.

The MPEG processor 100 as shown in Figure 1 includes a CD interface module 119 which is used as the connection between the processor itself and the MPEG compressed signal source. This signal source can be a CD-compatible device from VCD or DVD, as in this example described.

Under normal circumstances, the CD interface 110 receives data signals prepared in the MPEG compressed format that is sent serially. This is because standard CD-compatible drives, like many other magnetic media-based drives, access data stored on the surface of its storage media in a single-bit stream. Thus, although not shown in the drawing, the CD interface 110 may include a serial to parallel circuit which converts the received serial data into parallel data for processing in the internal circuit of the processor as in the specification of the MPEG standard . The input data thus processed is then buffered in a FIFO (first-in first-out) 112 and can then be brought to the next circuit module in the processor 100 for further processing.

The CD interface 110 is coupled to the rest of the circuit of the MPEG processor 100 via a data bus MEM_BUS. Essentially, in the example shown, the memory system 400 serving as the main memory for the processor is located on the data bus MEM_BUS, as shown in the drawing. The main function switching modules of the MPEG processor 100 are also located on this data bus¹007453 be able to access the system memory 400 when they are operating. The bi-directional designation of the bus segments going in and out of the function modules in the drawing schematically indicate that the data is sent in two directions if necessary.

In addition to the CD interface 110 which provides an input connection to the system, the function modules in the MPEG processor 100 include a CPU 120, an MPEG sound decoder 130, a PCM processor 132, an MPEG image decoder.

140, an image processor 142 and a memory controller 150. As mentioned, these modules reside on the data bus MEM_BUS, which allows the system memory 400 to be accessed when the MPEG processor 100 is operating to output sound and image output. from the MPEG data received over the external source via the CD interface 110.

The CPU 120 may be a microprocessor or microcontroller that performs an equipment routine to coordinate the operation of the function modules in the MPEG20 processor 100 in the process of decompressing MPEG data. When the routine is started, the CPU 120 coordinates all function modules in a preprogrammed priority scheme whereby, if necessary, each of the modules can access the memory source under the control of the memory controller 150. When the memory control unit 150 grants the right to access the memory source 400 via the data bus MEM_BUS based on the priority scheme to a module, the module, i.e. a module selected from the CD interface 110, has the MPEG sound decoder 130 , the PCM processor 132, the MPEG sound decoder 140, the image processor 142 and the CPU 120, the ability to access the memory source 400 independently.

As those skilled in the art will all know, several devices located on a common data bus can access the shared target memory source one by one. This is a process of competition over the access right to the data bus MEM_BUS which is performed according to the set schedule of prioritization. This scheme is a fixed procedure for conventional MPEG processors. Such prior art priority scheme requires the control, the memory control unit 150 in the case of the discussed hardware configuration of FIG. 1, to check the request status of all function modules, and grant the access right to the memory access data bus based on the priority method included in the equipment routine.

In the example of equipment configuration shown in Figure 1, the function modules in the MPEG processor 100 are coordinated under arbitration by the microcontroller 150 to access the data bus MEM_BUS in an appropriate manner. It should be noted that each of the function modules in the MPEG processor 100, in addition to being connected to the memory source 400 via the data bus MEM_BUS, is also equipped with additional connection confirmation control signal lines which are connected to the memory control unit 150. These control lines facilitate the control of approximation processing to the memory source by each of the modules.

The CPU 120 in the MPEG processor 100 is also responsible for the syntactic decomposition of the MPEG compressed data into audio, picture and other supporting data segments, which form the compressed data conforming to the MPEG standard. In the shown equipment example of FIG. 1 CD interface 110, as described above, receives the serial bitstream of compressed data from the external source, and then stores the received MPEG compressed data in the CD-FIFO 422 of memory source 400. As described, this process requires coordination of the memory control unit 150.

Thereafter, under the hardware routine control, the CPU 120 also performs a syntactic parsing on the CD1007453

FIFO 422 looks up data, then stores the generated sound and picture compressed signals in the sound buffer 412 and the picture buffer 414, respectively.

On the other hand, the MPEG sound decoder 130 and the MPEG picture decoder 140 mainly play the role of sound picture DSP which actually crunch their respective decoding data to obtain the associated sound and picture data in the uncompressed format. As is known, these operations involve the use of decoding algorithms.

For example, when the MPEG image decoder 140 requests to access the memory source 400, it flags the request signal over the VD_MEM control lines to the memory controller 150. Upon receipt of the request arbi15, the memory controller 150 treats based on the predetermined memory access priority scheme, and if the arbitration result obtained by the memory controller 150 is to grant access to the data bus MEM_BUS, MPEG image decoder 140 then initiate its memory approximation in the memory source 400 via the data bus MEM_BUS. The MPEG image decoder 140 may then, for example, look up the data stored in the allocated location, the image buffer 414 in the memory source 400, to perform the processing of the compressed image data previously parsed syntactically and displayed in images. buffer 414 was written by the CPU 120. On the other hand, the MPEG image decoder 140, for example, can also store its generated data in the allocated location, the frame buffer 432 in the memory source 400. This data stored in frame buffer 432 can later be similarly searched by the image processor 142, arbitration of the memory controller 150 taking place. The image processor 142 can then output its generated result as the image output, in the case of Fig. 1 an NTSC signal. As is known, the video processor 142 may then output a PAL signal in another case

1 run.

Thus, in the MPEG processor 100 with the hardware configuration outlined in Figure 1, the CPU 120 must efficiently perform the syntactic decomposition of the MPEG compressed data and the initial sound and picture decoding. In other words, the CPU 120 must be given a high priority of access right over the data bus to end that syntactic parsing and initial decoding as soon as possible. As mentioned above, prior art MPEG processors seem to facilitate this operation in a fixed priority scheme. In such fixed priority methods, when the CPU 120 is busy with the program loop steps, all function modules in the MPEG processor 100 cannot perform their respective function call operations. This fixed priority schedule has at least one major drawback. Namely, CPU 120 itself also consumes bandwidth of the data bus MEM_BUS when it executes its routine and accesses the memory source 400. Therefore, it often occurs that the CPU 120 is temporarily stuck in the program loop scan to see if a function module in the MPEG processor 100 requests access to the data bus MEM_BUS. During this stuck period, none of the function modules can perform their respective functions since the data bus MEM_BUS is locked by the CPU

120. So the situation often ends so that the MPEG processor

100 Spends more time looping than decompressing MPEG data. The overall performance of these prior art MPEG processors using fixed priority schemes is therefore very inefficient.

For example, due to the fact that CD drives (including VCD and DVD, the youngest members developed from the original CD family) output data in serial format, it is very likely that an empty CD-FIFO 422 in the memory source 400 will solve the bottleneck of internal operations in the entire MPEG processor 100. A bottleneck

2 is formed in such situations since the fixed priority method adopted by these prior art MPEG processors does not have the flexibility to other function modules, which are really the data bus

MEM_BUS should approach to have their function performed. These will have to circulate in the endless cycle, since all function modules in the MPEG processor are given the same priority. This requires that each of them be spun in a loop, and each of them must follow the same sequence of steps before it can be considered.

Fig. 2 shows a flow chart showing the equipment routine of a conventional MPEG processor operating in an endless loop. This prior art routine is based on a fixed priority method and is used to control the execution of the decompression operation on externally received MPEG compressed data. As shown in fig. 2, this prior art equipment routine performed by the CPU 120 in the equipment configuration of FIG. 1 consists of a continuous loop that loops back from step 220 when it started at step 200. More precisely, when the routine starts at step 200, the MPEG processor 100 sets the initial precedence scheme conditions for all functions to be performed by the processor in the process of performing the MPEG decompression.

In the endless prior art routine, in Fig. 2, the function modules in the PEG processor 100, including CD interface 112, MPEG sound decoder 130,

PCM processor 132, MPEG image decoder 140, image processor 142 and CPU 120 are all arbitrated by the memory controller 150 when the need arises to access the data bus MEM_BUS. Since the memory access priority is set in step 210, and no further step changes this priority, the principle operation of the syntactic parsing of the compressed data may be,

G £ J / 453

3 as well as the decoding of sound data and image data, benefit from the same and unaltered priority level.

In Fig. 2, the cycling routine at step 5220 first checks whether the function of sound decoding is necessary. For this decision-making step, CPU 120 determines whether or not it is necessary to perform sound decoding. The routine jumps to step 222, temporarily branching the endless routine from the loop to make a function call by executing a subroutine, namely function call A as identified in this step block. In this queried subroutine, CPU 120 decodes the data associated with the compressed audio data stored in the memory source 400. After decoding,

CPU 120 outputs the decoded compressed audio data to the memory source. This is accomplished by the CPU through access to the data bus MEM_BUS by the memory control unit 150. Thereafter, the program subroutine generally outlined in program step 222 may be terminated, and the program control may then be returned to the main cycle loop. In other words, the loop continues to 230 for further processing.

On the other hand, if CPU 120 decides in step 220 that it is not necessary to perform an initial sound decoding, the routine of Fig. 2 will proceed to step 230.

Similarly, at step 230, CPU 120 determines whether or not to parse the CD data or MPEG bitstream extracted from the external source by the CD interface 110 of the MPEG processor 100 or not syntactically.

If the functionality is requested through proper flagging, CPU 120 jumps out of the main program loop again and coordinates the performance of a series of operations referred to as function call B described in program step 232. These include CPU 120 which are sent via the

CD interface 110 obtained data parsed syntactically. The MPEG bitstream is also subject to syntactic reading1007453

4 thing at the system level. The data corresponding to the sound compressed data obtained as a result of the MPEG syntactic parsing operation is then output to the memory source 400. The syn5 tactically parsed image data is also decoded by the CPU 120, followed by the initial image decoding , and the result is then output to the image buffer 414 in memory 400. Then, the program transfer is returned to the main loop, and continues at step

240.

If the system has determined that the program jump to function call B is not needed in step 230, the main cycle loop proceeds to step 240. The routine decides in step 240 whether further MPEG decompression functionality, which in branched jump 242 is common. has been described as function call C as performed by the CPU 120 may or may not be necessary. If this is the case, the CPU 120 coordinates the corresponding continuation of the program jumps and then returns to the main loop. If the result of the decision is negative, the loop remains only in the main program cycle and returns to step 220, where the routine cycle is repeated again.

In the equipment routine of Fig. 2 for the conventional MPEG processor, the services branched from the main cycle loop at the function call subroutines, namely operations described in steps 222, 232 and 242, are ordered in the fixed diagram of service.

As mentioned above, a considerable amount of time is wasted going through the main program since function calls A, B and C would have to be run several times before their service modules can actually be executed.

An embodiment of the invention as shown in the flow chart of Fig. 3 includes a dynamic service 35 prioritization scheme to improve the effective service duty cycle of the MPEG processor equipment 15 routine, thereby promoting the overall efficiency of the MPEG decompression. As shown in Figure 3, the flow chart shows the equipment routine according to the preferred embodiment of the present invention for an MPEG processor. This routine is used to control the execution of a decompression that is performed over

<td>the compressed data daard.</td><td>that meet</td><td>On</td><td>the</td><td>MPEG standard</td>

<td>For a detailed</td><td>description</td><td>from</td><td>the</td><td>equipment</td>

<td colspan="2">10 routine shown in the flow chart of FIG</td><td> . 3</td><td>is</td><td>outlined,</td>

Considering the use of an MPEG processor 100 as shown in Fig. 1. As shown, this exemplary equipment routine performed by the CPU 120 in the equipment configuration of Fig. 1 has also been built around a continuous program loop that loops from step 320 when it started at step 300. Specifically, when the routine starts at step 300, the MPEG processor 100 realizes the initial conditions for the memory access priority scheme for all functions to be performed in the processor in the process of performing the MPEG decompression. Note, however, that this group of priority conditions is only the initial setting, parameters of which will be dynamically adjusted when the operation of the MPEG processor 100 performs its tasks.

As shown in Figure 3, the cycle main routine first checks whether the sound decoding functionality is necessary in step 320. For this decision making step, when the CPU 120 determines it is necessary to disable the initial sound decoding, the hardware routine jumps to step 322 where the access priority of the CPU 120 to the data bus MEM_BUS is increased. The priority elevation is relative to the original level set in step 310 when the routine initially started. Thereafter, the routine proceeds to step 324, where a function call is referred to as func1 00 7453

6 tie call A is made by executing a corresponding function subroutine. In the same manner as described above for the prior art routine, CPU 120 decodes the data corresponding to the sound compressed data stored in the memory source 400, and then stores the result again in the memory source 400 . This is facilitated by the CPU 120 controlling access to the data bus MEM_BUS via control by the memory control unit 150. Thereafter, the program subroutine generally described in the program step 324 can be terminated and the program control can then be transferred to step 326, where the priority level assigned to the CPU 120 for accessing the memory 400 via control over the data bus MEM_BUS is decreased. At this time, the CPU priority for requesting control over the data bus may be lowered to a level lower than the initial setting. Then the equipment routine proceeds to step 330 for another MPEG decompression 20 operation.

On the other hand, if the CPU 120 decides in step 320 that initial signaling decoding is not necessary, the routine of Fig. 3 will proceed directly to step 330.

At step 330, in a manner similar to that at step 320, CPU 120 determines whether or not service is requested to another function subroutine. For example, step 330 determines whether or not the CD data or MPEG bitstream as extracted from the external source by the CD interface 110 of the MPEG processor 100 is to be syntactically decomposed. If the functionality is requested through proper flagging, the routine proceeds to step 332 to increase the priority level for accessing the data bus MEM_BUS for the CPU 120. The priority increase is from the original level set at step 310 when the routine was initially started. Then, the routine proceeds to step 334, where

7 a function call identified as function call B is performed by executing a corresponding function subroutine. Again, as in the prior art routine described above, assigned function operations required in the process of executing the MPEG data decompression can be performed in this subroutine. For example, in this invoked subroutine, the operations may include CPU 120 which syntactically parses the CD data obtained through the CD interface 110. The MPEG bitstream is also subject to system-level syntactic parsing. The sound-compressed data obtained as a result of the MPEG syntactic decomposition operation is then output to the memory source 400. The image data is syntactically parsed and then the initial image decoding performed by the CPU 120 and the obtained data are output to the image buffer 414 in memory 400. Thereafter, the program controller is transferred to step 336, where the CPU priority for approximating the memory source 400 over the data bus MEM_BUS is decreased to normal. After this step, the routine proceeds to step 340.

However, if the system has decided that the program jump to service call B is not needed at step 330, the main cycle loop proceeds to step 340. The routine decides in step 340 whether further MPEG decompression functionality, which in the branch jump 342 is common. has been described as function call C made by the CPU 120, may or may not be necessary. If so, the CPU 120 coordinates according to the branching continuation and then returns to the main loop. If the decision is negative, the loop simply remains in the main program loop and goes back to step 320 where the routine cycle is repeated again.

In the hardware routine of Fig. 3, which depicts a preferred embodiment of the invention for operation of the MPEG processor, the services to function 1007453 call subroutines branched from the main cycle loop are operations described in the steps 324, 334 and 342 are arranged in a dynamic schedule of operating priority. The CPU priority for accessing the memory source 400 over the data bus MEM_BUS is only increased to a higher level than normal if it is necessary, and during all other periods when the CPU 120 is not required to control the data bus. priority of access reduced to normal. This avoids the situation where the CPU inadvertently occupies the data bus MEM_BUS when it is not actually needed. That is, just the fact that rotating the priority list points to the CPU 120 does not imply that the data bus would be busy unless another function module attempts to gain control. In the illustrated flow chart of Fig. 3, although the hardware routine main cycle loop points to the CPU 120 when it is not necessary to grant the data bus MEM_BUS access right, for other function modules in the

MPEG processor 100 will not be an obstacle to accessing the memory source 400. This is due to the fact that the priority level has been kept at its relatively low level. Accordingly, the overall efficiency of the MPEG decompression can be significantly improved over that of the prior art method.

Although the invention has been described by way of example and in terms of the preferred embodiment, it will be understood that the invention need not be limited to the described embodiments. On the other hand, it is intended that it covers several modifications and similar arrangements within the scope of the appended claims, the scope of which should be given the widest interpretation in order to include all those modifications and similar structures.

- conclusions 1 00 7 /