Direct digital synthesizer driven pll frequency synthesizer with clean-up pll.

(54) Tltle: DIRECT DIGITAL SYNTHESIZER PRIVEN PLL FREQUENCY SYNTHESIZER WITH CLEAN-UP PLL

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FIRST FREQUENCY

FREQUENCY CONTROL

CONTROL (57) Abstract

A frequency synthesizer (200) which uses a direct digital synthesizer (DDS) (204) to generate a highly accurate periodic signal. The DDS (204) output signal is bandpass ftltered utilizing a clean-up phase lock loop (PLL) (214) to produce a spectrally puré reference signal and promote overall fast settling time. A second or primary phase lock loop (220), having a much futer settling time than the first PLL (214), adjusts tbe frequency of the reference signal generated by the clean-up PLL (214). In one embodiment, the DDS frequency synthesizer (204) has a digital te analog converter (DAC) (206) cooptad to the clean-up PLL (214). Another embodiment (300) feeds the most significant bit (MSB) (310) or overflow bit from the DAC accumulator (306) into che clean-up PLL (318). Yet another embodiment (400) uses a switching apparatus to bypass the clean-up PLL (410) while it is settling on a new frequency.

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FREQUENCY SYNTHESIZER PLL EXCITED BY

DIRECT DIGITAL SYNTHESIZER WITH CLEANING PLL

BACKGROUND OF THE INVENTION

I. Field of the Invention

The present invention relates to frequency synthesizers. More particularly, the present invention relates to a novel and improved apparatus and method for synthesizing frequencies using a direct digital synthesizer in combination with one or more phase-locked loops (PLLs).

II.

Description of Related Technique

Conventional frequency synthesis can be performed in combination using a synthesizer with a phase locked loop synthesizer loop.

hitch digital reference

Phase way (PLL). Can Direct (DDS) for circuit for the ideal, a circuit for rejecting stray leads from the DDS reference signal, works over a wide range of frequencies and achieves a rapid stabilization time.

However, the achievement of difficult using a single? 1450 / 97KX

-2. .1 ι

PLL in combination with a DDS. A PLL designed to stabilize quickly at a new frequency is often unable to reject a wide range of stray leads found in the DDS reference signal. Decreasing the frequency stabilization time and increasing the rejection of parasitic leads presents a conflict in the design requirements of a PLL device.

The DDS reference signal is a digitized periodic signal whose frequency can be fine-tuned over a given bandwidth. This signal is produced by accumulating the phase at a higher rate consistent with sampling theory, transforming the phase into a periodic waveform using a lookup table, and converting the resulting digital representation of the periodic waveform to a signal. Analog that uses a digital to analog converter. However, the DDS output signal may contain stray leads due to quantization errors and truncation as well as noise due to thermal and semiconductor effects.

The analog signal, produced by the DDS, is the source of the PLL reference frequency. A PLL is designed to output a range of frequencies when the frequency resolution is equal to the reference frequency. Coarse adjustments in increments to the

P1450 / 97MX nominal DDS reference frequency output frequency can be made by varying the value of the loop divider, Fine frequency adjustments can be made by varying the DDS output frequency, for example, the reference frequency source of the phase locked circuit. The fine adjustment of the increment is the resolution of the frequency of the DDS output multiplied by the value of the circuit division.

The performance of a phase locked circuit is related to various factors including: (1) the frequency of the reference signal, (2) the magnitude of the divisor needed to divide the output frequency by lowering it to the reference frequency, and, (3) the bandwidth of the circuit filter. The frequency of the reference signal dictates the resolution of the frequency or size of the loop stage, that is, the smaller the reference frequency, the higher the frequency resolution. The magnitude of the circuit divider has a major impact on the noise performance of the circuit. As such, any phase noise or stray noise at the reference frequency will appear at the output of the circuit that has its original magnitude multiplied by the divisor of the circuit. The bandwidth of the loop filter, which is normally from five to

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-4 ten percent has an impact of the reference frequency or less, on the speed with which the loop can stabilize at a new frequency.

Thus, the narrower the filter bandwidth of the circuit, the more slowly the circuit will stabilize at the new frequency.

The synthesizer

PLL driven by conventional DDS with narrow bandwidth loop frequency resolution rejects noise and stray leads from the DDS reference signal and produces a synthesizer signal with high spectral purity. Examples

PLL excited by DDS are provided in the US Patent

state

United States of America No. 4,965,533, entitled DIRECT DIGITAL

SYNTHESIS DRIVEN PHASE LOCK LOOP

FREQUENCY SYNTHESIZER and, the Patent of the United States of America

No.

5,028,887 titled DIRECT DIGITAL

SYNTHESIZER DRIVEN

PHASE LOCK LOOP FREQUENCY SYNTHESIZER

WITH HARD LIMITER, which were assigned by the inventor to the assignee of the present invention and are mentioned herein by reference. The loop with small bandwidth required to obtain high spectral purity tends, however_F to increase the frequency stabilization time.

On a synthesizer

PLL excited by

Conventional DDS, a quick turnaround time

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<td colspan="3">stabilization and high purity</td><td>spectral</td><td colspan="2">present a</td>

<td>conflict</td><td>for</td><td>the requirements of</td><td>design.</td><td></td><td></td>

<td></td><td>By</td><td colspan="2">therefore a goal of</td><td>the</td><td>Present</td>

<td>invention</td><td>is</td><td>provide a</td><td>new</td><td>and</td><td>best prayed</td>

phase locked loop frequency synthesizer, excited by direct digital synthesizer, capable of achieving a fast stabilization time while producing a signal with high spectral purity.

Another object of the present invention is to provide a novel and improved phase locked circuit frequency synthesizer excited by

<td>digital synthesizer</td><td>direct</td><td>in</td><td>where he</td><td>synthesizer</td>

<td>direct digital no</td><td>requires</td><td>the</td><td>use of a</td><td>converter</td>

<td>digital-analog.</td><td></td><td></td><td></td><td></td>

<td>An objective</td><td>additional</td><td>of</td><td>the present</td><td>invention is</td>

use a switching arrangement to reduce the settling time of an improved phase-locked circuit frequency synthesizer excited by direct digital synthesizer.

SUMMARY OF THE INVENTION

An improved frequency synthesizer uses a pair of phase locked loop circuits to process a digitally generated analog signal. A direct digital synthesizer (DDS) is a method of producing the digital reference signal. DDS produces digitized periodic frequencies by accumulating the phase at a higher rate consistent with sampling theory, transforming the phase into a periodic waveform by a lookup table and converting the resulting digital representation of the periodic waveform to an analog signal, using a digital-to-analog converter.

In the first mode, the first cleaning or debugging PLL coupled to the DDS frequency source cleans or purifies the noise enclosed around the reference frequency.

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cleaning offers

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arrangements

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PLL

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conventional

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frequency

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inherent reference

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The abilities

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PLL band loop.

depend on the size of the width width

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band

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A

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frequencies

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PLL narrower one window

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Reference Frequency Normally, the cleaning PLL produces an output signal close to or the same as the input reference frequency, adjusting the value of the loop divider substantially to unity. A clean or debug PLL will provide a spectrally pure reference signal regardless of any additional filters that may be required by other t'145O / 97MX

-71 ... .1 J conventional synthesizers.

A second PLL circuit or primary PLL circuit accepts the spectrally pure reference signal from the cleaning PLL and adjusts the frequency as needed. The PLL circuit adjusts the output frequency, in increments of the input reference frequency, by adjusting the value of the loop divider to values ​​substantially larger than unity. A frequency control input to the primary PLL can be used to dynamically make coarse adjustments to the output frequency. Fine frequency control can be achieved by adjusting the DDS reference frequency used as input to the first of the PLL circuits.

The total stabilization time for the present invention to latch or sync on a new signal depends on the loop bandwidth of each PLL and the individual probability that each PLL will lose latch or sync with the provided signal. The cleaning PLL produces an output frequency that closely matches the input reference frequency, and during operation you will not normally lose latch. As a result, the longer stabilization time associated with the narrow loop bandwidth of the cleaning PLL does not contribute significantly to the total stabilization time equation. The PLL

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-8primary, which normally does not interrupt signal latch or sync when making large frequency adjustments, reduces stabilization time by making an arbitrarily large loop bandwidth.

The stabilization time of the present invention is greatly improved using two PLL circuits. Conventional DDS-excited PLL synthesizer designs, which typically use only one PLL, are constrained by mutually exclusive design requirements for closed filter and fast frequency stabilization time. In the present embodiment, a cleaning PLL separates the enclosed filtering function from the requirement of a fast frequency stabilization time, and thus adds an additional degree of freedom to the stabilization equation of a frequency synthesizer. The primary PLL of the present embodiment is no longer required to perform an enclosed filtering and can instead be designed to have an arbitrarily fast frequency stabilization time.

The present modality can also be used to imply the design requirements of reference digital frequency synthesizers. A typical digital frequency synthesizer comprises a direct digital synthesizer (DDS) coupled with a digital to analog converter (DAC) element. The present modality will also work with a frequency synthesizer that does not use a DAC. Instead of using the DAC output, the most significant bit (MSB) of the DDS accumulator is supplied directly to the cleaning PLL. The filtering qualities of the cleaning PLL eliminate the harmonic stray leads present in the DDS MSB signal and produce a sinusoidal signal. The resulting sinusoidal signal can be easily used by the primary PLL for additional signal processing.

An alternative embodiment uses a switching apparatus to minimize any settling time that can be contributed by the cleaning PLL of the present invention. This mode uses a power divider means to create a first duplicate and a second duplicate of the digitally generated periodic signal. The first duplicated periodic signal is supplied to the cleaning PLL and a subsequent switching means, to selectively pass the signal through a power adding means and into the primary PLL circuit. This switching means responds to a control signal produced by a switching control circuit.

The second duplicated periodic signal is

97MX

-1010 directly supplies a switching medium capable of selectively passing the signal through an adder medium and into the primary PLL circuit. This switching means also responds to a control signal produced by a switching control circuit.

This switching mode bypasses the cleaning PLL while stabilizing on the new frequency. This reduces the total stabilization time by eliminating the delay in stabilization time that the cleaning PLL can contribute to. When a frequency change occurs, the switch control produces control signals that open the switch associated with the cleanup PLL and close the switch associated with the second duplicate periodic signal. Once the cleaning PLL has stabilized at the new frequency, the switch associated with the cleaning PLL closes, and then the switch associated with the second duplicated periodic signal opens.

The preferred embodiments of the present invention provide several advantages over the prior art. The stabilization time can be improved by using one PLL as a clean or debug filter for the DDS reference signal and a second PLL as the frequency multiplier. A cleaning PLL eliminates parasitic shunts from DDS while in shape

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-11continuous tracks the output of the continuous phase DDS. Maintaining the frequency and phase lock between the cleaning PLL and the DDS output minimizes the settling time of this loop. Meanwhile, a second PLL operates or functions as a frequency multiplier. Increasing the loop bandwidth in the second PLL allows for wide frequency bandwidth output along with a fast frequency switching characteristic.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, objectives and advantages of the present invention will be more readily apparent from the detailed description set forth below when taken in conjunction with the drawings in which reference numbers are used consistently throughout the text and, where :

Figure 1 illustrates a phase locked loop frequency synthesizer (PLL) excited by a prior art direct digital synthesizer (DDS);

Figure 2 illustrates an embodiment of the present invention for a DDS-excited frequency synthesizer (PLL) with a cleaning PLL;

Figure 3 illustrates a first alternative embodiment of the DDS-excited PLL herein.

one. II invention; and

Figure 4 illustrates a second alternative embodiment of the DDS-excited PLL of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES

The preferred embodiment of the present invention provides many advantages over the frequency synthesizers of the prior art. Figure 1 illustrates, in block diagram, a phase locked loop frequency synthesizer (PLL) 100 excited by conventional digital direct synthesizer (DDS).

Synthesizer 100 typically comprises a frequency synthesizer 101 and a latch loop circuit used in combination to provide a desired synthesized output frequency.

The frequency synthesizer

101 is normally comprised of

DDS

102, Digital to Analog Converter (DAC)

108, of the filter 110 optionally, of a frequency divider 112.

In the embodiment illustrated in Figure 1, DDS 102 is comprised of a phase accumulator 104 and a sine lookup table 10 6. It should be noted that DAC 108 is external to DDS 102, but that an alternative design (not illustrated ) could include the DAC inside the device

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: .ji

DDS.

During operation, the DDS 102 of Figure 1 receives a fine frequency control signal 113 that determines the phase increment for accumulation in phase accumulator 104. The accumulated phase value is output to the lookup table. sine 106, typically a read-only memory that stores sine values, at the provided DDS rate or clock speed. Sine Lookup Table 106 provides an output signal, also at the DDS rate or clock rate, to an external digital to analog converter (DAC) 108. The output signal, produced by Sine Lookup Table 106 , is a digital representation of a periodic waveform. DAC 108 converts the digital representation of the periodic waveform to an output reference signal that is an analog amplitude value representation of the periodic waveform. Finally, the fine frequency control signal 113 alters the reference frequency signal generated by DDS 102.

The PLL 114 is comprised of a phase detector 116, a loop filter 118, a voltage controlled oscillator (VCO) 120, and a loop splitter 122. The output of the phase detector 116 is coupled to an input of the loop filter 118, normally constructed as an operational amplifier filter. The output of the loop filter 118 fl45O / 97MX

-14L. J .1.

It is coupled to the control input of a VCO 12 0. The output of VCO 120 is provided as the phase locked loop output signal and is also fed back to an input of the loop splitter 122. The output of the loop splitter 12 2 is coupled to the other input of phase detector 116.

Phase detector 116 serves as a comparator means for comparing the reference signal provided by the DDS circuitry with the split-loop output signal. Phase detector 116 responds to a difference in the frequency of the DDS circuit reference signal and the split-loop output signal to generate a frequency tuning control signal, the voltage level of which is proportional to the difference frequency of the compared signals.

Loop filter 118 serves as a filter for the tuning control signal. Loop filter 118 receives and filters the frequency tuning control signal and provides a VCO control signal. The VCO control signal is provided to the VCO 120 voltage control input.

The VCO 12 0 serves as a frequency generating means to generate the loop output signal in response to the VCO control signal. Specifically, the VCO 120 alters the frequency of the loop out signal

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-15LJ I in response to a change in the input VCO control signal voltage level. The VCO 12 0 can be a high quality voltage controlled oscillator (VCO), such as for example a voltage controlled crystal oscillator (VCXO) as needed according to additional spectral purity requirements. The VCO control signal is provided to the VCO 120 voltage control input.

Loop splitter 122 is coupled to the output of VCO 120 to receive the loop output signal. Loop splitter 122 serves as a loop splitter means that receives the loop output signal and generates a split loop signal that corresponds in frequency to the loop output signal divided by N. The loop signal is supplied to the another input of the phase detector 116 and has a frequency at or near the input value. Loop divider 122 responds to a coarse frequency control signal 126 to adjust the integer divisor value by which the frequency of the loop output signal is divided, to feed back to the phase detector 116. By changing the N value of the Loop divider 122 effectively increases the difference in frequency difference perceived by phase detector 116 and causes a frequency change in final output frequency 124. The resulting output signal 124t? 145ü / 97MX

-1616 from the VCO 120 on the PLL 114 is a spectrally pure reference signal of gradually increased frequency in proportion to the N value of the loop splitter.

A conventional synthesizer design, as illustrated in Figure 1, that utilizes a single PLL 114 must balance settling time with spectral purity to produce the desired output signal 124. Both the stabilization time, the time for a PLL not to change frequencies as well as the spectral purity of the signal depend on the value of the loop bandwidth of the PLL 114. By increasing the loop bandwidth of PLL 114, for example, the PLL, and consequently the synthesizer as a whole, is allowed to stabilize at a new frequency for a proportionally shorter time interval. The stabilization time in a PLL is inversely proportional to the bandwidth of the loop. Therefore, a proportionally greater loop bandwidth results in a proportionally faster stabilization time.

Obtaining an output signal 124 from synthesizer 100 with high spectral purity, however, requires a PLL with a relatively smaller loop bandwidth. DDS 102 normally produces parasitic frequency shunts enclosed in the

ΕΊ450 / 97ΜΧ

-17LL 1 i generated reference frequency. These parasitic leads, in turn, increase in proportion to the size of the PLL 114 loop splitter and are filtered based on the relative size of the PLL loop bandwidth. A narrower loop bandwidth will reduce stray shunts based on low-pass filtering characteristics, around the reference frequency of PLL 114. However, if the loop bandwidth of the PLL 114 is reduced to eliminate the enclosed parasitic leads generated by DDS 102, the frequency stabilization time will be increased. Although the PLL having a wide loop bandwidth will clean up a noisy VCO, such as VCO 120, it must be narrow to clean up the noise produced by DDS 102.

The preferred embodiment, as illustrated in Figure 2, meets the needs of these two conflicting variables, spectral purity and stabilization time, by using two separate PLLs. A first cleaning PLL 214 or PLL is designed to clean or filter the input variable reference signal generated by the frequency synthesizer 202. The cleaning PLL 214 is designed with a narrow loop bandwidth and a loop splitter value. little. As previously mentioned, a PLL designed with a bandwidth of

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-1818 narrow loop produces a signal that has high spectral purity by reducing the enclosed parasitic leads generated, in this case, by DDS 204 located in frequency synthesizer 202. A second PLL, such as for example primary PLL 220, Having a large loop splitter and a large loop bandwidth, it can then be used to gradually increase the reference frequency with a rapid stabilization time interval. This design, unlike the prior art, does not require one to sacrifice stabilization time at the expense of spectral purity or vice versa. In the preferred embodiment, the stabilization time and the spectral purity are substantially separate parameters that can be specified independently by the designer of the synthesizer.

Figure 2 illustrates an exemplary embodiment of a PLL 200 frequency synthesizer excited by DDS. Synthesizer 200 comprises a digital frequency synthesizer 202, a first cleaning PLL 214 or PLL 214, and a second primary PLL 220 or PLL 220. Additional filters well known in the art may be added as required by the particular design.

The digital frequency synthesizer 202 is comprised of a direct digital synthesizer (DDS) 204, a digital to analog converter (DAC) 206, a filter 208

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-1919 and an optional 210 divider. Digital synthesizer 202 serves as a variable reference source means for generating a selected reference frequency signal from a plurality of reference frequency signals, each at a different frequency.

DDS 204 provides an output signal indicative of the digital representation of a periodic waveform. The components and operation of DDS 204 are similar to DDS 102 in Figure 1. DDS 204 responds to a fine frequency control signal 212 capable of altering the frequency of the output reference signal. The DDS 204 further responds to a direct digital synthesizer (DDS) clock signal with which its internal digital hardware is excited. The direct digital synthesizer is well known in the art.

DAC 206, coupled with DDS 204, converts the digital representation of the periodic waveform output by DDS 204 to an analog representation of the waveform. The digital-to-analog conversion performed by DAC 206 substantially reduces the quantization errors present in the DDS 204 output signal.

Filter 2 08, coupled to DAC 206, normally reduces the bandwidth noise present in the DAC 206 output signal. The noise removed by the filter

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-20208 is normally external to the bandwidth of the subsequent first PLL 214 or second PLL 220. Optionally, the output of filter 208 is supplied to a reference frequency divider 210 having a divisor value M. The resulting frequency of periodic output and the noise surrounding the signal, if processed by the optional frequency divider 210, is reduced in proportion to a predetermined integer value M.

The output reference signal provided by the synthesizer 2 02, either the filter 208 or the optional frequency divider 210, is supplied to the input of the cleaning PLL 214. Unlike the PLL 114 in Figure 1, the primary function Cleaning PLL 214 serves as a low-pass filter that can trace to a range of continuous phase input frequencies, such as those generated by frequency synthesizer 202. Given a continuous phase variable frequency input signal, the Cleaning PLL 214 provides a spectrally pure output frequency, while maintaining phase and frequency lock. In an exemplary embodiment, cleaning PLL 214 performs a substantially small frequency multiplication.

The components and operation of PLL 214 are similar to those of PLL 114 in Figure 1 with two exceptions: The PLL loop splitter value and the PLL loop bandwidth. The value of the loop divider, indicated by the N value in PLL 114 of Figure 1, Cleaning PLL 214 is intentionally set to a small value substantially close to unity, because the frequency multiplication function is primarily performed by a primary PLL 220. The loop divider value of the cleaning PLL 214 is adjusted in response to a first frequency control signal 216. In an exemplary embodiment, the output of the cleaning PLL 214 produces a spectrally pure reference signal at a frequency substantially close to your input frequency.

Cleaning PLL 214 is typically designed with a small or narrow loop bandwidth. The size of the loop bandwidth is selected small enough, in order to filter out substantially all the noise enclosed around the carrier frequency created by the frequency signal synthesizer 202 or, more specifically, by the DDS 204, in comparison , the cleanup PLL has a significantly smaller loop bandwidth than the PLL of a conventional synthesizer, such as for example PLL 114 found in synthesizer 100 of Figure 1. The difference in bandwidth explains the increase in spectral purity available in synthesizers that

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-22 use a cleaning PLL. The only PLL used in conventional synthesizers, such as PLL 114 in Figure 1, typically do not have an arbitrarily small loop bandwidth, because they would suffer an arbitrarily large increase in stabilization time.

The output signal from the cleaning PLL 214 can be coupled through an additional filter 218 before being fed to the primary PLL 220. Filter 218 serves as a means of further increasing the spectral purity of the increased reference signal emitted by the PLL 214. An exemplary filter 218 can be either a low-pass filter (LPF) or a band-pass filter (BPF), as is well known in the art.

Filter output 218 is coupled to a second PLL or primary PLL 22 0. Generally, PLL 22 0 is used as a frequency tuning means to generate a loop output signal that has a periodic frequency that is a multiple integer the frequency of the input reference signal. In this particular embodiment, the primary PLL 220 increases or multiplies a signal that has a frequency generated by DDS 202 and the enclosed spectral purity provided by cleaning PLL 214.

The components of the PLL 22 0 are similar to the j .i components of the cleaning PLL 214 with two exceptions. Primary PLL 220 has a much larger loop splitter and much larger loop bandwidth than Cleaning PLL 216.

The range of values ​​of the loop splitter in the primary PLL 220 differs from the range of values ​​of the loop splitter in the cleaning PLL 214. In the cleaning PLL 214, the value of the loop splitter is set close to unity for it creates a narrow loop bandwidth and produces an output signal with high spectral purity. Cleaning PLL 214 is primarily used as a filter medium and not as a frequency multiplication medium. The primary PLL 220 requires, however, a loop divider value that is much larger than unity in order to increase the input frequency to the desired higher output frequency. The primary PLL in the preferred embodiment is primarily used as a frequency multiplication medium and not as a filter medium.

In the preferred embodiment, higher frequency multiplication can be achieved by adjusting to a larger primary PLL loop splitter value. Generally, a PLL will increase noise as well as increase frequency in proportion to the value of the loop divider. This factor could limit the multiplication of

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-24; .l II the frequency of the signal (ie the size of the loop splitter value) in a conventional synthesizer, because the amount of noise in the system can reach intolerable levels. However, in the preferred embodiment, a large loop splitter will not greatly increase noise because the cleaning PLL provides a reference signal that is spectrally pure.

The loop bandwidth of PLL 220 can be adjusted arbitrarily large because sufficient enclosed noise is reduced by cleaning PLL 216. Primary PLL 222 is designed to effect frequency multiplication and relies on cleaning PLL 214 to increase the spectral purity of the input signal. Generally, a PLL that has a large loop bandwidth will have a much faster stabilization time (i.e., the time it takes for the PLL to lock in at a new frequency) than a similar PLL that has a loop bandwidth Smaller, such as for example cleaning PLL 214 or primary PLL 114 in Figure 1. Specifically, the primary PLL of the present invention utilizes the substantially larger loop bandwidth which provides substantially faster stabilization times than a similar primary PLL, such as for example the PLL 114 used? 1 45Ü / 97MX

-2525 on synthesizer 100 of Figure 1, which has a smaller loop bandwidth. As a result, the present invention will have a faster total stabilization time than the conventional frequency synthesizer.

During operation, DDS produces digitized periodic waveforms, typically sine waves of a given frequency, accumulating phase values ​​at a rate or velocity higher than the frequency of the sine wave. The accumulated phase is transformed into a periodic waveform using a lookup table. The resulting digital representation of the periodic waveform is transformed into an analog form using a digital-to-analog converter.

The parasitic performance of the preferred embodiment of the present invention is easily analyzed. The DDS output includes stray signals normally caused by phase truncation of the output waveform, quantization of waveform amplitude, non-linearities of the DAC output and the like attributable to the sampling process. The phase noise in the DDS is governed by the characteristics of the phase noise of the DDS clock signal, as well as the performance or noise behavior of the digital circuitry comprising the DDS.

Cleaning PLL 214 filters shunts

-2626 frequency parasites enclosed in the signal generated by DDS 202. By designing cleaning PLL 214 with a very narrow loop bandwidth, the typical harmonic family of parasitic leads is drastically reduced and a spectrally pure signal frequency is generated by cleaning PLL 14. For further details and examples on the effect of PLL loop bandwidth that reduces parasitic shunts of a DDS reference signal, see United States Patent No. 4,965,533 referred to above.

A cleaning PLL will remain hooked or synchronized and will require little stabilization time if the reference frequency signal generated by DDS 202 does not vary beyond Afp_OR of the time delay for the acquisition of the phase when the coupling or synchronization of frequency and phase are maintained. The addition of a cleaning PLL 214 that remains hooked or synchronized does not contribute substantially to the overall stabilization time of the synthesizer and will add, as will be appreciated, a further degree of flexibility to the stabilization time equation. The following relationship describes the maximum change in frequency of a PLL comprising either a digital phase or frequency detector, such as for example the phase detector 116 in Figure 1, can admit before disengagement or? 145C / 9MX

-27 sync desynchronization or frequency lock:

A / po - 1,8 (2τι) (δ + 1) /_η (1) where:

Δ / ρο ^{is the} disengagement or desynchronization frequency, δ is the loop damping factor; and f_n is the natural frequency of the PLL.

Even though the reference frequency varies more than Δ /_ρο, the total stabilization time of the synthesizer 200 is improved by using a cleaning PLL 214 together with the primary PLL 220. The cleaning PLL 214 has a small value of the loop divider and thus the output frequency range of the PLL 214 is roughly equal to the output bandwidth of DDS 204. Also, Cleaning PLL 214 has a very small loop bandwidth. Typically, a small loop bandwidth corresponds to a long frequency stabilization time. However, in cleaning PLL 214, because the frequency changes are limited, the corresponding times to stabilize, if there are any, are still small. Therefore, even if the cleanup PLL 214 cuts or interrupts synchronization or latch and must re-acquire the signal, the time delay attributed to phase and frequency acquisition is still small.

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I

In comparison, when the synthesizer 100, shown in Figure 1, must interrupt synchronization and reacquire the reference signal produced by DDS 102, the total frequency delay time will continue to be significantly longer. Given the same narrow loop bandwidth as that of PLL 214 in Figure 2, PLL 114 in Figure 1 uses a much larger loop splitter to produce a wider order of magnitude of the frequency range. When the PLL 114 changes frequencies, the stabilization time cannot be improved by increasing the loop bandwidth unless the designer is willing to sacrifice spectral purity. Therefore, the stabilization time for a PLL to make large frequency changes requires more time than the stabilization time for a PLL to make small frequency changes when the loop bandwidth remains constant.

The preferred embodiment exemplified in the 2 00 synthesizer of Figure 2 decreases the time of

<td>stabilization in</td><td>the</td><td>PLL</td><td>primary</td><td> 220</td><td>inc rement ando</td><td>the</td>

<td>bandwidth</td><td>of the</td><td colspan="2">loop according</td><td>be</td><td>necessary.</td><td>In</td>

<td>straight away when</td><td>the</td><td>PLL</td><td>primary</td><td> 220</td><td>interrupts</td><td>the</td>

<td>synchrony, the great</td><td colspan="2">width</td><td>band</td><td>of the</td><td>improvement loop</td><td>in</td>

stabilization time noticeably and justifies

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-29 any complexity or added costs involved when adding a cleaning PLL 214. The increase in stabilization time reached in primary PLL 220 far outweighs any stabilization time lost even when cleaning PLL 214 may interrupt the timing or hitch.

By using Cleaning PLL 214 to produce a signal with high spectral purity, a degree of freedom is added to the stabilization time equation. Primary PLL 220 can have a relatively large loop bandwidth compared to conventional primary PLL devices, because the stray shunts of the input reference signal have been greatly reduced by the cleaning PLL. The large loop bandwidth used in combination by a large loop splitter in a primary PLL 220, allows the frequency synthesizer 200 to rapidly synchronize or latch on a wide range of frequencies. The added degree of flexibility in the stabilization time equation provides a means for an improved synthesizer design that was not previously available.

In practice, a conventional DDS-excited PLL synthesizer design will compromise stabilization time in exchange for superior spectral purity.

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L. JJ

Therefore, a brief comparison between the stabilization times of the conventional synthesizer with the preferred modality will clarify the overall benefit. For example, consider the conventional DDS-excited PLL 100 synthesizer of Figure 1, where the DDS portion produces a reference frequency of one MHz, the loop splitter of the primary PLL 114 equals 1000, and Δ / ρ_Ο = 25 kHz. The normal stabilization time, primarily attributed to the primary PLL for this synthesizer will be approximately 5 msec for a 25 MHz jump.

In the preferred modality, the cleaning PLL "

214 of Figure 2, has a narrow loop bandwidth at least as narrow as that of the primary PLL 114 of Figure 1. In addition, the primary PLL 220 of Figure 2 has a significantly larger loop bandwidth than the primary PLL 114 of Figure 1. Consider the case of the PLL 200 frequency synthesizer excited by DDS, where the DDS portion produces a reference frequency of one MHz, the loop splitter of the cleaning PLL is unity, the loop splitter of the primary PLL equals 1000 and the Δ / p_OR= 25 kHz for both PLLs. In this case, the stabilization time for this synthesizer is only approximately 2 msec, for a 25 MHz jump or hop. The largest loop bandwidth of the primary PLL 220 in the modality

ΕΊ4 5Ο / 37ΜΧ

-3131 preferred, significantly improves frequency stabilization time over conventional synthesizers that have a primary PLL with a smaller loop bandwidth. As previously mentioned, the cleanup PLL would contribute to a small delay in the total stabilization time even if the size of the frequency step exceeds Δ / ρ_Ο and the cleaning PLL interrupts synchronization or hooking.

A DDS-excited PLL frequency synthesizer that has an additional cleaning PLL can be configured in several ways to take advantage of the added degree of flexibility in the stabilization time equation. In the first exemplary embodiment of the embodiment, the loop splitter of the primary PLL is set to a predetermined value in response to a second frequency control signal 222. Cleaning PLL 214, as shown in Figure 2, has a loop splitter value, adjusted by the first frequency control 216, equal to 1 and a substantially small loop bandwidth. In the alternative, the cleaning PLL need not include a loop splitter and the output of its coupled VCO directly returned to an input of its phase detector. The primary PLL 220 of Figure 2 coupled to the cleaning PLL 214 may have a large loop splitter, adjusted opposite the second? 14 5 0 / 9'7MX

-32I I frequency 222 control, fixed on

1000 and a much larger loop bandwidth than the cleaning PLL

214. A reference frequency of 1 MHz provided by the DDS

Responding to fine frequency control 212, 202 can be adjusted upward downward by 25 kHz around the frequency of

The resulting synthesizer will have high spectral purity, due in this case to the narrow loop bandwidth of the PLL 214 and the unit loop splitter, as well as fast frequency switching times due to the large bandwidth of loop of the primary PLL 224. However, the output frequency range, obtained by multiplying the input reference frequency by the loop splitter of the primary PLL, shall be set to 50 MHz.

A second configuration of the invention improves the frequency range by varying, rather than setting, the value of the loop divider in the primary PLL 220. As before, the cleaning PLL 214 has a loop divider value substantially equal to 1 and a relatively small loop bandwidth. The corresponding primary PLL 224 also has a large loop bandwidth, but now includes a variable loop splitter. For example, frequency control 222 can be used to vary the PLL loop splitter

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-33 primary from 100 to 200. A 5 MHz reference frequency provided by DDS 202 responds to the fine frequency control 212 used to adjust 25 kHz up or down around the reference frequency. As previously mentioned, the resulting synthesizer will have high spectral purity, due to the narrow loop bandwidth and unit loop divider of the PLL 214, as well as fast frequency switching times, due to the large bandwidth of loop of the primary PLL 224. However, this mode will now operate over a wider frequency range, dictated by dynamically adjusting the primary loop splitter. The output frequency varies from 500 MHz to 1 GHz and will have an average stabilization time of approximately 2 msec.

The variable loop splitter configuration can also have an output signal with fine frequency resolution capabilities. The primary loop splitter is used as a coarse frequency control, while the DDS frequency control is used among all selected frequencies. Generally, the resolution of the output frequency is proportional to the frequency resolution of the DDS by the current loop divider value. A typical DDS that has a 32-bit accumulator will produce an output frequency that has a

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lL j I resolution of 0.93 Hz when the PLL loop splitter is primarily 200. Lower values ​​of the loop splitter will allow even finer frequency resolution adjustments. When the PLL loop splitter is set to 100, the frequency resolution is increased to 0.465 Hz.

Figure 3 illustrates in block diagram form an alternate embodiment of the present invention that utilizes a cleaning PLL 318 to avoid the need for various components. In Figure 3, synthesizer 300 includes a frequency synthesizer 302, a cleaning PLL 318, and a primary PLL 324.

In this embodiment, the synthesizer 302 comprises a DDS 304, a filter 314, and an optional divider 316. Of particular interest is that the DDS 304 may only require phase accumulator 306 to operate or operate if a cleaning PLL is also used. A sine lookup table, such as sine lookup table 106 in Figure 1, and a digital-to-analog converter (DAC), such as DAC 108 in Figure 1, are not required in this instrumentation. Phase accumulator 306 receives a fine digital frequency control signal that determines the phase increment for accumulation at the DDS rate or clock rate. The most significant bit (MSB) or the excess or excess bit 310 passes through filter 314 and the

Η145Ο / 97ΜΧ

-3535 optional 316 splitter media before supplied to cleaning PLL 318.

MSB 310 is coupled, through either filter 314 or an optional divider 316, to a cleaning PLL 318 that has components and operation similar to cleaning PLL 214 in the Figure. The input signal generated by the MSB 310 clearly indicates when the amplitude of the synthesized periodic signal has changed in inflection despite possible distortion in the actual sine wave. The phase detector on PLL 318 responds to changes on MSB 310. Effectively, the cleaning PLL 318 receives the input signal generated by the MSB 310 and perceives a square wave ”or truncated sine. The phase errors that may be present are inherently corrected by the narrow bandwidth of the cleaning PLL 318. The resulting output signal from the cleaning PLL 318 appears to be a sine wave.

The output of the cleaning PLL 318 is coupled to a primary PLL 324 and a filter 322 may be located between them. The primary PLL 324 is used as a frequency tuning means to generate a loop output signal having a periodic frequency. which is an integer multiple of the frequency of the input reference signal. Components and operation

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-36; .ιι of the primary PLL 324 are similar to those of the primary PLL 214 illustrated in Figure 2.

Cleaning PLL 318 effectively produces what appears to be a sine wave signal using only MSB 310. The sine wave produced by Cleaning PLL 318 is sufficient to drive the phase detector on primary PLL 324. Therefore, this mode avoids the need for a sine lookup table, such as for example the sine lookup table 106 of Figure 1 and the digital-to-analog converter, such as for example the digital-to-analog converter 108 of Figure 1. Using a reference signal

<td>generated</td><td>by</td><td>the MSB</td><td colspan="3">306 in combination</td><td>with the PLL</td><td>of</td>

<td>cleaning</td><td> 318</td><td>has the</td><td>advantage</td><td>of</td><td>costs</td><td>lower and</td><td>a</td>

<td>reduced</td><td colspan="2">complexity.</td><td></td><td></td><td></td><td></td><td></td>

<td></td><td>The</td><td>Figure 4</td><td>illustrates</td><td>in</td><td>shape</td><td>diagram</td><td>of</td>

<td>blocks i</td><td>Dtra</td><td>modality</td><td>alternates,</td><td>in</td><td colspan="2">where a synthesizer</td><td>of</td>

DDS driven PLL frequency with a cleaning PLL used in combination with a switching apparatus can be used to further improve the total stabilization time when switching frequencies. In Figure 4, the frequency synthesizer 400 includes a DDS 402, a digital-to-analog converter (DAC) 404, a filter medium 406, a power divider 408, a cleaning PLL filter 410, a switch SW1 414, a

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-3737 switch SW2 412, a switch control means 416, an adder 418 and a primary PLL 420.

Direct Digital Synthesizer (DDS) 402 serves as a variable reference source means for generating a reference frequency signal from the plurality of reference frequency signals. The operation or operation and components of DDS 402 are similar to those of DDS 2 04 as illustrated in Figure 2. The output of DDS 402 is coupled to DAC 404 whose operation is similar to DAC 206 also in Figure 2. .

The spectral purity of the signal produced by DDS 402 can optionally be improved by using filter 406. The output of DAC 404 is coupled to filter 406 to reduce broadband noise and also to improve signal quality when the PLL is off. Cleaning 410 may not be hooked or synchronized.

The output of DAC 404 or, optionally, filter 406 is coupled to the input of a power splitter 408 that distributes the signal into two separate branches. The output of the first branch of divider means 408 is coupled to a cleaning PLL 410. The operation and components of cleaning PLL 410 are similar to cleaning PLL 214 as illustrated in Figure 2. A switch 414 responds to a control means

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-3838 switch 416 and receive the output of cleaning PLL 410. The resulting output of switch 414 is coupled to an input of adder 418.

The output of the second branch of the dividing means 408 is coupled to the switch 412. The output of the switch SW2 412 is then also coupled to a second input of the adder 418. The output of the adder 418 is then supplied to the primary PLL 420.

This embodiment describes a switching technique to further reduce the settling time of the present invention when frequencies are switched. Before the frequency switching, the switching control means 416 will close switch 412 and open 414. After the frequency is changed, the switching control means 416 will delay a predetermined time necessary for the cleaning PLL 410 hook or sync on the new frequency. Once the cleaning PLL 410 has stabilized at the new frequency, the switching control means will close switch 414 and then open switch 412. Preferably, between switches SW1 414 and SW2 412 a technique of setting before is used. interrupt to minimize switching noise and signal discontinuities.

Mainly, this switching technique

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-3939 reduces any settling time that may be entered by the cleaning PLL by referring to PLL 410.

In this mode, the total frequency switching time will be limited only to the stabilization time of the primary PLL 420. It should be noted that while switch 414 remains open and switch 412 remains closed, stray signals may be output from adder 418 and to the PLL Primary 42 0. Typically, the stray signals to be transmitted are confined to the loop bandwidth of the primary PLL 420 and are of minimal duration.

The previous description of preferred embodiments are provided to enable any person skilled in the art to make or use the present invention. The various modifications to these modalities will be readily apparent to those skilled in the art, and the generic principles defined herein other modalities can be applied without the use of inventive step.

Thus, the present invention is not intended to be limited to the modalities shown herein, but will be in accordance with the widest scope consistent with the novel principles and features disclosed herein.

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-40J.i.