Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals.
Abstract
The present invention provides an apparatus for transmitting broadcast signals, the apparatus includes an encoder for encoding service data, a frame former for forming at least one signal frame when mapping the coded service data, a modulator for modulating data in the formation of at least one signal frame by an Orthogonal Frequency Division Multiplexing scheme, OFDM, and a transmitter to transmit the broadcast signals having the modulated data.

Term
7.9 yearsleft in the term
Expires 1 August 2034.
- Priority
- Filed
- Granted
- Today
- Expires
6 claims: 2 independent, 4 dependent
- 1REIVINDICACIONES 1. Un aparato para transmitir señales de difusión, el aparato que incluye:un codificador para codificar datos de 5 servicio de acuerdo a una palabra de código de 16200 bits y una tasa de codificación de 7/15 con base en direcciones en una matriz de comprobación de paridad;un formador de trama para formar al menos una trama de señal al inapear los datos de servicio codificados;un intercalador de frecuencia para datos 10 de intercalación de frecuencia en símbolos en la formación de al menos una trama de señal;un modulador para modular los datos intercalados de frecuencia en la formación de al menos una trama de señal por un esquema de Multiplexión de División por Frecuencia Ortogonal, OFDM;y un transmisor para transmitir 15 las señales de difusión que tienen los datos modulados, en donde la matriz de comprobación de paridad es: 553 742901 1327 1544217925193131 32803603378937924253534059345962 600466987793 8001 8058 812682768559 503 5905981185 1266 1336 18062473 3021 33563490368039364501 4659 5891 6132 6340 6602 7447 8007 8045 8059 8249 795 831 947 1330 1502 2041 2328 2513 2814 2829 4048 4802 6044 6109 6461 6777 6800 7099 7126 8095 8428 8519 8556 8610 601787 899 1757 2259 25182783 2816 2823 2949 339643304494 4684 4700 4837 48814975 5130 5464 6554 6912 7094 8297 4229 56287917 7992 150633744174 5547 4275 56508208 8533 1504 1747 3433 6345 3659 6955 7575 7852 607 3002 4913 6453 3533 6860 7895 8048 4094 63668314 2206 4513 5411 32 3882 5149 389 3121 4626 130844196520 2092 2373 6849 1815 3679 7152 3582 39796948 1049 2135 3754 22764442 6591 en donde cada fila corresponde a cada grupo de 360 127 bits d,e información, y en donde cada valor correspondiente a cada fila representa una dirección de un bit de paridad.
- 2El aparato de conformidad con la reivindicación 1, en donde el intercalador de frecuencia intercala los datos con un valor germinal de intercalado diferente para cada par de símbolos.
- 3El aparato de conformidad con la reivindicación 1, en donde la palabra de código tiene bits de información y bits de paridad, en donde los bits de paridad se calculan utilizando los bits de información basándose en las direcciones de la matriz de comprobación de paridad.
- 4Un aparato para recibir señales de difusión, el aparato que incluye:un receptor para recibir las señales de difusión;un desmodulador para desmodular las señales de difusión recibidas por un esquema de Multiplexión de División por Frecuencia Ortogonal, OFDM;un desintercalador de frecuencia para datos de desintercalado de frecuencia en símbolos en las señales de difusión desmoduladas;un analizador de trama para analizar al menos una trama de señal que incluye los datos desintercalados de frecuencia;y un descodificador para descodificar datos en la al menos una trama de señal analizada para producir datos de servicio de acuerdo con una 128 palabra de código de 16200 bits y una tasa de codificación de 7/15 con base en direcciones en una matriz de comprobación de paridad, en donde la matriz de comprobación de paridad es: 553 742 901 1327 1544 21792519 3131 3280 3603 3789 3792 4253 5340 5934 5962 6004 6698 7793 8001 8058 8126 8276 8559 503 590 598 1185 12661336 1806 2473 3021 3356 3490 3680 3936 4501 4659 5891 6132 6340 6602 7447 8007 8045 8059 8249 795 831 947 1330 15022041 23282513 2814 2829 40484802604461096461 6777 6800 70997126 80958428 8519 8556 8610 601 787 899 1757 2259 2518 2783 2816 2823 2949 33964330 4494 4684 4700 4837 4881 4975 5139 5464 6554 6912 7094 8297 4229 56287917 7992 1506 3374 4174 5547 4275 56508208 8533 1504 1747 3433 6345 3659 69557575 7852 607 300249136453 3533 68607895 8048 409463668314 220645135411 32 3882 5149 3893121 4626 130844196520 209223736849 181536797152 358239796948 10492135 3754 227644426591 en donde cada fila corresponde a cada grupo de 3 60
- 55 bits de información, y en donde cada valor correspondiente a cada fila representa una dirección de un bit de paridad. 5. El aparato de conformidad con la reivindicación 4, en donde el desintercalador de frecuencia desintercala los 10 datos con un valor germinal de desintercalado diferente para cada par de símbolos.
- 6El aparato de conformidad con la reivindicación 4, en donde la palabra de código tiene bits de información y 15 bits de paridad, en donde los bits de paridad se calculan utilizando los bits de información basándose en las direcciones de la matriz de comprobación de paridad. 129
Independent claims6
972 paragraphs in 6 sections, as filed
(54) Title: DEVICE FOR TRANSMITTING BROADCAST SIGNALS, DEVICE FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS.
(54) Title: APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS.
(57) Summary
The present invention provides an apparatus for transmitting broadcast signals, the apparatus includes an encoder for encoding service data, a frame former for forming at least one signal frame by mapping the encoded service data, a modulator for modulating data in the formation of at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data.
(57) Abstract
The present invention provides an apparatus of transmitting broadcast signs, the apparatus including, an encoder for encoding Service data, a frame builder for building at least one signal frame by mapping the encoded Service data, a modulator for modulating data ¡n the built at least one signal trame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signs having the modulated data.
”^^ JIíííííLuuh ^^
<img file="MX352013B_D0001.tif" />
IMPI * XI ΜΗ t 'H' ι5 · έ <! · .T. λ;
I \: »i η. Μ
PATENT TITLE No. 352013
Holder (s) í
LG ELECTRONICS INC.
D micilio:
128, Yeoui-daero, Yeongdeungpo-gu, Seoul, 150-721, REPUBLIC OF KOREA
D nomination:
APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR
CIP:
Classification:
CPC:
Inventor (s)
The reference patent
<img file="MX352013B_D0002.tif" />
nV * 6th rti ñas
NG ^^ WONG; JINWOO KIM;
Departmental and other subordinates of the Mexican Institute of Industrial Property. (DOF 12/15/1999, amended on 02/04/2000, 07/29/2004, 08/04/2004 and 09/13/2007).
temdcfonal
IB7 / 04; H04L1 / 00; H04L12 / 18;
2; IH04B7 / 0413; H04L1 / 0042;
SAfetoGHI ^ GWO
Núrqterai;
Validity: VBjtf
Date of Ve Date of Ex rite n: 6 of nm fum
In accordance with art¡cJfo% 3 from the date of filing in property l ^ tasp irrtawee ^ ly
Industrial.
CñeWlymprorrogables, counted to the rights.
Whoever signs this title is (Official Gazette of the Federation (DOF: 25/01/2006, 06/05 / 2009,06 / 01/2010, 18/06 of the Regulations of the Mexican Institute of the Prdfj redden to * * dis
199Γτβίοπη3 articles 1<sup>or</sup>, 3<sup>or</sup>, 4<sup>or</sup>, 5<sup>or</sup> fraction V part a), 16 fra
12/27/1999, amended 10/10/2002, 07/29/2004. 04 / 08® 04 and 13 Deputy Generals, Coordinator, Divisional Directors, Title the Industrial Property Law 1999, 01/26/2004, 06/16/2005, V subsection a), 4<sup>or</sup> and 12th fractions I and III> 2, 07/15/2004, 07/28/2004 and 09/07/2007); o Mexican Industrial Property (DOF of the Agreement that delegates powers to the Regional Directors, Divisional Deputy Directors, Coordinators
This document is signed with an advanced electronic signature (FIEL), based on articles 7 BIS 2 of the Industrial Property Law; 3 of its Regulations, and 1 section III, 2 section V, 26 BIS and 26 TER of the Agreement establishing the guidelines for the use of the Payment and Electronic Services Portal (PASE) of the Mexican Institute of Industrial Property, in the procedures indicated.
DIVISIONAL PATENT DIRECTOR NAHANNY CANAL REYES
Ξ
<img file="MX352013B_D0003.tif" />
Original string:
NAHANNY MARISOL CANAL REYES | 00001000000403252793 | Administration Service
Tax | 1695 || MX / 2017/90681 | MX / a / 2016/001355 | PCT patent title | 1223 | GAGV | Page (s)
2 | 9uubFz3xSp + HPFJCcn3M9rrjzJs =
Digital stamp:
crOCQtZoRTmreOQOsqRSwXRcKGKhw8DaRZE9kkeCe7UyrWZHHFk6IOSOVYXxSTx9m5eB9bj / l9ugV + d3 / 808cBkmWC
Dhb4j0lzWnTnFAsYr7wzv9OM9BJ1VYVkjiZwgQgNY9bdSPojbhlDqvyEjlnFNxkcL3EkvxbuTJItfP93oF3fjFroNy
M3G95iROQeYiL / njc + T5 + y2cJVqEOnqX9f3sFhG / VmOX2c3HrQzpOVaRA1QR38obVlrQd + í OxfB5L72frynOwXZ5XRa QkvpXsZgWODeOo9PTuoxYTMIRsf / rCAPxt7aoOo3SHHVNwPJsfSlvHs9lxxtVylkQ9FcdJOw == * Additional information on the back
Arenal No. 550. Floor 1, Pueblo Santa María Tepepan, Xochimilco, 16020, Mexico City.
(55) 53340700 www.gob.mx/impi
MX / 2017/90681 iOI6 / I3<sub>55</sub>
APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS
Technical Field
[1] The present invention relates to an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals, and methods for transmitting and receiving broadcast signals.
Background Technique
[2] As the transmission of analog broadcast signals comes to an end, various technologies are developed to transmit / receive digital broadcast signals. A digital broadcast signal can include a greater amount of video / audio data than an analog broadcast signal and also include several additional types of data in addition to the video / audio data.
[3] In other words, a digital broadcast system can provide HD (high definition) pictures, multi-channel audio, and various additional services. However, the data transmission efficiency for the transmission of large amounts of data, the robustness of the transmission / reception networks and the flexibility of the network in consideration of the mobile reception equipment need to be improved for digital broadcasting.
Description of the Invention Technical Problem
[4] An object of the present invention is to provide an apparatus and method for transmitting broadcast signals to multiplex data from a broadcast transmission / reception system that provides two or more different broadcast services in a time domain and transmits the data 10 multiplexed across the same RF signal bandwidth and an apparatus and method for receiving broadcast signals corresponding thereto.
[5] Another object of the present invention is to provide an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals and methods for transmitting and receiving broadcast signals for classifying data corresponding to component services, transmitting data corresponding to to each component as a data channel, receive and process the data.
[6] Still another object of the present invention is to provide an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals, and methods for transmitting and receiving broadcast signals to signal signaling information necessary to provide broadcast signals.
Solution to the problem
[7] To achieve the object and other advantages and in accordance with the purpose of the invention, as broadly represented and described herein, the present invention provides an apparatus for transmitting broadcast signals, the apparatus includes an encoder for encoding service data, a frame builder for forming at least one signal frame by mapping the encoded service data, a modulator for modulating data in the formation of at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM scheme, and transmitter for transmitting the broadcast signals having the modulated data.
Advantageous Effects of the Invention
[8] The present invention can process data according to service characteristics to control QoS (Quality of Service) for each service or service component, thereby providing various broadcast services.
[9] The present invention can achieve transmission flexibility by transmitting multiple broadcast services over the same RF signal bandwidth.
[10] The present invention can improve the data transmission efficiency and increase the robustness of the transmission / reception of broadcast signals using a MIMO system.
[11] According to the present invention, it is possible to provide broadcast signal transmission and reception methods and apparatus capable of receiving digital broadcast signals without error even with mobile reception equipment or in an indoor environment.
Brief Description of Drawings
[12] The accompanying drawings, which are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention . In the drawings:
[13] FIGURE 1 illustrates a structure of an apparatus for transmitting broadcast signals for future broadcast services according to the invention.
[14] FIGURE 2 illustrates input according to one invention.
[15] FIGURE 3 illustrates input according to another invention.
'[16] FIGURE 4 illustrates
<td>a</td><td colspan="2">modality of</td><td>the present</td>
<td>a</td><td>block</td><td>from</td><td>formatting</td>
<td colspan="2">modality</td><td>from</td><td>the present</td>
<td>a</td><td>block</td><td>from</td><td>formatting</td>
<td colspan="2">modality</td><td>from</td><td>the present</td>
<td>a</td><td>block</td><td>from</td><td>formatting</td>
input according to another embodiment of the present invention.
[17] FIGURE 5 illustrates a BICM block in accordance with one embodiment of the present invention.
[18] FIGURE 6 illustrates a BICM block according to another embodiment of the present invention.
[19] FIGURE 7 illustrates a framing block in accordance with one embodiment of the present invention.
[20] FIGURE 8 illustrates an OFMD generation block 10 in accordance with one embodiment of the present invention.
[21] FIGURE 9 illustrates a structure of an apparatus for receiving broadcast signals for future broadcast services in accordance with an embodiment of the present invention.
[22] FIGURE 10 illustrates a frame structure in accordance with one embodiment of the present invention.
[23] FIGURE 11 illustrates a frame signaling hierarchy structure in accordance with one embodiment of the present invention.
[24] FIGURE 12 illustrates preamble signaling data in accordance with one embodiment of the present invention.
[25] FIGURE 13 illustrates PLS1 data in accordance with one embodiment of the present invention.
[26] FIGURE 14 illustrates PLS2 data in accordance with one embodiment of the present invention.
[27] FIGURE 15 illustrates PLS2 data in accordance with another embodiment of the present invention.
[28] FIGURE 16 illustrates a logical structure of a frame in accordance with one embodiment of the present invention.
[29] FIGURE 17 illustrates PLS mapping in accordance with one embodiment of the present invention.
[30] FIGURE 18 illustrates EAC mapping in accordance with one embodiment of the present invention.
[31] FIGURE 19 illustrates FIC mapping in accordance with one embodiment of the present invention.
[32] FIGURE 20 illustrates one type of PD according to one embodiment of the present invention.
[33] FIGURE 21 illustrates PD mapping in accordance with one embodiment of the present invention.
[34] FIGURE 22 illustrates an FEO structure in accordance with one embodiment of the present invention.
[35] FIGURE 23 illustrates bit interleaving in accordance with one embodiment of the present invention.
[36] FIGURE 24 illustrates cell word demultiplexing in accordance with one embodiment of the present invention.
[37] FIGURE 25 illustrates a time slip in accordance with one embodiment of the present invention.
[38] FIGURE 2-6 shows a parity check matrix of a QC-IRA (quasi-cyclic irregular repeat accumulation) LDPC code.
[39] FIGURE 27 shows a process for encoding the QC-IRA LDPC code according to one embodiment of the present invention.
[40] FIGURE 28 illustrates a parity check matrix permutation process in accordance with one embodiment of the present invention.
[41] FIGURE 29 is a table showing addresses 10 of the parity check matrix in accordance with one embodiment of the present invention.
[42] FIGURE 30 is a table showing addresses of the parity check matrix according to another embodiment of the present invention.
[43] FIGURE 31 illustrates a method for sequentially encoding the LDPC code of QC-IRA according to one embodiment of the present invention.
[44] FIGURE 32 illustrates an LDPC decoder in accordance with one embodiment of the present invention.
[45] FIGURE 33 illustrates a frequency interleaving in accordance with one embodiment of the present invention.
[46] FIGURE 34 is a flow chart illustrating a method for transmitting broadcast signals in accordance with one embodiment of the present invention.
[47] FIGURE 35 is a flow chart illustrating a method for receiving broadcast signals in accordance with one embodiment of the present invention.
[48] FIGURE 36 illustrates the basic operation of a twisted row-column block interleaver in accordance with one embodiment of the present invention.
[49] FIGURE 37 illustrates an operation of a twisted row-column block interleaver in accordance with another embodiment of the present invention.
[50] FIGURE 38 illustrates a diagonal reading pattern of a twisted row-column block interleaver in accordance with one embodiment of the present invention.
[51] FIGURE 39 illustrates XFECBLOCK interleaves of each interleaving arrangement in accordance with one embodiment of the present invention.
[52] FIGURE 40 is a table showing addresses of the parity check matrix according to another embodiment of the present invention.
[53] FIGURE 41 is a table showing addresses of the parity check matrix according to another embodiment of the present invention.
Best way to carry out the invention
[54] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The detailed description, which will now be provided with reference to the accompanying drawings, is intended to explain exemplary embodiments of the present invention, rather than to show only embodiments that may be implemented in accordance with the present invention. The following detailed description includes specific details to provide a full understanding of the present invention.
However, it will be apparent to those skilled in the art that the present invention can be practiced without such specific details.
[55] Although most of the terms used in the present invention have been selected from the general ones widely used in the art, some terms have been arbitrarily selected by the invention and their meanings are explained in detail in the following description when need. Thus, the present invention should be understood on the basis of the intended meanings of the terms rather than their simple names or meanings.
[56] The present invention provides apparatus and methods for transmitting and receiving broadcast signals for future broadcast services. Future broadcast services according to one embodiment of the present invention include a terrestrial broadcast service, a mobile broadcast service, a UHDTV service, and so on. The present invention can process broadcast signals for future broadcast services through MIMO (Multiple Input Multiple Output) or with MIMO according to one embodiment. A non-MIMO scheme according to an embodiment 5 of the present invention may include a MISO (Multiple Input Single Output) scheme, a SISO (Single Input Single Output) scheme, etc.
[57] Although MISO or MIMO uses two antennas in the following for convenience of description, the present invention can be applied to systems that use two or more antennas.
[58] The present invention can define three physical layer (PL) profiles (base, rover and advanced profiles) each optimized to minimize the complexity of the receiver 15 while obtaining the performance required for a particular use case. Physical Layer Profiles (PHYs) are subsets of all the configurations that a corresponding receiver must implement.
[59] The three PHY profiles share most of the functional blocks but differ slightly in specific blocks and / or parameters. Additional PHY profiles may be defined in the future. For system evolution, future profiles can also be multiplexed with existing profiles on a single RF channel via a future extension frame (FEF). The details of each PHY profile are described below.
[60] 1. Base profile
[61] Base profile represents a main use case for fixed reception devices that are typically connected to a rooftop antenna. The base profile also includes portable devices that could be transported to a location but that belong to a relatively stationary reception category. Base profile usage could be extended to portable or even vehicular devices 10 by some improved implementations, but those use cases are not expected for base profile receiver operation.
[62] The target SNR reception range is approximately 10 to 20dB, which includes the 15dB SNR reception capability of the existing broadcast system (eg ATSC A / 53). Receiver complexity and power consumption is not as critical as in battery-operated portable devices, which will use the portable profile. The key system parameters for the base profile are listed in Table 1 below.
[63] Table 1
<td>LDPC codeword length</td><td>16K, 64K bit</td>
<td>Constellation size</td><td>4 ~ 10 bpcu (bits per channel usage)</td>
<td>Time de-interleaver memory size</td><td> 1 2<sup>19</sup> data cells</td>
<td>Pilot patterns</td><td>Pilot pattern for fixed reception</td>
<td>FFT size</td><td>16K, 32K dots</td>
[64] 2. Portable profile
[65] The portable profile is designed for use in portable and vehicular devices that operate on battery power. The devices can move with pedestrian or vehicle speed. The power consumption as well as the complexity of the receiver is very important for the implementation of the devices of the portable profile. The target SNR range of the portable profile is approximately 0 to 10dB, but can be configured to go below OdB when intended for deeper internal reception.
[66] In addition to low SNR capacity, flexibility for the Doppler effect caused by receptor mobility is the most important performance attribute of the wearable profile. Key system parameters for the portable profile are listed in Table 2 below.
[67] Table 2
[Table 2]
<td>LDPC codeword length</td><td>16K bits</td>
<td>Constellation size</td><td>2 ~ 8 bpcu</td>
<td>Time de-interleaver memory size</td><td> 2<sup>18</sup> data cells</td>
<td>Pilot patterns</td><td>Pilot patterns for mobile and internal reception</td>
<td>FFT size</td><td>8K, 16K dots</td>
[68] 3. Advanced Profile
[69] The Advanced Profile provides higher channel capacity at the cost of more complexity to implement. This profile requires the use of MIMO transmission and reception, and UHDTV service is an objective use case for which this profile is specifically designed. The scalability can also be used to allow a greater number of services in a given bandwidth, for example multiple SDTV or HDTV services.
[70] The target SNR range of the advanced profile is approximately 20 to 30dB. MIMO transmission may initially utilize existing elliptically polarized transmission equipment, with extension to full power cross-polarized transmission in the future. Key system parameters for Advanced Profile 25 are listed in Table 3 below.
[71] Table 3
<td>LDPC codeword length</td><td>16K, 64K bit</td>
<td>Constellation size</td><td>8 ~ 12 bpcu</td>
<td>Time de-interleaver memory size</td><td> 2<sup>19</sup> data cells</td>
<td>Pilot patterns</td><td>Pilot pattern for fixed reception</td>
<td>FFT size</td><td>16K, 32K dots</td>
[72] In this case, the base profile can be used as the profile for terrestrial broadcast service and mobile broadcast service. That is, the base profile can be used to define a concept of a profile that includes the roaming profile. Also, the advanced profile can be divided into advanced profile for a base profile with MIMO and advanced profile for a portable profile with MIMO. However, the three profiles 15 can be changed according to the designer's intention.
[73] The following terms and definitions may apply to the present invention. The following terms and definitions can be changed according to the design.
[74] auxiliary stream: sequence of cells that carry modulation data not yet defined and coding, which can be used for future extensions or as required by broadcasters or network operators
[75] base data channel: data channel carrying 25 service signaling data
[76] baseband frame (or BBFRAME): set of Abch bits that form the input into a FEC encoding process (BHC and LDPC encoding)
[77] cell: modulation value carried by an OFDM transmission carrier
[78] coded block: LDPC coded block of PLS1 data or one of the LDPC coded blocks of PLS2 data
[7 9] data channel: logical channel in the physical layer that carries service data or related metadata, which can carry one or more services or service components.
[80] data channel unit: a basic unit for allocating data cells to a DP in a frame.
[81] data symbol: OFDM symbol in a frame that is not a preamble symbol (frame signaling symbol and the frame edge symbol is included in the data symbol)
[82] DP_ID: This 8-bit field uniquely identifies a
DP within the system identified by the SYSTEM_ID
[83] dummy cell: cell carrying a pseudo-random value used to fill the remaining capacity not used for signaling PLS, DPs or auxiliary streams
[84] emergency alert channel: part of a frame
16.
carrying EAS information data
[85] frame: physical layer time interval that begins with a preamble and ends with a frame edge symbol
[86] frame repetition unit: a set of frames belonging to the same or different physical layer profile that includes an FEF, which is repeated 8 times in a • super frame
[87] fast information channel: a logical channel in a frame that carries mapping information between a service and the corresponding base DP
[88] FECBLOCK: LDPC encoded bit set of DP data
[89] FFT size: nominal FFT size used for a particular mode, equal to the active symbol period Ts expressed in cycles of the elementary period T
[90] frame signaling symbol: OFDM symbol with higher pilot density used at the beginning of a frame in certain combinations of FFT size ,. 20 protection interval and scattered pilot pattern carrying a portion of the PLS data
[91] frame edge symbol: OFDM symbol with higher pilot density used at the end of a frame in certain combinations of FFT size, 25 guard interval and scattered pilot pattern
[92] frame group: set of all frames having the same type of PHY profile in a super frame.
[93] future extension frame: physical layer time slot within the super frame that could be used 5 for future extension, starting with a preamble
[94] Future Broadcast UTB System: Proposed physical layer broadcast system, from which the input is one or more MPG-2 or IP or general TS streams and from which an RF signal is produced.
[95] input stream: A stream of data for a preamble of services provided to end users by the system.
[96] normal data symbol: data symbol excluding raster flag symbol and raster border symbol
[97] PHY profile: subset of all configurations that a corresponding receiver must implement
[98] PLS: physical layer signaling data consisting of PLS1 and PLS2
[99] PLS1: a first set of PLS data carried in the FSS symbols that have a fixed size, encoding and modulation, which carries basic information about the system as well as the necessary parameters 25 to decode the PLS2
[100] NOTE: PLS1 data remains constant for the duration of a group of frames
[101] PLS2: a second set of PLS data transmitted in the FSS symbol, carrying more detailed PLS data about the system and DPs
[102] PLS2 dynamic data: PLS2 data that can change dynamically from frame to frame
[103] PLS2 static data: PLS2 data that remains static for the duration of a group of frames
[104] preamble signaling data: signaling data carried by the preamble symbol and used to identify the basic mode of the system
[105] preamble symbol: fixed-length pilot symbol that carries basic PLS data and is located at the beginning of a frame
[106] NOTE: The preamble symbol is mainly used for fast start band to detect the system signal, its timing, frequency offset and FFT size.
[107] received for future use: not defined by this document but may be defined in the future
[108] superframe: set of repeating units of eight frames
[109] time interleaving block: (TI block) set of cells within which time interleaving is carried out, which corresponds to a use of the time interleaver memory
[110] IT group: unit on which a dynamic capacity allocation is carried out for a particular DP, made up of an integer, a number that varies dynamically from XFECBLOCK.
[111] NOTE: The IT group can be mapped directly to one frame or it can be mapped to multiple frames. It can contain one or more IT blocks.
[112] DP type 1: DP of a frame where all DPs are mapped into the frame in the form of TDM
[113] DP type 2: DP of a frame where all DPs are mapped into the frame in the form of FDM
[114] XFECBLOCK: set of Ncells cells that carry all the bits of an LDPC FECBLOCK
[115] FIGURE 1 illustrates a structure of an apparatus for transmitting broadcast signals for future broadcast services in accordance with one embodiment of the present invention.
[116] The apparatus for transmitting broadcast signals for future broadcast service in accordance with one embodiment of the present invention may include an input formatting block 1000, a BICM (bit interleaved coding and modulation) block 1010, a frame structure block 1020, an OFDM (Orthogonal Frequency Division Multiplexing) generation block 1030 and a signaling generation block 1040. A description of the operation of each module of the apparatus for transmitting broadcast signals will be provided.
[117] IP / packet stream and TS de, MPEG2 are the main input formats, other stream types are handled as General Streams. In addition to these data inputs, Management Information is entered to control the programming and allocation of the corresponding bandwidth for each input stream. One or more TS streams, IP streams and / or General Stream inputs are allowed simultaneously.
[118] The input format block 1000 may demultiplex each input stream into one or more 15 data channels, each of which is independently modulated and encoded. The data channel (DP) in the basic unit for robustness control, so it affects the quality of service (QoS). One or more services or service components can be carried by a single DP. Details of operations of the input format block 1000 will be described later.
[119] The data channel is a logical channel in the physical layer that carries service data or related metadata, which can carry one or more services or 25 service components.
[120] Also, in the data channel unit: a basic unit for allocating data cells to a DP in a frame.
[121] In BICM block 1010, parity data is added for error correction and the encoded bit streams are mapped to complex value constellation symbols.
The symbols are interleaved through a specific interleaving depth that is used for the corresponding DP. For the advanced profile, MIMO encoding is performed in the BICM block 1010 and the additional data path is added at the output for MIMO transmission. Details of operations of BICM block 1010 will be described later.
[122] The framing block 1020 may map the data cells of the incoming DPs to the OFDM symbols within a frame. After mapping, frequency interleaving is used for frequency domain diversity, especially to combat frequency-selective attenuation channels. Details of operations of the framing block 1020 will be described later.
[123] After inserting a preamble at the start of each frame, the OFDM generation block 1030 may apply conventional OFDM modulation that has a cyclic prefix as the protection interval. For antenna space diversity, a distributed MISO scheme is applied across the transmitters. In addition, a Peak to Average Power Reduction (PAPR) scheme is performed in the time domain. For flexible network planning, this proposal provides a set of various FFT sizes, protection interval lengths, and corresponding pilot patterns. Details of operations of the OFDM generation block 1030 will be described later.
[124] The Signal Generation block 1040 can create physical layer signaling information used for the operation of each functional block. This signaling information is also transmitted so that the services of interest are properly retrieved on the receiver side. Details of operations of block 1040 of Signaling Generation will be described later.
[125] FIGURES 2, 3, and 4 illustrate input format block 1000 in accordance with one embodiment of the present invention. A description will be provided for each figure.
[126] FIGURE 2 illustrates an input formatting block in accordance with one embodiment of the present invention. FIGURE 2 shows an input formatting module when the input signal is a single input stream.
[127] The input format block illustrated in
FIGURE 2 corresponds to one embodiment of the input formatting block 1000 described with reference to FIGURE 1.
[128] The input to the physical layer can be composed of one or more data streams. Each data stream is transported by a DP. The mode adaptation modules divide the incoming data stream into baseband frame (BBF) data fields. The system supports three types of input data streams. MPEG2 TS, Internet Protocol (IR) and Generic Stream (GS). The MPEG2 TS is characterized by fixed length packets (188 bits) with the first bit being a sync bit (0x47). An IP stream is made up of IP datagram packets of varying length, as outlined within the IP packet headers. The system supports IPv4 and IPv6 for the IP stream. GS can be made up of variable-length packets or constant-length packets denoted within encapsulated packet headers.
[129] (a) shows a mode adaptation block 2000 and a current adaptation 2010 for signal DP and (b) 20 shows a PLS generation block 2020 and a PLS scrambler 2030 for generating and processing LS data . A description will be given of the operation of each block.
[130] The Input Current Divider divides the input TS, IP, GS streams into multiple service or service component streams (audio, video, etc.).
The mode adaptation module 2010 is comprised of a CRC encoder, BB (baseband) Frame Division, and BB Frame Header Insertion block.
[131] The CRC Encoder provides three types of CRC encoding for error detection at the User Packet (UP) level, ie, CRC-8, CRC-16, and CRC-32. The calculated CRC bytes are appended after the UP, CRC-8 is used for the TS stream and CRC-32 for the IP stream. If the GS stream does not provide CRC encoding, the proposed CRC encoding should be applied.
[132] The BB Frame Divider maps the input to an internal logical bit format. The first bit received is defined to be the MSB. BB's Frame Divider assigns an input number equal to the available data field capacity. To allocate a number of input bits equal to the BBF payload, the UP packet stream is divided to fit the BBF data field.
[133] BB Frame Header Insertion Block can insert 2 byte fixed length BBF header which is inserted in front of BB frame. The BBF header is made up of STUFFI (1 bit), SYNCD (13 bits), and RFU (2 bits). In addition to the fixed 2-byte BBF header, the BBF may have an extension field (1 or 3 bytes) at the end of the 2-byte BBF header.
[134] The 2010 current adaptation is comprised of filling the insertion block and the BB scrambler.
[135] The padding insert block can insert padding field into a payload in a BB frame. If the input data in the stream adaptation is sufficient to fill a BB frame, STUFFI is set to '0' and the BBF has no fill field. Otherwise STUFFI is set to '1' and the padding field is inserted immediately after the BBF header. The padding field comprises two bytes of the padding field header and a variable size of padding data.
[136] The BB scrambler randomizes the entire BBF for energy dispersal. The randomization sequence is synchronous with the BBF. The randomization sequence is generated by the feedback shift register.
[137] PLS generation block 2020 can generate physical layer signaling (PLS) data.
The PLS provides a receiver with a means to access the physical layer DPs. The PLS data consists of PLS1 data and 20 PLS2 data.
[138] PLS1: a first set of PLS data carried in the FSS symbols that have a fixed size, encoding and modulation, which carries basic information about the system as well as the necessary parameters to decode the PLS2. The PLS1 data provides basic transmission parameters including parameters required to allow decoding reception of the PLS2 data. Also, the PFS1 data remains constant for the duration of a group of frames.
[139] The PLS2 data is a second set of PLS data transmitted in the FSS symbol, which carries more detailed PLS data about the system and the DPs. The PLS2 contains parameters that provide enough information for the receiver to decode the desired 10 DP. PLS2 signaling further consists of two types of parameters, static data from PLS2 (data from PLS2STAT) and dynamic data from PLS2 (data from PLS2-DYN). The static PLS2 data is PLS2 data that remains static for the duration of a group of frames and the dynamic PLS2 data is PLS2 data that can change dynamically from frame to frame.
[140] Details of the PLS data will be described later.
[141] The PLS scrambler 2030 can scramble the 20 generated PLS data for energy dispersal.
[142] The blocks described above can be omitted or replaced by blocks that have similar or identical functions.
[143] FIGURE 3 illustrates an input formatting block in accordance with another embodiment of the present invention.
[144] The input format block illustrated in FIGURE 3 corresponds to one embodiment of the input format block 1000 described with reference to FIGURE 1.
[145] FIGURE 3 shows a mode adaptation block of the input formatting block when the input signal corresponds to multiple input streams.
[146] The mode adaptation block of the input formatting block for processing the multiple input streams can independently process the multiple input streams.
[147] With reference to FIGURE 3, the mode adaptation block for respectively processing the multiple input currents may include an input current divider 3000 15, an input current synchronizer 3010, a delay block 3020 offset, a null packet suppression block 3030, a header compression block 3040, a CRC encoder 3050, a BB frame divider 3060 and a BB header insert block 3070. The description of each block of the mode adaptation block shall be provided.
[148] The operations of the CRC encoder 3050, the BB frame divider 3060, and the BB header insert block 3070 correspond to those of the CRC 25 encoder, BB frame divider, and the BB header insert block. described with reference to FIGURE 2 and thus the description thereof is omitted.
[149] The input current divider 3000 can divide the input TS, IP, GS streams into multiple service or service component streams (audio, video, etc.).
[150] Inrush current synchronizer 3010 may be referred to as ISSY. ISSY can provide adequate means to guarantee Constant Bit Rate (CBR) and constant end-to-end transmission delay for any input data format. The ISSY is always used for the case of multiple DPs carrying TS, and is optionally used for multiple DPs carrying GS streams.
[151] The offset delay block 3020 can delay the split TS packet stream after insertion of the ISSY information to allow for a TS packet recombination mechanism without requiring additional memory at the receiver.
[152] Null packet suppression block 3030 is used only for the TS input current case. Some TS input streams or split TS streams may have a greater number of null packets present to accommodate VBR (variable bit rate) services in a CBR TS stream. In this case, to avoid unnecessary transmission overhead, null packets can be identified and not transmitted. At the receiver, removed null packets can be re-inserted in the exact place where they were originally by reference to a null packet deleted (DNP) counter that is inserted into the transmission, thus ensuring constant bit rate and avoiding the need for time stamp update (PCR).
[153] The header compression block 3040 may provide packet header compression to increase transmission efficiency for TS or IP input streams. Because the receiver may have prior information on certain parts of the header, this known information may be suppressed at the transmitter.
[154] For transport streams, the receiver has a priori information about the synchronization bit configuration (0x47) and the packet length (188 bit). If the input TS stream carries content that only has one PID, that is, for only one service component (video, audio, etc.) or service sub-component (SVC base layer, SVC enhancement layer, base view or MVC-dependent views), TS packet header compression can (optionally) be applied to the transport stream. IP packet header compression is optionally used if the input stream is an IP stream.
[155] The blocks described above can be omitted or replaced by blocks that have similar or identical functions.
[156] FIGURE 4 illustrates an input formatting block in accordance with another embodiment of the present invention.
[157] The input formatting block illustrated in FIGURE 4 corresponds to one embodiment of the input formatting block 1000 described with reference to FIGURE 1.
[158] FIGURE 4 illustrates a current matching block of the input formatting module when the input signal corresponds to multiple input currents.
[159] With reference to FIGURE 4, the mode adaptation block for respectively processing the multiple input streams may include a 400 0 scheduler , a Frame 1 delay block 4010, a fill insertion block 4020, an in-band signaling 4030, a BB Frame scrambler 4040, a PLS generation block 4050, and a PLS scrambler 4060. The description will be provided for each block of the current adaptation block. '
[160] Operations of the fill insertion block 4020, the BB Frame scrambler 4040, the PLS generation block 4050, and the PLS scrambler 4060 correspond to those of the fill insert block, BB scrambler, the PLS generation block PLS and PLS scrambler described with reference to FIGURE 2, and thus the description thereof is omitted.
[161] The programmer 4000 can determine the overall cell allocation across the entire frame from the number of FECBLOCK of each DP. Including the mapping for PLS, EAC, and FIC, the programmer generates the PLS2-DYN data values, which are transmitted as in-band or PLS cell signaling in FSS of the frame. Details of FECBLOCK, EAC and FIC will be described later.
[162] Frame 1 delay block 4010 may delay input data by one transmit frame so that scheduling information about the next frame can be transmitted through the current frame for in-band signaling information to be inserted. in the DP.
[163] In-band 4030 signaling can insert a non-delayed portion of PLS2 data into a one-frame DP.
[164] The blocks described above can be omitted or replaced by blocks that have similar or identical functions. '
[165] FIGURE 5 illustrates a BICM block in accordance with one embodiment of the present invention.
[166] The BICM block illustrated in FIGURE 5 corresponds to one embodiment of the BICM block 1010 described with reference to FIGURE 1.
[167] As described in the above, apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention can provide a terrestrial broadcast service, mobile broadcast service, UHDTV service, etc.
[168] Since QoS (quality of service) depends on the characteristics of a service provided by the apparatus to transmit broadcast signals for future broadcast services according to an embodiment of the present invention, the data corresponding to respective services need be processed through different schemes. Accordingly, the BICM block according to an embodiment of the present invention can independently process the DPs entered thereto by independently applying SISO, MISO and MIMO schemes to the data channels corresponding respectively to the data paths. data. Accordingly, the apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention can control the QoS for each service or service component transmitted through each DP.
[169] (a) shows the BICM block shared by the base profile and the portable profile and (b) shows the BICM block of the advanced profile.
[170] The BICM block shared by the base profile and the portable profile and the advanced profile BICM block. 5 can include multiple processing blocks to process each DP.
[171] A description of each processing block will be provided from the BICM block for the base profile and the portable profile and the BICM block for the advanced profile.
[172] A BICM block processing block 5000 for the base profile and the portable profile may include a Data FEC encoder 5010, a bit interleaver 5020, a constellation mapper 5030, an SSD encoding block 5040 ( Signal Space Diversity) and a 5050 time interleaver.
[173] The Data FEC encoder 5010 can perform FEC encoding in the input BBF to generate the FECBLOCK procedure using outer encoding (BCH), and inner encoding (LDPC). Outer Encryption (BCH) is an optional encryption method. The details of operations of the Data FED encoder 5010 will be described later.
[174] The bit interleaver 5020 can interleave outputs from the Data FEC encoder 5010 to achieve optimized performance with a combination of the data codes.
LDPC and the modulation scheme while providing an efficiently implemented structure. Details of operations of the bit interleaver 5020 will be described later.
[175] The constellation mapper 5030 can modulate each cell word of the bit interleaver 5020 in the base and portable profiles, or the cell word of the cell-word demultiplexer 5010-1 in the advanced profile using either QPSK, QAM -16, non-uniform QAM (NUQ10 64, NUQ-256, NUQ-1024) or a non-uniform constellation (NUC16, NUC-64, NUC-256, NUC-1024) to provide a constellation point with normalized energy, for example . This constellation gap applies only to DP. Note that QAM16 and NUQ are square in shape, while NUCs are arbitrary in shape. When each constellation is rotated by any multiple of 90 degrees, the rotated constellation exactly overlaps its original. This symmetric property of the direction of rotation makes the capacities and the average powers of the real and imaginary components equal to each other. Both NUQ and NUC are specifically defined for each encoding rate and the particular used is signaled by the DP_MOD parameter presented in the PLS2 data.
[17 6] The SSD coding block 5040 can provide cells in two (2D), three (3D), and four (4D) dimensions to increase reception robustness under difficult dimming conditions.
[177] The time interleaver 5050 can operate at the DP level. Time Interleaved (TI) parameters can be set differently for each DP. Details of operations of the time interleaver 5050 will be described later.
[178] A B1CM block processing block 5000-1 for the advanced profile may include the 10 Data FEC encoder, bit interleaver, constellation mapper, and time interleaver. However, the processing block 5000-1 is distinguished from the processing block 5000 which further includes a cell-word demultiplexer 5010-1 and a MIMO encoding block 5020-1.
[179] Also, the operations of the data FEC encoder, bit interleaver, constellation mapper, and time interleaver in processing block 5000-1 correspond to those of the Data FEC encoder 5010, bit interleaver 5020, mapper Constellation 5030, and time interleaver 5050 described and thus the description thereof is omitted.
[180] Cell-word demultiplexer 5010-1 is used for Advanced Profile DP to split the single cell-word stream into two cell-word streams for MIMO processing. Details of operations of the cell-word demultiplexer 5010-1 will be described later.
[181] MIMO encoding block 5020-1 may process the output of cell-word demultiplexer 5010-1 using the MIMO encoding scheme. The MIMO coding scheme was optimized for broadcast signal transmission. MIMO technology is one way that promises increased capacity but is dependent on channel characteristics. Especially for broadcast, the strong LOS component of the channel or a difference in received signal power between two antennas caused by different signal propagation characteristics makes it difficult to obtain the MIMO capacity gains. The proposed MIMO coding scheme overcomes this problem by using a pre-coding based on rotation and phase scrambling of one of the MIMO signals.
[182] MIMO encoding is intended for a 2x2 MIMO system that requires at least two antennas at the transmitter and receiver. Two MIMO 20 encoding modes are defined in this proposal: full rate spatial multiplexing (FR-SM) and full rate full diversity spatial multiplexing (FRFD-SM). FR-SM encoding provides a capacity increase with a relatively small increase in complexity on the receiver side 25 while FRFD-SM encoding provides an additional capacity increase and diversity gain with a greater increase in complexity at the receiver side. The proposed MIMO coding scheme does not have any restrictions on the antenna polarity configuration.
[183] MIMO processing is required for the advanced profile frame, which means that all DPs in the advanced profile frame are processed by the MIMO encoder. MIMO processing is applied at the DP level. Constellation Mapper pairs produce NUQ (el, i and e2) which are fed to the input of the MIMO Encoder. The output of the MIMO Paired Encoder (gl, i and g2, i) is transmitted on the same carrier k and the OFDM symbol 1 of their respective TX antennas.
[184] The blocks described above can be omitted or replaced by blocks that have similar or identical functions.
[185] FIGURE 6 illustrates a BICM block according to another embodiment of the present invention.
[186] The BICM block illustrated in FIGURE 6 corresponds to one embodiment of the BICM block 1010 described with reference to FIGURE 1.
[187] FIGURE 6 illustrates a BICM block for protection of physical layer signaling (PLS), emergency alert channel (EAC) and fast information channel (FIC). EAC is part of a frame that carries EAS information data and FIC is a logical channel in a frame that carries the mapping information between a service and the corresponding base DP. Details of EAC and FIC will be described later.
[1188] With reference to FIGURE 6, the BICM block for PLS, EAC and FIC protection may include a PLS FEC encoder 6000, a bit interleaver 6010, a constellation mapper 6020 and time interleaver 6030.
[189] Also, the PLS FEC encoder 6000 may include a scrambler, BCH zero insert / encode block, LDPC encode block, and LDPC parity puncture block. The description will be provided for each block in the BICM block.
[190] PLS FEC Encoder 6000 can encode scrambled PLS 1/2 data, EAC section and FIC
[191] The scrambler can scramble PLS1 data and PLS2 data before BCH encoding and punctured and shortened LDPC encoding.
[192] The BCH zero insert / encode block can perform outer encoding on the scrambled PLS 1/2 data using the shortened code for PLS protection and insert null bits after BCH encoding. For PLS1 data only, the null insert output bits can be permuted prior to LDPC encoding.
[193] The LDPC coding block can encode the output of the BCH coding / zero insertion block using the LDPC code. To generate a complete coded block 5, Ci<sub>dpc</sub>, parity bits, Pldpc are systematically encoded starting with each PLS insert block inserted with zero, Iidpc and appending after it.
[194] Mathematical Figure 1
[Mathematical Equation 1]
[195] The LDPC code parameters for PLS1 and PLS2 are as follows in Table 4.
[196] Table 4
[Table 4]
<td>Signaling Type</td><td>K<sub>S.I.G</sub></td><td>Kfoch</td><td>Mjch_parity</td><td>íkLdpc (= N<sub>b</sub>ch)</td><td>A / ldpc</td><td>Wldpc_parity</td><td>encoding rate</td><td>Qldpc</td>
<td>PLS1</td><td> 342</td><td rowspan="2"> 1020</td><td rowspan="3"> 60</td><td rowspan="2"> 1080</td><td rowspan="2"> 4320</td><td rowspan="2"> 3240</td><td rowspan="2"> 1/4</td><td rowspan="2"> 36</td>
<td rowspan="2">PLS2</td><td> <1021</td>
<td> >1020</td><td> 2100</td><td> 2160</td><td> 7200</td><td> 5040</td><td> 3/10</td><td> 56</td>
[197] The LDPC parity punch block can puncture PLS1 data and PLS 2 data.
[198] When shorten is applied to PLS1 data protection, some LDPC parity bits are punctured after LDPC encoding. Also, for PLS2 data protection, PLS2 LDPC parity bits are punctured after LDPC encoding. These punctured bits are not transmitted.
[199] Bit interleaver 6010 can interleave each of the PLS1 data and the shortened and punctured PLS2 data.
[200] The constellation mapper 6020 can map PLS1 data and bit-interleaved PLS2 data into constellations.
[201] Time interleaver 6030 can interleave PLS1 data and mapped PLS2 data.
[202] The blocks described above can be omitted or replaced by blocks that have similar or identical functions.
[203] FIGURE 7 illustrates a framing block in accordance with one embodiment of the present invention.
[204] The framing block illustrated in
FIGURE 7 corresponds to one embodiment of the framing block 1020 described with reference to FIGURE 1.
[205] With reference to FIGURE 7, the framing block may include a delay compensation block 7000, a cell mapper 7010, and a frequency interleaver 7020. The description will be provided for each block of the framing block.
[206] The delay compensation block 7000 can adjust the time between the data channels and the corresponding 5 PLS data to ensure that they are co-synchronized at the transmitter end. The PLS data is delayed by the same amount as the data channels in addressing the data channel delays caused by the Input Format block and the BICM block. The BICM 10 block delay is mainly due to the 5050 time interleaver. In-band signaling data carries information from the next IT group so that a frame is carried in advance of the DPs to be signaled. The Delay Compensation block delays the in-band signaling data accordingly.
[207] The cell mapper 7010 can map the auxiliary streams of PLS, EAC, FIC, DP, and dummy cells to the active carriers of the OFDM symbols in the frame. The basic function of the 7010 cell mapper is to map data cells produced by ITs for each of the DPs, PLS cells, and EAC / FIC cells, if any, into active OFDM cell arrays that they correspond to each of the OFDM symbols within a frame. Service signaling data (such as 25 PSI (program specific information) / SI) can be collected separately and sent over a data channel. The Cell Mapper operates according to the dynamic information produced by the programming and the configuration of the frame structure. Details of the plot will be described later.
[208] Frequency interleaver 7020 may randomly interleave data cells received from cell mapper 7010 to provide frequency diversity. Also, the frequency interleaver 7020 can operate on each OFDM symbol pair comprised of two frequency symbols.
Sequential OFDMs using a different interleaving seed order to obtain the maximum interleaving gains in a single frame. Details of operations of the frequency interleaver 7020 will be described later.
[209] The blocks described above can be omitted or replaced by blocks that have similar or identical functions.
[210] FIGURE 8 illustrates an OFMD generation block in accordance with one embodiment of the present invention.
[211] The OFMD generation block illustrated in
FIGURE 8 corresponds to one embodiment of the OFMD generation block 1030 described with reference to FIGURE 1.
[212] The OFDM generation block modulates the OFDM carriers by the cells produced by the
Framing, inserts the pilots, and produces the time domain signal for transmission. Also, this block subsequently inserts guard intervals, and applies PAPR (Power Peak-to-Average Radius) reduction processing to produce the RF signal.
[213] With reference to FIGURE 8, the framing block may include a pilot and reserved tone insertion block 8000, a 2D-eSFN coding block 8010, an IFFT (Fast Fourier Transform) block 8020 Reverse), a 10 PAPR reduction block 8030, a guard interval insert block 8040, a preamble insert block 8050, another system insert block 8060, and a DAC block 8070. The description will be provided for each block of the framing block.
[214] The pilot and reserved tone insert block 8000 can insert pilots and the reserved tone.
[215] Several cells within the OFDM symbol are modulated with reference information, known as pilots, which have transmitted values known a priori at the receiver. The pilot cell information is made up of sparse pilots, continuous pilots, edge pilots, FSS (frame signaling symbol) pilots, and FES (frame edge symbol) pilots. Each pilot is transmitted at a particular boosted power level according to the type of pilot and the pilot pattern. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each carrier transmitted on any given symbol. The pilots can be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, and transmission mode identification, and can also be used to track phase noise.
[216] Reference information, taken from the reference sequence, is transmitted in pilot cells scattered in each symbol except the preamble, FSS and FES of the frame. Continuous pilots are inserted into each symbol of the frame. The number and location of continuous pilots depends on the size of the FFT and the sparse pilot pattern. The edge carriers are the edge pilots in each symbol except for the preamble symbol. They are inserted to allow frequency interpolation to the edge of the spectrum. FSS pilots are inserted into FSS and FES pilots are inserted into FES. They are inserted to allow time interpolation to the edge of the frame.
[217] The system according to one embodiment of the present invention supports the SFN network, where the distributed MISO scheme is optionally used to support each robust transmission mode. The 2D-eSFN is a distributed MISO scheme that uses multiple TX antennas, 25 of which are each located at a different transmitter site on the SFN network.
[218] The 2D-eSFN coding block 8010 can process 2D-eSFN processing to phase distort signals transmitted from multiple transmitters, to create time and frequency diversity in the SFN configuration. Therefore, burst errors due to low attenuation due to low flat fading or deep fading for a long time can be mitigated.
[219] IFFT block 8020 can modulate the output of 2D-eSFN coding block 8010 using the OFDM modulation scheme. Any cell in the data symbols that is not designated as a pilot (or reserved tone) carries one of the data cells from the frequency interleaver. Cells are mapped to OFDM carriers.
[220] PAPR reduction block 8030 can perform PAPR reduction on the input signal using a varied time domain PAPR reduction algorithm.
[221] Guard interval insertion block 8040 can insert guard intervals and preamble insert block 8050 can insert preamble in front of the signal. Details of a structure of the preamble will be described later. The other system insert block 8060 may multiplex signals from a plurality of time-domain broadcast transmission / reception systems so that data from two or more different broadcast transmission / reception systems providing broadcast services they can be transmitted simultaneously on the same RF signal bandwidth. In this case, two or more different broadcast transmission / reception systems refer to systems that provide different broadcast services. The different broadcast services can refer to a terrestrial broadcast service, mobile broadcast service, etc. The data related to respective broadcast services can be transmitted through different frames.
[222] The DAC block 8070 can convert an input digital signal to an analog signal from and produce the analog signal. The signal produced from the DAC blogue 7800 can be transmitted through multiple output antennas according to physical layer profiles. A 20 Tx antenna according to one embodiment of the present invention can have a vertical or horizontal polarity.
[223] The blocks described above can be omitted or replaced by blocks having similar or identical functions according to the design.
[224] FIGURE 9 illustrates a structure of an apparatus for receiving broadcast signals for future broadcast services in accordance with one embodiment of the present invention.
[225] The apparatus for receiving broadcast signals for future broadcast services according to one embodiment of the present invention may correspond to the apparatus for transmitting broadcast signals for future broadcast services, described with reference to FIGURE 1.
[226] Apparatus for receiving broadcast signals for future broadcast services in accordance with one embodiment of the present invention may include a synchronization and demodulation module 9000, a frame analysis module 9010, a decoding and de-mapping module 9020 , an output processor 9030 and a signaling decoding module 9040. A description will be provided of the operation of each module of the apparatus to receive broadcast signals.
[227] The synchronization and demodulation module 9000 can receive input signal through m Rx antennas, 20 perform signal detection and synchronization with respect to a system that corresponds to the apparatus to receive broadcast signals and carry out demodulation that it corresponds to a reverse procedure of the procedure performed by the apparatus for transmitting broadcast signals.
[228] The frame analysis module 9100 can analyze input signal frames and extract data through which a service selected by a user is transmitted. If the apparatus for transmitting broadcast signals performs interleaving, the frame analysis module 9100 may perform de-interleaving corresponding to a reverse interleaving procedure. In this case, the positions of a signal and the data that needs to be extracted can be obtained by decoding the data produced from the signaling decoding module 9400 to restore the programming information generated by the apparatus for transmitting broadcast signals.
[229] The unmapping and decoding module 9200 can convert the input signals into bit domain data and then de-interleave it when necessary. The demapping and decoding module 9200 can perform demapping for applied mapping for transmission efficiency and correcting an error generated in a transmission channel through decoding. In this case, the demapping and decoding module 9200 may obtain transmission parameters necessary for demapping and decoding by decoding the data produced from the signaling decoding module 9400.
[230] The output processor 9300 can perform inverse procedures of various signal compression / processing procedures which are applied by the apparatus to transmit broadcast signals to improve transmission efficiency. In this case, the output processor 9300 can acquire necessary control information from data produced from the signaling decoding module 9400. The output from the 8300 output processor corresponds to a signal input to the apparatus for transmitting broadcast signals and can be MPEG TS, IP streams (v4 or v6), and generic frames.
[231] The signaling decoding module 9400 can obtain PLS information from the signal demodulated by the synchronization and demodulation module 9000. As described above, the frame analysis module 9100, the unmapping and decoding module 9200, and the output processor 9300 can perform functions thereof using the data produced from the signaling decoding module 9400.
[232] FIGURE 10 illustrates a frame structure of. in accordance with one embodiment of the present invention.
[233] FIGURE 10 shows an exemplary configuration of frame types and FRUs in a super frame. (a) Shows a superframe according to an embodiment of the present invention, (b) shows FRU (Frame Repeat Unit) according to an embodiment of the present invention, (c) shows frames of variable PHY profiles in the FRU y (d) shows a structure of a frame.
[234] A super frame can be made up of eight FRUs. The FRU is a basic multiplexing unit for TDM of the frames, and is repeated eight times in a super frame.
[235] Each frame in 1 FRU belongs to one of the 5 profiles of PHY (base, portable k, advanced) or FEF. The maximum allowed number of frames on the FRU is four, and a given PHY profile can appear any number of times from zero times to four times on the FRU (for example, base, base, portable, advanced). The definitions of the PHY 10 profile can be extended using reserved values from the
PHY_PROFILE in the preamble, if required.
[236] The FEF portion is inserted into the end of the FRU, if included. When the FEF is included in the FRU, the minimum number of FEFs is 8 in a superframe. It is not recommended that the FEF parts be adjacent to each other.
[237] A frame is further divided into a number of OFDM symbols and a preamble. As shown in (d), the frame comprises a preamble, one or more frame signaling symbols (FSS), normal data symbols, and a frame edge symbol (FES).
[238] The preamble is a special symbol that enables fast UTB Futurecast system signal detection and provides a set of basic transmission parameters for efficient signal transmission and reception. The detailed description of the preamble will be described later.
[239] the main purpose of the FSS is to transport the PLS data. For fast tuning and channel estimation, and therefore fast decoding of PLS data, the FSS has a denser pilot pattern than the normal data symbol. The FES has exactly the same pilots as the FSS; This allows frequency-only interpolation within the FES and temporal interpolation, without extrapolation, for symbols immediately preceding the FES.
[240] FIGURE 11 illustrates a frame signaling hierarchy structure in accordance with one embodiment of the present invention.
[241] 'FIGURE 11 illustrates the signaling hierarchy structure, which is divided into three main parts: the preamble signaling data 11000, the PLS1 data 11010, and the PLS2 data 11020 11020.
The purpose of the preamble, which is carried by the preamble symbol in each frame, 'is to indicate the type of transmission and the basic transmission parameters of that frame. The PLS1 allows the receiver to access and decode the PLS2 data, which contains the parameters to access the DP of interest. The PLS2 is carried in each frame and is divided into two main parts: PLS2-STAT data and PLS2-DYN data. The static and dynamic portion of the PLS2 data is tracked by zero padding, if necessary. [242] FIGURE 12 illustrates preamble signaling data in accordance with one embodiment of the present invention.
[243] The preamble signaling data carries 21 bits of information that are needed to allow the receiver to access the PLS data and track the DPs within the frame structure. The details of the preamble signaling data are as follows
[244] PHY_PROFILE: This 3-bit field indicates the type of PHY profile of the current frame. The mapping of different types of PHY profiles is provided below in Table 5..
[245] Table 5
[Table 5]
<td>Value</td><td>PHY Profile</td>
<td> 000</td><td>Base profile</td>
<td> 001</td><td>Portable profile</td>
<td> 010</td><td>Advanced Profile</td>
<td> 011-110</td><td>Reserved</td>
<td> 111</td><td>FEF:</td>
[246] FFT_SIZE: This 2-bit field indicates the size of
FFT of the current frame within a group of frames, as described below in Table 6.
[247]
Table 6
[Table 6]
<td>Value</td><td>FFT size</td>
<td> 00</td><td>8K FFT</td>
<td> 01</td><td>16K FFT</td>
<td> 10</td><td>32K FFT</td>
<td> 11</td><td>Reserved</td>
[248] GI_FRACTION: This 3-bit field indicates the protection interval fraction value in the current superframe, as described in the following table 7.
[249] Table 7
[Table 7]
<td>Value</td><td>GI FRACTION</td>
<td> 000</td><td> 1/5</td>
<td> 001</td><td> 1/10</td>
<td> 010</td><td> 1/20</td>
<td> 011</td><td> 1/40</td>
<td> 100</td><td> 1/80</td>
<td> 101</td><td> 1/160</td>
<td> 110-111</td><td>Reserved</td>
[250] EAC_FLAG: This 1-bit field indicates whether the EAC is provided in the current frame. If this field is set to '1' the Emergency Alert Service (EAS) is provided in the current frame. If this field is set to '0', EAS does not overload on the current frame. This field can be dynamically changed within a super frame.
[251] PILOT — MODE: This 1-bit field indicates whether the pilot mode is mobile mode or fixed mode for the current frame in the current frame group. If this field is set to '0', the roving pilot mode is used. If the field is set to '1', the fixed pilot mode is used.
[252] PAPR_FLAG: This 1 bit field indicates whether the. 5 PAPR reduction is used for the current frame in the current frame group. If this field is set to the value '1', PAPR reduction tone reservation is used. If this field is set to '0', PAPR reduction is not used.
[253] FRU CONFIGURE: This 3-bit field indicates the PHY profile type configuration of the frame repetition units (FRUs) that are presented in the current superframe. All profile types carried in the current super frame are identified in this field in all 15 preambles in the current super frame. The 3-bit field has a different definition for each profile, as shown in the following table 8.
[254] Table 8
[Table 8]
<td></td><td>PHY_PROFIL E current = '000' (base)</td><td>Current PHY_PROFILE = '001' (portable)</td><td>Current PHY_PROFILE = '010' (advanced)</td><td>Current PHY_PROFILE = '111' (FEF)</td>
<td>FRU_CONFIGURE = 000</td><td>Only base profile present</td><td>Only portable profile present</td><td>Only advanced profile present</td><td>Only FEF present</td>
<td>FRU_CONFIGURE = 1XX</td><td>Portable profile present</td><td>Base profile present</td><td>Base profile present</td><td>Base profile present</td>
<td>FRU_CONFIGURE = XIX</td><td>Advanced profile present</td><td>Advanced profile present</td><td>Portable profile present</td><td>Portable profile present</td>
<td>FRU_CONFIGURE = XXI</td><td>FEF present</td><td>FEF present</td><td>FEF present</td><td>Advanced profile present</td>
[255] RESERVED: This 7-bit field is reserved for future use.
[256] FIGURE 13 illustrates PLS1 data in accordance with one embodiment of the present invention.
[257] The PLS1 data provides basic transmission parameters including parameters required to allow reception and decoding of PLS2. As mentioned in the above, the PLS1 data remains unchanged for the entire duration of a group of frames. The detailed definition of the signaling fields of the PLS1 data are as follows:.
[258] PREAMBLE_DATA: This 20-bit field is a copy of the preamble signaling data that excludes the
EAC_FLAG. ·
[259] NUM_FRAME_FRU: This 2-bit field indicates the number of frames per FRU.
[260] PAYLOAD_TYPE: This 3-bit field indicates the format of the. payload data carried in the frame group. PAYLOAD ΤΥΡΕ is marked as shown in table 9.
[261] Table 9
[Table 9]
<td>Value</td><td>Payload type</td>
<td>1XX</td><td>TS current is transmitted</td>
<td>XIX</td><td>IP stream is transmitted</td>
<td>XXI</td><td>GS current is transmitted</td>
[262] NUM_FSS: This 2-bit field indicates the number of 15 FSS symbols in the current frame.
[263] SYSTEM_VERSION: This 8-bit field indicates the version of the transmitted signal format. The SYSTEM_VERSION is divided into two 4-bit fields, which are a major version and a minor version.
[264] Major version: The four MSB bits of the field
SYSTEM VERSION indicates the highest version information. A change in the major version field indicates a non-backward compatible change. The default value '0000'. For the version described in this standard, the value is set to '0000'.
[265] Minor version: The four bits of LSB of
SYSTEM_VERSION where the field indicates minor version information. A minor version field change is backward compatible.
[266] CELL_ID: This is a 16-bit field that uniquely identifies a geographic cell in an ATSC network. An ATSC cell coverage area may consist of one or more frequencies depending on the number of frequencies used by UTB Futurecast system. If the value of CELL_1D is not known or is not specified, this field is set to '0'.
[267] NETWORK_ID: This is a 16-bit field that uniquely identifies the current ATSC network.
[268] SYSTEM_ID: This 16-bit field uniquely identifies the UTB Futurecast system within the 15 ATSC network. The UTB Futurecast system is the terrestrial broadcast system whose input is one or more input streams (TS, IP, GS) and whose output is an RF signal. The UTB Futurecast system carries one or more PHY and FEF profiles, if any. The UTB Futurecast system itself can carry different input currents and use different RF frequencies in different geographic areas, allowing for local service insertion. The frame and schedule structure is controlled in one place and is identical for all other transmissions within a UTB 25 Futurecast system. One or more UTB Futurecast systems may have
[275] PLS2_FEC_TYPE: This 2-bit field indicates the type of FEC used by the FLS2 protection. The type of FEC is designated according to Table 10. Details of the LDPC codes will be described later.
[276] Table 10
[Table 10]
<td>Content</td><td>PLS2 FEC Type</td>
<td> 00</td><td>4K-1/4 and 7K-3/10 LDPC codes</td>
<td> 01-11</td><td>Reserved</td>
[277] PLS2_MOD: This 3-bit field indicates the type of modulation used by PLS2. The type of modulation is indicated according to table 11..
[278] Table 11
[Table 11]
<img file="MX352013B_D0004.tif" />
QAM cells) from the collection of complete coded blocks for PLS2 that is carried in the current frame group. This value is constant for the entire duration of the current frame group.
[280] PLS2_STAT_S1ZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-STAT for the current frame group. This value is constant throughout the duration of the current frame group.
[281] PLS2JDYN_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-DYN for the current frame group. This value is constant for the entire duration of the current frame group.
[282] PLS2_REP_FLAG: This 1-bit field indicates whether the repeat mode of PLS2 is used in the current frame group. When the field is set to the value '1', the repeat mode of PLS2 is activated. When this field is set to the value '0', the repeat mode of PLS2 is disabled.
[283] PLS2_REP_SIZE_CELL: This 15-bit field indicates Ctotai_partiai_biock, the size (specified as the number of QAM cells) of the collection of partial coded blocks for PLS2 carried in each frame of the current 20-frame group, when PLS2 repeats used. If no repetition is used, the value of the field equals 0. This value is constant for the entire duration of the current frame group. '
[284] PLS2_NEXT_FEC_TYPE: This 2-bit field indicates the type of FEC used for PLS2 that is carried in each frame of the next group of frames. The type of FEC is indicated according to table 10.
[285] PLS2_NEXT_MOD: This 3-bit field indicates the type of modulation used for PLS2 that is carried in every 5 frames of the next group of frames. The type of modulation is indicated according to table 11.
[286] PLS2_NEXT_REP_FLAG: This 1-bit flag indicates whether the repeat mode of. PLS2 is used in the next group of frames. When the field is set to the value 10 '1', the repeat mode of PLS2 is activated. When this field is set to the value '0', the repeat mode of PLS2 is disabled.
[287] PLS2_NEXT_REP_SIZE_CELL: This 15-bit field indicates C<sub>to</sub>tai_fuii_biock, the size (specified as the number of 15 QAM cells) of the collection of complete coded blocks for PLS2 that is carried in each frame of the next group of frames, when PLS2 repeat is used. If repetition is not used in the next group of frames, the value of this field equals 0. This value is constant for the entire duration of the current group of frames.
[288] PLS2_NEXT_REP_STAT_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-STAT for the next group of frames. This value is constant in the current 25-frame group.
[289] PLS2 NEXT REP DYN SIZE BIT: This 14-bit field indicates the size, in bits, of the PLS2-DYN for the next group of frames. This value is constant in the current frame group.
[290] PLS2_AP_MODE: This 2-bit field indicates if additional parity is provided for PLS2 in the current frame group. This value is constant for the entire duration of the current frame group. The following table 12 provides the values for this field. When this field is set to '00', the additional parity is not used for PLS2 in the current frame group.
[291] Table 12
[Table 12]
<td>Value</td><td>PLS2-AP mode</td>
<td> 00</td><td>ΆΡ not provided</td>
<td> 01</td><td>API mode</td>
<td> 10-11</td><td>Reserved</td>
[292] PLS2_AP_SIZE_CELL: This 15-bit field indicates the size (specified as the number of QAM cells) of the additional parity bits of the PLS2. This value is constant for the entire duration of the current frame group.
[293] PLS2_NEXT_AP_MODE: This 2 bit field indicates whether additional parity is provided for PLS2 in the current frame group. This value is constant for the entire duration of the current frame group.
Table 12 defines the values for this field.
[294] PLS2 NEXT AP SIZE CELL: This 15-bit field indicates the size (specified as the number of QAM cells) of the PLS2 additional parity bits in each frame in the next group of frames. This value is constant 5 for the entire duration of the current frame group.
[295] RESERVED: This 32-bit field is reserved for future use.
[2 96] CRC_32: A 32-bit error detection code, which applies to all PLS1 signaling.
[297] FIGURE 14 illustrates PLS2 data in accordance with one embodiment of the present invention.
[298] FIGURE 14 illustrates PLS2-STAT data from PLS2 data. The PLS2-STAT data is the same within a group of frames, while the PLS2-DYN 15 data provides information that is specific to the current frame.
[299] The details of the PLS2STAT data fields are as follows:
[300] FIC_FLAG: This 1-bit field indicates if 20 FICs are used in the current frame group. If this field is set to '1', the FIC is provided in the current frame. If this field is set to '0', the FIC is not carried in the current frame. This value is constant for the entire duration of the current frame group.
[301] AUX_FLAG: This 1-bit field indicates whether the auxiliary stream (s) are used in the current frame group.
If this field is set to '1', the auxiliary stream is provided in the current frame. If this field is set to '0', the auxiliary stream is not carried in the current frame. This value is constant for the entire duration of the current frame group.
[302] NUM_DP: This 6-bit field indicates the number of bits transported within the current frame. The value of this field varies from 1 to 64, and the number of DPs is NUM_DP + 1.
[303] DP_ID: This 6-bit field indicates only one DP within a PHY profile.
[304] DP_TYPE: This 3-bit field indicates the type of DP. This is indicated according to the following table 13.
[305] Table 13
[Table 13]
<td>Value</td><td>PD type</td>
<td> 000</td><td>PD type 1</td>
<td> 001</td><td>PD type 2</td>
<td> 010-111</td><td>Reserved</td>
[306] DP_GROUP_ID: This 8-bit field identifies the DP group with which the current DP is associated. This can be used by a receiver to access the DPs of the service components associated with a particular service, which will have the same DP_GROUP_ID.
[307] BASE_DP_ID: This 6-bit field indicates the DP transport service signaling data (such as PSI / SI) used in the management layer. The DP indicated by BASE_DP_ID may be a normal DP carrying the service signaling data together with the service data or a
Dedicated DP carrying only the service signaling data.
[308] DP_FEC_TYPE: This 2-bit field indicates the type of FEC used by the associated DP. The type of FEC is indicated according to table 14 below.
[309] Table 14.
<img file="MX352013B_D0005.tif" />
points according to the following table 15.
[311] Table 15
[Table 15]
<td>Value</td><td>Encoding rate</td>
<td> 0000</td><td> 5/15</td>
<td> 0001</td><td> 6/15</td>
<td> 0010</td><td> 7/15</td>
<td> 0011</td><td> 8/15</td>
<td> 0100</td><td> 9/15</td>
<td> 0101</td><td> 10/15</td>
<td> 0110</td><td> 11/15</td>
<td> 0111</td><td> 12/15</td>
<td> 1000</td><td> 13/15</td>
<td>1001 ~ lili</td><td>Reserved</td>
[312] DP_MOD: This 4-bit field indicates the modulation used by the associated DP. Modulation is indicated according to the following table 16.
[313] Table 16
[Table 16]
<td>Value</td><td>Modulation</td>
<td> 0000</td><td>QPSK</td>
<td> 0001</td><td>QAM-16</td>
<td> 0010</td><td>NUQ-64</td>
<td> 0011</td><td>NUQ-256</td>
<td> 0100</td><td>NUQ-1024</td>
<td> 0101</td><td>NUC-16</td>
<td> 0110</td><td>NUC-64</td>
<td> 0111</td><td>NUC-256</td>
<td> 1000</td><td>NUC-1024</td>
<td> 1001-1111</td><td>Reserved</td>
[314] DP_SSD_FLAG: This 1-bit field indicates whether the SSD mode is used on the associated DP. If this field is set to value '1', SSD is used. If this field is set to value '0', SSD is not used.
[315] The following field appears only if PHY PROFILE equals '010', which indicates the advanced profile:
[316] DP_MIMO: This 3-bit field indicates what type of MIMO encoding process is applied to the associated DP. The type of MIMO encoding process is indicated according to 15 Table 17.
[317] Table 17
[Table 17]
<td>Value</td><td>MIMO encoding</td>
<td> 000</td><td>FR-SM</td>
<td> 001</td><td>FRFD-SM</td>
<td> 010-111</td><td>Reserved</td>
[318] DP_TI_TYPE: This 1-bit field indicates the type of time interleaving. A value of '0' indicates that an IT group corresponds to a frame and contains one or more IT blocks. A value of '1' indicates that an IT group is carried in more than one frame and contains only one IT block.
[319] DP_TI_LENGTH: The use of this 2-bit field (allowed values are 1, 2, 4, 8 only) is determined by the values set within the DP TI ΤΥΡΕ field as follows:
[320] If the DP_TI_TYPE is set to the value '1', this PI field indicates the number of frames to which each TI group is mapped, and there is one TI block per TI group (NTI = 1). The PI values allowed with the 2-bit field are defined in the following table 18.
[321] If the DP TI ΤΥΡΕ is set to the value '0', this field indicates the number of TI NTI blocks per TI group, and there is one TI group per frame (PI = 1).
The PI values allowed with the 2-bit field are defined in the following table 18.
[322]
Table 18
[Table 18]
<td>2-bit field</td><td>Pi</td><td>Nti</td>
<td> 00</td><td> 1</td><td> 1</td>
<td> 01</td><td> 2</td><td> 2</td>
<td> 10</td><td> 4</td><td> 3</td>
<td> 11</td><td> 8</td><td> 4</td>
[323] DP_FRAME_INTERVAL: This 2-bit field indicates the frame interval (Isalto) within the group of frames for the associated DP and the allowed values are 1, 2, 4, 8 (the corresponding 2-bit field 5 is '00 ',' 01 ',' 10 ', or' 11 ', respectively). For DPs that do not appear in every frame in the group of frames, the value of this field is equal to the interval between successive frames. For example, if a DP appears in frames 1, 5, 9, 13, etc., this field is set to '4'. For the DPs that appear in each frame, this field is set to '1'.
[324] DP_TI_BYPASS: This 1 bit field determines 5050 time interleaving availability. If time interleaving is not used for a DP, it is set to '1'. If time interleaving is used this is set to '0'.
[325] DP_FIRST_FRAME_ID'X: This 5-bit field indicates the index of the first frame of the super frame in which the current DP occurs. The value of DP_FIRST_FRAME_IDX ranges from 20 0 to 31.
[326] DP_NUM_BLOCK_MAX: This 10-bit field indicates the maximum value of DP_NUM_BLOCKS for this DP. The value of this field has the same margin as DP_NUM_BLOCKS.
[327] DP_PAYLOAD_TYPE: This 2-bit field indicates the type of payload data carried by the given DP. DP PAYLOAD ΤΥΡΕ is marked according to the following table 19.
[328] Table 19
[Table 19]
<td>Value</td><td>Payload Type</td>
<td> 00</td><td>TS</td>
<td> 01</td><td>IP</td>
<td> 10</td><td>GS</td>
<td> 11</td><td>Reserved</td>
[329] DP_INBAND_MODE: This 2-bit field indicates whether the current DP carries in-band signaling information. The type of in-band signaling is indicated according to the following table 20.
[330] Table 20
[Table 20]
<td>Value</td><td>In-band mode</td>
<td> 00</td><td>In-band signage is not transported.</td>
<td> 01</td><td>INBAND-PLS is transported only</td>
<td> 10</td><td>INBAND-ISSY is transported only</td>
<td> 11</td><td>INBAND-PLS and INBAND-ISSY are transported</td>
[331] DP_PROTOCOL_TYPE: This 2-bit field indicates the type of payload protocol carried by the given DP.
value '00'.
[336] Table 23
[Table 23]
<td>Value</td><td>Null packet suppression mode</td>
<td> 00</td><td>Not used</td>
<td> 01</td><td>DNP-NORMAL</td>
<td> 10</td><td>DNP-OFFSET</td>
<td> 11</td><td>Reserved</td>
[337] ISSY_MODE: This 2-bit field indicates the 10 ISSY mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS ('00'). The ISSY MODE is signaled according to the following table 24 If DP PAYLOAD ΤΥΡΕ is not TS ('00'), ISSY_MODE is set to the value '00'.
[338] Table 24.
[Table 24]
<td>Value</td><td>ISSY mode</td>
<td> 00</td><td>Not used</td>
<td> 01</td><td>ISSY-UP</td>
<td> 10</td><td>ISSY-BBF</td>
<td> . 11</td><td>Reserved</td>
[339] HC MODE TS: This 2-bit field indicates the TS header compression mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS ('00'). The HC_MODE_TS is designated according to the following table 25.
[340] Table 25
[Table 25]
<td>Value</td><td>Header compression mode</td>
<td> 00</td><td>HC_MODE_TS 1</td>
<td> 01</td><td>HC_MODE_TS. 2</td>
<td> 10;</td><td>HC_MODE_TS 3</td>
<td> 11</td><td>HC_MODE_TS 4</td>
[341] HC_MODE_IP: This 2-bit field indicates the IP header compression mode when DP PAYLOAD ΤΥΡΕ is set to IP ('01'). The HC_MODE_IP is designated according to the following table 26.
[342] Table 26
[Table 26]
<td>Value</td><td>Header compression mode</td>
<td> 00</td><td>No compression</td>
<td> 01</td><td>HC_MODE_IP 1</td>
<td> 10-11</td><td>Reserved</td>
[343] PID: This 13-bit field indicates the PID number for TS header compression when DP PAYLOAD ΤΥΡΕ is set to TS ('00') and HC MODE TS is set to '01' or ^ b ^ hb '10'.
[344] RESERVED: This 8-bit field is reserved for future use.
[345] The following field appears only if PHY FLAG equals '1':
[346] FIC_VERSION: This 8-bit field indicates the version number of the FIC.
[347] FIC_LENGTH_BYTE: This 13-byte field indicates the length, in bits, of the FIO.
[348] RESERVED: This 8-bit field is reserved for future use.
[349] The following field appears only if AUX_FLAG equals '1':
[350] NUM_AUX: This 4-bit field indicates the number of auxiliary streams. Zero means that no auxiliary current is used.
[351] AUX_CONFIG_RFU: This 8-bit field is reserved for future use.
[352] AUX STREAM ΤΥΡΕ: This 4-bit field is reserved for future use to indicate the type of the current auxiliary stream.
[353] AUX PRIVATE CONFIG: This 28-bit field is reserved for future use to signal auxiliary streams.
[354] FIGURE 15 illustrates PLS2 data in accordance with another embodiment of the present invention.
[355] FIGURE 15 illustrates PLS2-DYN data from PLS2 data. The PLS2-DYN data values can change for the duration of a group of frames, while the size of the fields remains constant.
[356] The details of the PLS2-DYN data fields are as follows:
[357] FRAME_INDEX: This 5-bit field indicates the frame index of the current frame within the superframe. The index of the first frame in the superframe is set to '0'.
[358] PLS_CHANGE_COUNTER: This 4-bit field indicates the number of superframes in advance where the configuration will change. The next superframes with configuration changes are indicated by the value indicated within this field. If this field is set to the value '0000', it means that a scheduled change is not expected: for example, value '1' indicates that there is a change in the next superframe.
[359] FIC_CHANGE_COUNTER: This 4-bit field indicates the number of superframes in advance where the configuration (ie the content of the FIC) will change. The next superframes with configuration changes are indicated by the value indicated within this field. If this field is set to the value '0000', it means that no scheduled change is expected: for example, value '0001' indicates that there is a change in the next superframe.
[360] RESERVED: This 16-bit field is reserved for future use.
[361] The following fields appear in the loop over NUM_DP, which describes the parameters associated with the DP carried in the current frame.
[362] DP_ID: This 6-bit field indicates only the DP within a PHY profile.
[363] DP_START: This 15-bit (or 13-bit) field indicates the start position of the first of the DPs using the DPU address scheme. The DP_START field has a different length according to the PHY profile and FFT size as shown in the following table 27.
[364] Table 27.
[Table 27]
<td rowspan="2">PHY Profile</td><td colspan="2">DP START field size</td>
<td>64K</td><td>16K</td>
<td>Base</td><td>13 bits</td><td>15 bits</td>
<td>Laptop</td><td> -</td><td>13 bits</td>
<td>Advanced</td><td>13 bits</td><td>15 bits</td>
[365] DP_NUM_BLOCK: This 10-bit field indicates the 10 number of FEC blocks in the current IT group for the current DP. The value of DP_NUM_BLOCK ranges from 0 to 1023.
[366] RESERVED: This 8-bit field is reserved for future use.
[367] The following fields indicate the FIC 15 parameters associated with the EAC.
[368] EAC_FLAG: This 1 bit field indicates the existence of the EAC in the current frame. This bit is the same value as the EAC FLAG in the preamble.
[369] EAS_WAKE_UP_VERSION_NUM: This 8-bit field indicates the version number of an activation indication.
[370] If the field of EAC_FLAG is equal to 1, the next 12 bits are allocated for the field of EAC_LENGTH_BYTE. If the field of EAC_FLAG equals '0', the next 12 bits are allocated for EAC_COUNTER.
[371] EAC_LENGTH_BYTE: This 12-bit field indicates the length, in byte, of the EAC.
[372] EAC_COUNTER: This 12-bit field indicates the number of frames before the frame where the EAC arrives.
[373] The following field appears only if the AUX FLAG field is equal to '1':
[374] AUX_PRIVATE_DYN: This 48-bit field is reserved for future use to signal auxiliary streams. The meaning of this field depends on the value of
AUX_STREAM_TYPE in the configurable PLS2-STAT.
[375] CRC_32: A 32-bit 15-bit error detection code, which applies to the entire PLS2.
[376] FIGURE 16 illustrates a logical structure of a frame in accordance with one embodiment of the present invention.
[377] As mentioned above, the PLS, EAC, FIC, DP, auxiliary streams and dummy cells are mapped to the active carriers of the OFDM symbols in the frame. The PFS1 AND PFS2 are first mapped to one or more FSS. After that, the EAC cells, if any, are mapped immediately 'after the PLS field, followed by the FIC cells, if any. The DPs are mapped almost after the PLS or EAC, FIC, if any. Type 1 DPs follow first, Type 2 DPs after. The details of a type of DP will be described later. In a certain case, DPs may carry some special data for EAS or service signaling data. The auxiliary stream or streams 5, if any, follow the DPs, which in turn are followed by the fictitious cells. Mapping them together in the order mentioned above, i.e. PLS, EAC, FIC, DP, auxiliary streams and dummy data cells exactly fill the capacity of cells in the frame.
[378] FIGURE 17 illustrates PLS mapping in accordance with one embodiment of the present invention.
[379] PLS cells are mapped to active FSS carriers. Depending on the number of cells occupied by PLS, one or more symbols are designated as FSS, and the number of 15 FSS Nfss is designated by NUM_FSS in PLS1. The FSS is a special symbol for transporting PLS cells. Since robustness and latency are critical issues in the PLS, the FSS has a higher density of pilots that allow fast synchronization and frequency-only interpolation within the FSS.
[380] PLS cells are mapped to active N carriers<sub>fss</sub> FSS in a top-down fashion as shown in an example in FIGURE 17. Cells in PLS1 are first mapped from the first cell of the first FSS in an increasing order of cell index. Cells in PLS2 follow immediately after the last cell of PLS1 and mapping continues down to the last cell index of the first FSS. If the total number of PLS cells required exceeds the number of active carriers of an FSS, mapping 5 proceeds to the next FSS and continues in exactly the same way as the first FSS.
[381] After the PLS mapping is complete, the DPs are then transported. If EAC, FIC, or both are present in the current frame, they are placed between normal PLS and DP 10.
[382] FIGURE 18 illustrates EAC mapping in accordance with one embodiment of the present invention.
[383] EAC is a dedicated channel for transporting EAS messages and links to DPs for EAS. EAS support is provided but EAC itself may or may not be present in every frame. EAC, if any, is mapped immediately after the cells of PLS2. EAC is not preceded by any of the FICs, DPs, ancillary streams, or dummy cells other than PLS cells. The procedure of mapping the cells of EAC 20 is exactly the same as that of PLS.
[384] The EAC cells are mapped from the next cell of the PLS2 in increasing order of the cell index as shown in the example in FIGURE 18. Depending on the EAS message size, the EAC cells may occupy 25 some symbols , as shown in FIGURE 18.
[385] EAC cells follow immediately after the last cell of PLS2 and mapping continues down to the last cell index of the last FSS. If the total number of EAC cells required exceeds the number of 5 remaining active carriers from the last FSS mapping proceed to the next symbol and continue in exactly the same way as FSS. The next symbol to map in this case is the normal data symbol, which has more active carriers than an FSS.
[386] After the EAC mapping is complete, the FIC is transported next, if one exists. If FIC is not transmitted (as noted in the PLS2 field), DP follows immediately after the last cell of the EAC.
[387] FIGURE 19 illustrates FIC mapping in accordance with one embodiment of the present invention.
[388] shows an exemplary cell mapping of FIC without EAC and (b) shows an exemplary cell mapping of FIC with EAC.
[389] FIC is a dedicated channel for carrying cross-layer information to allow fast service acquisition and channel scanning. This information mainly includes information to hide channel between the DPs and the services of each broadcaster. For fast scanning, a receiver can decode FIC and obtain information such as a broadcaster ID, number of services, and BASE_DP_ID.
For fast service acquisition, in addition to FIC, base DP can be decoded using BASE_DP_ID. Unlike the content it carries, a base DP is encoded and mapped into a frame in exactly the same way as a normal DP. Therefore, no additional description is required for a base DP. FIC data is generated and consumed in the Management Layer. The data content of FIC is as described in the management layer specification.
[390] The FIC data is optional and the use of FIC is signaled by the FIC_FLAG parameter in the static part of PLS2. If FIC is used, FIC_FLAG is set to '1' and the signaling field for FIC is defined in the static part of PLS2. Indicated in this field are the uses of FIC_VERSION, and FIC_LENGTH_BYTE. FIC uses the same modulation coding and time interleaving parameters as PLS2. FIC shares the same signaling parameters as PLS2_MOD and PLS2JFEC. The FIC data, if any, is mapped immediately after PLS2 'or EAC if any. FIC is not preceded by any of the normal DP, ancillary streams, or dummy cells. The cell mapping method of FIC is exactly the same as that of EAC which again is the same as PLS.
[391] Without EAC after PLS, FIC cells are mapped from the next cell of PLS2 in increasing order of cell index as shown in an example in (a). Depending on the FIC data size, the FIC cells can be mapped to some symbols, as shown in (b).
[392] FIC cells follow immediately after the last cell in PLS2 and mapping continues down to the last cell index in the last FSS. If the total number of FIC cells required exceeds the number of remaining active carriers from the last FSS, the mapping proceeds to the next symbol and continues in exactly the same way as FSS. The next symbol to map in this case is the normal data symbol that has more than 10 active carriers than one FSS.
[393] If EAS messages are transmitted in the current frame, the EAC proceeds FIC, and the FIC cells are mapped from the next EAC cell in increasing order of cell index as shown in (b).
[394] After FIC mapping is complete, one or more DPs are mapped, followed by ancillary streams, if any, and dummy cells.
[395] FIGURE 20 illustrates one type of PD according to one embodiment of the present invention.
[396] FIGURE 20 shows PD type 1 and (b) shows the
DP type 2.
[397] After the preceding channels, ie PLS, EAC and FIC, are mapped, the DP cells are mapped. A PD is characterized into one of two types according to the mapping method 25:
[398] DP type 1: DP is mapped by TDM
[399] DP type 2: DP is mapped by FDM
[400] The type of DP is indicated by the field of DP_TYPE in the static part of PLS2. FIGURE 20 illustrates the 5 mapping orders of Type 1 DPs and Type 2 DPs. Type 1 DPs are first mapped in the increasing order of cell index, and after reaching the last cell index, the symbol index is increased by one. Inside the next symbol, the DP continues to map in the incremental order of 10 cell index starting from p = 0. With a number of the DPs mapped together in a frame, each of the Type 1 DPs are grouped in time, similar to TDM multiplexing of DPs.
[401] Type 2 DPs are mapped first in the 15th increasing order of symbol index, and after reaching the last OFDM symbol in the frame, the cell index increments by one and the symbol index is returned to the first symbol available and then increments from that available index. After mapping a number of the 20 DPs together in a frame, each of the Type 2 DPs are sequenced together, similar to FDM multiplexing of DPs. [402] Type 1 DPs and Type 2 DPs can coexist in a frame if needed with a constraint; Type 1 DPs always precede Type 2 DPs. The total number of 25 OFDM cells carried by Type 1 DPs and Type 2 DPs cannot exceed the total number of OFDM cells available for transmission of the DPs:
[403] Mathematical Figure 2
[Math Equation 2] ^ DPi + ^ DP2 - ^ DP
[404] where D<sub>DP</sub>i is the number of OFDM cells occupied by DP Type 1, DDP2 is the number of cells occupied by Type 2 DP. Since PLS, EAC, FIC all are mapped in the same way as DP 'Type 1, all follow Type 1 mapping rule. Therefore, generally, Type 1 mapping always precedes Type 2 mapping.
[405] FIGURE 21 illustrates DP mapping in accordance with one embodiment of the present invention.
[406] (a) shows an OFDM cell address to map DP type 1 and (b) shows an OFDM cell address to map DP type 2.
[407] The address of OFDM cells for DP Type 1 mapping (0, ..., dpi<sup>-</sup>1) is defined for active data cells of DP Type 1. The addressing scheme defines the order in which the cells of the TIs for each of the DP Type 1 are assigned to the active data cells. It is also used to mark the locations of the DPs in the dynamic part of the PLS2.
[408] Without EAC and FIC, address 0 refers to the cell immediately after the last cell leading to the PLS in the last FSS. If EAC is transmitted and FIC is not in the corresponding frame, address 0 refers to the cell immediately after the last cell carrying EAC. If FIC is transmitted in the corresponding frame, address 0 refers to the cell immediately after the last cell carrying FIC. Address 0 for Type 1 DPs can be calculated considering two different cases as shown in (a). In the example in (a), PLS, EAC and FIC are all assumed to be transmitted. The extension to cases where either or both of EAC and FIC are omitted is straightforward. If there are cells remaining in the FSS after mapping all cells to FIC as shown on the left side of (a).
[409] The address of OFDM cells to map DP 15 Type 2 (0, ..., D<sub>dp2</sub>-1) is defined for the active data cells of Type 2 DPs. The addressing scheme defines the order in which the cells of the TIs for each of the Type 2 DPs are assigned to the active data cells. It is also used to mark the locations of the DPs in the dynamic part 20 of the PLS2.
[410] There are three slightly different cases that are possible as shown in (b). For the first case shown on the left side of (b), the cells in the last FSS are available for DP Type 2 mapping. For the second case shown in the middle, FIC occupies the cells of a normal symbol, but the number of FIC cells in that symbol is not bigger than C<sub>FS</sub>s The third case, shown on the right side (b), is the same as the second case except that the number of FIC cells mapped to that 5 symbol exceeds C<sub>FS</sub>s
[411] The extension to the case where Type 1 DPs precede Type 2 DPs is straightforward since PLS, EAC and FIC follow the same Type 1 mapping rule as Type 1 DPs.
[412] A data tube unit (DPU) is a basic unit for assigning data cells to a DP in a frame.
[413] A DPU is defined as a signaling unit for locating DPs in a frame. A 7010 Cell Mapper can map the cells produced by ITs for each of the DPs. A time interleaver 5050 produces a series of TI blocks and each TI block comprises a variable number of XFECBLOCKs which in turn are made up of a set of cells. The number of cells in an XFECBLOCK, Nceidasz depends on the size of FECBLOCK, Ni<sub>dpc</sub>, and the number of bits transmitted per constellation symbol. A DPU 20 is defined as the greatest common divisor of all possible values of the number of cells in an XFECBLOCK, N<sub>cells</sub>, supported in a given PHY profile. The length of a DPU in cells is defined as L<sub>DF</sub>or·
Since each PHY profile supports 25 different combinations of FECBLOCK size and a different number of bits per constellation symbol, L<sub>DPU</sub> it is defined on a PHY profile basis.
[414] FIGURE 22 illustrates a FEC structure in accordance with one embodiment of the present invention.
[415] FIGURE 22 illustrates an FEC structure in accordance with one embodiment of the present invention prior to bit interleaving. As mentioned in the above, the data FEC encoder can perform FEC encoding in the input BBF to generate the FECBLOCK procedure using outer encoding (BCH), and inner encoding (LDPC). The illustrated FEC structure corresponds to the FECBLOCK. Also, the structure of FECBLOCK and FEC have the same value that corresponds to an LDPC codeword length.
[416] The BCH encoding is applied to each BBF (K<sub>bch </sub>bits), and then the LDPC encoding is applied to BCH-encoded BBF (K<sub>ldpc</sub> bits = N<sub>bch</sub> bits) as illustrated in FIGURE 22.
[417] The value of Ni<sub>dpc</sub> it is either 64800 bits (long FECBLOCK) or 16200 bits (short FECBLOCK).
[418] The following Table 28 and Table 29 show FEC encoding parameters for a long FECBLOCK and a short FECBLOCK, respectively.
[419] Table 28
[Table 28]
<td>Cup of LDPC</td><td>Nldpc</td><td>Kldpc</td><td>Kfcch</td><td>BCH error correction capability</td><td>Nbch Kbch</td>
<td></td><td rowspan="9">64800 Such</td><td> 21600</td><td> 21408</td><td rowspan="9"> 12</td><td rowspan="9"> 192</td>
<td> 6/15</td><td> 25920</td><td> 25728</td>
<td> 7/15</td><td> 30240</td><td> 30048</td>
<td> 8/15</td><td> 34560</td><td> 34368</td>
<td> 9/15</td><td> 38880</td><td> 38 68 8</td>
<td> 10/15</td><td> 43200</td><td> 43008</td>
<td> 11/15</td><td> 47520</td><td> 47328</td>
<td> 12/15</td><td> 51840</td><td> 51648</td>
<td> 13/15 [420]</td><td>56160 21 to 29</td><td> 55968</td>
[Table 29]
<td> 5</td><td>LDPC rate</td><td>Nldpc</td><td>Nidpc</td><td>N¿> ch</td><td>BCH error correction capability</td><td>Nbch Kbch</td>
<td></td><td> 5/15</td><td></td><td> 5400</td><td> 5232</td><td></td><td></td>
<td></td><td> 6/15</td><td></td><td> 6480</td><td> 6312</td><td></td><td></td>
<td></td><td> 7/15</td><td></td><td> 7560</td><td> 7392</td><td></td><td></td>
<td></td><td> 8/15</td><td></td><td> 8640</td><td> 8472</td><td></td><td></td>
<td></td><td> 9/15</td><td> 16200</td><td> 9720</td><td> 9552</td><td> 12</td><td> 168</td>
<td> 10</td><td> 10/15</td><td></td><td> 10800</td><td> 10632</td><td></td><td></td>
<td></td><td> 11/15</td><td></td><td> 11880</td><td> 11712</td><td></td><td></td>
<td></td><td> 12/15</td><td></td><td> 12960</td><td> 12792</td><td></td><td></td>
<td></td><td> 13/15</td><td></td><td> 14040</td><td> 13872</td><td></td><td></td>
[421] The details of encoding operations
BCH and LDPC encoding are as follows:
[422] An error correction BCH code 12 is used for external encoding of the BBF. The generator
Polynomial BCH for short FECBLOCK and long FECBLOCK are obtained by multiplying all polynomials together.
[423] The LDPC code is used to encode the result of the outer BCH encoding. To generate a completed 5 Bidpc (FECBLOCK), Pi<sub>dpc</sub> (parity bits) is encoded systematically from each Ii<sub>dpc</sub> (BBF encoded by BCH), and appended to Ii<sub>dpc</sub>. The bi<sub>dpc</sub> completed (FECBLOCK) is expressed as follows in the Mathematical Figure.
[424] Mathematical Figure 3
[Mathematical Equation 3] ^ Idpc <sup>=</sup> [ϊ / φΓ ^ Idpc J <sup>=</sup> [ <sup>Z</sup>0 ’ <sup>Z</sup>one - - - /%.-! 'A> A' · · · 'Av ^ -K ^ -l]
[425] The parameters for long FECBLOCK and short FECBLOCK are provided in Table 28 and 29 above, respectively. .
[426] The detailed procedure to calculate the 15 bits of parity N<sub>ldpc</sub> - Ki<sub>dpc</sub> for long FECBLOCK, it is as follows:
[427] 1) Start the parity bits,
[428] Mathematical Number 4
[Mathematical equation 4]
Po = P <= Pz = - P «„ „- K ^ = 0
[429] 2) Accumulate the first bit of information - iO, in the parity bit addresses specified in the first row of the parity check address matrix. The details of the parity check address matrix will be described later. For example, for the.
rate 13/15:
[430]
Mathematical Figure 5
[Equation
5]
P<sub>Ki</sub> = PoM ® '<
Plüli <sup>-</sup> P1S15 ® 6
P<sub>W</sub> = i ® 'or
A'js'j - A '> sp ®' o
P ^, = P ^ ®k
Pwi - Peen ® <sup>;</sup>or
Pí <m “A974 ® 4>
P-572 = P ^ 2®'o
Pls26V - P (2 <i0 ® i0
[431]
3)
For the following .359 bits of information, i<sub>s</sub> s = l, 2
359 The parity bit addresses are accumulated using the following Mathematical Figure.
[432]
Mathematical Figure 6
[Mathematical Equation 6] {x + (5 mod 360) XQ<sub>ldpc</sub>} mod (N<sub>ldpc</sub> - K<sub>/ dpc</sub>)
[433] where x indicates the address of the accumulator of parity bits that corresponds to the first bit i<sub>0</sub>, and Qi<sub>dpc</sub> is a code rate dependent constant specified in the parity check address array. Continuing with the example, Qi<sub>dpc</sub> = 24 for rate 13/15, so for the il bit of information, the following operations are performed:
[434] Mathematical Number 7
[Mathematical Equation 7]
Piafo <sup>=</sup> ΡίΜΠ ® / ^ 2839 <sup>=</sup> / ^ 2839 ® a
ΛδόΙ <sup>=</sup> PiSfil ® A Pían ~ Pífot ® A
TO." = Pñ ^ ® ή P ™ = Pw ® A
P ^ - <sup>=</sup> Pem © '1 /' í'WS <sup>=</sup> Pm ® A
P -. Í = Ps-, 1 ® '1 Ps2S1 <sup>=</sup> Pf2M ® A
P ^ P ^ ® ',
[435] 4) For the 361st information bit ³360, the addresses of the parity bit accumulators are provided in the second row of the parity check address matrix. In a similar way, the addresses of the parity bit accumulators for the next 359 bits i<sub>s</sub> of information, s = 361, 362, ..., 719 are obtained using the mathematical figure 6, where x indicates the address of the parity bit accumulator that corresponds to the 36th information bit, that is, the entries in the second row address of the parity check address array.
[436] 5) In a similar way, for each group of 360 new bits of information, a new row of parity confirmation address arrays used to find the addresses of the accumulated parity bits.
[437] After all the information bits have been exhausted, the final parity bits are obtained as follows:
[438] 6) Perform the following operations sequentially starting with i = l
[439] Mathematical Figure 8
[Mathematical Equation 8]
Pί ~ P¡ ® Pí- \ · <sup>? =</sup> L2, .A¡<sub>dpc</sub> - K<sub>Dpc</sub> — 1
[440] where the final content of pi, i = 0, 1,. . , N<sub>ldpc</sub> - K<sub>ldpc</sub>
- 1 equals the parity bit pi.
[441] Table 30
[Table 30]
<td>Encoding Rate</td><td>Qldpc</td>
<td> 5/15</td><td> 120</td>
<td> 6/15</td><td> 108</td>
<td> 7/15</td><td> 96</td>
<td> 8/15</td><td> 84</td>
<td> 9/15</td><td> 72</td>
<td> 10/15</td><td> 60</td>
<td> 11/15</td><td> 48</td>
<td> 12/15</td><td> 36</td>
<td> '13/15</td><td> 24</td>
[442] This LDPC encoding procedure for a
Short FECBLOCK is according to an LDPC encoding procedure for long FECBLOCK, except that it replaces table 30 with table 31, and replaces the array of parity check addresses for long FECBLOCK with the array of parity check addresses for the short FECBLOCK.
[443] Table 31
[Table 31]
<td>Encoding Rate</td><td>Qldpc</td>
<td> 5/15</td><td> 30</td>
<td> 6/15</td><td> 27</td>
<td> 7/15</td><td> 24 .</td>
<td> 8/15</td><td> 21</td>
<td> 9/15</td><td> 18</td>
<td> 10/15</td><td> 15</td>
<td> 11/15</td><td> 12</td>
<td> 12/15</td><td> 9</td>
<td> 13/15</td><td> 6</td>
[444] FIGURE 23 illustrates a bit interleaving in accordance with one embodiment of the present invention.
[445] The LDPC encoder results are bit interleaved, which consists of parity interleaving followed by Quasi-Block-Cycle (QCB) interleaving and intergroup interleaving.
[446] interleaved sample of Quasi-Block-Cyclic (QCB) and 10 (b) sample interleaved between groups.
[447] The FECBLOCK can be collated by parity. In the parity interleaving result, the LDPC codeword consists of 180 adjacent QC blocks in a long FECBLOCK and 45 adjacent QC blocks in a short FECBLOCK.
Each QC block in either a long or a short FECBLOCK consists of 360 bits. The LDPC codeword interleaved by parity is interleaved by QCB interleaving. The QCB interleaving unit is a QC block. The QC blocks in parity interleaving result are swapped for QCB interleaving as illustrated in FIGURE 23, where Nceidas = 64800 / nmod or 16200 / nmod according to the length of FECBLOCK. The QCB interleaving pattern is unique for each LDPC coding rate and modulation type combination.
[448] After the QCB interleaving, the interleaving between groups is performed according to the type of modulation and order (nmod) which is defined in the following table 32. The number of QC blocks for an internal group, N<sub>QC</sub>b_ig, is also defined.
[449] Table 32
[Table 32]
<td>Modulation type</td><td>nmod</td><td>NqcB_IG</td>
<td>QAM-16</td><td> 4</td><td> 0</td>
<td>NUC-16</td><td> 4</td><td> 4</td>
<td>NUQ-64</td><td> 6</td><td> 3</td>
<td>NUC-64</td><td> 6</td><td> 6</td>
<td>NUQ-256</td><td> 8</td><td> 4</td>
<td>NUC-256</td><td> 8</td><td> 8</td>
<td>NUQ-1024</td><td> 10</td><td> 5</td>
<td>NUC-1024</td><td> 10</td><td> 10</td>
[450] The intergroup interleaving process is performed with Nqcb_ig QC blocks from the QCB interleaving result.
Intergroup interleaving has a process for writing and reading the bits of the inner group using 360 columns and N<sub>Q</sub>cb_ig rows. In the write operation, the bits of the QCB interleaving result are written in rows. The read operation is performed by columns to read m bits from each row, where m is equal to 1 for NUC and 2 for NUQ.
[451] FIGURE 24 illustrates cell word demultiplexing in accordance with one embodiment of the present invention.
[452] (a) shows a cell-word demultiplexion for 8 and 12 bpcu MIMO and (b) shows a cell-word demultiplexion for 10 bpcu MIMO.
[453] Each cell-word (c0, l, cl, l, ..., c mod1,1) of the bit interleaving result is demultiplexed into (dl, 0, m, dl, l, m ..., gave, <sup>1</sup> mod-l, m) and (d2,0, m, d2, l, m ..., d2, <sup>1</sup> mod-l, m) as shown in (a), which describes the cell-word demultiplexing process for an XFECBLOCK. .
[454] For the case of 10 bpcu MIMO that uses different types of NUQ encoding for MIMO encoding, the Bit Interleaver for NUQ-1024 is reused. Each cell word (c0, l, cl, l, ..., c9, l) of the Bit Interleaved result is demultiplexed into (dl, 0, m, dl, l, m ..., dl, 3, m ) and (d2,0, m, d2, l, m ..., d2,5, m), as shown in (b).
[455] FIGURE 25 illustrates a time lapse in accordance with one embodiment of the present invention.
[456] a (c) show TI mode examples.
[457] The time interleaver operates at the DP level.
Time Interleaved (TI) parameters can be set differently for each DP.
[458] The following parameters, which appear in the data part of PLS2-STAT, configure the TI:
[459] DP TI ΤΥΡΕ (allowed values: 0 or 1 Represents the CT mode; '0' indicates the mode with multiple CT blocks (more than one CT block) per CT group. In this case, a group of CTs TI is directly inactive in a frame (no interframe interleaving). '1' indicates the mode with only one TI block per TI group. In this case, the TI block can propagate over more than one frame (interleaved between frames ).
[460] DP_TI_LENGTH: If DP_TI_TYPE = '0', this parameter is the number of TI NTI blocks per TI group. For DP_TI_TYPE = '1', this parameter is the number of propagated P1 frames of a TI group.
[461] DP_NUM_BLOCK_MAX (allowed values: 0 to 1023): Represents the maximum number of XFECBLOCKs per IT group.
[462] DP FRAME INTERVAL (allowed values: 1 2 4.8 MM * .M ^ *
Represents the number of ISALTO frames between two successive frames carrying the same DP of a given PHY profile.
[463] DP_TI_BYPASS (allowed values: 0 or 1): If time interleaving is not used for a DP, this parameter is set to '1'. It is set to '0' if time interleaving is used.
[464] Additionally, the parameter DP NUM BLOCK of the PLS2-DYN data is used to represent the number of XFECBLOCK carried by a group of IT's of the DP.
[465] When interleaving is not used for a DP, the next IT group, time interleaving operation, and IT mode are not considered. However, the Delay Compensation block for the programmer's dynamic configuration information will still be required. On each DP, the required XFECBLOCKs from SSD / MIMO encoding are grouped into IT groups. That is, each TI group is a set of an integer of XFECBLOCK and will contain a dynamically variable number of XFECBLOCK. The number of XFECBLOCK in IT group of index n is indicated by N<sub>x</sub>block_group (n) and is designated as DP_NUM_BLOCK in the PLS2-DYN data. Note that N<sub>xBLOC</sub>K_Group (n) can vary from the minimum value of 0 to the maximum value N<sub>XBLOC</sub>K_Grou<sub>P</sub>_MAx (which corresponds to DP_NUM_BLOCK_MAX) of which the largest value is 1023.
[466] Each TI group is directly mapped into one frame or propagated over P1 frames. Each IT group is also divided into more than one IT block (NTI), where each IT block
TI corresponds to a memory usage of the time interleaver. TI blocks within the TI group may contain slightly different XFECBLOCK numbers. If the IT group is divided into multiple IT blocks, it is directly mapped to only one frame. There are three 5 options for time lapse (except for the additional option to skip time lap) as shown in the following table 33.
[467] Table 33
[Table 33]
<td rowspan="4">10 fifteen • twenty [ d c</td><td>Modes</td><td>Descriptions</td><td rowspan="4">) CK of of</td>
<td>Option 1</td><td>Each TI group contains one TI block and is mapped directly into a frame as shown in (a). This option is signaled in the PLS2-STAT by DP TI TYPE = 'O' and DP TI LENGTH = '1' (N<sub>T</sub>i = l).</td>
<td>Option 2</td><td>Each TI group contains one TI block and is mapped on more than one frame, (b) shows an example where a TI group is mapped on two frames, i.e. DP_TI_LENGTH = '2' (PI = 2) and DP_FRAME_INTERVAL (Isalto = 2). This provides greater time diversity for low data rate services. This option is signaled in the PLS2-STAT by DP TI TYPE = 'l'.</td>
<td>Option 3 468] and enter < odification</td><td>Each TI group is divided into multiple TI blocks and directly mapped into a frame as shown in (c). Each TI block can use entire TI memory, to provide the maximum bit rate for one DP. This option is signaled in the PLS2STAT signaling by DP TI TYPE = W 'and DP. TI LENGTH = N<sub>T</sub>t In reed DP, —the — Ti memory — stores the XFECBLC while P<sub>z</sub> = 1). da (the output XFECBLOCKs of the SSD / MIMO block). Assume that the XFECBLOCK</td>
input are defined as
[469] id <sub>nn</sub>, d <sub>nv</sub> ,, d,<sub>n</sub>, ..., d,<sub>v</sub> d „, ,,<sub>n</sub>, ..., d <sub>v</sub> ,, A 'V, Q, 0' ηΑ · θ <1 '' ί ^, ΟΛαΒ, -Ι '«J.1.0' '. η, ί, Ι, Λ ^, - Ι '' η ^^ Βζχχχ_π ('<sup>,</sup>.·<sup>ί</sup>Η Ο ''
[470] where d<sub>n</sub>,<sub>s</sub>,<sub>r</sub>, q is the nth cell of r<sup>esima</sup> XFECBLOCK in the s<sup>esima</sup> n IT block<sup>esima</sup> IT group and represents the results of SSD and MIMO encodings as follows [471] /, the result of SSD encoding <sub>7</sub> ns ^ rq <sup>1</sup> a - <nsfc¡ '' Sn, s, rg? the result of MIMO encoding
[472] Also, assume that the XFECBLOCKs of the 5050 time interleaver are defined as
[473] (Λζ, ί, Ο '' '· *' fyw '* * *' ^ η ^, Ν<sub>χΒΕΟ (ΖΚ</sub>_<sub>YOU</sub>{n, s ^ N<sub>cells</sub>-\ )
[474] where h<sub>n</sub>,<sub>s</sub>, ij is the i<sup>esima</sup> output cell (for i = 0, .. N ~<sub>jnCK T</sub>r (n, s) x N ..
'' xBLOCk_TI \ 'J Cells) <sub>in the</sub> gCsima <sub>Block of</sub>
IT of the n<sup>esima</sup> IT group.
[475] Typically, the time interleaver will also act as a buffer for DP data prior to the framing process. This is accomplished by means of two memory banks for each DP. The first IT block is written to the first bank. The second TI block is written to the second bank while the first bank is read, and so on. ·
[476] The TI is a twisted row-column block interleaver. For the s-th TI block of the n-th TI group, the number of rows N<sub>r</sub> of a TI memory is equal to the number of cells N<sub>EC</sub>idas, that is, N<sub>r</sub>= N<sub>EC</sub>gone while the number of columns N<sub>EC</sub>idas equals the number of Nx<sub>B</sub>lock_ti (n, s).
[477] FIGURE 26 shows a parity check matrix of a QC-IRA (quasi-cyclic irregular repeat accumulation) LDPC code.
[478] The above-described LDPC encoder can encode a parity of an LDPC encoding block 10 using the parity check matrix.
[479] The parity check matrix according to the present invention is a parity check matrix of the QC-IRA LDPC code and can be in the form of a quasi-cyclic matrix called the H matrix and is represented as Hgc .
[480] (a) shows a parity check matrix in accordance with one embodiment of the present invention. As shown in (a), 'the parity check matrix is a matrix that has a horizontal size of Qx (K + M) and a vertical size of QxM and can include an information part and a parity part. The information part can include an array that has a horizontal size of QxK and a vertical size of QxM, and the parity part can include an array that has a horizontal size of QxM and a vertical size of QxM. In this case, a rate of
100 LDPC encoding corresponds to K / (K + M).
[481] The parity check matrix according to one embodiment of the present invention may include randomly distributed 1's and 0's and may be referred to as an edge.
The position of 1 in the parity check matrix, that is, the position of each edge can be represented as a circulating sub-matrix shifted identity matrix having a horizontal size of Q and a vertical size of Q. That is, A submatrix can be represented as a circulating shifted identity matrix QxQ that includes only 1 and 0. Specifically, the submatrix according to an embodiment of the present invention is represented as identity matrices Ix including 10, II, 12, II ..., having different positions of 1 according to the number of circulating shifts. The number of sub-matrices according to one embodiment of the present invention can be (K + M) xM.
[482] (b) shows circulating displaced identity matrices Ix representing subarrays according to one embodiment of the present invention.
[483] The subscript x of Ix indicates the number of circulating displacements of columns of a circulating displaced identity matrix. That is, II represents an identity matrix in which the columns are circularly shifted once and 12 represents a matrix of
101 identity in which the columns circulate twice. IQ, which is an identity matrix, shifts in a circulating way Q times that corresponds to the total number of columns, Q, can be the same matrix as 10 due to its circulating characteristics.
[484] 10 + 2 represents a submatrix that corresponds to a combination of two circulating displaced identity matrices. In this case, the sub-matrix corresponds to a combination of the identity matrix 10 and a circulating displaced identity matrix twice.
[485] II represents a circulating displaced identity matrix in which the edge of the last column of the corresponding submatrix, ie 1 has been removed while corresponding to the submatrix II.
[486] The parity part of the QC-IRA LDPC code parity check matrix can include only sub-matrices 10 and II and the position of sub-matrices 10 can be fixed. As shown in (a), the subarrays 10 can be distributed in a diagonal direction in the parity part.
[487] An edge in the parity check matrix represents that the corresponding row (checksum node) and corresponding column (variable node) are physically connected. In this case, the number of 1 included in each column (variable node) can be referred to as degree
102 and columns can have the same degree or different degrees. Therefore, the number, positions and x-value of the identity matrices Ix representing the edges grouped by sub-matrix are important factors in determining the LDPC coding performance of QC-IRA and unique values can be determined by coding rate.
[488] (c) shows a base matrix of the parity check matrix according to an embodiment of the present invention. The base matrix represents only the number 10 and positions of the identity matrices Ix as specific numbers, ignoring the x value of Ix. As shown in (c), a base matrix can have a horizontal size of K + M and a vertical size of M and is represented as Hbase. When Ix is not a matrix that corresponds to the combination of 15 sub-matrices, the position of the corresponding sub-matrix can be represented as 1. When a sub-matrix is represented as 10 + 2, this sub-matrix is a matrix that corresponds to a combination of two matrices circulating displaced identity cards. and thus the submatrix 20 needs to be discriminated from a submatrix represented as a circulating displaced identity matrix. In this case, the position of the submatrix can be represented as 2 which is the number of the combined circulating displaced identity matrices. In the same way, the position of 25 a sub-matrix that corresponds to a combination of N matrices
103 circulating displaced identity cards can be represented as N.
[489] FIGURE 27 shows a process for encoding the QC-IRA LDPC code in accordance with one embodiment of the present invention.
[490] The QC-IRA LDPC code can be sub-matrix encoded, distinguished from conventional sequential encoding, to reduce processing complexity.
[491] (a) shows the arrangement of a QC-IRA parity check matrix in a QC form. The QC-IRA parity check matrix can be divided into 6 regions A, B, C, D, E, and T when arranged in QC form. When an information vector of QxK s, a parity vector pl that has a length of Q and a parity vector p2 that has a length of Qx (Ml) are used, a codeword x can be represented as x = {s , pl, p2}.
[492] When the Richardson efficient coding math cipher is used, the codeword x can be obtained by directly acquiring p and p2 from the parity check matrix arranged in the form of QC. Richardson's efficient coding mathematical figure is as follows.
[493] Mathematical Number 9
[Mathematical Equation 9]
104 φ = -ΕΤ ~ 'Β + D = - ^ (- ΕΤ ^ Α + CV
Ρ2 = -T - '(As<sup>r</sup> + ΒρΓ)
[494] (b) shows matrices φ
<img file="MX352013B_D0006.tif" />
Derivatives according to the efficient coding mathematical figure.
[495] As shown in (b),
<img file="MX352013B_D0007.tif" />
can be represented as a lower left (sub) triangular matrix. The parity vector p2 can be obtained by calculating s and pl according to the mathematical figure described above. When the parity matrix of QC-IRA is coded according to the mathematical Richardson efficient coding figure, at least Q parity nodes can be processed simultaneously in parallel according to the characteristics of a sub-matrix of QxQ.
[496] FIGURES 28 to 31 illustrate a process for sequentially encoding the QC-IRA LDPC code in accordance with one embodiment of the present invention. This sequential encoding may correspond to the aforementioned LDPC encoding.
105
[497] FIGURE 28 illustrates a parity check matrix permutation process in accordance with one embodiment of the present invention.
[498] (a) shows a QC-IRA H1 LDPC parity check matrix arranged in the form of a QC. As shown in (a), a parity part of matrix H1 may include subarrays distributed in a staggered fashion, which corresponds to the QC-IRA LDPC parity check matrix described above. To easily perform sequential coding, rows and columns of matrix H1 are moved so that matrix H1 is modified into matrix H2 in accordance with one embodiment of the present invention.
[499] (b) shows modified matrix H2. As shown in (b), a parity part of matrix H2 can include a double diagonal matrix. In this case, a row and column applied by applied row and column permutation math figure is as follows.
[500] Mathematical Figure 10
[Mathematical Equation 10] = (r. + Where r, = 0.X2 ..... OM-1 c<sub>t</sub> = {(te, -OOmodíW + [te, -OXWj ♦ where ς = Μ +1 ... A'í -1
[501] According to the above permutation mathematical figure, the rx-th row of matrix H1 can move to the ry-th row of matrix H2 and the cx-th column of matrix H1 can move to cy- th column of the matrix
106
Η2. In this case, the column permutation can be applied only to one parity processing period (QK ^ cx ^ Q (K + M) 1) and the LDPC code characteristics can be maintained even if permutation is applied.
[502] FIGURE 29 is a table showing addresses of the parity check matrix in accordance with one embodiment of the present invention.
[503] The table shown in FIGURE 29 represents a parity check matrix (or matrix H) having a codeword length of 16200 and a code rate of 7/15. The table represents addresses of 1 in the parity check matrix. In this case, the table according to an embodiment of the present invention may be referred to as addresses of a parity check matrix.
[504] In the table of (a), i indicates the blocks generated when the length of the matrix H or codeword times the length of a sub-matrix. A sub-matrix according to one embodiment of the present invention is a 360x360 20 matrix having a codeword length of 16200, and in this way the number of blocks can be obtained by dividing 16200 by 360. Each block can be indicated sequentially starting from 0. Therefore, i can have a value in the range from 0 to 44. Also, i can indicate bit of 25 information that corresponds to the first column in each
107 block.
[505] (b) shows the positions (or directions) of 1 (or edges) in the first column in [506] The matrix H can using all rows and next mathematical figure 11 is [507] Mathematical Figure 11 [Mathematical Equation 11] r = [z (/. /) / Q jx O + (> '(;. 4 · m) moc O c - i xQ + m jxj the largest integer less than or equal to x / = l ... .loníWdex © .77-0 ..... O - IO = 36'J each block.
be represented as H (r, c) columns of it.
used to derive H (r,
0, sf = 0 and c = 16199
The
[508] In the mathematical figure, X (i, j) represents the jth value of the i-th line in the table. Specifically, x (0,0) = l, x (0,1) = 158 and x (l, 0) = l, which corresponds to the positions of the rows that have 1 (or directions of 1) that correspond to the i-th line of matrix H. In this case, maximum values of r and c can be 9719 and 16199, respectively.
[509] The performance of the LDPC code may depend on the distribution of the degrees of nodes of the parity check matrix, the circumference according to the positions of 1 or edges of the parity check matrix, cyclic characteristic, connection between nodes
108 check and variable nodes, etc. The matrix H shown optimizes the node degree distribution in the case of the 16200 codeword, Q = 360 and encoding rate = 6/15 and optimizes the 1 or edge positions under the optimized degree distribution condition, Q and encoding rate.
[510] Matrix H configured according to the table has the QC-IRA LDPC structure described above. Hqc can be obtained using H (r, c) derived using the mathematical figure and a base matrix Hbase can be derived from Hqc.
[511] Furthermore, the matrix H according to one embodiment of the present invention may include a matrix H in a different one of, which has the same degree distribution as the lengths of x (i) (or degrees of corresponding variable nodes ) from the table shown in FIGURE 4. Furthermore, when a transmitter performs encoding using the corresponding matrix H, the efficient encoding described above for QC-IRA LDPC can be employed.
[512] Consequently, a transmitting side can implement an encoder having high encoding performance, low complexity and high throughput, and a receiving side can perform parallel decoding up to 360 level using Q and effectively design a receiver. with high production using the proposed matrix H.
109
[513]
The following table 34 shows the distribution of degrees.
[514]
Table 34
[Table 34]
<td>Variable node degree</td><td> 24</td><td> 4</td><td> 3</td><td> 2</td>
<td>(# of variable node) / Q</td><td> 4</td><td> 9</td><td> 8</td><td> 24</td>
[515] When i is 0 to 3, the numbers from 1 in the 0-th block to the 3-th block are 24. Therefore, when the variable node degree is 24, the number of blocks having the same degree is represented as 4. When i corresponds to 21 to 44, the numbers from 1 in the twenty-one 10 block to the forty-four block are 2. Therefore, when the variable node degree is 2, the number of blocks that has the same degree is 24. As described above, since the parity part of the matrix H includes only sub-matrices represented as 10 distributed diagonally in a staggered fashion, the variable node degree is always 2. Therefore, the blocks that have a variable node degree of 2 can be considered as blocks that correspond to the parity part. The number of real variable nodes corresponding to each node degree
110 variable can be obtained by multiplying the number of blocks shown in the table by Q of the submatrix.
[516] FIGURE 30 is a table showing addresses of the parity check matrix according to another embodiment of the present invention.
[517] The table shown in FIGURE 30 shows the H2 matrix obtained by modifying the HI matrix.
[518] In sequential encoding, the edges used in a parity processing period are typically represented by a mathematical figure and thus the edges can be omitted from the table. That is, blocks that have a degree of 2 that corresponds to the parity part are not represented in the table.
[519] Since the property of the matrix is maintained even if the matrix is modified, as described above, the characteristic of node degree, cycle, circumference, connection between check nodes and variable nodes, etc., is keep. Accordingly, equal coding performance can be obtained, and sequential coding can be performed using matrix H2 according to the table.
[520] FIGURE 31 illustrates a method for sequentially encoding the QC-IRA LDPC code in accordance with one embodiment of the present invention.
[521] When the parity check matrix is
111 modified in matrix H2 through the permutation process described above, the sequential encoding can be performed through updating each parity checksum using the information bits of a code word and updating checksum between the parity checksums.
[522] As shown in FIGURE 31, the codeword can be represented using the QK information bits and the QM parity checksums. The information bits can be represented as iz according to position, and parity checksums can be represented as ps.
[523] A process of updating parity checksums through the information bits 15 can be represented by the following mathematical figure 12.
[524] Mathematical Number 12
[Mathematical Equation 12]
P<sub>w</sub> = p<sub>w</sub> Φ i<sub>z</sub> ... (1) w = {iz + (zmodO) Mmod (ÚW) where z = 0,1,2, ..., C7 / Í-1 '
[525] Here, iz represents a z-th bit of information and pw denotes a parity checksum that needs to be updated using iz. The mathematical figure (1) represents that the parity checksum pw corresponds to the w-th row is updated through a
112 XOR operation performed on the z-th information and parity checksum pw. According to the mathematical figure (2), the position of w is calculated using the table described above representing the matrix H2. Here, v 5 indicates a number that corresponds to each row in the table that represents matrix H2. As described in the above, a row in the table representing the matrix H2 corresponds to the position of a block generated when the length of the matrix H or codeword is divided by the length of the sub-matrix. Accordingly, the information processing period shown in FIGURE 6 is divided by the sub-matrix length Q and then the row numbers corresponding to each Q-th iz are read. With the completion of the checksum update using the 15 information bits of the information processing period, the checksum update of the parity processing period can be performed. The checksum update of the parity processing period can be represented by the following mathematical figure 13.
[526] Mathematical Figure 13
[Mathematical Equation 13]
P<sub>s</sub> = p<sub>s</sub> © p<sub>s</sub>_y where S = 1, 2, .., QM - 1
[527] When S is 0, the parity checksum corresponds to the parity pO and the parity values from pl to
113 pQM-1 can be derived sequentially through XOR operations performed on the parity values and the parity values immediately before them.
[528] FIGURE 32 illustrates an LDPC decoder according to one embodiment of the present invention.
[529] The LDPC decoder 700 in accordance with one embodiment of the present invention may include a variable node update block 710, a check node update block 720, a barrel shift block 730, and a block 740 of check sum. Each block will now be described.
[530] Variable node block 710 may update each variable node in matrix H using an input from the LDPC decoder and a message distributed across 15 edges of the check node block.
[531] Check node block 720 may update a check node of matrix H using a message transmitted across the edges of a variable node. A node update algorithm according to an embodiment of the present invention may include product of addition algorithm, belief propagation algorithm, min-sum algorithm, modified min-sum algorithm, etc., and can be changed from agreement with the designer. Furthermore, since the connection between the variable nodes and the check nodes is represented in the form of
114 A circulating identity matrix of QxQ due to the characteristics of the QC-IRA LDPC messages, Q between variable nodes and the check node block can be processed simultaneously in parallel. The barrel displacement block 730 can control the circulating connection.
[532] Checksum block 740 is an optional block that hard decides a decoding message for each variable node update and performs the parity checksum operation to reduce the number of decoding interactions required. for bug fixes. In this case, the LDPC decoder 700 according to one embodiment of the present invention can produce a final LDPC decode output through the timing decision even if the checksum block 740 permanently decides the decoding message.
[533] FIGURE 33 illustrates a frequency interleaving in accordance with one embodiment of the present invention.
[534] FIGURE 33 illustrates basic operation of the
Frequency Interleaver using two memory banks in the transmitter, which allows de-interleaving of a single memory in the receiver.
[535] (a) shows the demultiplexing process, (b) shows the interleaving process and (c) shows the process of
115 multiplexing.
[536] In FIGURE 33 two memory banks are used for each pair of OFDM symbols. Operationally, the first pair of OFDM symbols (indexed - in pairs) is interleaved in memory bank A, while the second pair of OFDM symbols (indexed in nones) is interleaved in memory bank B, etc., alternating between A and B. The DEMUX and MUX blocks control the input sequential OFDM symbols that are interleaved, and the produced pair of 10 OFDM symbols will be transmitted, respectively.
Different germline values of interleaving are used for each pair of OFDM symbols.
[537] FIGURE 34 illustrates is a flow chart illustrating a method for transmitting broadcast signals in accordance with one embodiment of the present invention.
[538] The apparatus for transmitting broadcast signals according to an embodiment of the present invention can encode service data (S34000). As described in the above, the service data is transmitted through a data channel which is a logical channel in the physical layer that carries data and related services or metadata, which can carry one or more services or components of services. The data transported in a data channel can be referred to as the DP data or the service data.
The detailed process of step S34000 is as described
116 in FIGURES 1, 5, 22 to 26, 32.
[539] As described in FIGS. 26 to 32, the apparatus for transmitting broadcast signals according to an embodiment of the present invention can encode a parity of an LDPC encoding block using the parity check matrix. Also, the FEC structure according to one embodiment of the present invention before bit interleaving by using the FEC encoding parameters for a long FECBLOCK and a short FECBLOCK.
[540] The apparatus for transmitting broadcast signals according to an embodiment of the present invention can form at least one signal frame according to the encoded service data (S34010). The detailed process of step S33010 is as described in FIGURES 7, 10 to 11, 16 to 21.
[541] Then, the apparatus for transmitting broadcast signals according to an embodiment of the present invention can modulate data in the formation of at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplexing) scheme (S34020) . The detailed process of this stage is as described in FIGURE 1 and FIGURE 8.
[542] Sequentially, the apparatus for transmitting broadcast signals according to one embodiment of the
117 The present invention can transmit the broadcast signals that include at least one modulated signal frame (S34030). The detailed process of this stage is as described in FIGURE 1 and FIGURE 8.
[543] FIGURE 35 is a flow chart illustrating a method for receiving broadcast signals in accordance with one embodiment of the present invention.
[544] The flow diagram shown in FIGURE 35 corresponds to a reverse process of the method of transmitting 10 broadcast signals according to an embodiment of the present invention, described with reference to FIGURE 34.
[545] The apparatus for receiving broadcast signals according to an embodiment of the present invention can receive the broadcast signals. (S35000).
[546] The apparatus for receiving broadcast signals according to an embodiment of the present invention can demodulate received broadcast signals using an OFDM (Orthogonal Frequency Division Multiplexing) scheme (S35010). The detailed process of this stage is as described in FIGURE 9 ..
[547] The apparatus for receiving broadcast signals according to an embodiment of the present invention can analyze at least one signal frame of the demodulated broadcast signals. (S35020). Details are as described in FIGURE 9. Also, the signal frame of
118 According to one embodiment of the present invention it has a structure described in FIGS. 11 to 21.
[548] Sequentially the apparatus for receiving broadcast signals according to an embodiment of the present invention can decode service data in at least one analyzed signal frame (S35030). Details are as described in FIGURE 9. As described in the above, the service data is transmitted through a data channel which is a logical channel in the physical layer that carries data and related services or metadata, which can carry one or multiple services or service components. . The data carried in a data channel can be referred to as DP data or the service data.
[549] FIGURE 36 illustrates the basic operation of a twisted row-column block interleaver in accordance with one embodiment of the present invention.
[550] '(a) shows a write operation in the time interleaver and (b) shows a read operation in the time interleaver. The first XFECBLOCK is written by columns to the first column of TI memory, and the second XFECBLOCK is written to the next column, and so on as shown in (a). Then, in the interleaving arrangement, the cells are read diagonally. During the diagonal reading of the first row (directly along the row beginning with the
119 leftmost column) to the last row, cells are read as shown in (b). In detail, assuming<sub>z</sub>n, s, i (i = 0, ..., N<sub>r</sub>N<sub>c</sub>) as the TI memory cell portion that is read sequentially, the reading process in such an interleaving arrangement is done by calculating the row index <sub>Rn</sub>,<sub>s</sub>, i, the column index Cn, s, i, and the associated twist parameter Tn, s, i as in the following expression.
[551] Mathematical Figure 14
[Mathematical Equation 14]
GENER.4TE (R „<sub>X</sub> = mod (/<sub>;</sub>Aj.).
T<sub>ns</sub>, -modíSC ^ .xR<sub>nj</sub>, N<sub>and</sub>),
C<sub>ns</sub>. - mod ^ ,. +
X,)
[552] where S<sub>sh</sub>ift is a common offset value for the process of reading diagonally from N<sub>XBLO</sub>ck_ti (n, s), and this is determined by N<sub>xB</sub>lock_ti_mm given in the PLS2-STAT as in the following mathematical figure.
[553]
Mathematical Figure 15
[Math Equation 15] for ^ xBLOCK n ~ ^ iBIOCK TI MAX <sup>+</sup>1’ <sup>S</sup>^ XBLOCX TI MAX ^ 0 (12 = 0 ^ xBiOCK TI .MAX ~ ^ xBLOCK TI.MAX '^ .rBLOCKΠ.ΜΑΧ = I xBLQCK Tl JUAX <sup>1</sup>
120
[554] As a result, the cell positions that are read are calculated by a coordinate such as Z<sub>n</sub>,<sub>s</sub>, i = N<sub>r</sub>C<sub>n <s</sub>, i + R<sub>n</sub>,yes.
[555] FIGURE 37 illustrates an operation of a twisted row-column block interleaver in accordance with another embodiment of the present invention.
[556] More specifically, FIGURE 37 illustrates the interleaving arrangement in TI memory for each TI group, including virtual XFECBLOCK when N<sub>xBLO</sub>ck_ti (0,0) = 3, Nxblock_ti (1,0) = 6, N<sub>xBL</sub>ock_ti (2,0) = 5.
[557] The variable number N<sub>xBL</sub>ock_ti (n, s) = N<sub>r</sub>, will be less than or equal to N<sub>xB</sub>lock ti_max · In this way, to achieve a single memory deinterleaving on the receiver side, regardless of N<sub>xBLO</sub>ck_ti (n, s), the interleaving arrangement for use in a crooked row-column block interleaver is set to the size of N<sub>r</sub> x N<sub>c</sub> = N<sub>EC</sub>ii<sub>s</sub> x N<sub>x</sub>block_ti_max for inserting virtual XFECBLOCKs into TI memory and the reading process is achieved as in the following mathematical figure.
[558] Mathematical Figure 16
[Mathematical Equation 16] p = 0;
for ¡= o, í <„« «u - * *।
Yes n (ns) i 2. ,,, =<sup>l</sup>j; ^ = ^ + 1; ))
121
[559] The number of TI groups is set to 3. The time interleaver option is signaled in the PLS2-STAT data by DP_TI_TYPE = '0', DP_FRAME_INTERVAL = '1', and DP TI LENGTH = '1' , that is, N<sub>YOU</sub> = 1, I<sub>JUM</sub>p = 1 / and Pl = 1. The 5 number, of XFECBLOCK, of which each has N<sub>EC</sub>i<sub>you give</sub> = 30, per IT group is indicated in the PLS2-DYN data by N<sub>x</sub>block_ti (0,0) = 3, Nxblockjti (1 r 0) <sup>=</sup> 6, N<sub>xBL</sub>ock_ti (2,0) = 5, respectively, the maximum number of XFECBLOCK is signaled in the PLS2-STAT data by N<sub>xB</sub>LocK_Groy<sub>P</sub>_MAxr which leads to
[560] FIGURE 38 illustrates a diagonal reading pattern of a twisted row-column block interleaver in accordance with one embodiment of the present invention.
[561] More specifically, FIGURE 28 shows a diagonal reading pattern of each array of 15 interspersed with parameters of N<sub>xBLO</sub>ck_ti_max = 7 and S<sub>sh</sub>if<sub>t</sub> = (7-1) / 2 = 3. Notice that in the reading process shown in the _Group _ M4X 'TI J <sup>=</sup> xfíLOCK _TJ _MAX <sup>=</sup> θ above pseudocode, if Vi N<sub>C</sub>eiisNx<sub>B</sub>LocK_Ti (n, s), the value of Vi is skipped and the next calculated value of Vi is used.
[562], FIGURE 39 illustrates XFECBLOCK interleaves of each interleaving arrangement in accordance with one embodiment of the present invention.
[563] FIGURE 39 illustrates the interleaved XFECBLOCKs of each interleaving arrangement with parameters of N<sub>xBL</sub>ock_ti_max
122
- 7 and S<sub>s</sub>hift 3.
[564] FIGURE 40 is a table showing addresses of the parity check matrix according to another embodiment of the present invention.
[565] The table shown in FIGURE 40 represents a parity check matrix (or matrix H) having a codeword length of 16200 and a code rate of 7/15. The details in the table are the same as the details described in FIGURE 29. The following table shows the grade distribution.
[566] Table 35
[Table 35]
<td>Variable node degree</td><td> 23</td><td> 8</td><td> 3</td><td> 2</td>
<td>(# of variable node) / Q</td><td> 3</td><td> 5</td><td> 13</td><td> 24</td>
[567] When i is 0 to 2, the numbers from ones in the 0th block to the second all block are 23. Therefore, when the variable node degree is 23, the number of blocks having the same degree is represented as 3 When i corresponds to 3 to 7, the numbers from ones in the third block to the seventh block 8. Therefore, when the variable node degree is 8, the number of blocks that
123 has the same degree is 5. As described above, since the parity part of matrix H includes only sub-matrices represented as 10 distributed diagonally in a staggered fashion, the variable node degree 5 is always 2. By Therefore, the blocks having a variable node degree of 2 can be considered as blocks corresponding to the parity part. The number of real variable nodes that corresponds to each variable node degree can be obtained by multiplying the number of blocks 10 shown in the table by Q of the submatrix.
[568]
[569] FIGURE 41 is a table showing addresses of the parity check matrix according to another embodiment of the present invention.
[570] The table shown in FIGURE 41 shows the matrix
H2 obtained by modifying the HI matrix.
[571] In sequential encoding, the edges used in a parity processing period are typically represented by an equation and in this way the edges 20 can be omitted from the table. That is, 24 blocks that have a grade of 2 corresponding to the parity part are not represented in the table.
[572] Since the property of the matrix is maintained even if the matrix is modified, as described in the previous 25, the characteristic of node degree, cycle,
124 circumference, connection between check nodes and variable nodes, etc., are maintained. Accordingly, the same coding performance can be obtained and sequential coding can be performed using the 5 H2 matrix according to the table.
[573] It will be appreciated by those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, the present invention is intended to cover modifications and variations of this invention as long as they fall within the scope of the appended claims and their equivalents.
[574] The invention of the apparatus and method is mentioned in this description and the descriptions of both inventions of the apparatus and method can be applied in a complementary manner to each other.
Mode for Invention
[575] Various modalities have been described in best mode for carrying out the invention.
Industrial Applicability
[576] The present invention is available in a number of broadcast signal arrangement fields.
[577] It will be apparent to those of experience in the
125 technical that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, the present invention is intended to cover modifications and variations of this invention as long as they fall within the scope of the appended claims and their equivalents.
126
Contents6
35 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35
203 members in 7 offices
Priority claims29
| Document | Office | Kind | Date |
|---|---|---|---|
| 201361861379 | United States of America | P | |
| 201361861379 | United States of America | P | |
| 61861379 | United States of America | – | |
| 201361876713 | United States of America | P | |
| 201361876713 | United States of America | P | |
| 61876713 | United States of America | – | |
| 201361881418 | United States of America | P | |
| 201361881418 | United States of America | P | |
| 61881418 | United States of America | – | |
| 201361882012 | United States of America | P | |
| 201361882012 | United States of America | P | |
| 61882012 | United States of America | – | |
| 201361883957 | United States of America | P | |
| 201361883957 | United States of America | P | |
| 61883957 | United States of America | – | |
| 2014007132 | Republic of Korea | W | |
| 2014007132 | Republic of Korea | W | |
| 61861379 | – | – | – |
| 61876713 | – | – | – |
| 61881418 | – | – | – |
| 61882012 | – | – | – |
| 61883957 | – | – | – |
| PCTKR2014007132 | – | – | – |
| US201361861379P | – | – | – |
| US201361876713P | – | – | – |
| US201361881418P | – | – | – |
| US201361882012P | – | – | – |
| US201361883957P | – | – | – |
| WO2014KR07132 | – | – | – |
Members203
| Document | Office | Kind | |
|---|---|---|---|
| US2014314177A1 | United States of America | A1 | |
| WO2014175606A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016661A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016662A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016663A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016664A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016665A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016666A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016668A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016669A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016670A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016671A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016672A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016673A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016674A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2015016676A1 | World Intellectual Property Organization (WIPO) | A1 | |
| US2015092881A1 | United States of America | A1 | |
| WO2015046886A1 | World Intellectual Property Organization (WIPO) | A1 | |
| US9191082B2 | United States of America | B2 | |
| CN105075208A | China | A | |
| EP2957083A1 | European Patent Office (EPO) | A1 | |
| KR20160002666A | Republic of Korea | A | |
| US2016049998A1 | United States of America | A1 | |
| KR20160019544A | Republic of Korea | A | |
| KR20160019545A | Republic of Korea | A | |
| KR20160021252A | Republic of Korea | A | |
| KR20160021253A | Republic of Korea | A | |
| KR20160021254A | Republic of Korea | A | |
| KR20160021255A | Republic of Korea | A | |
| KR20160023803A | Republic of Korea | A | |
| KR20160023846A | Republic of Korea | A | |
| KR20160023847A | Republic of Korea | A | |
| KR20160024931A | Republic of Korea | A | |
| KR20160024955A | Republic of Korea | A | |
| KR20160024956A | Republic of Korea | A | |
| CN105453506A | China | A | |
| CN105453548A | China | A | |
| CN105453549A | China | A | |
| CN105453550A | China | A | |
| CN105453551A | China | A | |
| CN105453552A | China | A | |
| CN105453553A | China | A | |
| MX2016001355A | Mexico | A | |
| CN105493461A | China | A | |
| CN105519100A | China | A | |
| CN105531993A | China | A | |
| CN105531994A | China | A | |
| KR20160045799A | Republic of Korea | A | |
| CN105580377A | China | A | |
| CN105637859A | China | A | |
| EP3028426A1 | European Patent Office (EPO) | A1 | |
| EP3028427A1 | European Patent Office (EPO) | A1 | |
| EP3028448A1 | European Patent Office (EPO) | A1 | |
| EP3028449A1 | European Patent Office (EPO) | A1 | |
| EP3028450A1 | European Patent Office (EPO) | A1 | |
| EP3028451A1 | European Patent Office (EPO) | A1 | |
| EP3028452A1 | European Patent Office (EPO) | A1 | |
| EP3028453A1 | European Patent Office (EPO) | A1 | |
| EP3028454A1 | European Patent Office (EPO) | A1 | |
| EP3028455A1 | European Patent Office (EPO) | A1 | |
| EP3028456A1 | European Patent Office (EPO) | A1 | |
| EP3028457A1 | European Patent Office (EPO) | A1 | |
| EP3028458A1 | European Patent Office (EPO) | A1 | |
| EP3028460A1 | European Patent Office (EPO) | A1 | |
| US2016164628A1 | United States of America | A1 | |
| US2016164630A1 | United States of America | A1 | |
| US2016164634A1 | United States of America | A1 | |
| US2016164635A1 | United States of America | A1 | |
| US2016164648A1 | United States of America | A1 | |
| US2016165269A1 | United States of America | A1 | |
| US2016165273A1 | United States of America | A1 | |
| US2016165274A1 | United States of America | A1 | |
| US2016173181A1 | United States of America | A1 | |
| US2016173312A1 | United States of America | A1 | |
| US2016191081A1 | United States of America | A1 | |
| US2016191289A1 | United States of America | A1 | |
| US2016192026A1 | United States of America | A1 | |
| US2016197688A1 | United States of America | A1 | |
| EP3050303A1 | European Patent Office (EPO) | A1 | |
| EP3028426A4 | European Patent Office (EPO) | A4 | |
| EP3028451A4 | European Patent Office (EPO) | A4 | |
| JP2016533082A | Japan | A | |
| US9503167B2 | United States of America | B2 | |
| EP2957083A4 | European Patent Office (EPO) | A4 | |
| US2017026141A1 | United States of America | A1 | |
| US9571127B2 | United States of America | B2 | |
| KR20170018486A | Republic of Korea | A | |
| KR101714445B1 | Republic of Korea | B1 | |
| EP3028427A4 | European Patent Office (EPO) | A4 | |
| EP3028450A4 | European Patent Office (EPO) | A4 | |
| EP3028454A4 | European Patent Office (EPO) | A4 | |
| EP3028458A4 | European Patent Office (EPO) | A4 | |
| US9614760B2 | United States of America | B2 | |
| EP3028452A4 | European Patent Office (EPO) | A4 | |
| EP3028460A4 | European Patent Office (EPO) | A4 | |
| EP3028449A4 | European Patent Office (EPO) | A4 | |
| EP3028453A4 | European Patent Office (EPO) | A4 | |
| EP3028455A4 | European Patent Office (EPO) | A4 | |
| EP3028456A4 | European Patent Office (EPO) | A4 | |
| EP3028457A4 | European Patent Office (EPO) | A4 |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Grant or registrationFG | FG |
Numbers
- Publication
- 352013
- Publication, DOCDB
- 352013
- Publication, EPODOC
- MX352013
- Application
- 2016001355
- Application, DOCDB
- 2016001355
- Application, EPODOC
- MX20160001355
Titles2
- Spanish
- APARATO PARA TRANSMITIR SEÑALES DE DIFUSIÓN, APARATO PARA RECIBIR SEÑALES DE DIFUSIÓN, MÉTODO PARA TRANSMITIR SEÑALES DE DIFUSIÓN Y MÉTODO PARA RECIBIR SEÑALES DE DIFUSIÓN.
- English
- APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS.
Classification
- CPC, 16
- H04L1/0057
- H04L5/0023
- H04L1/0071
- H04L27/2626
- H04L27/2647
- H04L2001/0093
- H04L1/0041
- H04L1/0042
- H04L27/2602
- H04L27/2649
- H04B7/0413
- H04L5/0007
- H03M13/2792
- H03M13/616
- H04L12/18
- H04L27/2627
- IPC, 8
- H04B7 02
- H03M13 00
- H03M13 27
- H04B7 04
- H04L1 00
- H04L12 18
- H04L27 26
- H04L5 00