Vector checksum instruction.
Abstract
An instruction of the Vector Checksum. The elements of a second operand are added one by one to obtain a first result. The sum includes performing one or more addition operations with final rounding haul. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

Term
7.2 yearsleft in the term
Expires 4 December 2033.
- Priority
- Filed
- Granted
- Today
- Expires
14 claims: 4 independent, 10 dependent
- 1REIVINDICACIONES 1. Un medio de almacenamiento no transitorio legible por computadora para implementar una indicación de la 5 máquina en una unidad de procesamiento central, que comprende un método, el cual comprende:obtener, mediante un procesador, una indicación de la máquina para la implementación, la indicación dela máquina se define para la implementación por la computadora 10 de acuerdo con una arquitectura de la computadora,la indicación de la máquina comprende: al menos un campo opcode para proporcionarun opcode, el opcode identifica una operación de Sumade Comprobación del Vector;15 un primer campo del registro a ser utilizado para designar el primer registro, el primer registro comprende un primer operando;un segundo campo del registro a ser utilizado para designar un segundo registro, el segundo registro comprende 20 un segundo operando;y un campo de extensión para ser utilizado al designar uno o más registros, en donde el primer campo de registro se combina con una primera porción del campo de extensión para designar el primer registro, y el segundo 25 campo de registro se combina con una segunda porción del IMPI^ INSTITUTO MEXICANO ^4“ · Dt LA PROFIFDAO INDUSTRIAL campo de extensión para designar el segundo registro;e implementar la indicación de la máquina, la implementación comprendiendo: sumar una pluralidad de elementos del segundo operando para obtener un primer resultado, en donde la suma comprende realizar una o más operaciones de suma con acarreo de redondeo final;basándose en realizar una operación de suma con acarreo de redondeo final y producir una suma, sumar un acarreo de una posición elegida de la suma, si lo hay, a una posición seleccionada en un elemento seleccionado del primer operando;y colocar el primer resultado en el elemento seleccionado del primer operando.
- 2El medio de almacenamiento de conformidad con la reivindicación 1, en donde la posición elegida es la posición del bit cero, la posición seleccionada es la posición del bit 31, y el elemento seleccionado del primer operando es el elemento uno del primer operando.
- 3El medio de almacenamiento de conformidad con la reivindicación 2, en donde la implementación comprende además colocar ceros en uno o más de otros elementos del primer, aperando.
- 4El medio de almacenamiento de conformidad con la reivindicación 3, en donde el primer operando comprende 100 IMPI INSTITUT· MEXICANO DE LA PROPIEDAD INDUSTRIAL cuatro elementos del tamaño de una palabra, y en donde la colocación comprende colocar ceros en los elementos cero, dos y tres del primer operando.
- 5El medio de almacenamiento de conformidad con 5 la reivindicación 1, en donde la pluralidad de elementos del segundo operando comprende una pluralidad de elementos del tamaño de una palabra.
- 6El medio de almacenamiento de conformidad con la reivindicación 1, en donde la indicación de la máquina 10 comprende además un tercer campo del registro a ser utilizado para designar un tercer registro, el tercer registro comprende un tercer operando, y en donde la implementación comprende además sumar el primer resultado a un elemento seleccionado del tercer operando para obtener un segundo 15 resultado, la suma del primer resultado se hace utilizando una operación de suma con acarreo de redondeo final.
- 7El medio de almacenamiento de conformidad con la reivindicación 1, en donde la implementación comprende además sumar el primer resultado a un elemento seleccionado 20 de un tercer operando para obtener un segundo resultado, la suma del primer resultado se hace utilizando una operación de suma con acarreo de redondeo final, y en donde la colocación comprende colocar el segundo resultado en el elemento seleccionado del primer operando. 101 IMPIAS INSTITUTO MEXICANO U**4rj Dt LA PROPIEDAD
- 8El medio de almacenamiento de corí¥SlfF^daa~cc ri la reivindicación 7, en donde el tercer ο^οΓαπ^^ί 'incluye en la indicación de la máquina.
- 9Un sistema de computadora para implementar una indicación de la máquina en una unidad de procesamiento central, el sistema de computadora comprende:una memoria;y un procesador en comunicación con la memoria, en donde el sistema de computadora está configurado para realizar un método, el método comprende: obtener, mediante un procesador, una indicación de la máquina para la implementación, la indicación dela máquina se define para la implementación por la computadora de acuerdo con una arquitectura de la computadora,la indicación de la máquina comprende: al menos un campo opcode para proporcionarun opcode, el opcode identifica la operación de Sumade Comprobación del Vector;un primer campo del registro a ser utilizado para designar el primer registro, el primer registro comprende un primer operando;un segundo campo del registro a ser utilizado para designar un segundo registro, el segundo registro comprende un segundo operando;y un campo de extensión para ser utilizado al 102 IMPI^ INSTITUTO MEXICANO DE LA rXOMEDAD INDUSTRIAL designar uno o más registros, en donde el primer campo de registro se combina con una primera porción del campo de extensión para designar el primer registro, y el segundo campo de registro se combina con una segunda porción del campo de extensión para designar el segundo registro;e implementar la indicación de la máquina, la implementación comprende: sumar una pluralidad de elementos del segundo operando para obtener un primer resultado, en donde la suma comprende realizar una o más operaciones de suma con acarreo de redondeo final;basándose en realizar una operación de suma con acarreo de redondeo final, y producir una suma, sumar un acarreo de una posición elegida de la suma, si lo hay, a una posición seleccionada en un elemento seleccionado del primer operando;y colocar el primer resultado en el elemento seleccionado del primer operando.
- 10El sistema de computadora de conformidad con la reivindicación 9, en donde la posición seleccionada está en la posición del bit cero, la posición seleccionada está en la posición del bit 31, y el elemento seleccionado del primer operando es el elemento uno del primer operando.
- 11El sistema de computadora de conformidad con la reivindicación 9, en donde la pluralidad de elementos del 103 ?ητττ·σο segundo operando comprende una pluralidad de elementos del tamaño de una palabra.
- 12El sistema de computadora de conformidad con la reivindicación 9, en donde la indicación de la máquina comprende además un tercer campo del registro a ser utilizado para designar un tercer registro, el tercer registro comprende un tercer operando, y en donde la implementación comprende además sumar el primer resultado a un elemento seleccionado del tercer operando para obtener un segundo resultado, la suma del primer resultado se hace utilizando una operación suma con acarreo de redondeo final.
- 13El sistema de computadora de conformidad con la reivindicación 9, en donde la implementación además comprende sumar el primer resultado a un elemento seleccionado de un tercer operando para obtener un segundo resultado, la suma del primer resultado se hace utilizando una operación de suma con acarreo de redondeo final, y en donde el la colocación comprende colocar el segundo resultado en el elemento seleccionando del primer operando.
- 14El sistema de computadora de conformidad con la reivindicación 13, en donde el tercer operando se incluye en la indicación de la máquina. 104
Independent claims14
497 paragraphs in 95 sections, as filed
(54) Title: VECTOR CHECK SUM INSTRUCTION.
(54) Title: VECTOR CHECKSUM INSTRUCTION.
(57) Summary
A Vector Checksum instruction. The elements of a second operand are added one by one to obtain a first result. Addition includes performing one or more addition operations with a final round carry. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry from a chosen position of the sum, if any, is added to a selected position on an element of the first operand.
(57) Abstract
A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding ineludes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand. A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand. Front load washing machine (1) with incorporated drying system and heat pump, maintaining the advantage of performing the washing and drying within the size ie the standard overall size for the machines in question. Besides the washing system, the machine comprises a drying system with a heat pump Circuit adapted to condense the air extracted from the washing tub (3) via a condensation group (10) and subsequently reintroduce the air into the tub (3) after heating if via a heating group (11) of the heat pump Circuit. Said condensation and heating steps are actuated by special exchangers arranged centrally and above the washing tub (3) and connected thereto through a series of mouthpieces or fittings for delivery and return, and ventilator means (16) for the circulation of air. Preferably the washing machine is provided with an intermediary filter (19) for collecting impurities. A collection container (17) diverts the condénsate water towards the pump of the machine.
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Institute Π
Mexican T of Property Q ÍljHÍ
Industrial Π ___SE___
SÍCRÍTMIh Dí towé
PATENT TITLE NO. 344922
Headlines)
INTERNATIONAL BUSINESS MACHINES CORPORATION
Home
NewOrchard Road, Armonk, New York, 10504, USA
Denomination;
VECTOR CHECK SUM INSTRUCTION.
Classification lnt.CI.8: G06F9 / 30
Inventor (s)
JONATHAN DAVID BRADBURY; ERIC MARKSCHWARZ
REQUEST
Number:
International filing date:
MX / a / 2015/009457 of December 2013
PRIORITY
Country:
Date:
Number
US January 2013
13/748,495
Validity: Twenty years
Expiration Date: December 4, 2033
The reference patent is granted based on articles 1, 2<sup>or</sup> fraction V, 6<sup>or</sup> Section IB, and 59 of the Industrial Property Law.
In accordance with article 23 of the Industrial Property Law, this patent is valid for twenty years, non-extendable, counted from the filing date of the international application and will be subject to the payment of the fee to keep the rights in force. . .
Whoever signs this title does so based on the provisions of articles 6, sections III and 7<sup>or</sup> bis 2 of the Industrial Property Law (Official Gazette of the Federation (DOF) 06/27/19 Γ, amended on 08/02/1994 10/25/1996, 12/26/1997, 05/17/1999, 01/26/2004 06/16/2005, 01/25/2006, 05/06/2009, 01/06/2010, 06/18/2010, 06/28/2010, 01/27/2012 and 04/09 / 2012); items 1<sup>or</sup>, 3<sup>or</sup> fraction V part a), 4<sup>or</sup> and 12th sections I and III of the Regulations of the Mexican Institute of Industrial Property (DOF 12/14/1999, amended on 07/01/2002, 07/15/2004, 07/28/2004 and 09/07/2007 ); Articles 1, 3<sup>or</sup>, 4<sup>or</sup>, 5<sup>or</sup> Section V subsection a), 16 sections I and III and 30 of the Organic Statute of the Mexican Institute of Industrial Property (DOF 12/27/1999, amended on 10/10/2002, 07/29/2004, 08/04/2004 and 09/13/2007) 1<sup>or</sup>, 3rd and 5th subsections a) of the Agreement that delegates powers to the Deputy General Directors, Coordinator, Divisional Directors, Heads of Regional Offices, Divisional Deputy Directors, Departmental Coordinators and other subordinates of the Mexican Institute of Industrial Property. (DOF 12/15/1999, amended on 02/04/2000, 07/29/2004, 08/04/2004 and 09/13/2007).
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Issue Date: January 11, 2017
THE DIVISIONAL DIRECTOR OF PATENTS
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NAHANNY CANAL REYES
Aren-i No 550. Floor 1.
Coi. Santa María Tepepan town.
Xochimilcc. CP 16020,
Mexico City
Tel. (55) 53 34 07 00 www.impigob.mx
MX / 2017/3956
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IMPI
MEXICAN INSTITUTE OF INDUSTRIAL PROPERTY
VECTOR CHECKS SUM INSTRUCTION
BACKGROUND OF THE INVENTION
One or more aspects relate, in general, to processing within a computing environment, and in particular, to vector processing within such an environment.
Processing within a computing environment includes controlling the operation of one or more central processing units (CPUs). Normally, the operation of a central processing unit is controlled by instructions in storage. The instructions can have different formats and often specify the registers to be used to perform various operations.
Depending on the architecture of the central processing unit, various types of registers can be used, including, for example, general-purpose registers, special-purpose registers, floating-point registers, and / or vector registers, as examples. Different types of registers can be used with different types of instructions. As examples, floating-point registers store floating-point numbers to be used by floating-point instructions; and the 25 vector registers hold the data for the
IMPI
MEXICAN INSTITUTE OF INDUSTRIAL HUMIDITY
<img file="MX344922B_D0005.tif" />
vector processing performed by the instructions of
Single Instruction, Multiple Data (SIMD), including vector instructions.
BRIEF SUMMARY OF THE INVENTION
The disadvantages of the prior art are addressed and advantages are provided through the provision of a computer program product for executing a machine instruction. The computer program product includes a computer-readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform a method. The method includes, for example, obtaining, by a processor, a machine instruction for execution, the machine instruction is defined for execution by the computer according to a computer architecture, the machine instruction includes : at least one opcode field to provide an opcode, the opcode identifies a Vector Checksum operation, a first field of the record to be used to designate the first record, the first record includes a first operand; a second field of the register to be used to designate a second register, the second register includes a second operand and execute the machine instruction, the execution includes: adding a
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IMPI
MEXICAN INSTITUTE
OF INDUSTRIAL PROPERTY plurality of elements of the second operand to obtain a first result, where the addition includes performing one or more addition operations with final rounding carry, based on performing an addition operation with final rounding carry and producing a sum , add a carry from a chosen position of the sum, if any, to the selected position in a selected element of the first operand, and place the first result in the selected element of the first operand.
Methods and systems that relate to one or more aspects are also described and claimed in this document. In addition, services that relate to one or more aspects are also described and can be claimed in this document.
Additional features and benefits are achieved through the techniques of one or more aspects. Other embodiments and aspects are described in detail herein, and are considered part of the claims.
BRIEF DESCRIPTION OF THE VARIOUS VIEWS OF THE DRAWINGS
One or more aspects are particularly indicated and clearly claimed as examples in the claims at the conclusion of the specification. The above and other objects, features and advantages are
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evident from the following detailed description, ____ taken__at _____..., - in conjunction with the accompanying drawings, in which:
Figure 1 describes an example of a computing environment for incorporating and using one or more aspects;
Figure 2A depicts another example of a computing environment for incorporating and using one or more aspects;
Figure 2B describes the additional details of the memory of Figure 2A;
Figure 3 describes an example of a log file;
Figure 4A depicts an example of an Immediate Class Instruction Format of Vector Floating Point Test Data;
Figure 4B describes an example of the bit values of the third operand of the instruction of the Immediate Class of the Floating Point Test Data of the Vector of Figure 4A;
Figure 4C depicts one embodiment of the logic associated with the instruction of the Immediate Class of the Vector Floating Point Test Data of Figure 4A;
Figure 4D describes an example of a block diagram of the instruction execution of the Immediate Class of the Floating Point Test Data of the
Vector of Figure 4A;
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<sup>5</sup> IMPI
INSTITUTO MEXICANO OE LA PROPERTY INDUSTRIAL
Figure 4E depicts an example of a ripf: rH ri An of various kinds of binary floating point data;
Figure 5A depicts an example of a Vector Checksum instruction format;
Figure 5B depicts one embodiment of the logic associated with the Vector Checksum instruction of Figure 5A;
Figure 5C describes an example of a block diagram of the execution of the Vector Checksum instruction of Figure 5A;
Figure 6A depicts an example format of a Multiply, Add and Accumulate Galois Vector Field instruction;
Figure 6B depicts one embodiment of the logic associated with the instruction to Multiply, Add and Accumulate the Galois Vector Field of Figure 6A;
Figure 6C depicts an example of a block diagram of the execution of the instruction Multiply, Add and Accumulate the Galois Vector Field of Figure 6A;
Figure 7A depicts an example of a format for a Generate Vector Mask command;
Figure 7B depicts one embodiment of the logic associated with the Generate Vector Mask command of Figure 7A;
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Figure 7C depicts an example of wa — diagram da ----- blocks of the execution of the Generate Vector Mask instruction of Figure 7A;
Figure 8A depicts an example format of a Rotate Vector Element and Insert Under Mask command;
Figure 8B depicts one embodiment of the logic associated with the instruction to Rotate the Vector Element and Insert It Under the Mask of Figure 8A;
Figure 8C depicts an example of a block diagram of the execution of the instruction to Rotate Vector Element and Insert Under Mask of Figure 8A;
Figure 9A depicts an example of a Vector Exception Code;
Figure 9B depicts one logic mode for setting the Vector Exception Code of Figure 9A;
Figure 10 depicts an embodiment of a computer program product incorporating one or more aspects;
Figure 11 depicts one embodiment of a central computer system;
Figure 12 depicts a further example of a computer system;
Figure 13 depicts another example of a computer system comprising a computer network;
MEXICAN INSTITUTE OF INDUSTRIAL PROPERTY
Figure 14 depicts a multi-element embodiment of a computer system;
Figure 15A depicts one embodiment of the execution unit of the computer system of Figure 14;
Figure 15B depicts one embodiment of the branch unit of the computer system of Figure 14;
Figure 15C depicts one embodiment of the load / storage unit of the computer system of Figure 14; and
Figure 16 depicts one embodiment of an emulated host computer system.
DETAILED DESCRIPTION OF THE INVENTION
In accordance with one or more aspects, a vector function is provided that includes various vector instructions, as well as vector exception processing. Each of the instructions described herein is a Single Instruction, Multiple Data (SIMD) instruction that uses one or more registers of the vector (also referred to herein as vectors). A vector register is, for example, a processor register (also referred to here as a physical elements register), which is a small amount of storage (for example, not main memory), available as part of a processing unit central (CPU) or other processor.
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Each record in the vector contains an operand of the verb -r that has one or more elements, and one element is, for example, one, two, four, or eight bytes long. In other embodiments, the elements can be of other sizes; and a vector instruction need not be a SIMD instruction.
One embodiment of a computing environment for incorporating and utilizing one or more aspects is described with reference to Figure 1. A computing environment 100 includes, for example, a processor 102 (eg, a central processing unit), a memory 104 (for example, main memory), and one or more input / output devices (1/0) and / or interconnections 106 coupled to another path, for example, one or more buses 108 and / or other connections.
In one example, processor 102 is based on the z / Architecture offered by International Business Machines Corporation, and is part of a server, such as the System z server, which is also offered by International Business Machines Corporation and implements the z / Architecture. One embodiment of z / Architecture is described in an IBM publication entitled, z / Architecture Principles of Operation, No. IBM Publication SA22-7832-09, Tenth Edition, September 2012, which is incorporated herein by reference in its entirety. In one example, the processor runs an operating system, such as z / OS, also offered by International Business Machines
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Corporation. IBM, Z / ARCHITECTURE and Z / OC oon - registered trademarks of International Business Machines Corporation, Armonk, New York, USA. Other names used in this document may be registered trademarks, trademarks, or product names of International Business Machines Corporation or other companies.
In a further embodiment, processor 102 is based on the Power Architecture offered by International Business Machines Corporation. One embodiment of Power Architecture is described in Power ISA ™, Version 2.06 Revision B, International Business Machines Corporation, July 23, 2010, which is incorporated herein by reference in its entirety. POWER ARCHITECTURE<sup>0</sup> is a registered trademark of International Business Machines Corporation.
In yet a further embodiment, processor 102 is based on an Intel architecture offered by Intel Corporation. One modality of Intel architecture is described in Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2B, Instructions Set Reference, AL, Order Number 253666-045US, January 2013, and Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2B, Instructions Set Reference, MZ, Order Number 253667-045US, January 2013, each of which is incorporated herein <sup>10</sup>
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OF THE PROPERTY v »« Z3 INDUSTRIAL. ® document for reference in its entirety. Intel is a registered trademark of Intel Corporation, Santa Clara, California.
Another embodiment of a computing environment for incorporating and using one or more aspects is described with reference to Figure 2A. In this example, a computing environment 200 includes, for example, a native central processing unit 202, a memory 204, and one or more input / output devices and / or interconnects 206 coupled to another path, for example, one or more more buses 208 and / or other connections. As examples, the computing environment 200 may include a PowerPC processor, a pSeries server, or an xSeries server offered by International Business Machines Corporation, Armonk, New York; an HP Superdome with Intel Itanium II processors offered by Hewlett Packard Co., Palo Alto, California; and / or other machines based on architectures offered by International Business Machines Corporation, Hewlett Packard, Intel, Oracle, or others.
Native central processing unit 202 includes one or more native registers 210, such as one or more general-purpose registers and / or one or more special-purpose registers used during processing within the environment. These records include information that represents the state of the environment at any particular point
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IMPI
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Furthermore, the native central processing unit 202 executes instructions and a code that are stored in memory 204. In a particular example, the central processing unit executes the code of the emulator 212 stored in memory 2 04. This code allows the Processing environment configured on one architecture emulates another architecture. For example, the code in emulator 212 allows machines based on architectures other than z / Architecture, such as PowerPC processors, pSeries servers, xSeries servers, HP Superdome servers, or others, to emulate the z / Architecture and run the programs and instructions developed based on the z / Architecture.
Additional details that relate to the emulator 212 code are described with reference to Figure 2B. The guest instructions 250 stored in memory 204, comprise program instructions (for example, that correlate with machine instructions), which were developed to be executed on a different architecture than that of the native CPU 202. For example, the guest instructions 250 may have been designed to run on a z / Architecture 102 processor, but are instead being emulated on the native CPU 202, which may, for example, be a
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IMPI
MEXICAN INSTITUTE
INDUSTRIAL PROPERTY Intel Itanium II processor. In an example 7th "eT code from emulator 212 includes an instruction lookup routine 252 to get one or more guest instructions 250 from memory 2 04, and optionally provide a local buffer for the obtained instructions. It also includes an instruction translation routine 254, to determine the type of guest instruction that has been obtained and translate the guest instruction into one or more corresponding native instructions 256. This translation includes, for example, identifying the function to be performed by the guest instruction and choosing the native instructions to perform that function.
Additionally, the emulator 212 includes an emulation control routine 260 to make native instructions execute. The emulation control routine 26 0 can make the native CPU 2 02 execute a routine of the native instructions that emulate one or more previously obtained guest instructions and, at the conclusion of such execution, return control to the search routine of the statement to emulate getting the next guest statement or a group of guest statements. The execution of native instructions 256 can include load data in a memory register 2 04; store the data back into the memory of a record; or perform
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some kind of arithmetic or logical operation, as determined by the translation routine.
Each routine is, for example, implemented in the program, which is stored in memory and executed by the native central processing unit 202. In other examples, one or more of the routines or operations are implemented in the fixed instructions, elements physical, programs, or some combination thereof. The emulated processor registers can be emulated by using the native CPU registers 210 or by using the memory locations 204. In the modes, the guest instructions 250, the native instructions 256, and the emulator code 212 may reside in the same memory, or they may be distributed among different memory devices.
As used herein, fixed instructions include, for example, the microcode, millicode, and / or macrocode of the processor. They include, for example, the instructions at the physical element level and / or the data structures used in the implementation of a higher level machine code. In one embodiment, they include, for example, proprietary code that is typically supplied as the microcode that includes the tested program or the specific microcode for the physical elements and underlying controls that operate the system's access to the physical elements of the system.
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INSTITUTO MEXICANA 'DF LA PROMEDAO INDUSTRIAL
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In one example, a guest statement 250 qup se.
get, translate, and execute is an instruction described in this document. The instruction, which is from one architecture (e.g. z / Architecture), is fetched from memory, translated, and rendered as a sequence of 256 native instructions from another architecture (e.g. PowerPC, pSeries, xSeries, Intel , etc.). These native instructions are executed next.
In one embodiment, the instructions described herein are vector instructions, which are part of a vector function. The vector function provides, for example, vectors of fixed size ranging from one to sixteen elements. Each vector includes data that is operated in the vector instructions defined in the function. In one embodiment, if a vector is made up of multiple elements, then each element is processed in parallel with the other elements. Statement completion does not occur until processing of all elements is complete. In other embodiments, the items are partially processed in parallel and / or sequentially.
Vector instructions can be implemented as part of various architectures, including but not limited to z / Architecture, Power, x86, IA-32, IA-64, etc. Although the modalities described in this document are for the z / Architecture, the vector instructions described in the aspects, can
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present document and one or more of others be based on many other<sup>_</sup> architectures. The z / Architecture is just one example.
In a mode in which the vector function is implemented as part of the z / Architecture, to use vector registers and instructions, a vector enable control and a register control on a specified control register (for example, register of control 0) are set to, for example, one. If the vector function is installed and a vector instruction executes without the enable controls set, an exception is recognized in the data. If the vector function is not installed and a vector instruction executes, an exception to the operation is recognized.
In one embodiment, there are 32 vector records and other types of records can be assigned to a quadrant of the vector records. For example, as shown in Figure 3, a register file 300 includes 32 registers from vector 302 and each register is 128 bits in length. Sixteen floating point records 304, which are 64 bits long, can be overlaid on the vector records. So, as an example, when the record for floating point 2 is modified, then the record for vector 2 is also modified. Other assignments for other types of records are also possible.
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The vector data appears in storage, for example, in the same sequence left to right as the other data formats. The bits of a data format that are numbered 0-7 make up the byte at the leftmost (lowest numbered) byte location in storage, bits 8-15 of the byte at the next sequential location, and so on. In a further example, the vector data may appear on storage in another sequence, such as right to left.
Each of the vector instructions described herein has a plurality of fields, and one or more of the fields has a subscript number associated with it. The subscript number associated with a field in the instruction denotes the operand to which the field applies. For example, the subscript number 1 associated with the vector record Vi denotes that the record in V<sub>x</sub> includes the first operand, and so on. A register operand is a register in length, which is, for example, 128 bits.
Also, many of the vector instructions provided with the vector function have a specified bit field. This field, referred to as the register extension bit or RXB, includes the most significant bit for each of the operands designated by the vector register. The bits for
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Register designations not specified by the statement are to be reserved and set to zero. The most significant bit is concatenated, for example, to the left of the four-bit register designation to create a five-bit vector register designation.
In one example, the RXB field includes four bits (for example, bits 0-3), and the bits are defined, as follows:
- Most significant bit for the first designation of the vector register (for example, in bits 8-11) of the instruction.
- Most significant bit for the second designation of the vector register (for example, in bits 12-15) of the instruction, if any.
- Most significant bit for the third designation of the vector register (for example, in bits 16-19) of the instruction, if any.
- Most significant bit for the fourth vector register designation (for example, in bits 32-35) of the instruction, if any.
Each bit is set to zero or one by, for example, the assembler, depending on the register number.
For example, for registers 0-15, the bit is set to 0; for registers 16-31, the bit is set to 1, etc.
In one embodiment, each RXB bit is a bit of <sup>18</sup> IMPI® tNSTITllTCMÍXICANí
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The extension for a particular location in an instruction that includes one or more records in the vector. For example, in one or more vector instructions, bit 0 of RXB is an extension bit for location 8-11, which is designated to, for example, Vi; bit 1 of RXB is an extension bit for location 12-15, which is assigned to, for example, V<sub>2</sub>; and so on. In an additional embodiment, the RXB field includes additional bits, and more than one bit is used as an extension for each vector or location.
An instruction provided according to an aspect that includes the RXB field is an Immediate Class instruction from the Floating Point Test Data of the
Vector (VFTCI), an example of which is described in Figure 4Ά. In one example, the instruction for the Immediate Class of the Floating Point Test Data of the
Vector 400 includes opcode fields 402a (for example, bits 0-7), 402b (for example, bits 40-47), indicating an Immediate Class operation of the Vector Floating Point Test Data; a first vector record field 404 (eg, bits 8-11) used to designate a vector record (Vi); a second vector record field 406 (e.g. bits 12-15) used to designate a second vector record (V<sub>2</sub>); an immediate field (I<sub>3</sub>) 408 (eg bits 16-27) to include a bit mask; a first field of the mask (M<sub>5</sub>) 410 (for example, bits
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28-31); a second field of the mask (M<sub>4</sub>) 412 (for example, bits 32-35); and an RXB field 414 (eg bits 36-39). Each of the 404-414 fields, in one example, are separate and independent from the opcode fields. Furthermore, in one embodiment, they are separate and independent from each other; however, in other modalities, more than one field can be combined. Additional information on the use of these fields is described below.
In one example, the selected bits (eg, 10 the first two bits) of the opcode designated by the opcode field 402a, specify the length of the instruction. In this particular example, the selected bits indicate that the length is three half words. Also, the instruction format is an immediate vector register operation with an extended opcode field. Each of the fields in the vector (V), together with its corresponding extension bit specified by RXB, designates a record in the vector. In particular, for vector registers, the register containing the operand is specified using, for example, a four-bit field of the register field, with the addition of its corresponding register extension bit (RXB) bit as the bit more significant. For example, if the four-bit field is 0110 and the extension bit is 0, then the five-bit field 00110 indicates register number 6.
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Also, in one mode of the VFTCI instruction,
I saw 404 and V<sub>2</sub> 406, specify the registers of the vector that include a first operand and a second operand, respectively, for the instruction. Furthermore, I<sub>3</sub> 408 includes a bit mask having a plurality of bits, and each bit is used to represent a class and a sign (positive or negative) of the binary floating point element, as described in further detail below.
In a further embodiment, the bit mask may be provided in a general purpose register, in memory, in an element of a vector register (which differs depending on the element), or from an address calculation, as examples. It can be included as an explicit operand of the instruction or as an implicit operand or input.
Field M<sub>5</sub> 410 has, for example, four bits, 0-3, and specifies a control of a single element (S) on, for example, bit 0. If bit 0 is set to one, the operation takes place only on the element with the zero index in the vector. The bit positions in all other elements in the first vector of the operand are unpredictable. If bit 0 is set to zero, the operation occurs on all elements in the vector.
Field M<sub>4</sub> 412 is used, for example, to specify the size of the floating point numbers in the
<img file="MX344922B_D0019.tif" />
second operand of the instruction. In one example, this field is set to 3, indicating a double precision binary floating point number. Other examples are also possible.
In executing one mode of the Vector Floating Point Test Data Immediate Class instruction, the class and sign of the floating point element or elements of the second operand are examined to select one or more bits of the third operand. If a selected bit is set, all bit positions of the corresponding element in the first operand are set to ones; otherwise, they are set to zero. That is, if the class / sign of the floating point number contained in an element of the second operand corresponds to a set bit (that is, a bit set to, for example, one) in the third operand, then an element of the first operand that corresponds to the element of the second operand is set to ones. In one example, all elements of the operand contain long-form BFP (binary floating point) numbers.
As indicated herein, the 12 bits of the third operand, bits 16-27 of the instruction text, are used to specify 12 class and sign combinations of the BFP data. In one example, as shown in Figure 4B, the elements of the BFP operand are<sup>22</sup> IMPIAS
INSTITUTO MEXICANO DE LA PROPIEDAD INDUSTRIAL divided into six classes 430: zero, normal number, subnormal number, infinity, NaN (Not a Number) silent, and NaN signaling, and each class has a sign 432 (either positive or negative) associated with the same. So, for example, bit 0 of I<sub>3</sub> specifies a class zero with a positive sign, and bit 1 specifies a class zero with a negative sign, and so on.
One or more of the bits of the third operand can be set to one. Also, in one embodiment, the instruction can operate on one or more items at the same time.
The elements of the operand, including SNaNs (Signaling NaNs) and QNaNs (Silent NaNs), are examined without causing an IEEE exception.
Resulting Summary Condition Code for all elements:
The selected bit is 1 for all elements (matches)
The selected bit is 1 for at least one, but not all elements (when the S bit is zero)
2--
The selected bit is 0 for all elements (does not match)
IEEE Exceptions: None
Program Exceptions:
• Data with an FE of the exception code of the <sup>23</sup> IMPI ^
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INDUSTRIAL ^ • R — üí — Sdatos (DXC), Vectorial Instruction, indicating that a vector function is not enabled • Operation (if the vector function for the z / Architecture is not installed) • Specification • Transaction constraint
Programming Notes:
1. This instruction provides a way to test the elements of the operand without a risk of exception or IEEE flag setting.
2. When the S bit is set, a Condition Code of 1 is not used.
Additional details regarding one modality of the instruction of the Immediate Class of Vector Floating Point Test Data are described with reference to Figures 4C and 4D. In particular, Figure 4C depicts one mode of the logic associated with the Immediate Class instruction of Vector Floating Point Test Data performed by a processor (for example, a CPU), and Figure 4D depicts an example of a block diagram illustrating the execution of the Vector Floating Point Test Data Immediate Class instruction.
Referring to Figure 4C, initially, a variable referred to as an element index (Ei), starts
<img file="MX344922B_D0020.tif" />
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INSTITUTO MEXICANO DE LA TRONEDA »INDUSTRIAL to zero, STEP 450. Next, the value in-ei-element Ei, which in this case is element 0, is extracted from the second operand of the instruction (for example, from the operand stored in the register designated by V<sub>2</sub>), STEP 452. This value, which is a long-form binary floating point value, is converted to a type number to get a class and sign for the floating point element of the second operand, as described below, STEP 454. In one example, the size of the floating point number 453 is entered into the conversion logic. The class and sign obtained are associated with a particular class / sign bit, as described with reference to Figure 4B. For example, if the conversion indicates that the floating point number is a positive, normal number, then bit 2 is associated with the floating point number.
Post-conversion, the bit in the third operand (referred to as the selected bit) that corresponds to the particular bit that was determined based on the conversion is checked, STEP 456. If the selected bit is set, QUESTION 458, then the item in the first operand corresponding to element (Ei) is set equal to all ones, STEP 460; otherwise, that element in the first operand is set equal to zero, STEP 462. For example, if the conversion of the floating point number in element 0 indicates a positive normal number, then bit 2 is associated
<img file="MX344922B_D0021.tif" />
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INSTITUTO MEXICANO DE LA RROMEDAO. INDUSTRIAL with the number. Thus, bit 2 of the third operand is checked, and if it is set to one, the el'ei! IeiTW ~ TÍ 'of the first operand is set to all ones.
Subsequently, a determination is made whether Ei is equal to the maximum number of elements of the second operand, QUESTION 464. If not, then Ei is incremented by, for example, one, STEP 466, and processing continues with STEP 452. From otherwise, if Ei is equal to the maximum number of elements, then a summary condition code is generated, STEP 468. The summary condition code, summarizes the processing for all elements of the second operand. For example, if the selected bit is one for all elements (matches), then the resulting condition code is zero. On the other hand, if the selected bit is 1, for at least one, but not all elements (when the S bit is not zero), then the condition code is 1, and if the selected bit is zero for all other elements (does not match), then the condition code is 3.
The above processing is shown schematically in the block diagram of Figure 4D. As described, a vector record 480 includes a plurality of items 482a-482n, each including a floating point number. Each floating point number and the size of the floating point number 483a-483n are
<img file="MX344922B_D0022.tif" />
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INSTITUT MEXICANA DE LA PROPIEDAD INDUSTRIAL introduce the logic of converting to the type number 484a-484n, and the result is a particular bit that represents a class / sign for the floating point number. Next, a selected bit in each mask 486a-486b that corresponds to each particular bit is checked. Depending on whether the selected bit is set, the first operand in a vector 488 register is set. For example, if for element 0 of the second operand, the selected bit is set, then element 490a of the first operand is set to all ones. Similarly, if the bit selected for item 1 of the second operand is not set (for example, it is set to zero), then item 490b of the first operand is set to zero, etc.
The additional details of a mode of the logic of converting to the type number are now described. Initially, the floating point number, which is a standard IEEE binary floating point number, is converted into three parts: a sign, an exponent (8 bits) + 12 7, and a fraction (23 bits), as it is known. Next, the values of all three parts are checked to determine the class and sign, as shown in Figure 4E. For example, the sign is the value of the sign part, and the class (also known as an entity in Figure 4E), is based on the values of the exponent and the fraction (the unit bit in Figure 4E is a
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As an example, if the exponent and fraction values (including the unit bit) are zeros, then the class is zero and if the sign part is positive, then the sign is positive. Thus, bit 0 (Figure 4B) represents the class / sign of this floating point number.
A modality of an instruction to test the floating-point class of elements in a vector and set a mask of the resulting bit was described above. The instruction of the Immediate Class of
Vector Floating Point Test Data has an immediate field, where each bit represents a class of the floating point numbers to detect. Each floating point element of an input vector is tested to see if the value is in any of the classes specified by the statement. If the floating point element is one of the classes, the bit positions of the corresponding element of the output vector are set to 1. This provides a technique to determine some properties (for example, class and sign) on a binary floating point number without causing any exceptions or interrupts.
In a further embodiment, the test can be performed by checking which bits of the third operand are set (eg, to one), and then determining whether the class / sign of one or more elements of the
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INDUSTI1AI second operand are the same as one of the set bits. The first operand is set below, based on the comparison.
In a further aspect, a Vector Checksum instruction is provided, an example of which is described in Figure 5A. In one example, the Vector Checksum 500 instruction includes opcode fields 502a (for example, bits 0-7), 502b (for example, bits 40-47), which indicate a vector checksum operation ; a first vector record field 504 (eg, bits 8-11), used to designate a first vector record (Vi); a second record field of vector 506 (for example, bits 12-15) used to designate a second record of the vector (V<sub>2</sub>); a third record field of vector 508 (e.g. bits 16-19) used to designate a third record of the vector (V<sub>3</sub>); and an RXB field 510 (eg bits 36-39). Each of the fields 504 through 510, in one example, is separate and independent from the opcode fields. Furthermore, in one embodiment, they are separate and independent from each other; however, in other modalities, more than one field can be combined.
In a further embodiment, the third register field of the vector is not included as an explicit operand of the instruction, but is instead an explicit or input operand. Also, the value provided in the
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INSTITUTO MEXICAN DE LA PROPIEDAD INDUSTRIAL operating can be provided in other ways, such as in a general purpose register, in memory, as an address calculation, etc.
In still another embodiment, the third operand, explicit or implicit, is not provided at all.
In one example, the selected bits (for example, the first two bits) of the opcode designated by the opcode 502a field, specify the length of the instruction. In this particular example, the selected bits indicate that the length is three half words. Also, the instruction format is a record vector and record operation, with an extended opcode field. Each of the fields of the vector (V), together with this corresponding extension bit specified by RXB, designates a record of the vector. In particular, for vector registers, the register containing the operand is specified using, for example, a four-bit field of the register field, with the addition of its corresponding register extension bit (RXB) in the plus bit. significant.
In the execution of a modality of the Vector Checksum instruction, the elements for the second operand, which are, for example, the size of a word, are added together one by one, along with a selected element of the third operand, for example, the element in word one of the third operand. (In another mode, the
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addition of the selected element of the third 'operand is optional). The sum is placed in a selected location, for example word one, of the first operand. Zeros are set to the other elements of the word, for example, word elements 0, and 2-3, of the first operand. Word-sized items are all treated as 32-bit unsigned binary integers. After each addition of an element, a carry of, for example, the position of bit 0 of the sum, is added, for example, to the position of bit 31 of the result in the element of word one of the first operand.
Condition Code: The code remains unchanged.
Program Exceptions:
• Data with an FE of the data exception code (DXC), Vector Instruction, indicating that the vector function is not enabled • Operation (if the vector function for z / Architecture is not installed) • Transaction constraint
Programming Notes:
1. The content of the third operand will contain zero at the beginning of an algorithm for calculating the checksum.
2. 16 bit checksum is used <sup>31</sup> PREVENTS
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INDUSTRIAL -in, for example, a TCP / IP application. The following program can be run after a 32-bit checksum has been calculated:
VERLLF V2, VI, 16 (0) (VERLLF - Logic to Rotate Vector Element to the Left - 4 byte value)
VAF V2, V1, V2 (VAF - Add Vector - byte value)
The half word in item 2 contains the 16-bit checksum.
Additional details regarding the Vector Checksum instruction are described with reference to Figures 5B and 5C. In one example, Figure 5B depicts a mode of logic performed by a processor executing the Vector Checksum instruction, and Figure 5C depicts a block diagram of an example of the execution of the instruction of the Vector Checksum.
Referring to Figure 5B, initially, the element index (Ey) for the first operand (OP1) is set, for example, to one, indicating element 1 of the first operand, STEP 530. Similarly, the element index (Ex) for the third operand (OP3) is set, for example, to one, indicating element 1 of the third operand, STEP 532. Next, the index of the element (Ei) is
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sets equal to 0, and the element at the element's index (Ey), that is, element 1 in this example, is initialized to zero, STEP 534. In an additional mode, Ex and Ey can be set to any index of the element valid.
A final round carry (EAC) sum is performed in which OPl (Ey) = OP1 (Ey) + OP2 (Ei) + OP2 (Ei + l), STEP 536. Thus, element 1 of the output vector ( 0P1) is set equal to the content of that element plus the value in element 0 of the second operand (0P2) and the value in element 1 of the second operand. With a final round carry sum, an addition operation is performed and no addition carry is added back to the sum to produce a new sum.
In a further embodiment, instead of adding as described above, the following is done: a temporary accumulator value is defined and initialized to zero, and then one item is added at a time. As an additional modality, all the words are added in parallel and there is no temporary accumulator. Other variations are also possible.
Subsequently, a determination is made if there are additional elements to be added in the second operand, QUESTION 538. For example, if Ei-2 <# of elements of the second operand. If there are more elements of the second operand to be added, then Ei is increased, for example, by
USTITUT · MEXICANO dos, STEP 540, and processing continues c <9H · * j ^<sup>r</sup>”IiaS
After the sum of the elements through the second operand, the result is added to a value in the third operand. For example, a sum with final rounding is performed of the element (Ey) of the first operand (which is the sum of the EAC sum through all the elements of the second operand), and a value in the element (Ex) of the third operand (0P3) (ie EAC ADD OP1 (Ey) + 0P3 (Ex)), STEP 542. This is shown graphically in Figure 5C.
As shown in Figure 5C, the second operand 550 includes a plurality of elements 552a-552n, and those elements are added together one by one together with the element in word 1 (562) of the third operand 56 0. The result is put in element 1 (572) of the first operand 570. This is shown mathematically by the equation Ey = Ex + the sum of Ei, where i = 0 to n, and the addition is an addition with final rounding carry.
An embodiment of a Vector Checksum instruction that performs a checksum through the elements of a vector record, rather than performing lane arithmetic, was described above. In one embodiment, the Vector Checksum instruction performs the checksums by performing a cross sum with carry sums of
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<img file="MX344922B_D0027.tif" />
final rounding. In one example, the Vector Checksum instruction takes 4-byte integer elements from a vector record and adds them together. Any carries of the sum are added back. The 4-byte sum is added to a 4-byte element in another operand, and then stored in yet another record of the vector (for example, the low-order 4-byte element of a vector record with zeros stored in the elements vector registry higher order).
In an additional embodiment, the additional vector register or another register is not used to store the value, but instead one of the other registers (that is, operands) is used as an accumulator.
The checksum that is provided can be used to preserve the integrity of the data. The checksum is frequently applied to the data and sent on a noisy channel in order to verify that the received data is correct. In this example, as described in this document, the checksum is calculated by adding the integers of 4 sequential bytes. If there is a carry of the integer mathematical operation, the carry, and an additional one, are added to the sum being performed.
Although checksums are described in this document, a similar technique can be used for other sums with final rounding carry.
<img file="MX344922B_D0028.tif" />
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An additional instruction provided according to one aspect is a Multiply, Add and
Accumulate the Vector Galois Field (VGFMA), an example of which is described in Figure 6A. In one example, the instruction Multiply, Add, and Accumulate Galois Vector Field 600, includes opcode fields 602a (for example, bits 0-7), 602b (for example, bits 40-47), indicating a Multiply operation , Add and Accumulate the Galois Vector Field; a first vector field 604 (eg, bits 8-11) used to designate a first vector record (Vi); a second vector record field 606 (for example, bits 12-15) used to designate a second vector record (V<sub>2</sub>); a third vector register field 608 (for example, bits 16-19) used to indicate a third vector register (V<sub>3</sub>), · A mask field (M<sub>s</sub>) 610 (for example, bits 20-23); a fourth record field of vector 612 (for example, bits 32-35) used to designate a fourth record of the vector (V<sub>4</sub>); and an RXB 614 field (eg, bits 3 6-3 9). Each of the 60 4-614 fields , in one example, is separate and independent from the opcode fields. Furthermore, in one embodiment, they are separate and independent from each other; however, in other modalities, more than one field can be combined.
In one example, the selected bits (for example, the first two bits) of the opcode that designates the opcode field
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<img file="MX344922B_D0029.tif" />
602a specify the length of the instruction. In this particular example, the selected bits indicate that the length is three half words. Also, the format of the instruction is a register operation of the vector and register with an extended opcode field. Each of the fields in the vector (V), together with its corresponding extension bit specified by RXB, designates a record in the vector. In particular, for vector registers, the register containing the operand is specified using, for example, a 4-bit field of the register field with the addition of its corresponding register extension bit (RXB) as the most significant bit .
Field M<sub>5</sub> 610 has, for example, 4 bits, 0-3, and specifies the element size control (ES). The element size control specifies the size of the elements in vector register operators two and three; the elements in the first and fourth operating as twice the size of that specified in the ES control. For example, a value of 0 in M<sub>5</sub>, indicates one-byte size elements; 1 indicates a half word; 2 indicates a word; and 3 indicates a double word, as examples.
In executing a modality of the Multiply, Add, and Accumulate Galois Vector Field instruction, each element of the second operand is multiplied into a Galois field (that is, a finite field that has a <sup>37</sup>
INSTITUTO MEXICANO DE LA PROPIEDAD | <β industrial X —'Wff-jy finite number of elements), with the corresponding element of the third operand. That is, each element of the second operand is multiplied with the corresponding element of the third operand, using no-carry multiplication. The Galois field has an order of two, in one example. This multiplication is similar to standard binary multiplication, but instead of adding the changed multiplicand, it undergoes exclusive OR (XOR) operation. Even-odd pairs resulting from, for example, products with the size of a double element, are exclusively ORed with each other, and are exclusively ORed with the corresponding elements, for example, elements with width double, of the fourth operating. The results are placed in, for example, the elements with double width of the first operand.
Condition Code: The code remains unchanged.
• Exceptions to the Program:
• Data with a data exception code FE (DXC), Vector Instruction, indicating that the vector function is not enabled • Operation (if the vector function for z / Architecture is not installed) • Specification
Transaction restriction
<img file="MX344922B_D0030.tif" />
In a further embodiment, the instruction can include one or fewer operands. For example ”, instead of a fourth operand, the value to be subjected to the exclusive OR operation is the first operand, which will also include the results. Other variations are also possible.
Additional details regarding one mode of execution of a Multiply, Add and Accumulate Galois Vector Field instruction is described with reference to Figures 6B and 6C. In one example, Figure 6B describes a mode of logic performed by a processor to execute a Multiply, Add and Accumulate Galois Vector Field instruction, and Figure 6C describes an example of a block diagram showing the execution of the logic .
Referring to Figure 6B, initially, the even / odd pairs are extracted from the second operand (OP2), the third operand (OP3), and the fourth operand (OP4), STEP 630, and a multiply function is performed without carry , add, and accumulate, STEP 632. For example, when operating on a Galois field of a power of 2, no carry multiplication is an offset and XOR (exclusive OR), which effectively ignores any carry. The result is placed in the first operand (0P1), STEP 634, and a determination is made if there are more pairs to be extracted, QUESTION 636. If there are more pairs, then processing continues with STEP 630; otherwise,<sup>q1</sup> pmnaoam-Lont-A · ends, STEP 638. In one example, the size of element 631 is the input to STEPS 630-634.
Additional details of the multiply without carry, add and accumulate function from STEP 632 are described with reference to Figure 6C. As shown, a pair of operands OP2H 652a, OP2L 652b are extracted from the second operand 650. Also, the pair of operand OP3H 662a, OP3L 662b are extracted from the third operand 660, and the pair of operand OP4H 672a and OP4L 672b are extracted of the fourth operating 670. Operand OP2H 652a is multiplied with no carry multiplication to operand OP3H 662a, and a Result H 680a is provided. In a simulated manner, operand OP2L 652b is multiplied using no carry multiplication to operand OP3L 662b, and a Result L 680b is provided. Result H 680a is then exclusive ORed with Result L 680b, and the result is exclusive ORed with operand OP4H 672a and operand OP4L 672b, and the result is placed in OP1H 690a, OP1L 690b.
Described herein is a vector instruction that performs a multiply no carry operation and then performs a final exclusive OR operation to create a running sum.
This technique can be used with various aspects of
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<img file="MX344922B_D0031.tif" />
cryptography and error detection codes that perform operations on a finite field with an order of 2.
In one example, the instruction performs a carry-free multiplication operation on a plurality of elements of a vector register to obtain a sum. Additionally, the statement performs a final exclusive OR operation on the sum to create a running sum. When executed, the instruction multiplies in a Galois field the corresponding elements of a second vector and a third vector, and the shifted multiplicand is XORed. Each double-width product is XORed against the other, and the result is XORed with a corresponding double-width element from a first vector. The result is stored in the first record of the vector. Although double word elements were described above, word-sized elements of other element sizes can be used. The instruction can operate on multiple different element sizes.
A further instruction provided in accordance with one aspect is a Generate Vector Mask (VGM) instruction, an example of which is described with reference to Figure 7A. In one example, the Generate Vector Mask 700 instruction includes opcode fields 702a (for example, bits 0-7), 702b (for example, bits 40-47), which indicate a Generate Vector Mask operation; a
<img file="MX344922B_D0032.tif" />
vector first record field 704 (eg, bits 8-11), used to designate a first vector record (Vi); an immediate first field I<sub>2</sub> 706 (eg bits 16-24) used to specify a first value; a second immediate field (I<sub>3</sub>) 708 (eg bits 24-32) used to specify a second value; a mask field (M<sub>4</sub>) 710 (eg bits 32-35); and an RXB field 712 (eg bits 36-39). Each of the 704-712 fields, in one example, is separate and independent from the opcode fields. Furthermore, in one embodiment, they are separate and independent from each other; however, in other modalities, more than one field can be combined.
In a further embodiment, the first value and / or the second value may be provided in a general purpose register, in memory, in an element of a vector register (which differs depending on the element), or from a calculation of the address , as examples. It can be included as an explicit operand of the instruction or as an implicit operand or input.
In one example, the selected bits (for example, the first two bits) of the opcode designated by the opcode 702a field specify the length of the instruction. In this particular example, the selected bits indicate that the length is three half words. Also, the instruction format is a vector register operation and
<img file="MX344922B_D0033.tif" />
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INSTITUTO MEXICANO DF LA PROFIFDAD INDUSTRIAL immediate with an extended opcode field. '' Each '' of the vector fields (V), together with its corresponding extension bit specified by RXB, designates a record in the vector. In particular, for vector registers, the 5 register containing the operand is specified using, for example, a four-bit field of the register field with the sum of its corresponding register extension bits (RXB), as the bit more significant.
Field M<sub>4</sub> specifies, for example, an element size (ES) control. The element size control specifies the size of the elements in the vector register operands. In one example, bit 0 of the M field<sub>4 </sub>specify a byte; bit 1 specifies a half word (for example, 2 bytes); bit 2 specifies a word (for example, 4 bytes; also known as a whole word); and bit 3 specifies a double word.
In the execution of a modality of the Generate Vector Mask instruction, for each element in the first operand, a bit mask is generated. Mask 20 includes bits set to one starting at the specified bit position, for example, by the value of the unsigned integer in I<sub>2</sub>, and ending with the bit position specified, for example, by the value of the unsigned integer in I<sub>3</sub>. All other bit positions are set to zero. In one example, only the number of bits required<sup>43 </sup>INSTITUTO MEXICAN · J *
DE LA PROEISDA · INDUSTRIAL to represent all bit positions for the specified element size are used from the I fields<sub>2</sub> and I<sub>3</sub>; other bits are ignored. If the position of the bit in field I<sub>2</sub> is greater than the position of the bit in field I<sub>3</sub>, the bit range is wrapped at the maximum bit position for the specified element size. For example, assuming the elements of the byte size, if I<sub>2</sub> = 1 and I<sub>3</sub> = 6, the resulting mask is o b'oIIIIIIo '. However, if he<sub>2</sub> = 6 and I<sub>3</sub> = 1, so the resulting mask is x'si 'or b'10000001'.
Condition Code: The code remains unchanged.
Program Exceptions:
• Data with an FE of the data exception code (DXC), Vector Instruction, indicating that the vector function is not enabled • Operation (if the vector function for z / Architecture is not installed) • Specification • Transaction constraint
Additional details regarding one embodiment of the Generate Vector Mask command are described with reference to Figures 7B and 7C. In particular, Figure 7B describes a modality of the logic associated with the Generate Vector Mask instruction
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<img file="MX344922B_D0034.tif" />
performed by a processor, and Figure 7C depicts an example of a block diagram illustrating one mode of executing the Generate Vector Mask instruction.
Referring to Figure 7B, initially, a mask is generated for each element in the first operand, STEP 720. This step uses several inputs, including the value specified in the second operand field as the starting position (722), and the value specified in the third operand field as the end position (724), and the size of the elements as specified in the M field<sub>4</sub> (726). These inputs are used to generate the mask and fill the positions of a selected element, for example, element 0, of the first operand (Opl), STEP 730. For example, element 0 of the first operand (Opl) includes a plurality of positions (for example, bit positions) and starting at the position specified by the value of the unsigned integer in I<sub>2</sub> and ending in the specified position in the value of the unsigned integer in I<sub>3</sub>, in the positions (eg bits) of element 0 of the first operand are set to 1. The other positions of the bit are set to 0. Subsequently, a determination is made whether there are more elements in the first operand, QUESTION 734. If there are more items, then processing continues to STEP 720. Otherwise, processing is complete,
<img file="MX344922B_D0035.tif" />
STEP 73 6. _____
The generation of the mask and the filling of the first operand are graphically described in Figure 7C. As shown, the masks for each element of the first operand are generated 720, using the inputs (eg 722-726), and the results of generating the masks are stored in the elements of the first operand 740.
An instruction to generate bit masks for each element of a vector was described in detail above. In one embodiment, the instruction takes a start bit position and a final bit position and creates a bit mask that is reproduced for each element. The instruction specifies a bit span and each bit within the span is set to one for each element of the vector register, while other bits are set to zero.
In one embodiment, using an instruction to generate the bit masks provides benefits, for example, to load the bit masks from memory, increasing a cache space of a stream of instructions, and depending on how many masks are needed, it could increase latency in a critical loop.
Yet another instruction provided according to appearance, is a Rotate Vector Element instruction and
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Insert Under Mask (VERIM), an example of which is depicted in Figure 8A. In one example, the instruction to Rotate Vector Element and Insert It Under Mask 800, includes opcode fields 802a (for example, bits 0-7), 802b (for example, bits 40-47), which indicate an operation of
Rotate the Vector Element and Insert It Under the Mask; a first vector record field 804 (eg, bits 8-11) used to designate a first vector record (Vi); a second vector record field 8 06 (for example, bits 12-15) used to designate a second vector record (V<sub>2</sub>); a third record field of vector 808 (for example, bits 16-19) used to designate a third record of the vector (V<sub>3</sub>); an immediate field (I<sub>4</sub>) 812 (eg bits 24-31) which includes, eg, an unsigned binary integer specifying the number of bits to rotate each item; a mask field (M<sub>5</sub>) 814 (for example, bits 32-35); and an RXB field 816 (eg bits 36-39). Each of the 804-816 fields, in one example, is separate and independent from the opcode fields. Furthermore, in one embodiment, they are separate and independent from each other; however, in other modalities, more than one field can be combined.
In one example, the selected bits (for example, the first two bits) of the opcode designated by the opcode 802a field specify the length of the instruction. In
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In this particular example, the selected bits indicate that the length is three half words. Also, the instruction format is an immediate vector register operation with an extended opcode field. Each of the fields in the vector (V), together with its corresponding extension bit specified by RXB, designates a record in the vector. In particular, for vector registers, the register containing the operand is specified using, for example, a 4-bit field of the register field with the sum of its corresponding register extension bit (RXB) as the most significant bit .
Field M<sub>5</sub> specifies the element size control (ES). The element size control specifies the size of the elements in the vector register operands. In one example, bit 0 of the M field<sub>5</sub> specify a byte; bit 1 specifies a half word (for example, 2 bytes); bit 2 specifies a word (for example, 4 bytes; also known as a whole word); and bit 3 specifies a double word.
In the execution of a modality of a Rotate Vector Element and Insert Under Mask instruction, each element of the second operand is rotated to the left by the number of bits specified by the fourth operand. Each bit shifted from the element's leftmost bit position re-enters the furthest bit position.
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DE LA MORIEDAi TO INDUSTRIAL ”right of the element. The third operand includes a 'mask on each element. For each bit in the third operand that is one, the corresponding bit of the rotated elements in the second operand, replaces the corresponding bit in the first operand. That is, a value of the corresponding bit of the rotated elements, replacing a value of the corresponding bit in the first operand. For each bit in the third operand that is zero, the corresponding bit of the first operand remains unchanged. Except for the case when the first operand is the same as the second or third operand, the second and third operands remain unchanged.
The fourth operand is, for example, an unsigned binary integer that specifies the number of bits by which to turn each element in the second operand. If the value is greater than the number of bits in the specified element size, the value is the reduced modulus of the number of bits in the element.
In one example, the mask included in the third operand is generated using the VGM instruction described in this document.
Condition Code: The code remains unchanged.
Program Exceptions:
Data with an FE of the data exception code (DXC), Vector Instruction indicates
<img file="MX344922B_D0038.tif" />
vector function is not enabled • Operation (if vector function for z / Architecture is not installed) • Specification • Transaction constraint
Programming Notes:
1. A combination of VERIM and VGM can be used to achieve the full functionality of a Rotate and Insert Selected Bits instruction.
2. Although the bits of the I field<sub>4</sub> are defined to contain an unsigned binary integer that specifies the number of bits to rotate each element counterclockwise, a negative value can be encoded, which effectively specifies a clockwise rotated amount.
Additional details regarding the execution of the Rotate Vector Element and Insert Under Mask command are described with reference to Figures 8B and 8C. In particular, Figure 8B describes a modality of the logic associated with the instruction to Rotate the Vector Element and Insert It Under the Mask, performed by a processor, and Figure 8C graphically describes an example of the execution of the instruction to Rotate the Element of the Vector and Insert It Under the Mask.
Referring to Figure 8B, an element
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INSTITUTO MlXIONO © t The selected industrial PROPERTY of the second operand is rotated, 'PA ^ O 830, by a specified amount in a fourth operand (820). If the value specified in the fourth operand is greater than the number of bits specified in the element size (822), then that value is the reduced modulus of the number of bits in the element.
Subsequent to the rotation of the element bits, a merge is performed under the mask, STEP 832. For example, for each bit in the third operand (824) which is 1, the corresponding bit of the element turned in the second operand replaces corresponding bit in the first operand.
Subsequently, a determination is made as to whether there are more items to be rotated, QUESTION 834. If there are more items to be rotated, then processing continues with STEP 830. Otherwise, processing is complete, STEP 836.
Referring to Figure 8C, as shown, the elements of the second operand are rotated 830 based on inputs 820 and 822. Furthermore, a merge under the mask is performed 832 using input 824. The output is provided in a first operand 850 .
An example of an instruction to Rotate Vector Element and Insert Under Mask was described above. This instruction is used to rotate the
<img file="MX344922B_D0040.tif" />
elements in an operand selected by a defined number of bits. Although bits are specified, in a further embodiment, elements can be rotated by a number of positions, and the positions can be different from bits. Also, the instruction can be used with different element sizes.
As an example, such an instruction is used to select certain bit ranges out of numbers for table lookups.
During the execution of certain vector instructions or other SIMD operations, an exception can occur. When an operation occurs in a SIMD operation, it is usually unknown which element of the vector record caused the exception. An interrupt handler in the program has to extract each element and re-compute in scalar mode to determine which element or elements were causing the exception. However, according to one aspect, when the machine (e.g. processor) processes a program interrupt due to a vector operation, an index of the element is reported indicating, for example, the lowest indexed element in the vector that caused The exeption. The program interrupt handler can immediately skip the item in question and perform any required or desired action.
For example, in a mode, when an exception
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of the vector data causes a program interrupt, a vector exception code (VXC) is stored in, for example, the real memory location (for example, location 147 (x'93 '), and the zeros are they store in, for example, real memory locations 144-146 (x'90 'x'92¡). In a further embodiment, the VXC is also placed in a data exception code (DXC) field of a floating point control register, if a specified bit (for example, bit 45) of a designated control register ( for example, CRO) is 1. When bit 45 of control register 0 is 0 and bit 46 of control register 0 is 1, the DXC of the FPC register and the contents of the storage at location 147 (X ^ 93 ' ) are unpredictable.
In one embodiment, the VXC distinguishes between various types of vector floating point exceptions, and indicates which element caused the exception. In one example, as described in Figure 9A, a vector exception code 900 includes a vector index (VIX) 9 02, and a vector interrupt code (VIC) 904. In one example, the vector's index includes bits 0-3 of the vector's exception code, and this value is the index of the leftmost element in a record in the selected vector that recognized the exception. Also, the vector interrupt code is included in bits 4-7 of the vector exception code, and has the following values, as examples:
<img file="MX344922B_D0042.tif" />
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0001 IEEE Invalid operation <
0010 IEEE Division by zero
0011 IEEE Overflow
0100 IEEE Subflow
0101 IEEE Inaccurate
In a further embodiment, the VXC includes only the vector index or other indicator of the position of an element causing an exception.
In one embodiment, the VXC can be set by various instructions, including, for example, the following instructions: Sum of the Floating Point (FP) of the Vector, Compare Scalar of the Vector FP, Compare Equal to the Vector FP, Compare High or Equal to the Vector FP, Convert to 64 Fixed Bits of the Vector FP, Convert from the 64 Bit Logic of the Vector Vector FP, Convert to 64 Fixed Bits of Vector FP, Convert to 64 Bit Logic of Vector FP, Divide Vector FP, Integer of Vector Load FP, Elongated Vector FP Load, Rounded FP Load Vector, Multiplication of Vector FP, Multiply and Add Vector FP, Multiply and Subtract Vector FP, Square Root of Vector FP and Subtract Vector FP, as examples, as well as other types of vector floating point instructions and / or other instructions.
Additional details regarding setting the vector exception code are <sup>54</sup>
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INDUSTRIAL _-- described with reference to Figure 9B. In one embodiment, a processor in the computing environment performs this logic.
Referring to Figure 9B, initially, an instruction that operates on a vector register is executed, such as one of the instructions listed above or another instruction, STEP 920. During the execution of the instruction, an exception condition is encountered, STEP 922. In one example, this exception condition causes an interrupt. A determination is made as to which element of the vector record caused the exception, STEP 924. For example, one or more units of the physical elements of the processor that perform the calculation on one or more elements of the vector register, determines the exception and provides a signal. For example, if a plurality of units of the physical elements is performing the calculation on a plurality of elements of a record of the vector in parallel, and an exception is encountered during the processing of one or more of the elements, the units of the elements Physicists performing the processing that encountered the exception, signals an exception condition, as well as an indication of the item it was processing. In an additional mode, if the elements of the vector are executed sequentially, and an exception is encountered during the processing of an element, the physical elements will indicate on which element in the sequence
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Based on the exception being flagged, the vector's exception code is set, STEP 926. This includes, for example, indicating a position of an element in the vector's record that caused the exception, as well as the interrupt code.
A vector exception code that provides efficient vector exception handling was described in detail above. In one example, when a machine processes a program interrupt due to a vector operation, an element index is reported, indicating a lower indexed element in the vector register that caused the exception. As a particular example, if a vector sum is being performed and there are two elements per vector record, giving A0 + B0 and Al + Bl, and an inaccurate result is received for A0 + B0, but not for Al + Bl, then VIX is set to 0 and VIC is set equal to 0101. In a further example, if it happens that A0 + B0 does not receive an exception, but Al + Bl receives an exception, then VIX is set equal to 1 (VIC = 0101). If they both take an exception, then VIX is set to 0 because it is the leftmost indexed position and VIC = 0101.
Several vector instructions were described in detail above, as well as a vector exception code that indicates the position of an exception within
<img file="MX344922B_D0044.tif" />
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INDUSTRIAL a vector log. In the flowcharts provided, some processing may appear sequential, however; In one or more modes, items are processed in parallel, and therefore there may be a need for verification, for example, if there are more items to be processed. Many other variations are also possible.
Furthermore, in additional embodiments, the content of one or more fields of an instruction can be provided in a general-purpose register, in memory, in an element of a vector register (which differs depending on the element), or of a calculation of the address, as examples. They can be included as an explicit operand of the instruction or as an implicit operand or input. Also, one or more instructions can use fewer operands or inputs, and one or more operands can instead be used for multiple operations or steps.
In addition, instead of including an element size control in an instruction field, the element size control can be provided in other ways, as described herein. Also, the size of the element can be designated by the opcode. For example, a particular opcode of the instruction designates the operation, as well as the size of the elements, etc.
In this document, memory, main memory, storage and main storage are <sup>57</sup> 11Λ rr>
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As will be appreciated by one of skill in the art, the aspects can be incorporated as a computer program system, method or product. Consequently, the aspects can take the form of a modality of physical elements completely, a modality of programs completely (including fixed instructions, resident program, microcode, etc.) or a modality that combines the aspects of physical elements and programs, which can generally referred to herein as a circuit, module, or system. In addition, one or more aspects may take the form of a computer program product embedded in one or more computer-readable media having computer-readable program code embedded therein.
Any combination of one or more computer-readable media can be used. The computer-readable medium can be a computer-readable storage medium. A computer-readable storage medium may, for example, but not exclusively, be an electronic, magnetic, optical, electromagnetic, infrared or semiconductor device, apparatus or system, or any suitable combination of the foregoing. The more specific examples (a non-exhaustive list) from the medium of
<img file="MX344922B_D0045.tif" />
Computer-readable storage includes the following: an electrical connection that has one or more wires, a laptop disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM, or Flash memory ), an optical fiber, a portable or compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by, or in connection with, an instruction execution system, apparatus, or device.
Referring now to Figure 10, in one example, a computer program product 1000 includes, for example, one or more non-transient computer-readable storage media 1002 for storing the computer-readable or logic program code media 1004 in the same, to provide and facilitate one or more aspects of the present invention.
Program code embedded in a computer-readable medium may be transmitted using an appropriate medium, including but not limited to, wireless, wired, fiber optic cable, RF, etc., or
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The computer program code to carry out the operations for the aspects can be written in any combination of one or more programming languages, including an object-oriented programming language, such as Java, Smalltalk, C ++ or the like, and other languages. procedural programming languages, such as the C programming language, assembler or similar programming languages. The program code can run entirely on the user's computer, partially on the user's computer, as a standalone program package, partially on the user's computer, and partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can connect to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection can be made to a computer. external (for example, via the Internet using an Internet Service Provider).
Aspects are described herein with reference to flowchart illustrations and / or block diagrams of the methods, apparatus (systems) and products of the computer program according to one or more modalities. It will be understood that each block of the
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illustrations of the flow chart and / or ^ / ΆΠίΓίΡ ru κι and the combinations of blocks in the illustrations of the flow chart and / or block diagrams, can be implemented by the instructions of the computer program. These computer program instructions can be supplied to a processor of a general-purpose computer, special-purpose computer, or other data processing apparatus programmed to produce a machine, so that the instructions, which are executed via the processor of the computer or other programmable data processing apparatus, creates means to implement the functions / acts specified in the flow chart and / or the block or blocks of the block diagram.
These computer program instructions may also be stored on a computer-readable medium that can direct a computer, other programmable data-processing apparatus, or other devices to function in a particular way. such that the instructions stored in the computer-readable medium produce a fadrication article that includes the instructions that implement the function / act specified in the flowchart and / or the block or blocks of the block diagram.
The instructions of the computer program can also be loaded into a computer, other
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programmable data processing, or other devices to cause a series of operating steps to be performed on the computer, other programmable devices or other devices to produce a computer-implemented process, so that the instructions that are executed on the computer or other programmable apparatus, provide processes to implement the functions / acts specified in the flow diagram and / or the block or blocks of the block diagram.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of computer program systems, methods, and products according to various modalities. In this regard, each block in the flow diagram or block diagrams may represent a module, segment or portion of a code, comprising one or more executable instructions to implement the specified logic functions. It should be noted that in some alternate implementations, the functions indicated in the block may occur out of the order indicated in the Figures. For example, two blocks displayed in succession may, in fact, run substantially concurrently or the blocks may sometimes run in the reverse order, depending on the functionality involved. It will also be noted that each block of the
<img file="MX344922B_D0048.tif" />
Block diagrams and / or illustration of the flow diagram and combinations of blocks in the block diagrams and / or illustration of the flow diagram, can be implemented by systems based on the special-purpose physical elements, which perform the specified functions or acts , or combinations of special purpose physical items and computer instructions.
In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc., by a service provider offering customer media management. For example, the service provider may create, maintain, support, etc., a computer code and / or a computer infrastructure that performs one or more aspects for one or more clients. In turn, the service provider may receive a payment from the customer under a subscription and / or rate agreement, as examples. Additionally or alternatively, the service provider may receive payment for the sale of the advertising content to one or more third parties.
In one aspect, an application can be deployed to perform one or more aspects. As an example, deploying an application comprises providing a computer infrastructure to perform one or more aspects.
As an additional aspect, an infrastructure of
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computation can be deployed, comprising a computer-readable code integral to a computing system, in which the code, in combination with the computing system, is capable of performing one or more aspects.
As yet one aspect of a process for integrating one comprises integrating additional code, computer-readable computing infrastructure can be provided in a computer system. The computer system comprises a computer-readable medium, in which the computer medium comprises one or more aspects. The code in combination with the computer system is capable of performing one or more aspects.
Although various embodiments were described above, these are only examples. For example, computing environments on other architectures may incorporate and use one or more aspects. In addition, vectors of other sizes can be used, and changes can be made to the instructions without departing from one or more aspects. In addition, records other than the vector records can be used. Also, in other embodiments, an operand of the vector may be a memory location, rather than a record of the vector. Other variations are also possible.
Additionally, other types of computing environments can benefit from one or more aspects. As an example, * - · »- * - αλλλβ. · <A«> MirjauΕ> Μ «- K1HM
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INSTITUTO MEXICANO DE ΙΑ PROPERTY INDUSTRIAL a data processing system suitable for storing and / or executing a program code is useful, which includes at least two processors directly or indirectly coupled to memory elements through a system bus. The memory elements include, for example, a local memory used during the actual execution of the program code, a mass storage and a cache memory that provides temporary storage of at least some program code, in order to reduce the number of times code must be retrieved from mass storage during execution.
Devices
Input / Output or I / O (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, flash drives, and other memory media, etc.), can be attached to the system either directly or through intermediate I / O controllers. Network adapters can also be attached to the system to allow the data processing system to be attached to other data processing systems or remote printers or storage devices over private or public mezzanine networks. Modems, cable modems, and Ethernet cards are just a few types of network adapters available.
Referring to Figure 11, the components
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Representatives of a Central Computer 5000 system to implement one or more aspects are represented. Representative central computer 5000 comprises one or more CPUs 5001 in communication with computer memory (i.e., central storage) 5002, as well as I / O interconnects for storage medium devices 5011 and networks 5010 to communicate with others. computers or SAN and the like. The CPU 5001 complies with an architecture that has a designed instruction set and designed functionality. CPU 5001 may have dynamic address translation (DAT) 5003 to transform program addresses (virtual addresses) into actual memory addresses. A DAT typically includes a translation look-ahead buffer (TLB) 5007 to cache translations so that subsequent accesses to the memory block of computer 5002 do not require delay of address translation. Typically, a cache memory 5009 is employed between the memory of the computer 5002 and the processor 5001. Cache 5009 can be hierarchical, having a large cache available for more than one CPU and smaller, faster (lower level) caches between the large cache and each CPU. In some implementations, the lower level caches are split to provide level caches
<img file="MX344922B_D0051.tif" />
lower separate to find instructions_ - v — Iesaccesses the data. In one embodiment, an instruction is searched from memory 5002 by an instruction search unit 5004 via cache memory 5009. The instruction is decoded in an instruction decode unit 5006 and sent (with other instructions in some modes ) to the execution unit or units of instruction 5008. Typically, several execution units 5008 are employed, for example, an arithmetic execution unit, a floating point execution unit, and a branch instruction execution unit. The instruction is executed by the execution unit, having access to the operands of the specified registers of the instruction or of memory, as needed. If an operand (loaded or stored) of memory 5002 is to be accessed, a load / store unit 5005 typically handles the access under the control of the instruction being executed. The instructions can be executed in the circuits of the physical elements or in the internal microcode (fixed instructions) or by a combination of both.
As noted, a computer system includes information in local (or main) storage, as well as addressing, protection, and reference and record of change. Some aspects of addressing include the<sup>67</sup> IMPI ^ Mexican Institute
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address format, the concept of address spaces, the various types of addresses, and the manner in which each type of address is translated into another type of address. Some of the main storages include permanently assigned storage locations. Main storage provides the system with directly addressable, fast-access data storage. Both data and programs are loaded into main storage (of input devices) before they can be processed.
Main storage can include one or more smaller, faster-accessible buffers, sometimes called caches. A cache is typically physically associated with a CPU or an I / O processor. the effects, except on performance, of physical construction and use of the distinctive storage medium are generally not observable by the program.
Separate caches can be kept for instructions and data operands. Information within a cache is kept in contiguous bytes in an integral boundary called a cache block or cache line (or line for short). A model can provide an EXTRACT ATTRIBUTE FROM MEMORY CACHE statement that returns the size of
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<img file="MX344922B_D0052.tif" />
A buffer line in byl-pg- Πη can also provide PRE-SEARCH DATA and RELATIVELY LONG SEARCH DATA instructions, which perform pre-search of the instruction data or cache storage or release of the instruction data. the cache.
Storage is viewed as a long horizontal bit string. For most operations, storage accesses proceed in a sequence from left to right. The bit string is subdivided into units of eight bits. Each eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte location in storage is identified by a unique non-negative integer, which is the address of that byte location, or simply, the address of the byte. The adjacent byte locations have consecutive addresses, starting with 0 on the left, and proceeding in a sequence from left to right. The addresses are unsigned binary integers and are 24, 31 or 64 bits.
Information is transmitted between storage and a CPU or a one-byte channel subsystem, or a group of bytes at a time. Unless specified otherwise in, for example, z / Architecture, a group of bytes in storage is directed by the leftmost byte of the
<img file="MX344922B_D0053.tif" />
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OF THE ERONEBAD ÍNM'STWIAL GROUP. The number of bytes in the group is SS ^ ecified implicitly or explicitly by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, in, for example, z / Architecture, the bits are numbered in a sequence from left to right. In z / Architecture, the leftmost bits are sometimes referred to as the higher-order bits and the rightmost bits as the lower-order bits. Bit numbers are not storage addresses, however. Only bytes can be addressed. To operate on the individual bits of a byte in storage, the entire byte is accessed. The bits in a byte are numbered 0 through 7, from left to right (in, for example, z / Architecture). The bits in an address can be numbered 8-31 or 40-63 for 24-bit addresses, or 1-31 or 33-63 for 31-bit addresses; they are numbered 0-63 for 64-bit addresses. Within any other fixed-length multi-byte format, the bits that make up the format are numbered consecutively starting from 0. For error detection purposes, and preferably for correction, one or more check bits may be transmitted with each byte or with a group of bytes. Such check bits are generated automatically by the machine, and cannot be controlled
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INDUSTRIAL directly by the program. The rapani daHac --- storage are expressed in numbers of bytes. When the length of a field in the store operand is implied by the operation code of an instruction, the field is said to have a fixed length, which can be one, two, four, eight, or sixteen bytes. Larger fields can be involved for some instructions. When the length of a storage operand field is not implied but explicitly stated, the field is said to have a variable length. Variable-length operands can vary in length in one-byte increments (or with some instructions, in multiples of two bytes or other multiples). When information is placed in storage, the contents of only those byte locations that are included in the designated field are replaced, although the width of the physical path for storage may be greater than the length of the field being stored.
Certain units of information are for an integral limit on storage. A limit is called an integral for a unit of information when its storage address is a multiple of the length of the unit in bytes. Special names are given to 2, 4, 8, 16, and 32-byte fields in an integral boundary. A half word is a group of two consecutive bytes in a two-byte boundary and
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is the basic building block of the word instruroirmoc is a group of four consecutive bytes in a four-byte boundary. A double word is a group of eight consecutive bytes in an eight-byte boundary. A quad word is a group of 16 consecutive bytes in a 16-byte boundary. An eightword is a group of 32 consecutive bytes in a 32-byte boundary. When the storage addresses designate half words, words, double words, quad words, and eight words, the binary representation of the address contains one, two, three, four, or five leading zero bits, respectively. The instructions are to be two-byte integral limits. The storage operands of most instructions have no limit alignment requirements.
On devices that implement separate caches for instructions and data operands, a significant delay can be experienced if the program is stored in a cache line from which instructions are subsequently retrieved, regardless of whether storage disrupts instructions to be searched later.
In one embodiment, the invention can be practiced by a program (sometimes referred to as an authorized internal code, fixed instructions, microcode,
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millicode, picocode and the like, any of which would be consistent with one or more aspects). Referring to Figure 11, program code incorporating one or more aspects can be accessed by processor 5001 of central system 5000 of long-term storage medium devices 5011, such as a CD-ROM drive, a drive tape or a hard drive. The program code can be incorporated into any of a variety of media known for use with the data processing system, such as a floppy disk, hard disk, or CD-ROM. The code may be distributed on such a medium, or it may be distributed to users of the memory of computer 5002 or storage of a computer system on a network 5010 to other computer systems for use by users of such other systems.
The program code includes an operating system that controls the function and interaction of the various components of the computer and one or more application programs. The program code is typically paged on the device from storage medium 5011 to relatively higher speed computer storage 5002, where it is available for processing by processor 5001. The techniques and methods for incorporating the program code in memory, on the physical medium and / or distributing the program code via networks, are well
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INt> UST «ITB ------- known and will not be discussed further in this document. Program code, when sT'creates and stores on tangible medium (including but not limited to, electronic memory (RAM) modules, flash memory, Compact Disks (CD), DVD, Magnetic Tape and the like, often it is referred to as a computer program product. The medium of the computer program product is typically readable by a processing circuit, preferably in a computer system for execution by the processing circuit.
Figure 12 illustrates a representative server workstation or hardware system, in which one or more aspects may be practiced. System 5020 of Figure 12 comprises a representative base computer system 5021, such as a personal computer, workstation, or server, including optional peripheral devices. Base computer system 5021 includes one or more processors 5026 and a bus used to connect and enable communication between processor 5026 and the other components of system 5021, according to known techniques. The bus connects the 5026 processor to 5025 memory and 5027 long-term storage, which can include a hard drive (including any of a magnetic media, CD, DVD, and Memory
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Snapshot, for example) or a tape drive ^ —p ^ eg emolo.
The 5021 system may also include a user interface adapter, which connects the 5026 microprocessor via the bus to one or more interconnect devices, such as a 5024 keyboard, 5023 mouse, 5030 printer / scanner, and / or other devices. interface, which can be any user interface device, such as a touch screen, digitized input pad, etc. The bus also connects a display device 5022, such as an LCD screen or monitor, to the microprocessor 5026 via a display adapter.
System 5021 can communicate with other computers or computer networks via a network adapter, capable of communicating 5028 with a 5029 network. Exemplary network adapters are communication channels, ring networks, Ethernet, or modems. Alternatively, the 5021 system can communicate using a wireless interface, such as a CDPD (cellular digital packet data) card. The 5021 system can associate with such other computers on a Local Area Network (LAN), or a Wide Area Network (WAN), or the 5021 system can be a client in a client / server array with another computer, etc. All of these configurations, as well as appropriate communications hardware and programs, are known in the art.
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Figure 13 illustrates a data processing network 5040 in which one or more aspects can be practiced. The data processing network 5040 may include a plurality of individual networks, such as a wireless network and a wired network, each of which may include a plurality of individual workstations 5041, 5042, 5043, 5044. Furthermore, as those of skill in the art will appreciate, one or more LANs may be included, wherein a LAN may comprise a plurality of smart workstations 10 coupled to a central processor.
Still referring to Figure 13, networks can also include central computers or servers, such as a gateway computer (client server 5046) or application server (remote server 5048 that can access a data warehouse, and can also accessed directly from a 5045 workstation). A 5046 gateway computer serves as an entry point into each individual network. A gateway is required when one network protocol connects to another. Gateway 5046 20 may preferably be coupled to another network (the Internet 5047, for example), via a communications link. Gateway 5046 can also be directly coupled to one or more workstations 5041, 5042, 5043, 5044 using a communication link. The gateway computer can be deployed using a z server eServer ™ System from<sup>76</sup> IMPIQ
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Concurrently referring to Figure 12 and Figure 13, programming code that may incorporate one or more aspects of the present invention can be accessed by processor 5026 of long-term storage medium 5027 system 5027, such as a CD-ROM drive or hard disk. The programming code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard disk, or CD-ROM. The code may be distributed on such a medium, or it may be distributed to users 5050, 5051 of the memory or storage of one computer system over a network to other computer systems for use by users of such other systems.
Alternatively, the programming code can be embedded in memory 5025, and accessed by processor 5026 using the processor bus. Such programming code includes an operating system that controls the function and interaction of the various components of the computer and one or more application programs 5032. Program code is typically paged from storage medium 5027 to high speed memory 5025, where it is available for processing by the processor.
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5026. Techniques and methods for embedding the programming tool in memory, on the physical medium, and / or distributing program code via networks, are well known, and will not be discussed further herein. Program code, when created and stored on tangible media (including but not limited to, electronic memory (RAM) modules, flash memory, Compact Disks (CD), DVDs, Magnetic Tape, and the like, are often referred to as a computer program product. The medium of the computer program product is typically readable by a processing circuit, preferably in a computer system for execution by the processing circuit.
The cache that is most readily available to the processor (typically faster and smaller than other processor caches), is the lowest cache (L1 or level one), and main storage (main memory) is the cache memory of highest level (L3 if there are 3 levels). The lowest-level cache is often divided into an instruction cache (I-Memory Cache) that holds the machine's instructions to be executed and a data cache (D-Cache) that holds the operands. of the data.
Referring to Figure 14, one embodiment of the
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Exemplary processor is described for processor 5026.
Typically, one or more levels of cache 5053 are used for buffer blocks in order to improve processor performance. The 5053 cache is a high-speed buffer that maintains the cache lines of memory data that are likely to be used. Typical cache lines are 64, 128, or 256 bytes of memory data. Separate caches are often used for staging data. Cache consistency (synchronization of line copies in memory and in caches) is often provided by various spy algorithms well known in the art. The storage of the main memory 5025 of a processor system is often referred to as a cache memory. In a processor system that has 4 levels of cache 5053, main storage 5025 is sometimes referred to as cache level 5 (L5), since it is typically faster and only holds a portion of the storage (DASD, tape , etc.), which is available for a computer system. Main storage 5025 staging data pages paged into and out of main storage 5025 by the operating system.
A program counter (program counter
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branch statement, for example. In a context switch operation, the current program counter value is stored in the program status word along with other status information about the program that is running (such as condition codes), and a New value of the program counter is loaded pointing to an instruction of a new program module to be executed. A branch operation taken is performed in order to allow the program to make decisions or loop within the program to load the result of the branch instruction into program counter 5061.
Typically, an instruction search unit 5055 is used to search for instructions on behalf of processor 5026. The search unit searches for either the next sequential instructions, the target instructions of the instructions to take the branch, or the first instruction of a program after a context change. Modern Instructions search units often employ pre-search techniques to speculatively pre-search for instructions based on the probability that the pre-search instructions can be used. For example, a search unit can search for 16 bytes of the instruction that includes the next sequential instruction and the extra bytes of the furthest sequential instructions.
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Searched instructions are ----- ajarnf add ..— then__ by processor 5026. In one mode, the searched instructions are passed to a search unit sending unit 5056. The sending unit decodes the instructions and sends the information about the decoded instructions to the appropriate units 5057, 5058, 5060. An execution unit 5057 will typically receive the information about the decoded arithmetic instructions from the instruction search unit 5055, and will perform the arithmetic operations on the operands according to the opcode of the instruction. Operands are provided to execution unit 5057 preferably from memory 5025, designed registers 5059, or from the immediate field of the instruction being executed. Execution results, when stored, are stored either in memory 5025, registers 5059, or other physical elements of the machine (such as control registers, PSW registers, and the like).
A processor 5026 typically has one or more units 5057, 5058, 5060 to execute the function of the instruction. Referring to Figure 15A, an execution unit 5057 can communicate 5081 with the general designed registers 5059, a decoding / sending unit 5056, a load storage unit 506 0, and other processor units 5065 by means of a logic from<sup>82 </sup>MEXICAN INSTITUTE OF rtOPUDAO Ί
INDUSTRIAL-5071 interconnect. A 5057 execution unit may employ several register circuits 5067, 5068, 5069 to maintain the information that will operate in the arithmetic logic unit (ALU) 5066. The ALU performs arithmetic operations such as addition , subtraction, multiplication, and division, as well as logical functions such as and, or, and exclusive-or (XOR), rotate, and shift. Preferably, the ALU supports specialized operations that are design dependent. Other circuits may provide other 5072 designed facilities including condition codes and recovery support logic, for example. Typically, the result of an ALU operation is maintained in a register-out circuit 5070 that can send the result to a variety of other processing functions. There are many arrangements of processor units, the present description is only intended to provide a representative understanding of one embodiment.
An ADD statement, for example, would run in a 5057 execution unit that has arithmetic and logic functionality, while a floating-point instruction, for example, would run in a floating-point execution that has specialized floating-point capability. . Preferably, an execution unit operates on operands identified by a
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Execution unit 5057 performs the arithmetic addition of two operands and stores the result in a third operand, where the third operand can be a third register or one of the two source registers. The execution unit preferably uses an Arithmetic Logic Unit (ALU) 5066, which is capable of performing a variety of logic functions such as Shift, Rotate, And, Or, and XOR, as well as a variety of algebraic functions including any summation , subtraction, multiplication, division. Some ALU 5066s are designed for scalar operations and some for floating point. The data can be of Inverse Format (Big Endian) (where the least significant byte is in the direction of the highest byte), or of Direct Format (Little Endian) (where the least significant byte is in the direction of the highest byte). low), depending on the architecture. IBM's z / Architecture is Big Endian. The signed fields can be sign and magnitude, complement or complement to 2 depending on the architecture. A 2's complement number is advantageous in that the ALU need not design a subtraction capability.
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Referring to Figure 15B, the branch instruction information for executing a branch instruction is typically sent to a branch unit 5058 which often employs a branch prediction algorithm, such as a branch history table 5082. to predict the outcome of the fork before other conditional operations are completed. The target of the current branch instruction will be speculatively searched and executed before the conditional operations are completed. When the conditional operations are completed, the speculatively executed branch instructions are terminated or unloaded based on the conditions of the conditional operation and the speculated result. A typical branching instruction can test the condition codes and branch to a target address If the condition codes meet the branching instruction requirement for branching, a target address can be calculated based on multiple numbers, including ones found in the fields of
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The execution of a group of instructions can be interrupted for a variety of reasons, including a context switch initiated by an operating system, a program exception or an error that causes a context switch, an I / O interrupt signal that causes a changing the context or a multi-threaded activity of a plurality of programs (in a multi-threaded medium), for example. Preferably a context switch action saves state information about a currently running program, and then loads state information about another program that is invoked. The status information can be stored in the registers of the physical elements or in a memory, for example. The status information preferably comprises a program counter value pointing to the next instruction to be executed, condition codes, memory translation information, and content of the designed register. A context switch activity can<sup>86</sup> IMPI ^
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A processor accesses the operands according to the methods defined by the instruction. The instruction can provide an immediate operand using the value of a portion of the instruction, it can provide one or more record fields pointing explicitly to general-purpose registers or special-purpose registers (floating point registers, for example) . The instruction can use the involved registers identified by an opcode field as operands. The instruction can use instructions from memory for operands. A memory location of an operand can be provided by a record, an immediate field, or a combination of records and the immediate field as exemplified by the z / Architecture long offset facility, where the statement defines a base register , an index register and an immediate field (offset field), which are added together to provide the address of the operand in memory, for example. The location here typically implies a location in main memory (main storage), unless stated otherwise.
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Referring to Figure 15C, a processor accesses storage using a 5060 load / storage unit. The load / store unit 5060 may perform a load operation by obtaining the address of the target operand in memory 5053, and loading the operand into a register 5059 or other memory location 5053, or it may perform a store operation, obtaining the address of the target operand in memory 5 0 53 and storing the data obtained from a register 5059 or other location of memory 5053 at the location of the target operand, in memory 5053. The loading / storage unit 5060 may be speculative and may access memory in a sequence that is out of order relative to the instruction sequence, however the loading / storage unit 5060 must maintain appearance for programs, that the instructions were executed in order. A load / storage unit 5060 can communicate 5084 with the general registers 5059, the decoding / sending unit 5056, the cache / memory interface 5053 or other elements 5083, and comprises several register circuits 5086, 5087, 5088 and 5089 , ALU 5085, and control logic 5090 to calculate storage addresses, and to provide flow sequencing to keep operations in order. Some operations may be out of order, but the load / storage unit provides -la. functionality to make out-of-order operations appear to the program as having been performed in order, as is well known in the art.
Preferably the addresses that an application program sees are often referred to as virtual addresses. Virtual addresses are sometimes referred to as logical addresses and effective addresses. These virtual addresses are virtual in that they are redirected to the physical memory location by one of a variety of dynamic address translation (DAT) technologies including, but not limited to, simply prefixing a virtual address with a compensated value, translate the virtual address via one or more translation tables, the translation tables preferably comprise at least one segment table and one page table alone or in combination, Preferably, the segment table has an entry indication for the page table. In z / Architecture, a translation hierarchy is provided that includes a first region table, a second region table, a third region table, a segment table, and an optional page table. The performance of address translation is often improved by using a translation look-ahead buffer of
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In the case where the processor is a processor in a multi-processor system, each processor is responsible for keeping shared resources, such as I / O, buffers, TLBs, and memory, locked for consistency. Typically, spy technologies will be used to maintain cache consistency. In a spy environment, each cache line can be marked as being in any of a shared state, an exclusive state, a changed state, an invalid state, and the like, in order to facilitate sharing.
The 1/0 5054 drives (Figure 14) provide the processor with means to attach to peripheral devices, including tapes, disks, printers, displays, and networks, for example. 1/0 units are presented with
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frequency to the program drivers program. In such as IBM's System z, the central computer system adapters, which between the operating system and the
Also, other types
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The open computing environments provide devices can benefit from one or more aspects. As an example, an environment may include an emulator (for example, program or other emulation mechanisms), in which a particular architecture (including, for example, instruction execution, designed functions, such as address translation and designed registers), or a subset of it is emulated (for example, in a native computer system that has a processor and memory). In such an environment, one or more emulator functions of the emulator may implement one or more modalities, although a computer running the emulator may have a different architecture than the capabilities being emulated. As an example, in the emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
In an emulation environment, a central computer includes, for example, a memory for storing the instructions and data, a search unit of Isa instructions for searching the instructions from a memory, and optionally providing local storage for the searched instruction, a instruction decoding unit for receiving the searched instructions and determining the type of instructions that have been searched; and an instruction execution unit for executing the instructions. Execution may include loading the data into a memory register, storing the data back into a register memory, or performing some type of arithmetic or logic operation, as determined by the decoding unit. In one example, each unit is implemented in the program. For example, the operations being performed by the units are implemented as one or more subroutines within an emulator program.
More particularly, in a central computer, the designed machine instructions are used by programmers, usually today's C programmers, often by means of a compiler application. These instructions stored on the storage medium can be executed natively on an IBM z / Architecture Server, or alternatively, on machines running other architectures. They can be emulated on © © existing and future host servers
IBM and other IBM machines (for example, Power servers
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machines running Linux on a wide variety of machines using physical elements made by IBM®, Intel®, AMD ™ and others. In addition to running on these physical elements under z / Architecture, Linux can be used as well as machines that use emulation through Hercules, UMX or FSI (Fundamental Software, Inc), where the execution is generally in an emulation mode. In emulation mode, the emulation program is run by the native processor to emulate the architecture of an emulated processor.
The native processor typically runs the emulation program comprising the physical instructions or a native operating system to emulate the emulated processor. The emulation program is responsible for finding and executing the instructions for the emulated processor architecture. The emulation program maintains a counter of the emulated program to keep track of the instruction limits. The emulation program may search for one or more instructions from the emulated machine at a time, and convert one or more instructions from the emulated machine to a corresponding set of instructions from the native machine for execution by the native processor. These converted instructions can be temporarily stored so that a faster conversion can be achieved. Without
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However, the emulation program must maintain the architecture rules of the emulated processor architecture to ensure that the operating systems and applications written by the emulated processor operate correctly. In addition, the emulation program must provide resources identified by the emulated processor architecture including, but not limited to, control registers, general-purpose registers, floating-point registers, dynamic address translation function, including segment tables, and tables on the page, for example, interrupt mechanisms, context switch mechanisms, Time of Day (TOD) clocks, and interconnects designed for 1/0 subsystems, so that an operating system or an application program designed to run on the emulated processor can run on the native processor that has the emulation program.
A specific instruction being emulated is decoded, and a subroutine is called to perform the function of the individual instruction. A function of the emulation program that emulates a function of an emulated processor, is implemented, for example, in a subroutine or C controller, or some other method to provide a controller for specific physical elements, as will be within the experience of those in the art after understanding the description of one or more modalities.
INDUSTRIAL
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Various software and physical element emulation patents including, but not limited to, US Patent Document No. 5,551,013, entitled Multiprocessor for Emulation of Physical Elements, by Beausoleil et al .; and the United States Patent Document
States No. 6,009,261, entitled Preprocessing Stored Target Routines to Emulate Incompatible Instructions on a Target Processor, by Scalzi et al; and United States Patent Document No. 5,574,873, entitled 10 Decoding a Guest Instruction to Access
Directly to Emulation Routines Emulating Guest Instructions, by Davidian et al; and United States Patent Document No. 6,308,255, entitled Symmetric Multiprocessing Bus and Microcircuit Used for 15 Coprocessor Support Allowing Code No.
Native Run in a System, by Gorishek et al; and US Patent Document No. 6,463,582, entitled Dynamic Optimization of Object Code Translator for Architecture Emulation and Dynamic Optimization Method of Object Code Translation, by Lethin et al; and United States Patent Document No. 5,790,825, entitled Method of Emulating Guest Instructions on a Central Computer Through Dynamic Collection of Central Instructions, by 25 Eric Traut, each of which is incorporated herein
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document for reference in its entirety; and many others.
illustrate a variety of known ways to achieve emulation of an instruction format designed for a different machine than a target machine available to those of skill in the art.
In Figure 16, an example of an emulated host computer system 5092 is provided that emulates a host computer system 5000 'of a core architecture. In the 5092 emulated central computer system, the 5091 central processor (CPU) is an emulated central processor (or virtual central processor), and comprises a 5093 emulation processor that has a different native instruction set architecture than the 5091 processor of the central computer 5000 '. The emulated host computer system 5092 has a memory 5094 accessible to the emulation processor 5093. In the exemplary mode, the memory 5094 is divided into a portion of the computer memory 5096 and a portion of the emulation routines 5097. The memory from the 5096 mainframe is available to the 5092 emulated mainframe programs according to the mainframe architecture. The emulation processor 5093 executes the native instructions of a set of instructions designed of a different architecture than that of the emulated processor 5091, the native instructions obtained
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The terminology used herein is for the purpose of describing the particular modalities only, and is not intended to be limiting. How I know
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used herein, the singular forms a. una and el, la, are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and / or comprising, when used in this specification, specify the presence of indicated characteristics, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more of other characteristics, integers, steps, operations, elements, components and / or groups thereof.
The corresponding structures, materials, acts and equivalents of all means or elements of passage plus function in the following claims, if any, are intended to include any structure, material or act to perform the function, in combination with other elements claimed as claimed specifically. The description of one or more embodiments has been presented for purposes of illustration and description, but it is not intended to be exhaustive or limited to the manner described. Many modifications and variations will be apparent to those of ordinary skill in the art. The modality was chosen and described in order to better explain various aspects and practical application, and to enable others of ordinary skill in the art to understand various modalities with various modifications that are suitable for the particular use contemplated.
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Contents95
98 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36 Sheet 37 Sheet 38 Sheet 39 Sheet 40 Sheet 41 Sheet 42 Sheet 43 Sheet 44 Sheet 45 Sheet 46 Sheet 47 Sheet 48 Sheet 49 Sheet 50 Sheet 51 Sheet 52 Sheet 53 Sheet 54 Sheet 55 Sheet 56 Sheet 57 Sheet 58 Sheet 59 Sheet 60 Sheet 61 Sheet 62 Sheet 63 Sheet 64 Sheet 65 Sheet 66 Sheet 67 Sheet 68 Sheet 69 Sheet 70 Sheet 71 Sheet 72 Sheet 73 Sheet 74 Sheet 75 Sheet 76 Sheet 77 Sheet 78 Sheet 79 Sheet 80 Sheet 81 Sheet 82 Sheet 83 Sheet 84 Sheet 85 Sheet 86 Sheet 87 Sheet 88 Sheet 89 Sheet 90 Sheet 91 Sheet 92 Sheet 93 Sheet 94 Sheet 95 Sheet 96 Sheet 97 Sheet 98
32 members in 12 offices
Priority claims9
| Document | Office | Kind | Date |
|---|---|---|---|
| 13748495 | United States of America | – | |
| 201313748495 | United States of America | A | |
| 201313748495 | United States of America | A | |
| 2013060637 | International Bureau of the World Intellectual Property Organization (WIPO) | W | |
| 2013060637 | International Bureau of the World Intellectual Property Organization (WIPO) | W | |
| 13748495 | – | – | – |
| PCTIB2013060637 | – | – | – |
| US201313748495 | – | – | – |
| WO2013IB60637 | – | – | – |
Members32
| Document | Office | Kind | |
|---|---|---|---|
| US2014208078A1 | United States of America | A1 | |
| CA2895650A1 | Canada | A1 | |
| WO2014115001A1 | World Intellectual Property Organization (WIPO) | A1 | |
| US2015143080A1 | United States of America | A1 | |
| SG11201503779XA | Singapore | A | |
| AU2013375139A1 | Australia | A1 | |
| CN104937542A | China | A | |
| IL240106A0 | Israel | A0 | |
| MX2015009457A | Mexico | A | |
| KR20150110497A | Republic of Korea | A | |
| EP2948843A1 | European Patent Office (EPO) | A1 | |
| JP2016509715A | Japan | A | |
| EP2948843A4 | European Patent Office (EPO) | A4 | |
| US9471311B2 | United States of America | B2 | |
| US9513906B2 | United States of America | B2 | |
| MX344922BThis record | Mexico | B | |
| RU2608663C1 | Russian Federation | C1 | |
| AU2013375139B2 | Australia | B2 | |
| US2017031683A1 | United States of America | A1 | |
| US2017039067A1 | United States of America | A1 | |
| KR101740839B1 | Republic of Korea | B1 | |
| US9733938B2 | United States of America | B2 | |
| US9740483B2 | United States of America | B2 | |
| US2017262284A1 | United States of America | A1 | |
| CN104937542B | China | B | |
| JP6323837B2 | Japan | B2 | |
| US10101998B2 | United States of America | B2 | |
| US2019034202A1 | United States of America | A1 | |
| IL240106A | Israel | A | |
| IL240106B | Israel | B | |
| US10606589B2 | United States of America | B2 | |
| CA2895650C | Canada | C |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Grant or registrationFG | FG |
Numbers
- Publication
- 344922
- Publication, DOCDB
- 344922
- Publication, EPODOC
- MX344922
- Application
- 2015009457
- Application, DOCDB
- 2015009457
- Application, EPODOC
- MX20150009457
Titles2
- Spanish
- INSTRUCCIÓN DE SUMA DE COMPROBACIÓN DEL VECTOR.
- English
- VECTOR CHECK SUM INSTRUCTION.
Classification
- CPC, 10
- G06F9/3001
- G06F9/30
- G06F7/508
- G06F9/30036
- G06F9/30038
- G06F7/38
- G06F9/30098
- G06F11/1004
- G06F9/30032
- G06F9/3013
- IPC, 1
- G06F9 30