Micro light emitting diode.
Abstract
A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Term
6.1 yearsleft in the term
Expires 8 November 2032.
- Priority
- Filed
- Granted
- Today
- Expires
31 claims: 5 independent, 26 dependent
- 1REIVINDICACIONES 1. Una estructura de microLEDs que comprende:un microdiodo p-n;5 una capa de metalización;en donde la capa de metalización se encuentra entre el microdiodo p-n y una capa de enlace formada en un sustrato;y una capa de barrera de conformación que comprende una sola capa de un mismo material que se extiende a las paredes laterales del microdiodo 10 p-n, paredes laterales de la capa de metalización y paredes laterales de la capa de enlace.
- 2La estructura de microLEDs de conformidad con la reivindicación 1, donde la capa de enlace tiene una temperatura de liquidus por debajo de aproximadamente 350 °C. 15
- 3La estructura de microLEDs de conformidad con la reivindicación 1, en donde la capa de barrera de conformación forma un contorno de la topografía de las paredes laterales del microdiodo p-n, las paredes laterales de la capa de metalización, y las paredes laterales de la capa de enlace. 20
- 4La estructura de microLEDs de conformidad con la reivindicación 1, en donde la sola capa de un mismo material es una capa de de barrera dieléctrica de conformación se extiende parcialmente a una I Μ. Ρ ϊ INSTITUTO MEXICANO ΓχDE ΙΑ mOTIEDAD O induSTMal * superficie inferior del microdiodo p-n. —
- 5La estructura de microLEDs de conformidad con la reivindicación 4, que además comprende una abertura en la capa de barrera dieléctrica de conformación que expone una superficie superior del 5 microdiodo p-n, en donde la abertura tiene una anchura seleccionada del grupo que consiste en:mayor a una anchura de la superficie superior del microdiodo p-n;menor a la anchura de la superficie superior del microdiodo p-n;y aproximadamente la misma que la anchura de la superficie superior 10 del microdiodo p-n.
- 6La estructura de microLEDs de conformidad con la reivindicación 1, en donde:el microdiodo p-n comprende una superficie superior y una superficie inferior;i 15 la capa de metalización comprende una superficie superior y una superficie inferior;y , la superficie inferior del microdiodo p-n es más ancha que la superficie superior de la capa de metalización.
- 7La estructura de microLEDs de conformidad con la 20 reivindicación 1, en donde la capa de enlace comprende indio o estaño.
- 8La estructura de microLEDs de conformidad con la reivindicación 1, en donde la capa de enlace comprende polietileno o IMPI INSTITUTO MEXICANO DE IA RROPIIDAD INDUSTRIAL polipropileno. ____
- 9La estructura de microLEDs de conformidad con la reivindicación 1, en donde el microdiodo p-n comprende nitruro de galio.
- 10La estructura de microLEDs de conformidad con la reivindicación 1, en donde la capa de metalización comprende una capa de electrodo y una capa de barrera entre la capa de electrodo y la capa de enlace.
- 11La estructura de microLEDs de conformidad con la reivindicación 1, en donde el microdiodo p-n comprende una superficie superior, una superficie inferior y paredes laterales ahusadas.
- 12El microLED de conformidad con la reivindicación 11, en donde la superficie inferior es más ancha que la superficie superior.
- 13El micro LED de conformidad con la reivindicación 11, en donde la superficie superior es más ancha que la superficie inferior o tiene el mismo ancho que la superficie inferior.
- 14La estructura de microLEDs de conformidad con la reivindicación 1, en donde:el microdiodo p-n comprende una superficie superior y una superficie inferior;la capa de enlace comprende una superficie superior y una superficie inferior;y la superficie inferior del microdiodo p-n es más ancha que la superficie superior de la capa de enlace. ΙΜΡΪ INSTITUTO MEXICANO DF LA PROPIEDAD INDUSTRIAL
- 15La estructura de microLEDs de cüllfUlllilLlad' luii lareivindicación 1, en donde:el microdiodo p-n comprende una superficie superior y una superficie inferior;la capa de enlace comprende una superficie superior y una superficie inferior;y la superficie inferior del microdiodo p-n es de aproximadamente la misma anchura que la superficie superior de la capa de enlace.
- 16La estructura de microLEDs de conformidad con la reivindicación 1, en donde la sola capa de un mismo material que se extiende a las paredes laterales del microdiodo p-n, paredes laterales de la capa de metalización, y las paredes laterales de la capa de enlace es continua.
- 17La estructura de microLEDs de conformidad con la reivindicación 1, en donde el mismo material comprende AI2O3.
- 18Un arreglo de microLEDs que comprende:una pluralidad de ubicaciones de una capa de enlace en un sustrato;una pluralidad correspondiente de estructuras de microLEDs en la pluralidad de ubicaciones de la capa de enlace, en donde cada estructura de microLEDs comprende: un microdiodo p-n;y una capa de metalización, en donde la capa de ΙΜΡΙ INSTITUTO MEXICANO ’/J-'&iKSÍrSÍDI LA PROPIEDAD CV.JÍ3Sj ^>.¿1 INDUSTRIAL metalización se encuentra entre el microdiodo p-n y unaWluauiÜll lUspuuLIvade la capa de enlace;y una capa de barrera de conformación que comprende una sola capa de un mismo material que se extiende a las paredes laterales de cada micro 5 diodo p-n, paredes laterales de la capa de metalización, y paredes laterales de cada una de la pluralidad de ubicaciones de la capa de enlace.
- 19El arreglo de microLEDs de conformidad con la reivindicación 18, donde la capa de enlace tiene una temperatura de liquidus por debajo de aproximadamente 350 °C. 10 20. El arreglo de microLEDs de conformidad con la reivindicación 18, en donde la capa de barrera de conformación forma un contorno de la topografía de las paredes laterales del microdiodo p-n, las paredes laterales de la capa de metalización, y las paredes laterales de la capa de enlace. 21. El arreglo de microLEDs de conformidad con la reivindicación 15 18, en donde la sola capa de un mismo material es una capa de barrera dieléctrica de conformación se extiende parcialmente a una superficie inferior del microdiodo p-n. 22. La estructura de microLEDs de conformidad con la reivindicación 21, que además comprende una pluralidad de aberturas en la
- 2020 capa de barrera dieléctrica de conformación que expone una superficie superior de cada microdiodo p-n, en donde cada abertura tiene una anchura seleccionada del grupo que consiste en:IMPI INSTITUTO MEXICANO OE LA PROPIEDAD INDUSTRIAL mayor a una anchura de la superficie superiorde on~niiuiudiodo p-n correspondiente;menor a la anchura de la superficie superior del microdiodo p-n correspondiente;y aproximadamente la misma que la anchura de la superficie superior del microdiodo p-n correspondiente.
- 2123. La estructura de microLEDs de conformidad con la reivindicación 18, en donde la pluralidad de ubicaciones de la capa de enlace se separa lateralmente.
- 2224. El arreglo de microLEDs de conformidad con la reivindicación 23, en donde el sustrato comprende una pluralidad respectiva de pilares, y la pluralidad de ubicaciones de la capa de enlace se forma en la pluralidad respectiva de pilares.
- 2325. El arreglo de microLEDs de conformidad con la reivindicación 24, en donde cada microdiodo p-n comprende una superficie inferior que es de aproximadamente la misma anchura que una superficie superior de un pilar respectivo.
- 2426. El arreglo de microLEDs de conformidad con la reivindicación 24, en donde cada microdiodo p-n comprende una superficie inferior que es más ancha que la anchura de una superficie superior de un pilar respectivo.
- 2527. El arreglo de microLEDs de conformidad con la reivindicación 24, en donde la pluralidad respectiva de pilares tiene cada uno, una altura respectiva que es mayor a un grosor respectivo de cada una de las ubicaciones de la capa de enlace.
- 2628. El arreglo de microLEDs de conformidad con la reivindicación 27, en donde, en donde cada altura respectiva es por lo menos dos veces el grosor respectivo.
- 2729. El arreglo de microLEDs de conformidad con la reivindicación 18, en donde la pluralidad de ubicaciones de la capa de enlace no se separa lateralmente.
- 2830. El arreglo de microLEDs de conformidad con la reivindicación 18, en donde:cada microdiodo p-n comprende una superficie superior y una superficie inferior;cada capa de metalización comprende una superficie superior y una superficie inferior;y la superficie inferior de cada microdiodo p-n es más ancha que la superficie superior correspondiente de la capa de metalización.
- 2931. El arreglo de microLEDs de conformidad con la reivindicación 18, en donde cada microdiodo p-n comprende una superficie superior y una superficie inferior la cual es más ancho que la superficie superior.
- 3032. La estructura de microLEDs de conformidad con la reivindicación 18, en donde cada porción de la sola capa de un mismo material que se extiende a las paredes laterales de cada microdiodo p-n, las paredes IMPI INSTITUTO MEXICANO DS LA MtOMEDAD INDUSTRIAL laterales de cada capa de metalización, y las paredes laterales de la uapsTdS enlace es continua.
- 3133. La estructura de microLEDs de conformidad con la reivindicación 18, en donde el mismo material comprende AI2O3. IMPI INSTITUT· MEXICANO O€ LA FROHEDAD INDUSTRIAL
Independent claims31
285 paragraphs in 83 sections, as filed
(54) Title: LIGHT EMITTING MICRODIODE. (54) Title: MICRO LIGHT EMITTING DIODE.
(57) Summary
A light emitting microdiode (LED) and a method of forming an array of microLEDs for transfer to a receptor substrate are described. The microLED structure can include a pn microdiode and a metallization layer, with the metallization layer between the pn microdiode and a bonding layer. A dielectric forming barrier layer can extend to the side walls of the pn microdiode. The microLED structure and microLED array can be collected and transferred to a receptor substrate.
(57) Abstract
A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may inelude a micro pn diode and a metallization layer, with the metallization layer between the micro pn diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro pn diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
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of the
SE eCSfUWM, Ot iCONOMÍA
Mexican Institute of Industrial Property _ PATENT TITLE NO. 340348
Owner (s): APPLE INC.
Address: 1 Infinite Loop, Cupertino, California, 95014, USA
Name: LIGHT EMITTING MICRODIODE.
Classification: lnt.CI.8: H01L27 / 15; H01L29 / 18; H01L33 / 00; H01L33 / 08
Inventor (s): ANDREAS BIBL; JOHN A. HIGGINSON; HUNG-FAI STEPHEN LAW; HSIN-HUA
HU
REQUEST
Number: International filing date:
MX / a / 2014/005969 November 08, 2012
PRIORITY
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<td>Country:</td><td>Date:</td><td>Number:</td>
<td>US</td><td>November 18, 2011</td><td> 61/561,706</td>
<td>US</td><td>February 3, 2012</td><td> 61/594,919</td>
<td>US</td><td>February 13, 2012</td><td> 13/372,222</td>
<td>US</td><td>February 13, 2012</td><td> 13/372,245</td>
<td>US</td><td>February 13, 2012</td><td> 13/372,258</td>
Validity: Twenty years
Expiration Date: November 8, 2032
The reference patent is granted based on articles 1. 2nd fraction V, 6th fraction IH, and 89 data Industrial Property Law.
In accordance with article 23 of the Industrial Property Law, this patent has a validity of twenty non-expendable years, cut from the date of filing of the international application and will be subject to payment of the fee to maintain the validity of the ^ rights. ·. · ·
Whoever subscribes to this title does so under the provisions of articles 0 * sections lll and 7 ° bis 2 of the Industrial Property Law (Official Reference of the Federation (DO.F.) 06/27/1881, amended at 08/02/1894 10/25/1996, 12/26/1397, 05/17/1999, 01/26/2004, 06/16/2005, 01/25/2006, 05/06/2009 / 06 / 01/2010, 18/08 / 2010,28 / 06/2010, 27/01 / 20- / 2 and 04/09/2012); Articles 1 ', 3rd fraction V Clause a), sub clause ii) 4th and diffractions I and lll of the Regulation dét ΙΜβΜΟίΟΜβοηο of Industrial Property (DC ^ F 14/12/1999, deformed on 07/01/2002, 07/15/2 ^ 14,28 / 07/2004 and 7/09/2007), articles 1, 3, 4, 5, section V, item a), subsection iii), 16 fifecdones I and lll and SO of the Organic Statute of the Mexican Institute of Property tndustrfat (OOF 12/27/1399, reformed et 10/10/2002, 07/29/2004, 08/04/2004 and 09/13/2007); 1, 3 and 5 Subsection a) and antepenultimate paragraph of the Agreement that delegates powers to the Deputy Directors General, Coordinator, Divisional Directors, Heads of Regional Offices, Divisional Deputy Directors, Departmental Coordinators and other subordinates of the Mexican Institute of Property Industrial. (DOF 12/15/1999, amended on 02/04/2000, 07/29/2004, 08/04/2004 and 09/13/2007).
Issue Date: July 6, 2016
DIVISIONAL ASSISTANT DIRECTOR OF PATENT FUND EXAMINATION, AREAS
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Saw ^ g
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MEXICAN INSTITUTE OF INDUSTRIAL PROPERTY
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LIGHT EMITTING MICRODIODE
FIELD OF THE INVENTION
The present invention relates to semiconductor microdevices. More particularly, the embodiments of the present invention relate to a method of forming an array of microdevices such as light emitting diodes (LEDs) to transfer to a different substrate.
BACKGROUND OF THE INVENTION
Gallium nitride (GaN) based light emitting diodes (LEDs) are expected to be used in high-efficiency lighting applications in the future, replacing incandescent and fluorescent lighting lamps. Current GaN-based LED devices are prepared by heteroepitaxlal growth techniques on foreign substrate materials. A typical wafer-level LED device structure may include a lower n doping GaN layer formed on a sapphire growth substrate, a single quantum well (SQW) or multiple quantum wells (MWQ), and a GaN layer doping p higher.
In one implementation, the wafer level LED device structure is etched into a table array on the sapphire growth substrate by acid etching through the top p doping GaN layer,
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quantum well layer, and towards the doping GaN layer n. An upper p electrode is formed on the upper p doping GaN surfaces of the table array, and an n electrode is formed on a portion of the doping GaN layer n that is in contact with the table array. Tabletop LED devices remain on the sapphire growth substrate in the final product.
In another implementation, the wafer-level LED device structure is transferred from the growth substrate to an acceptor substrate such as silicon, which has the advantage of being more easily chopped to form individual chips than a composite GaN / sapphire structure . In this implementation, the wafer level LED device structure is permanently bonded to the acceptor substrate (silicon) with a permanent bonding layer. For example, the electrode p formed on the doping GaN surfaces p of the table array can be bonded to the acceptor substrate (silicon) with a permanent bonding layer. The sapphire growth substrate is then removed to expose the inverted wafer level LED device structure, which is then thinned to expose the table arrangement. The n contacts are then made with the exposed doping GaN n, and the p contacts are made on the silicon surface that is in electrical contact with the p electrode. Tabletop LED devices remain on the acceptor substrate in the final product. The GaN / silicon combination can also be chopped to
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form individual chips.
SUMMARY OF THE INVENTION
A light emitting microdiode (LED) and a method of forming an array of microLEDs for transfer to a receptor substrate are described. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with redistribution metal lines. In one embodiment, a microLED structure includes a pn microdiode and a metallization layer, with the metallization layer between the pn microdiode and a bonding layer formed on a substrate. The metallization layer can include one or more layers. For example, the metallization layer can include an electrode layer and a barrier layer between the electrode layer and the tie layer. The pn microdiode and metallization layer may each have a top surface, a bottom surface, and side walls. In one embodiment, the bottom surface of the pn microdiode is wider than the top surface of the pn microdiode, and the side walls taper outward from top to bottom. The top surface of the pn microdiode can also be wider than the bottom surface of the pn diode, or approximately the same width. In one embodiment, the bottom surface of the pn microdiode is wider than the top surface of the
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INSTITUTO MtXICANC Dt LA PROPERTY INDUSTRIAL metallization layer. The bottom surface of the pn microdiode may also be wider than the top surface of the metallization layer, or approximately the same width as the top surface of the metallization layer.
A forming dielectric barrier layer can optionally be formed on the pn microdiode and other exposed surfaces. The forming dielectric barrier layer may be thinner than the pn microdiode, the metallization layer, and optionally the bonding layer, so that the forming dielectric barrier layer forms a contour of the topography on which it is shape. In one embodiment, the forming dielectric barrier layer extends to the side walls of the pn microdiode, and can cover a layer of quantum wells in the pn microdiode. The dielectric forming barrier layer can also partially extend to the bottom surface of the pn microdiode, as well as extend to the side walls of the metallization layer. In some embodiments, the forming dielectric barrier layer also extends to the side walls of an etched bonding layer. A contact opening can be formed in the forming dielectric barrier layer, which exposes the top surface of the pn microdiode. The contact opening may have a width that is greater than, less than, or approximately the same width as the top surface of the pn microdiode. In one embodiment, the contact opening has a
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INDUSTRIAL width that is less than the width of the top surface of the pn microdiode, and the forming dielectric barrier layer forms a rim around the edges of the top surface of the pn microdiode.
In some embodiments, the bonding layer may be formed from a material having a liquidus temperature or melting temperature below about 350 ° C or more specifically, below about 200 ° C. For example, the tie layer can include indium, tin, or a thermoplastic polymer such as polyethylene or polypropylene. The tie layer may be laterally continuous from one side of the substrate to the other, or it may also be formed at laterally spaced locations.
For example, a laterally spaced location of the link layer may have a width that is less than or approximately the same width as that of the bottom surface of the pn microdiode or metallization layer.
In one embodiment, an array of microLEDs includes a plurality of link layer locations on a carrier substrate, and a corresponding plurality of microLED structures at the plurality of link layer locations. Each microLED structure includes a pn microdiode and a metallization layer, with the metallization layer between the pn microdiode and a respective link layer location. A conformal dielectric barrier layer can be deposited in the array of microLEDs on the substrate, with the dielectric barrier layer of
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Mexican INSTITUTE
OF THE PROPERTY
INDUSTRIAL conformation extending to the side walls of each pn microdiode. The dielectric forming barrier layer can also partially extend to the bottom surface of each pn microdiode, and the side walls of each metallization layer. A plurality of contact openings may be formed in the forming dielectric barrier layer, exposing a top surface of each pn microdiode in which each contact opening has a width that may be greater, less, or approximately the same width as that of the upper surface of each corresponding pn microdiode.
The plurality of locations of the link layer may or may not be laterally separated from each other. In some embodiments, the plurality of tie layer locations are laterally separated and the forming dielectric barrier layer extends to the side walls of each of the plurality of laterally separated tie layer locations. In some embodiments, the substrate includes a respective plurality of pillars on which the plurality of tie layer locations are formed. For example, each pn microdiode may include a bottom surface that is approximately the same width as a top surface of a respective abutment, or wider than the top surface of the respective abutment. The pillars can also have a height that is greater than a respective thickness of the tie layer locations. In one embodiment, the respective height is at least twice the thickness
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respective.
A microLEDs structure and microLEDs array can be formed using existing heterogeneous growth technologies. In one embodiment, a pn diode layer and metallization layer are transferred from a growth substrate to a carrier substrate. In accordance with the embodiments of the invention, the pn diode layer and the metallization layer can be etched before or after transfer to the carrier substrate. Transfer of the pn diode layer and the metallization layer to the carrier substrate may include bonding the metallization layer to a bonding layer on the carrier substrate. For example, the tie layer can have a liquidus temperature or melting temperature below about 350 ° C or more specifically, below 200 ° C. For example, the tie layer can be formed from indium or an indium alloy. After etching the pn diode layer and metallization layer to form a plurality of separate pn microdiodes and a plurality of separate locations of the metallization layer, a forming dielectric barrier layer is formed which extends to the side walls of the plurality of separate pn microdiodes. The dielectric forming barrier layer can form an outline of the topography on which it is formed, and can be thinner than the pn microdiodes and the metallization layer. For example, the forming dielectric barrier layer can be formed by atomic layer deposition (ALD). The barrier layer
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Dielectric shaping can also be formed on a portion of the bottom surface of each separate pn microdiode.
In one embodiment, the pn diode layer and an etched metallization layer, including a plurality of separate locations of the metallization layer in the pn diode layer, are transferred from the growth substrate to the carrier substrate. The pn diode layer can be partially etched before transferring from the growth substrate to the carrier substrate, to form micro-pits separated by ditches in the pn diode layer. In one embodiment, a plurality of pillars are formed on the carrier substrate prior to transferring the pn diode layer and etched metallization layer to the carrier substrate. The link layer can be formed on the plurality of pillars in the carrier substrate before transferring the pn diode layer and the etched metallization layer to the carrier substrate.
In one embodiment, the metallization layer is etched to form a plurality of separate locations of the metallization layer after transferring the metallization layer and the pn diode layer from the growth substrate to the carrier substrate. In such an embodiment, the pn diode layer is etched to form a plurality of separate pn microdiodes, followed by etching of the metallization layer. Etching of the metallization layer may include acid etching the metallization layer to a maximum width of the plurality of separate locations of the layer
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INDUSTRIAL
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metallization is less than a width of the bottom surface of each of the plurality of separate pn microdiodes. In one embodiment, the link layer is etched after transferring the pn diode layer and the metallization layer from the growth substrate to the carrier substrate. For example, the link layer may be acid etched until a maximum width of the plurality of separate locations of the link layer is less than a width of a lower surface of each of the plurality of separate pn microdiodes. A plurality of abutments can also be formed in the carrier substrate before transferring the pn diode layer and the metallization layer from the growth substrate to the carrier substrate. The link layer can be formed on the plurality of pillars in the carrier substrate before transferring the pn diode layer and the etched metallization layer to the carrier substrate.
Once formed, the microLED structure and microLED array can be collected and transferred to a receptor substrate. A transfer head can be placed on the carrier substrate having an array of microLED structures arranged thereon, and an operation is performed to create a state change in the link layer for at least one of the microLED structures. For example, the operation may be to heat the bond layer above a liquidus temperature or melt temperature of the bond layer, or to alter a crystalline phase of the bond layer. The structure or structures of
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microLEDs, including the pn microdlode and metallization layer and, optionally, a portion of the link layer for the microLED structure (s), can be collected with a transfer head and placed on a receiving substrate. IF a forming dielectric barrier layer has already been formed, a portion of the forming dielectric barrier layer can also be collected with the pn microdiode and metallization layer. Alternatively, a conformal dielectric barrier layer can be formed on the microLEDs structure, or plurality of microLEDs structures, after being placed on the receiving substrate.
In one embodiment, the dielectric forming barrier layer extends to a portion of the bottom surface of the pn microdlode, extends to the side walls of the metallization layer, and extends from one side to the other of a portion of the layer link adjacent to the metallization layer. The forming dielectric barrier layer can be cleaved after contacting the microLEDs structure with the transfer head and / or creating the state change in the bonding layer, which may be prior to collecting the pn microdiode and the layer metallization with the transfer head. For example, cleavage of the forming dielectric barrier layer may include transferring a pressure from the transfer head to the forming dielectric barrier layer and / or heating the bonding layer above a liquidus temperature of the bonding layer. .
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MEXICAN INSTITUTE OF INDUSTRIAL PROPERTY
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BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1A is a cross-sectional side view illustration of a volume LED substrate, in accordance with one embodiment of the invention.
Figure 1B is a cross-sectional side view illustration of an etched metallization layer in accordance with one embodiment of the invention.
Figure 1C is a cross-sectional side view illustration 10 of an etched pn diode layer, in accordance with one embodiment of the invention.
Figures 2A-2E are illustrations in side cross-sectional view of a carrier substrate with bonding layer , according to an embodiment of the invention.
Figure 3 is a cross-sectional side view illustration of the bond of a growth substrate and carrier substrate as a whole, in accordance with an embodiment of the invention.
Figure 4 is a cross-sectional side view illustration of various possible structures after bonding the growth substrate and carrier substrate together, in accordance with one embodiment of the invention.
Figure 5 is a side view illustration in cross section
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of the growth substrate removed from the linked structure, according to an embodiment of the invention.
Figure 6 is a cross-sectional side view illustration of a thinned pn diode layer, in accordance with one embodiment of the invention.
Figure 7 is a cross-sectional side view illustration of the acid etching of the pn diode layer to form pn microdiodes, in accordance with one embodiment of the invention.
Figures 7'-7 "are illustrations in side view in cross section of the acid etching of the layers, according to an embodiment of the invention.
Figure 8 is a cross-sectional side view illustration of various microLED structures, in accordance with one embodiment of the invention.
Figures 9-9 'are cross-sectional side view illustrations of the formation of contact openings in an array of microLEDs, in accordance with one embodiment of the invention.
Figures 10-10 ”are cross-sectional side view illustrations of the formation of contact openings in an array of microLEDs, in accordance with one embodiment of the invention.
Figures 11A-11C are illustrations in cross-sectional side view of an absorbed bonding layer, according to one embodiment
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of the invention.
Figures 12A-12B include cross-sectional top and side view illustrations of a carrier wafer and array arrangement of microLEDs, including pn microdiodes, in accordance with one embodiment of the invention.
Figure 13 is an illustration of a method for collecting and transferring a microLED structure from a carrier substrate to a receptor substrate, in accordance with an embodiment of the invention.
Figure 14 is a cross-sectional side view illustration of a transfer head collecting a microLED structure of a carrier substrate, in accordance with an embodiment of the invention.
Figure 15 is a cross-sectional side view illustration of a bipolar microdevice transfer head, in accordance with one embodiment of the invention.
Figure 16 is a cross-sectional side view illustration of a receptor substrate with a plurality of microLEDs, in accordance with an embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
The embodiments of the present invention describe semiconductor microdevices and a method of forming an array of semiconductor microdevices such as light emitting microdiodes
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MEXICAN INSTITUTE • F. INDUSTRIAL PROPERTY
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(LEDs) for transfer to a receiving substrate. For example, the receiving substrate may be, but is not limited to, a display substrate, an Illumination substrate, a substrate with functional devices such as transistors or Integrated circuits (ICs), or a substrate with redistribution metal lines. Although the embodiments of the present invention are specifically described with respect to microLEDs comprising pn diodes, it should be appreciated that the embodiments of the invention are not limited in this way, and that certain embodiments may also be applicable to other semiconductor microdevices, which are designed in such a way that an electronic function (for example diode, transistor, integrated circuit) or photonic function (LED, laser) default.
In various embodiments, the description is made with reference to the figures. However, certain modalities can be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details, such as specific configurations, dimensions and processes, etc., are set forth in order to provide a comprehensive understanding of the present invention. In other cases, recognized semiconductor processes and manufacturing techniques have not been particularly described in detail in order not to unnecessarily overshadow the present invention. The reference throughout the specification to “a
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"embodiment," or the like, means that a particular attribute, structure, configuration, or feature, described in connection with the embodiment, is included in at least one embodiment of the invention. Thus, the occurrences of the phrase "in one embodiment", or the like, in various places throughout this specification, do not necessarily refer to the same embodiment of the invention. Additionally, the particular attributes, structures, configurations or characteristics can be combined in any suitable way in one or more modalities.
The terms "extending to," over "," to "," between "and" in ", as used herein, may refer to a relative position of a layer relative to other layers. A layer "extending to" "over" or "in" another layer or bonded to "another layer, may be in direct contact with the other layer or may have one or more intermediate layers. A layer "between" layers can be in direct contact with the layers or can have one or more intermediate layers.
The terms "microdevice", "pn microdiode" or "structure of microLEDs", as used herein, may refer to the descriptive size of certain devices or structures, according to the embodiments of the invention. As used herein, the terms "microdevices" or "microstructures" are intended to refer to the scale of 1 to 100 pm. However, it should be appreciated that the embodiments of the present invention are not necessarily so limited, and that certain
<img file="MX340348B_D0017.tif" />
Aspects of the modalities may be applicable to larger and possibly smaller size scales.
In one aspect, the embodiments of the invention describe a method of processing a volume LED substrate to an array of microLEDs structures which are ready to be collected and transferred to a receptor substrate. In this way, it is possible to integrate and assemble structures of microLEDs to integrated systems in a heterogeneous way. The microLED structures can be collected and transferred individually, in groups, or as the entire array. In this way, the microLED structures in the array of microLED structures are ready to be collected and transferred to a receiving substrate such as a viewing substrate of any size that varies from micro-displays to large-area displays, and at high rates of transfer. In some embodiments, the array arrangements of microLEDs that are about to be collected are described with a spacing of 10 pm by 10 pm, or spacing of 5 pm by 5 pm. At these densities, a 15.24 cm (6 inch) substrate, for example, can accommodate approximately 165 million microLED structures with a spacing of 10 pm by 10 pm, or approximately 660 million microLED structures with a spacing of 5 pm to 5 pm. In this way, a high density of pre-made microdevices with specific functionality can be produced in a way in which
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<img file="MX340348B_D0018.tif" />
they are ready to be collected and transferred to a receiving substrate.
The techniques described in this document are not limited to microLEDs structures, and can also be used in the elaboration of other microdevices.
In another aspect, the embodiments of the invention describe a microLEDs structure and microLEDs array in which each pn microdiode is formed on a respective location of a link layer. The respective locations of the link layer may or may not be laterally separated locations. An operation can be performed at a respective link layer location that corresponds to a microLED during the microLED collection process in which the respective link layer location undergoes a state change that aids in the collection process . For example, the respective location of the tie layer may change from solid to liquid in response to a temperature cycle. In the liquid state, the respective location of the link layer can hold the pn microdiode in place on a carrier substrate through surface tension forces, while also providing a means from which the pn microdiode is readily releasable . Furthermore, the liquid state can act as a protection or damper to absorb forces exerted by a transfer head if a transfer head makes contact with the microLED structure during the harvesting process. In this form, the liquid state can
<img file="MX340348B_D0019.tif" />
INDUSTRIAL PROPERTY compensate for uneven topography in the mlcroLEDs arrangement or transfer head arrangement by smoothing over the underlying surface in response to the compressive forces exerted by a transfer head. In other embodiments, the respective location of the link layer may not undergo a complete state change. For example, the respective location of the tie layer can be made substantially more malleable in response to a temperature cycle, while remaining partially in the solid state. In another embodiment, the respective location of the link layer can be subjected to a crystalline phase change in response to an operation, such as a temperature cycle.
Referring now to Figure 1, a semiconductor device layer 110 may be formed on a substrate 101. In one embodiment, the semiconductor device layer 110 may include one or more layers and is designed such that it is performed, in a controlled manner , a predetermined electronic function (eg diode, transistor, integrated circuit) or photonic function (LED, laser). It should be appreciated that although the semiconductor device layer 110 can be designed such that a predetermined function is performed in a controlled manner, the semiconductor device layer 110 cannot be made fully functional.
For example, contacts such as an anode or cathode cannot yet be formed. For reasons of conciseness and not to overshadow the
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In embodiments of the invention, the following description is made with respect to the semiconductor device layer 110 as a pn diode layer 110 grown on a growth substrate 101 according to conventional heterogeneous growth conditions.
The pn diode layer 110 may include a composite semiconductor that has an energy gap that corresponds to a specific region in the spectrum. For example, the pn diode layer 110 may include one or more layers based on ll-VI materials (eg, ZnSe) or lll-V nitride materials (eg, GaN, AIN, InN, and their alloys). Growth substrate 101 can include any suitable substrate such as, but not limited to, silicon, SiC, GaAs, GaN, and sapphire (AI2O3).
In a particular embodiment, the growth substrate 101 is sapphire, and the pn diode layer 110 is formed from GaN. Despite the fact that sapphire has a higher network constant and coefficient of thermal expansion relative to GaN, sapphire is reasonably low in cost, widely available, and its transparency is compatible with laser-based survey techniques. of excimers (LLO). In another embodiment, another material such as SiC can be used as the growth substrate 101 for a GaN 110 pn diode layer.
Like sapphire, SiC substrates can be transparent. Various growth techniques can be used for growth of the pn 110 diode layer such as metal-organic chemical vapor deposition
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(MOCVD). GaN, for example, can be grown by simultaneously introducing the precursors trimethylgalium (TMGa) and ammonia (NH3) into a reaction chamber with the sapphire growth substrate 101 heated to an elevated temperature such as 800 ° C to 1000 ° C. In the particular embodiment illustrated in Figure 1A, the pn diode layer 110 may include a GaN layer of volume 112, a doping layer n 114, a quantum well 116 and the doping layer p 118. The volume 112 GaN layer may be doping n due to contamination by silicon or oxygen, or it may be intentionally doped with a donor such as silicon. The doping GaN layer 114 can also be doped with a donor such as silicon, while the doping layer p 118 can be doped with an acceptor such as magnesium. A variety of alternative pn diode configurations can be used to form pn diode layer 110. Also, a variety of single quantum well (SQW) or multiple quantum well (MQW) configurations can be used to form quantum well 116. In addition, various intermediate layers can be included as appropriate. In one embodiment, the sapphire growth substrate 101 is approximately 200 pm thick, the volume 112 GaN layer is approximately 5 pm thick, the n 114 doping layer is approximately 0.1 pm - 3 pm thick , the quantum well layer 116 has a thickness of less than about 0.3 pm and the doping layer p 118 has a thickness of about 0.1 pm 21
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A metallization layer 120 can then be formed on the pn diode layer 110. As illustrated in Figure 1A, the metallization layer 120 can include an electrode layer 122 and, optionally, a barrier layer 124, although other layers can be included. In one embodiment, the metallization layer has a thickness of about 0.1 pm - 2 pm. The electrode layer 122 can make ohmic contact with the doping GaN layer p 118, and can be formed of a high working function metal, such as Ni, Au, Ag, Pd and Pt. In one embodiment, the layer of Electrodes 122 can be reflective of light emission. In another embodiment, the electrode layer 122 may also be transparent to light emission. Transparency can be achieved by making the electrode layer very thin to minimize light absorption. Barrier layer 124 may optionally be included in metallization layer 120 to prevent diffusion of impurities into diode pn 110. For example, barrier layer 124 may include, but is not limited to, Pd, Pt, Ni, Ta , Ti and TiW. In certain embodiments, barrier layer 124 can prevent diffusion of link layer components into diode layer pn 110.
In accordance with certain embodiments of the invention, the pn diode layer 110 and metallization layer 120 are grown on a growth substrate 101 and subsequently transferred to a carrier substrate 201, such as one illustrated in Figures 2A -2E and described with
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MEXICAN INSTITUTE OF INDUSTRIAL PROPERTY more detail in the following description. As described in greater detail in the following figures and description, the metallization layer 120 and pn diode layer 110 can be etched before being transferred to a carrier substrate 201. The carrier substrate 201 and tie layer 210 can also be etched prior to transfer of the pn diode layer 110 and metallization layer 120 to the carrier substrate 201. Accordingly, the embodiments of the invention can be implemented in a multitude of variations during the formation of an array of microLEDs for subsequent transfer to a recipient substrate.
Referring now to Figure 1B, the metallization layer 120 can be etched before transferring to a carrier substrate 201. In one embodiment, the structure of Figure 1B can be achieved by forming a etched photoresin layer on the pn diode layer 110, followed by deposition of the metallization layer 120. The photoresin layer is then lifted (in conjunction with the portion of the metallization layer in the photoresin layer) leaving behind the laterally separated locations of the metallization layer 120 illustrated in Figure 1B. In certain embodiments, the spacing of the laterally spaced locations of the metallization layer 120 may be 5 pm, 10 pm, or greater, corresponding to the spacing of the array of microLEDs. For example, a spacing of 5 pm may be formed from laterally spaced locations 3 pm wide of metallization layer 120 separated by a gap of 2 pm.
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A spacing of 10 pm may be formed from locations 8 pm wide of the metallization layer 120 separated by a gap of 2 pm. However, these dimensions are considered exemplary and the embodiments of the invention are not so limited. In some embodiments, the width of the laterally spaced locations of the metallization layer 120 is less than or equal to the width of the bottom surface of the pn 150 microdiode array, as discussed in greater detail in the following description and figures.
Referring now to Figure 1C, etching of the metallization layer 120 can be followed by etching of the pn diode layer 110. In one embodiment, the structure of Figure 1C can be accomplished by forming a second etched photoresin layer on the Laterally separated locations of metallization layer 120 and an etching reagent are applied to acid etch the diode layer pn 110 to acid etch trenches 134 and form a plurality of micro-tables 130. Referring again to the enlarged section of the pn diode layer 110 in Figure 1A, in one embodiment, acid etching is performed to acid etch trenches through doping layer p 118, quantum well 116, and towards doping layer n 114 or volume layer 112. Acid etching of the GaN 110 pn diode layer can be performed using dry plasma etching techniques such as reactive ion etching (RIE), electronic cyclotron resonance (ECR), ion reactive etching by
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inductively coupled plasma ICP-RIE, and chemically assisted ion beam etching (GAIBE). Engraving chemistries can be halogen based, as they contain species such as CI2, BCI3 or SiCI<sub>4</sub>. In the particular embodiment illustrated in Figure 1C, the micro tables 130 may have side walls 132 tapered up to 15 degrees. For example, RIE can be used with a chlorine-based etching chemistry. Alternatively, the side walls can be vertical. For example, ICP-RIE can be used with a chlorine-based etching chemistry to obtain vertical side walls.
In certain embodiments, the spacing of the micro tables 130 may be 5 pm, 10 pm, or greater. For example, a microtable arrangement 130 with a spacing of 5 pm may be formed of 3 pm microtablets separated by a space of 2 pm. An array of microtablets 130 with a spacing of 10 pm can be formed of 8 pm wide microtablets separated by a space of 2 pm. However, these dimensions are considered exemplary and the embodiments of the invention are not so limited.
Figures 2A-2E are cross-sectional side view illustrations of various embodiments of a carrier substrate 201 with bonding layer 210 for bonding to metallization layer 120 on growth substrate 101. Figure 2A illustrates a carrier substrate 201 and link layer 210 that is not recorded before the link. Figures 2B - 2D illustrate
ΙΜΡΪ
MEXK-ΛΝθ INSTITUTE OF INDUSTRIAL PROPERTY a carrier substrate 201 which has been etched to form a plurality of posts 202 having side walls 204 and separated by trenches 206. Posts 202 may have a maximum width equal to or less than one width of the microdiodes pn 135, 150, as will become more apparent in the following description and figures. In one embodiment, the trench posts 202 are at least twice as high as a thickness of the tie layer 210. In one embodiment, tie layer 210 can be approximately 0.1 pm - 2 pm thick, and trench posts are at least 0.2 pm - 4 pm high. In the particular embodiment illustrated in Figure 2B, a shaping link layer 210 is formed on posts 202, and on side walls 204 and within trenches 206. In the particular embodiment illustrated in Figure 2C, the tie layer 210 is deposited anisotropically so that it forms only on the top surface of posts 202 and within trenches 206, without a significant amount being deposited on side walls 204. In the particular embodiment illustrated in Figure 2D, tie layer 210 is formed only on the top surface of posts 202. Such a configuration can be formed by etching posts 202 and link layer 210 with the same etched photoresin. In the particular mode illustrated in Figure
2E, the laterally spaced locations of the link layer 210 can be formed with a photoresin survey technique in which a coverage layer of the link layer is deposited on a layer of
JL
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INDUSTRIAL etched photoresin, which is then lifted (in conjunction with the bonding layer portion in the photoresin layer) leaving behind the laterally separated locations of bonding layer 210 illustrated in Figure 2E, although other processing techniques may be used.
As described above with respect to Figures 2B-2E and
Figures 1B-1C, certain embodiments of the invention include laterally spaced locations of metallization layer 120 and / or laterally spaced locations of tie layer 210. With respect to Figure 2B, in which a conformal tie layer 210 formed on the posts 202, and on the side walls 204 and within the trenches 206, the particular locations of the tie layer on top of the posts 202 are separated laterally by the trenches 206. In this way, even though the forming bonding layer 210 is continuous, the locations of the bonding layer 210 at the top of the posts 202 are laterally spaced locations. Also, the individual discrete locations of the link layer 210 in Figure 2E are separated laterally by the space between them. Where posts 202 exist, the ratio of the thickness of the tie layer 210 to the height of the post 202 may contribute to the lateral separation of the tie layer locations.
210.
Link layer 210 can be formed from a variety of suitable materials. The link layer can be formed from a
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MIXICAN INSTITUTE OF INDUSTRIAL PROPERTY material that is capable of adhering a microLED structure to a carrier substrate. In one embodiment, link layer 210 may undergo a state change in response to an operation such as a change in temperature. In one embodiment, the link layer may be removable as a result of the state change. In one embodiment, the tie layer can re-melt or re-flow fluidly. In one embodiment, the tie layer can have a liquidus temperature or melting temperature below about 350 ° C or more specifically, below about 200 ° C. At such temperatures, the link layer can undergo a state change without substantially affecting the other components of the microLED structure. For example, the tie layer can be formed of a metal or metal alloy, or a thermoplastic polymer that is removable. In one embodiment, the tie layer can be conductive. For example, in cases where the link layer undergoes a state change from solid to liquid in response to a change in temperature, a portion of the link layer may remain in the microLED structure during the harvesting operation, as described in greater detail in the following description. In such an embodiment, it may be conducive for the link layer to be formed of a conductive material so that it does not adversely affect the structure of microLEDs when subsequently transferred to a receptor substrate. In this case, the conductive bonding layer portion that remains in the structure of
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INDUSTRIAL microLEDs during the transfer operation can help to bind the microLED structure to a conductive pad on the receptor substrate.
Solders may be suitable materials for bonding layer 210 since many are generally ductile materials in their solid state and exhibit favorable wetting with semiconductor and metal surfaces. A typical alloy does not melt at a single temperature, but over a range of temperatures. In this way, solder alloys are often characterized by a liquidus temperature corresponding to the lowest temperature at which the alloy remains liquid, and a solidus temperature corresponding to the highest temperature at which the alloy remains solid. An exemplary list of low melting point solder materials that can be used with the embodiments of the invention is provided in Table 1.
INDUSTRIAL
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Table 1.
<td>Chemical composition</td><td>Temperature of liquidus (° C)</td><td>Temperature of solidus (° C)</td>
<td>100 in</td><td> 156.7</td><td> 156.7</td>
<td>66.3ln33.7B¡</td><td> 72</td><td> 72</td>
<td>51ln32.5B, 16.5Sn</td><td> 60</td><td> 60</td>
<td>57Bi26ln17Sn</td><td> 79</td><td> 79</td>
<td>54.02Bi29.68ln16.3Sn</td><td> 81</td><td> 81</td>
<td>67Bi33ln</td><td> 109</td><td> 109</td>
<td>50ln50Sn</td><td> 125</td><td> 118</td>
<td>52Sn48ln</td><td> 131</td><td> 118</td>
<td>58Bi42Sn</td><td> 138</td><td> 138</td>
<td>97ln3Ag</td><td> 143</td><td> 143</td>
<td>58Sn42ln</td><td> 145</td><td> 118</td>
<td>99.3lnO.7Ga</td><td> 150</td><td> 150</td>
<td>95ln5Bi</td><td> 150</td><td> 125</td>
<td>99.4lnO.6Ga</td><td> 152</td><td> 152</td>
<td>99.6lnO.4Ga</td><td> 153</td><td> 153</td>
<td>99.5lnO.5Ga</td><td> 154</td><td> 154</td>
<td>60Sn40Bi</td><td> 170</td><td> 138</td>
<td>100Sn</td><td> 232</td><td> 232</td>
<td>95Sn5Sb</td><td> 240</td><td> 235</td>
An exemplary list of thermoplastic polymers that can be used with the embodiments of the invention is provided in Table 2.
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Table 2.
<td>Polymer</td><td>Melting temperature (° C)</td>
<td>Acrylic (PMMA)</td><td> 130-140</td>
<td>Polyoxymethylene (POM or Acetal)</td><td> 166</td>
<td>Polybutylene terephthalate (PBT)</td><td> 160</td>
<td>Polycaprolactone (PCL)</td><td> 62</td>
<td>Polyethylene terephthalate (PET)</td><td> 260</td>
<td>Polycarbonate (PC)</td><td> 267</td>
<td>Polyester</td><td> 260</td>
<td>Polyethylene (PE)</td><td> 105-130</td>
<td>Polyether Ether Ketone (PEEK)</td><td> 343</td>
<td>Polylactic acid (PLA)</td><td> 50-80</td>
<td>Polypropylene (PP)</td><td> 160</td>
<td>Polystyrene (PS)</td><td> 240</td>
<td>Polyvinylidene chloride (PVDC)</td><td> 185</td>
In accordance with the embodiments of the invention, the bonding layer 210 is formed with a uniform thickness and can be deposited by a variety of suitable methods, depending on the particular composition. For example, the solder compositions can be vaporized by sputtering, deposited by electron beam evaporation (E beam), or coated with a growth layer to obtain a uniform thickness.
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Posts 202 can be formed from a variety of materials and techniques. In one embodiment, posts 202 can be integrally formed with carrier substrate 201 by etching carrier substrate 201 by an etching or stamping process. For example, carrier substrate 201 may be a silicon substrate with posts 202 integrally formed. In another embodiment, the posts can be formed on top of the carrier substrate 201. For example, posts 202 can be formed by a photoresist coating and lifting technique. The posts can be formed from any suitable material including semiconductors, metals, polymers, dielectrics, etc.
Referring now to Figure 3, growth substrate 101 and carrier substrate 201 can be bonded together under heat and / or pressure. It should be appreciated that although Figure 3 illustrates the linking of the etched structure of Figure 1B with the unengraved structure of Figure 2A, any combination of Figures 1A-1C and Figures 2A-2E is contemplated according to the modalities of the invention. Furthermore, although it has been described that bonding layer 210 is formed in carrier substrate 201 before bonding, it is also possible that bonding layer 210 is formed in metallization layer 120 of growth substrate 101 before bonding. For example, tie layer 210 may be formed on metallization layer 120, and etched with metallization layer 120 during
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INDUSTRIAL formation of the laterally separated locations of the metallization layer illustrated in Figure 1B. Although not illustrated, depending on the particular arrangement and composition of the layers formed on the substrates to be bonded together, an oxidation resistant film can be formed on the top surface of either or both substrates to prevent oxidation before bonding. For example, in one embodiment, a thin gold film may be deposited on any or both of the exposed surface of the metallization layer 120 and the bonding layer 210. During bonding of the substrates illustrated in Figure 3, the bonding layer 210 can partially soak the gold film, resulting in a gold alloy at the bonding interface between the substrates.
Figure 4 is a cross-sectional side view illustration of various possible non-limiting structures after bonding growth substrate 101 and carrier substrate 201. Particular combinations of substrates are described in Table 3. For example, the particular embodiment illustrated in Example 4A it represents the binding of the carrier substrate illustrated in Figure 2D to the growth substrate illustrated in Figure 1C.
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Table 3.
<td></td><td>Ex. 4A</td><td>Ex. 4B</td><td>Ex- 4C</td><td>Ex- 4D</td><td>Eg 4E</td><td>Ex- 4F</td><td>Ex- 4G</td><td>Ex- 4H</td>
<td>Carrier substrate (2A-2D)</td><td>2D</td><td>2 C</td><td>2B</td><td>2D</td><td>2 C</td><td>2B</td><td>2A</td><td>2E</td>
<td>Substrate increase (1 B)</td><td>1 C</td><td>1 C</td><td>1 C</td><td>1A</td><td>1A</td><td>1A</td><td>1A</td><td>1A</td>
<td></td><td>Ex. 4I</td><td>Ex- 4J</td><td>Ex. 4K</td><td>L —1 UJ</td><td>Ex. 4M</td><td>UJ</td><td>Ex. 40</td>
<td>Carrier substrate (2A-2D)</td><td>2A</td><td>2E</td><td>2D</td><td>2 C</td><td>2B</td><td>2A</td><td>2E</td>
<td>Substrate increase (1 B)</td><td>1 C</td><td>1 C</td><td>1 B</td><td>1 B</td><td>1 B</td><td>1 B</td><td>1 B</td>
As described above, the structures of many of the examples can also be created by forming bonding layer 210 on the growth substrate, followed by bonding of growth substrate 101 to carrier substrate 201. For example, example 40, also can be created by etching bonding layer 210 and metallization layer 210 onto growth substrate 101, followed by bonding growth substrate 101 to carrier substrate 201.
Referring now to Figure 5, growth substrate 101 is
INSTITUTO MEXICAN * '• t LA MOHEDA!) Industrial
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has removed from the linked structure. Growth substrate 101 can be removed by a suitable method such as etching or an excimer laser based (LLO) survey if the growth substrate is transparent. In one embodiment, the LLO of a GaN 110 pn diode layer of a transparent sapphire growth substrate 101 is accomplished by irradiating the layer interface 101/110 through the transparent sapphire growth substrate 101 with a short Pulse (eg, tens of nanoseconds) from an ultraviolet laser such as an Nd-YAG laser or KrF excimer laser. Absorption in the GaN 110 pn diode layer at the interface results in localized heating of the interface, resulting in decomposition in the interface GaN to the liquid metal Ga and nitrogen in gas. Once the desired has been irradiated, the transparent sapphire growth substrate 101 can be removed by re-melting the Ga in an iron.
Referring now to Figure 6, the pn diode layer 110 is thinned to a desirable thickness. Referring again to the enlarged pn diode layer 110 in Figure 1A, a predetermined amount of the volume 112 GaN layer (which may be of the n type) or a portion of the n 114 type GaN layer is removed so that an operable pn diode remains after thinning. Depending on the underlying structure, the thinning process can be performed using suitable techniques such as buffing, etching, or
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<img file="MX340348B_D0025.tif" />
dry etched. For example, a combination of polishing and / or timed engraving can be performed to a desired thickness. In circumstances where there are underlying engraved structures, such as abutments or micro-tables, a timed engraving to a desired thickness can be performed in order to avoid damaging the engraved structures. As shown in Examples 6A, 6B, 6C, 61 and 6J where pn diode layers 110 were pre-recorded to form micro-tables 130, there are now autonomous pn microdiodes 135.
If any of the growth substrate structures 101 or 10 carrier substrate 201 were not pre-etched or only partially pre-etched before bonding, then additional etching can be performed after thinning of the pn 110 diode layer illustrated in Figure 6. As illustrated in Figure 7 an etched masking layer 140 can be formed on the unengraved pn diode layer 110 to acid etch the pn diode layer 110 to form the autonomous pn microdiodes 150. The masking layer 140 can be formed from photoresin or a variety of materials such as metal (eg, chromium, nickel) or dielectric (silicon nitride, silicon oxide) which are more resistant to acid etching conditions than GaN than photoresin. Acid etching of the GaN 110 pn diode layer can be performed using dry plasma etching techniques such as reactive ion etching (RIE), electronic cyclotron resonance (ECR), ion reactive etching by
ΪΜΡΙ
ΙΝΤΠΤυΤΟ MIXICANO
OF THE PRONITY
INOUSTRIAL Inductively Coupled Plasma (ICP-RIE), and Chemically Assisted Ion Beam Etching (CAIBE). Engraving chemistries can be halogen based, as they contain species such as CI2, BCI3 or SiCI<sub>4</sub>.
In the particular embodiment illustrated in Figure 7, the p5 n 150 microdiodes may have outwardly tapered side walls 153 (top to bottom of the pn 150 microdiodes) up to 15 degrees. For example, RIE can be used with a chlorine-based etching chemistry. Alternatively, the side walls 153 can be vertical. For example, ICP-RIE can be used with a chlorine-based etching chemistry to obtain vertical side walls. As will be apparent from the description in Figure 16, outwardly tapered side walls may be favorable in some embodiments when a common contact is formed through a series of microLED structures that have been collected and transferred to a receptor substrate. In certain embodiments, the spacing between the pn 150 microdiodes can be 5 pm, 10 pm, or greater. For example, a pn 150 microdiode with a spacing of 5 pm may be formed of 3 pm wide pn microdiodes separated by a space of 2 pm. A pn 150 microdiode with a spacing of 10 pm can be formed of 8 pm wide pn microdiodes separated by a space of 2 pm.
Referring now to Figures 7'-7 ", the etching may optionally be continued on the metallization layer 120 and / or layer
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bonding 210 using suitable acid etching chemistries based on the particular materials in the metallization layer 120 and bonding layer 210. In certain embodiments illustrated in Figure 7 ', anisotropic acid etching with etching chemistry Dry can be used to acid etch the metallization layer 120 and / or tie layer 210 so that the layers 120, 210 have a width coincident with the overlapping underside of the pn 150 microdiode. In certain embodiments illustrated in Figure 7, the etching can be used to "undermine" the metallization layer 120 and / or bonding layer 210 below the overlapping bottom surface of the pn 150 microdiode as illustrated in the
Examples 7 "D-7" H. Although not specifically illustrated, it will be understood that acid etching can also be performed to "undermine" the underlying layers 120, 210 below the pn 135 microdiodes.
Upon completion of the acid etching processes for the pn microdiodes, metallization layer, or bonding layer, the masking layer 140 can be removed, for example, by using a selective acid etching technique, resulting in the arrangement of microLEDs illustrated in Figure 8. As illustrated, the array of microLEDs includes a carrier substrate 201, a plurality of link layer locations
210 (which may or may not be separated laterally) on the carrier substrate, and a respective plurality of separate pn microdiodes 135, 150 on the plurality of locations of the link layer 210. A plurality of
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Separate locations of the metallization layer 120 is formed between the respective plurality of separate pn microdiodes 135, 150 and the plurality of locations of the link layer 210. In some embodiments, the carrier substrate includes a respective plurality of pillars 202 in which the plurality of laterally spaced locations of the link layer 210 is formed, as illustrated in Examples 8A-8F and Examples 8K8M.
In some embodiments, the pn 150 microdiodes (as well as the pn 135 microdiodes) include a top surface 152 and a bottom surface 151, and the metallization layer 120 includes a top surface
121 and a bottom surface, and the bottom surface 151 of the pn 150 microdiode (as well as the pn 135 microdiodes) is wider than the top surface 121 of the metallization layer 120.
In some embodiments, the plurality of pn 135, 150 microdiodes each include a bottom surface 151 that is approximately the same width as a top surface 203 of each of the respective plurality of pillars 202. In other embodiments, the plurality of pn 135, 150 microdiodes each include a bottom surface 151 that is wider than a top surface 203 of each of the respective plurality of pillars 202. The ratio of the bottom width of the pn 135, 150 microdiodes and top surface of the underlying pillar 202 can affect the harvesting process. For example, if the link layer
<img file="MX340348B_D0029.tif" />
MIXICAN INSTITUTE
D £ THE PROPERTY 0 · «« «^ INDUSTRIAL
210 exhibits a state change from solid to liquid during the harvesting process, then the pn 135,150 microdiode essentially floats in a liquid layer. Surface tension forces in the liquid bonding layer 210 can hold the microdiode pn 135,150 in place at the top of the pillar 202. In particular, the surface tension forces associated with the edges of the upper surface of the pillar 202 can further help to hold the microdiode pn 135, 150 in place, where the upper surface width of the pillar 202 is less than or approximately equal to the bottom width of diodes pn 135, 150.
In some embodiments, the plurality of pn 135, 150 microdiodes are placed on an un-etched link layer 210. For example, as illustrated in Example 6I and Example 7'N, the link layer 210 may be a uniform layer on the carrier substrate and the corresponding plurality of locations of the link layer 210 is not laterally separated from each other. In other embodiments, the plurality of pn 135, 150 microdiodes is placed on an etched link layer 210. For example, as illustrated in Examples 8A-8M and Example 80, the etched link layer may include a plurality of locations separated laterally from the link layer 210. In one embodiment, the plurality of pn 135, 150 microdiodes includes , each, a bottom surface 151 having approximately the same width, or greater, than a corresponding top surface 211 for a plurality of laterally spaced locations of the link layer 210.
IMPÍ
MEXICAN INSTITUTE · -?> I
OF INDUSTRIAL PROPERTY
<img file="MX340348B_D0030.tif" />
As previously described, the tie layer can absorb compressive forces associated with contact of the microLED structure with a transfer head during the collection process. As a result, the tie layer can absorb compressive forces and project laterally. In cases where each microLED structure is etched to have a small separation distance of 2 pm for example, the amount of link layer projecting laterally from each microLED structure must be minimized in order not to interfere with a microLED structure. adjacent microLEDs during the collection process. In certain embodiments where trenches 206 occur between posts 202, the trenches can act as bond layer deposits in which the molten bond layer can flow without interfering with an adjacent microLED structure.
In some embodiments, the microLEDs structures or array of microLEDs structures of Figure 8 (as well as the microLEDs structures of Figure 6 Example 6I, and Figure 7 Examples 7Ό-7Ί after removal of layer 140) are found ready to be collected and transferred to a receiving substrate, for example with a transfer head 300 described in greater detail with respect to Figures 1420 16. In other embodiments, a thinly formed dielectric barrier layer can be formed from an array of any of the pn microdiodes
135, 150 before being collected and transferred to a receiving substrate. In
IMPI
MEXICAN INSTITUTE OF INDUSTRIAL PROPERTY
<img file="MX340348B_D0031.tif" />
Referring now to Figures 9'-9 ", a thinly formed dielectric barrier layer 160 can be formed on an array of any of the pn 150 microdiodes of Figures 7-7". In one embodiment, the thin forming dielectric barrier layer 160 can protect against charged arcing between adjacent pn microdiodes 150 during the harvesting process, and consequently protect against adjacent pn microdiodes 150 from not adhering during the process of harvest. The thin forming dielectric barrier layer 160 can also protect the side walls 153, quantum well layer
116 and bottom surface 151, of the pn 150 microdiodes from contamination that may affect the integrity of the pn 150 microdiodes. For example, the thinly formed dielectric barrier layer 160 may function as a physical barrier to the absorption of the bonding layer material 210 of the side walls and quantum layer 116 of the pn 150 microdiodes as described in greater detail with respect to Figures 11A-11C in the following description. The thin forming dielectric barrier layer 160 can also isolate the pn 150 microdiodes once they are placed on a receptor substrate. In one embodiment, the thinly formed dielectric barrier layer 160 is aluminum oxide (AI2O3) approximately 50-600 angstroms thick. The dielectric forming barrier layer 160 can be deposited by a variety of suitable techniques such as, but not limited to, atomic deposition of
IMPI
MEXICAN INSTITUTE OF THE PKOPIEDA OR INDUSTRIAL
<img file="MX340348B_D0032.tif" />
layers (ALD).
The thin forming dielectric layer and contact openings can be formed using a masking layer lifting technique. Referring to Figures 9-9 ', the masking layer
140 Illustrated in Figure 7 for etching microdlode pn 150 can also be used in a survey technique to form the thin forming dielectric barrier layer 160 and contact opening 162. The thin forming dielectric barrier layer 160 can be formed on a array of any of the pn 150 microdiodes in Figure 7,
Figure 7 'or Figure 7 "and conforms to and extends from one side to the other of the exposed surfaces of the masking layer 140, and side walls 153 and the bottom surface 151 of the pn diode 150. The forming dielectric barrier layer 160 it can also extend from one side to the other of the exposed surfaces of the metallization layer 120, bonding layer
210, as well as the carrier substrate and posts 202, if applicable. The masking layer 140 is then removed, lifting the portion of the thinly formed dielectric barrier layer 160 formed therein, resulting in the structure illustrated in Figure 9 ', including the contact openings 162. In the particular embodiment Illustrated in Figure 9 ', the forming dielectric barrier layer 160 does not form on the top surface 152 of the pn 150 microdiodes.
Referring to Figures 10-10 "the dielectric layer of
IMPI
<img file="MX340348B_D0033.tif" />
INSTITUTO MEXICANO Ksaík.vk'Z-íí u DE LA PROPIEDAD {S - ^%, 'INDUSTRIAL “' ·> 'thin conformation can also be formed on the array of microdiodes pn 135, 150 of Figure 8 (as well as the structures of microLEDs of Figure 6 Example 6I, and Figure 7 Examples 7Ό-7Ί after removal of layer 140) followed by etching to create contact apertures 162. As illustrated in Figure 9, the thin-forming dielectric barrier layer 160 can be formed over an array of any of the pn 150 microdiodes and is shaped to and extends along the exposed top surface and side walls of the pn diodes 150. The dielectric barrier layer 160 can also extend along the exposed bottom surface 151 of the pn diodes 135, 150 and surfaces of the metallization layer 120, bonding layer 210, as well as the carrier substrate 201 and posts 202, if is the case. A photoresin coverage layer can then be formed on the pn diode array and carrier substrate 201, and then etched to form the openings on each pn microdiode 135,150. The thin forming dielectric barrier layer 160 can then be etched to form contact openings 162 on the top surface of each microdiode pn 135, 150. Contact openings 162 are illustrated in Figures 10'-10 "after removal of recorded photoresin. As illustrated in Figure 10 ', the contact openings 162 may be slightly smaller in width than the top surface of the pn 135, 150 microdiodes. The difference in width can be a result of adjusting to Include a
IMPI6s ^; 5
INSTITUT # MEXICANO DE LA MONEDAD INDUSTRIAL alignment tolerance when recording photoresin. As a result, the forming dielectric barrier layer 160 can form a rim around the top surface and side walls of the pn microdiodes
135, 150. As illustrated in Figure 10 ", the contact openings 162 may be slightly larger in width than the top surface of the pn 135, 150 microdiodes. In the embodiment illustrated in Figure 10" the contact openings 162 expose the top surfaces of the pn 150 microdiodes and an upper portion of the side walls of the pn 150 microdiodes, while the dielectric barrier layer 160 covers and isolates the layers of quantum wells 116.
Referring now to Figures 11A-11C, in accordance with some embodiments of the invention, it is possible that an amount of the bonding layer 210 is absorbed along the side surfaces of the metallization layer 120 and along the Bottom surface 151 of the pn diode layer 110 during the bonding operation illustrated in Figure 3. Referring to Figure 10B, it is possible that, after forming the pn 150 microdiodes, the amount of bond layer 210 that has been absorbed may potentially continue to migrate along the side walls 153 of the pn 150 microdiode during processing subsequent.
Continued migration to the quantum well layer 116 may interfere with the operation of the pn 150 microdiode. Referring now to Figure 10C, in accordance with the embodiments of the invention, the
<img file="MX340348B_D0034.tif" />
Dielectric forming barrier 160 can function as a physical barrier to protect the side walls 153 and quantum well layer 116 of the pn 150 microdiodes from contamination by the bond layer material 210 during subsequent temperature cycles (particularly at temperatures above of the liquidus or melting temperature of the bonding layer material 210) such as during harvesting of the microdevice from the carrier substrate, and releasing the microdevice on the receptor substrate. Although Figures 11A-11C have been illustrated and described with reference to the pn 150 microdiodes, it is also contemplated that it is possible that an amount of bonding layer 210 may be absorbed and continue its migration along the side walls of micro-tables 130 used to form the pn 135 microdiodes during the link operation illustrated in Figure 3. The dielectric forming barrier layer 160 can similarly function as a physical barrier to protect the side walls and quantum well layer 116 of the pn 135 microdiodes from contamination by the bonding layer material
210.
Figures 12A-12B include cross-sectional top and side view illustrations of a carrier substrate 201 and arrangement of microLEDs structures, in accordance with an embodiment of the invention. In the particular embodiments illustrated, arrays are produced from microLEDs structures of Example 10'N, including the microdiode pn i
MEXICAN INSTITUTE
Dt LA PROPigOAD
INDUSTRIAL r¿¿.
150. However, it should be appreciated that Figures 12A-12B are intended to be exemplary, and that the array of microLEDs structures can be formed from any of the previously described microLEDs structures. In the embodiment illustrated in Figure 12A, each individual pn microdiode
150 it is illustrated as a pair of concentric circles having different diameters or widths corresponding to the different widths of the top and bottom surfaces of the pn 150 microdiode, and the corresponding tapered side walls extending between the top and bottom surfaces. In the embodiment illustrated in Figure 12B, each individual pn microdiode 150 is illustrated as a pair of concentric squares with tapered or rounded corners, with each square having a different width corresponding to the different widths of the upper and lower surfaces of the pn microdiode. 150, and corresponding tapered side walls extending from the top and bottom surfaces.
However, the embodiments of the invention do not require tapered side walls, and the top and bottom surfaces of the pn 150 microdiode may have the same diameter, or width, and vertical side walls. As illustrated in Figures 12A-12B, the arrangement of microLEDs structures is described with a spacing (P), space (S) between each microLED structure and maximum width (W) of each microLED structure. For clarity and conciseness purposes, only the x-dimensions are illustrated by the dotted lines in the top view illustration, although it will be understood that
IMPI
A r ** STT7VTO MEXICANO M LA Π5ΟΜΕΡΑΟ INDUSTRIAL dimensions and similar may exist, and may have the same or different dimensional values. In the particular embodiments illustrated in Figures 12A-12B, the x and y dimensional values are Identical in the top view illustration. In one embodiment, the array of microLED structures can have a spacing (P) of 10 pm, with each array of microLEDs having a gap (S) of 2 pm and maximum width (W) of 8 pm. In another embodiment, the array of microLED structures can have a spacing (P) of 5 pm, with each array of microLEDs having a space (S) of 2 pm and maximum width (W) of 3 pm. However, the embodiments of the invention are not limited to these specific dimensions, and any suitable dimension can be used.
An embodiment of a method for transferring a structure of microLEDs to a receptor substrate is described in Figure 13. In such an embodiment, a carrier substrate is provided having an array of microLEDs structures disposed therein. As described above, each microLED structure can include a pn microdiode and a metallization layer, with the metallization layer between the pn microdiode and a bonding layer on the carrier substrate. A forming dielectric barrier layer can optionally extend to the side walls of the pn microdiode. The forming dielectric barrier layer may additionally extend to a portion of the bottom surface of the pn microdiode, as well as the side walls of the
IMPI
MEXICAN INSTITUTE
FROM ΙΛ FROPIBOAD
INDUSTRIAL metallization layer, and tie layer, if applicable. Then, in step 1310, a state change is created in the link layer for at least one of the microLEDs structures. For example, change of state may be associated with heating the bonding layer above a melting temperature or liquidus temperature of a material that forms the bonding layer or alters a crystalline phase of a material that forms the bonding layer. link. The pn microdiode and metallization layer, optionally a portion of the forming dielectric barrier layer for at least one of the microLED structures, and optionally a portion of the link layer 210, can then be collected with a transfer head in step 1320 and then placed on a receiving substrate in step 1330.
A general illustration of operation 1320 in accordance with one embodiment is provided in Figure 14 in which a transfer head 300 collects a pn microdiode, metallization layer, a portion of the forming dielectric barrier layer for at least one of the microLEDs structures, and a portion of the link layer 210. In the particular embodiment illustrated, a shaping dielectric barrier layer has been formed, however, in other embodiments, a shaping dielectric barrier layer may not be present. In some embodiments, a portion of the link layer 210, such as about half, can be lifted with the structure of "SgS3> ..Art
IMPI
INSTITUT MEXICANO OE LA PROPIEDAD INDUSTRIAL microLEDs. Although a specific microLED structure is illustrated that includes the pn 150 microdiode, it will be understood that any of the microLED structures that include any of the pn 150 microdiodes described herein can be collected. Furthermore, although the modality illustrated in Figure 14 shows a transfer head 300 that collects a single microLED structure, the transfer head 300 can collect a group of microLED structures in other modalities.
Still referring to Figure 14, in the particular embodiment illustrated, the bottom surface of the pn 150 microdiode is wider than the top surface of the metallization layer 120, and the dielectric forming barrier layer 160 extends to the side walls. of the pn 150 microdiode, a portion of the bottom surface of the pn 150 microdiode and side walls of the metallization layer 120. This also applies to the pn 135 microdiodes. In one aspect, the portion of the forming dielectric barrier layer 160, which is wound under the pn microdiode
135, 150, protects the forming dielectric barrier layer 160 on the side walls of the pn 150 microdiode from chipping or breaking during harvesting operation with transfer head 300. Tension points can be created in the forming dielectric barrier layer
160 adjacent to metallization layer 120 or tie layer 210, particularly at corners and locations with acute angles. By contacting the microLED structure with the transfer head 300
IMPÍ ^ - *
MEXICAN INSTITUTE Dt LA PXOF1F.DAD
INDUSTRIAL
<img file="MX340348B_D0035.tif" />
and / or create the change of state in the bonding layer, these stress points become natural breakpoints in the forming dielectric barrier layer 160 at which the forming dielectric layer can split. In one embodiment, the forming dielectric barrier layer
160 it cleaves at natural breakpoints after contacting the mlcroLEDs structure with the transfer head and / or creating the state change in the link layer, which may be before or during pn microdlode harvesting and the metallization layer. As previously described, in the liquid state, the tie layer can be smoothed over the underlying structure in response to the compressive forces associated with contact of the microLED structure with the transfer head. In one embodiment, after the mlcroLEDs structure is brought into contact with the transfer head, the transfer head is rubbed from one side to the other of an upper surface of the microLEDs structure before creating the state change in the layer of link. Friction can detach any particles that may appear on the contact surface of any of the transfer head or mlcroLEDs structure. Friction can also transfer pressure to the dielectric barrier layer. In this way, transferring a pressure from the transfer head 300 to the forming dielectric barrier layer 160 and heating the bonding layer above a liquidus temperature of the bonding layer can contribute to cleavage
IMPI: τττυτσ MEXICANO
OF INDUSTRIAL PROPERTY
<img file="MX340348B_D0036.tif" />
the conformal dielectric barrier layer 160 at a location below the pn 135, 150 microdiode and can preserve the integrity of the microLEDs and quantum well layer structure. In one embodiment, the bottom surface of the pn 135, 150 microdiode is wider than the top surface of the metallization layer 120 to the extent that there is a possibility that the forming dielectric barrier layer 160 is formed on the bottom surface of the microdiode pn 135, 150 and create breakpoints, although this distance can also be determined by lithographic tolerances. In one embodiment, a distance of 0.25 pm to 1 pm on each side of the microdiode pn 135,150 accommodates a dielectric barrier layer 160 of 50 angstroms to 600 angstroms in thickness.
A variety of suitable transfer heads can be used to aid harvesting and placement operations 1320, 1330 in accordance with the embodiments of the invention. For example, transfer head 300 can exert collection pressure on the microLED structure in accordance with the principles of vacuum, magnetic, adhesive, or electrostatic, in order to collect the microLED structure.
Figure 15 is a cross-sectional side view illustration of a bipolar microdevice transfer head operating in accordance with electrostatic principles in order to collect the structure of microLEDs, in accordance with one embodiment of the invention. How I know
IMPI
INDUSTRIAL PROPERTY MEXICAN INSTTTVTO illustrates, the microdevice transfer head 300 may include a base substrate 302, a table structure 304 including a top surface 308 and side walls 306, an optional passivator layer 310 formed on the table structure 304 and including a top surface 309 and side walls 307, a pair of 316A electrodes, 316B formed on the table frame 304 (and optional passivator layer 310) and a dielectric layer 320 with a top surface 321 covering the 316A, 316B electrodes. Base substrate 302 can be formed from a variety of materials such as silicon, ceramic, and polymers that are capable of providing structural support. In one embodiment, the base substrate has a conductivity of between 10<sup>3</sup> and 10<sup>18</sup> ohm-cm. The base substrate 302 may additionally include wiring (not shown) to connect the microdevice transfer heads 300 to the operating electronics of an electrostatic handle assembly.
FIG. 16 is an illustration of a receptor substrate 400 on which a plurality of microLED structures have been placed, in accordance with one embodiment of the invention. For example, the receptor substrate can be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors, or a substrate with redistribution metal lines. In the illustrated particular embodiment, each microLED structure can be placed on a driving contact 410. A common contact line 420 can then
IΜ Ρ ϊ
MEXICAN INSTITUTE OF PROPERTY
INDUSTRIAL
<img file="MX340348B_D0037.tif" />
formed on the series of pn 135, 150 microdiodes. As illustrated, the tapered side walls of the pn 135, 150 microdiodes can provide a topography that facilitates the formation of a continuous contact line. In one embodiment, the common contact line 420 can be formed on a series of red-emitting, green-emitting, or blue-emitting microLEDs. In certain embodiments, the common contact line 420 will be formed from a transparent contact material such as indium tin oxide (ITO). In one embodiment, the plurality of microLEDs can be arranged in pixel groups of three, including a red-emitting microLED, a green-emitting microLED, and a blue-emitting microLED.
Still referring to Figure 16, a close-up illustration of a pn diode 135,150 is provided in accordance with an embodiment of the invention. In one embodiment, the pn diode 135,150 may include a top doping layer n 114 with a thickness of approximately 0.1 pm - 3 pm, the layer of quantum wells 116 (which may be SQW or MQW) with a thickness less than approximately 0.3 pm, and p 118 doping undercoat with a thickness of approximately 0.1 pm - 1 pm. In one embodiment, the top doping layer # 114 may be 0.1 pm - 6 pm thick (which may include or replace the volume layer 112 previously described). In a specific embodiment, diodes pn 135, 150 can be less than 3 pm thick, and less than 10 pm wide.
In using the various aspects of this invention, it should be obvious
MFI i
INSTITUTO MSXICANO OE LA PÍOFIEOAD
INDUSTRIAL to a person skilled in the art that combinations or variations of the above modalities are possible to form an array of microLEDs structures that are ready to be collected and transferred to a receptor substrate. Although the present invention has been described in specific language of structural attributes and / or methodological actions, it will be understood that the invention defined in the appended claims is not necessarily limited to the specific attributes or actions described. The specific attributes and actions disclosed, instead, are to be understood as particularly elegant implementations of the claimed invention, useful in illustrating the present invention.
ΙΜΡϊ
MEXICAN INSTITUTE OF LA FROHEDAD
INDUSTRIAL
Contents83
56 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36 Sheet 37 Sheet 38 Sheet 39 Sheet 40 Sheet 41 Sheet 42 Sheet 43 Sheet 44 Sheet 45 Sheet 46 Sheet 47 Sheet 48 Sheet 49 Sheet 50 Sheet 51 Sheet 52 Sheet 53 Sheet 54 Sheet 55 Sheet 56
157 members in 11 offices
Priority claims11
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Numbers
- Publication
- 340348
- Application
- 5969
Titles2
- Spanish
- MICRODIODO EMISOR DE LUZ.
- English
- MICRO LIGHT EMITTING DIODE.
Classification
- CPC, 11
- H10H20/018
- F21V7/00
- H10H20/812
- H10H20/819
- H10W90/00
- H10W72/0198
- H10H29/10
- H10D62/124
- H10H20/811
- H10H20/823
- H10H20/824
- IPC, 6
- H01L27 15
- H01L29 18
- H01L33 00
- H01L33 08
- H10P72 30
- H10P95 00