Fault tolerant data processing system initialisation.

The present invention relates to a data processing system of the type in which the system initialization routines control the self-test and initialization of each of a first pair and a second partner pair of processors, and their respective associated hardware, where each pair of processors and their associated hardware is brought into safe passage with the other pair, upon successful self-test and initialization, and where the pairs of processors and their hardware subsequently perform identical operations in safe passage under the control of a first operating system, and programs that have a first instruction architecture, comprising the improvement: an additional first pair of processors and an additional partner pair of processors, each pair adapted to perform identical operations under the control of a second operating system, and programs that have a second instruction architecture; an element for directly coupling each processor of the additional pairs with a respective processor of the first and second partner pairs; a logical element controlled by application program instructions that run on the first and second processor partner pairs, to decouple the first and second processor partner pairs from their associated hardware, and concurrently couple the first and second processor partner pairs with respective processors in the additional pairs, by means of said direct coupling element for the transfer of commands and data between them; an element controlled by the application program associated with the first and second processor partner pairs, to initiate and control the self-test of the initialization of the additional processor pairs, by means of commands and data applied to said direct coupling element , while the first pair of processors are decoupled from their hardware; a second logical element effective during system initialization, to inhibit the removal of the first and second processor partner pairs, towards safe passage operation, until the additional processor pairs are self-tested and initialized in a manner indiscernible to the first operating system; and an element that initiates the concurrent removal of the first and second processor partner pairs, and the removal of said additional first pair and processor partner pairs in safe passage operation upon completion of all self-testing and initialization in an indiscernible manner to the first operating system.