Data processing systems

The invention relates to an arrangement for processing operands of programs in a central unit of a data processing system that contains only one arithmetic unit.

The processing of logical and arithmetic commands of programs is carried out in the arithmetic unit of a central unit of a data processing system. The arithmetic unit must be able to perform various operations. If operands have to be linked via several operations when processing commands, several passes through the linking unit are necessary. This has an unfavorable effect on the command duration.

In modern data processing systems, however, the command processing must be as fast as possible. In addition, the

Monitoring of the arithmetic unit with regard to transmission and processing errors should be possible during command processing.

The object of the invention is therefore to specify an arrangement for processing operands of programs in only one arithmetic unit of a central unit, in which the command processing is carried out in an accelerated manner and the operand processing can be monitored. Addresses that are modified in the arithmetic unit are also understood as operands. 25th

The object is achieved in that the units (linkage units) of the arithmetic unit are designed at least twice, so that each of these linkage units is suitable for processing OpeVPA 9/210/2009 II / Hlg - 2 2 edges of full data width, so that the linkage units can be controlled that they perform both different, independent and similar operations. · '

The full data width corresponds to the width of the general purpose registers and the data bus in the central processing unit. The logic units contain not only adders, but also registers and shift registers.

The linking units are advantageously constructed in such a way that they can be interconnected. They then act like a single link unit. This makes it possible to process operands with a larger than normal data width in one pass. The interconnected linking units are set to the same operation. This option is particularly useful when processing long floating point arithmetic.

The link units can be set to operate independently of one another. Different operands can then be supplied to each logic unit, these operands can be linked in different ways in the logic units and the logic results can be evaluated separately. This simultaneous work results in a considerable reduction in processing time. If only two logic units are provided in the arithmetic unit, the processing time is halved.

It is also possible that an operand is tested in one link unit and the same operand is linked in the other link unit.

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In the embodiment of the arithmetic unit according to the invention, it is also possible to detect errors that have arisen in the transmission and processing of operands. For this purpose, for example, the same output operands are fed to the logic units and these are linked in the same way. The linking results from the various linking units are shown with. Checked for equality with the help of a comparator. If they match, the command continues as normal. If the link results are not equal, the command execution is aborted, the command address is checked and an error diagnosis routine is initiated. The same check can of course also be carried out when processing simple address invoices. This monitoring does not increase the command duration. 15th

It is also possible to test the logic unit or parts of it, even if no operands are linked. If, for example, no link unit is required in the course of command processing, the link units are loaded in the same way with any operands and set for similar operations. The linking units work independently of one another. The linking units are advantageously set to operations that cannot be tested in the general sequence.25 Here too, the linking results are compared with one another and an error signal is generated if they are not identical. If an error signal occurs, the command processing is aborted as described above. If there is no error signal, command processing is not impaired in any way.

If a displacement device is provided in the linking unit, its function can also be checked. One gives

VPA 9/210/2009 - 4 - 4 10 introduces the same operands into the shift devices in the various logic units, executes shift commands and then compares the result during the saving process.

In the prop. 1 and 2, a possible basic structure of a part of a central unit, in which the arrangement according to the invention is used, is shown as an exemplary embodiment. The working memory is referred to as ASP. The main memory ASP is directly connected to the arithmetic unit RW, ie the two operand registers B1 and B2. The arithmetic unit is also connected to a register set RES. The register set RES contains the general purpose registers accessible by the programmer. Each general purpose register is duplicated (block A and block B). Both blocks always have the same content, but can be read out separately. This enables instruction acceleration for register-register instructions.

In the exemplary embodiment, an arithmetic unit consists of two logic units VE1 and VE2. Each logic unit is preceded by two operand storage registers (operand registers A, B). These each take up a pair of operands that are to be linked. The registers can also be designed as shift registers for processing hit commands. A pair of operands is accordingly assigned to each logic unit VE1, VE2. The operand pair can either be loaded in parallel into the operand memory register, then registers A1 and A2 or B1 and B2 contain the same information (same operand pairs). They can also be loaded one after the other, in which case registers A1, A2, B1 and B2 can contain different information (= different pairs of operands). Each linking unit can optionally be used as a source for the ArbeitsVPA 9/210/2009 '- 5 - 5 10

Memory ASP, the register set RES or the operand memory registers A, B themselves are used. The intermediate storage registers ZSP1 and ZSP2 are used to temporarily store the results from the logic units. The outputs of the logic units are connected to one another via a comparator VG.

The individual units shown can be implemented in a known manner. The logic units VE thus contain adders and sets of registers, the comparison circuit VG can consist of an EXCLUSIVE-OR element, the intermediate storage registers ZSP contain sets of registers and the main memory ASP can be a core memory or a semiconductor memory.

If two different pairs of operands are to be processed simultaneously in the arithmetic unit RW, then one pair of operands is fed to the pair of operand registers A1, B1, and the other pair of operands is fed to the pair of operand registers A2, B2. From there, one pair of operands goes into one link unit VE1, the other pair of operands into the other link unit VE2. The operands are linked in these linking units VE1 and VE2 according to the command to be processed. The result of this linking is temporarily stored in the intermediate storage registers ZSP1 or ZSP2 or the operand register pairs A1, B1 or A2, B2 and then either returned to the main memory ASP or fed to the register set RES.

If the transmission or processing of operands is to be checked, the operand pairs are loaded in parallel into the operand register pairs A1, B1 or A2, B2 and passed to the logic units VE1 and VE2. The linking units VE1 and VE2 are set to the same operation. The same pair of operands is then linked in the same way both in the linkage unit VE1 9/210/2009 - 6 - 6 and in the linkage unit VE2. If the linking units are working correctly and if no errors occurred during the transmission of the operands, then the linking result at the output of the linking unit VE1 and at the output of the linking unit VE2 must be the same. This is checked with the aid of the comparator VG. If the linking results are the same, the one linking result can then be stored back, for example in the main memory ASP. The other link result is superfluous. However, if the comparator VG indicates inequality, then it emits a signal that identifies the fault. Then, for example, the location of the fault within the central unit can be determined with the aid of a test program.

In the case of operands that have a larger data width, for example twice as long as normal operands, the logic units VE1 and VE2 are interconnected and set to an operation of the same type. The linking units then act like a single linking unit.

In the figure, only the data paths are shown, the lines for the control signals have been omitted.

With the arrangement according to the invention, approximately the same effect can thus be achieved with little effort as with secure computing systems which, for example, consist of two computers operating in parallel. By using several linking units, it is possible to increase the speed of command processing in a program. Finally, operands that are twice as long can be processed in one pass. Furthermore, the arithmetic unit can be tested during the link without spending any time. A testing of the arithmetic unit or parts of it

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- 7 is also possible if the same is not used for processing.