A coherent phase demodulator for power line communication system

[Name of invention]

synchronous detector

[Brief Description of Drawings]

1 is a block diagram of a communication terminal equipped with a synchronization detector of the present invention.

Fig. 2 is a detailed functional block diagram of the synchronization detector shown in Fig. 1;

Fig. 3 shows graphs A, B, and C showing the sampling characteristics provided during a binary base bed data signal and a carrier received and initially processed by the synchronous detector shown in Figs. 1 and 2;

FIG. 4 is a graph illustrating a method of storing a sample signal derived from a carrier input according to the operation of the synchronous detector shown in FIGS. 1 and 2 and generating a phase-coded binary image signal obtained as a result;

5A and 5B are graphs of fundamental frequency relative phase angle vectors and corresponding quarter terns stored in the sync detector shown in FIG. 2;

6A and 6B are graphs of second harmonic relative phase angle vectors and corresponding quarter terns stored in the sync detector shown in FIG.

FIG. 7 is a graph showing the logical state of eight different phase-coded binary image signals with respect to the eight relative phase angle reference lines in FIGS. 5B and 6B and the sample count values mutually coincident;

FIG. 8 is a graph showing a vector plane of a reference actor VR and its quarter phase components generated in response to the operation of the synchronization detector shown in FIG. 2. FIG.

9A, 9B, and 9C are detailed block diagrams of the sync detector repeated in FIG.

Fig. 10 is a time graph for illustrating the operation of the M-storage register and the M-SUM storage register of Fig. 9c during the data bit-synchronized mode of operation;

11(a) and 11b are graphs showing the planes of the components I2avg and Q2avg of the V2avge vector and the components IR and QR of the VR vector, respectively, according to the operation of each vector divider shown in FIGS. 2 and 9b. A graph for explaining generation of a vector in a plane in FIG. 11b by dividing a vector in a plane by 2 in FIG. 11a.

Fig. 12 is a block diagram of one preferred embodiment of a system having a synchronous detector operated in accordance with the block diagrams of Figs. 2 and 9a, 9b and 9c;

[Details of the invention]

The present invention relates to an improved synchronization detector for use in a plurality of communication terminals repairing a carrier wave to be binary phase modulated, and in particular, a phase derived by sampling a subdata symbol segment of a carrier wave. A synchronous detector for generating phase angle vector signals of a fundamental frequency and a double frequency in response to a coded signal. Basic vector signals representing each carrier and segment are compared with reference fundamental phase angle vector signals derived from vector signals of double frequency representing multiple segments, so that a plurality of correlation signals added for each data symbol are make it happen

In general, in a carrier communication method, a carrier wave is modulated and transmitted by binary coded data signals, and the modulated carrier wave undergoes carrier and signal attenuation, noise and other interference phenomena, and severe coral attenuation during subsequent repair. Even after being subjected to the resulting distortion, the data bit information must be detected so that it can be reproduced quickly, reliably and accurately. In the automatic power line communication method, since the carrier and the signal are transmitted together with the power transmitted through the power line distribution conductor, severe interference impulse and broadband noise are particularly present. Also, a powerline communication system has one or more transmitting stations, arbitrary signal repeaters, and an extremely large number of remote end stations located at desired power consumption locations, where message coded carrier signals are often simultaneously received by multiple groups of remote end stations; It is transmitted in an alternating addressing mode to be received by individual repeaters or single stations, and when a carrier signal of multiple frequencies is used, it is practically complicated to determine the frequency to avoid signal interference, and a single frequency voice signal or In the case of using a carrier and a signal, it is important to quickly detect a carrier signal of a receiving end station or a repeater because a plurality of messages are newly multiplexed for selective addressing of each of a plurality of end stations or repeaters. The complexity of the power line communication device is further increased by using a pilot sync signal, that is, an unmodulated sync signal, or coded and combined data and sync pulses for the sync detector. For synchronization of the carrier, for example, 50 Hz. or 60 Hz. It is known that it is desirable to use a power signal of can't be done

In asynchronous detectors, as is often used for frequency-shifted, modulated carrier signals, the carrier and amplitude envelopes of the signal are often used to intimately know the start of the message. Noise impulses and spikes often act as notifiers of mis-initiation of messages, causing poor address decoding and other ambiguity at the receiver, resulting in performance degradation. Therefore, the general detection requirements for the receiving end station of the power line carrier communication method are: optimally detecting the carrier signal in the presence of noise and other interference signals, selecting a basis for detecting the presence of the carrier signal, To provide little deviation from the ideal performance of receiver and detector operation, to synchronize the receiver and detector to the carrier signal, to synchronize each data bit of the coded message information, and to synchronize the message information as originally transmitted. polarity-synchronizing the data bits of the data bits with the binary state of the data bits to cause an eventual error-free reproduction, in order to yieldly satisfy these requirements, The carrier signal of the synchronous phase modulated type is used to reproduce the carrier data contained in the carrier phase relationship, so that there is no need to observe the envelope amplitude of the carrier wave. The signal processing adjustment method of the received phase modulated carrier signal is to limit the noise spike in the wide band, clip it, amplify it in the narrow band and limit the signal, so that the reproduction carrier at the input side of the synchronous detector is less sensitive to the noise impulse of the wide band. will be.

Often in the detection of a constant phase modulated signal, the locally generated or oscillating signal needs to be synchronized to the selection signal before correlation begins. Some actual time is required before signal processing to detect the received data.

Another common phase detection technique is the so-called differential phase shift modulated technique, in which an incoming signal is applied to a delay line and processed for comparison with the immediately preceding data bit so that it has the same polarity as the preceding data bit. causes a signal of reverse polarity to be output. A drawback of this type of phase detection technique is that the reference technique uses information contained in only a single bit, and contains as much noise as is contained in the data bit being processed, resulting in performance degradation. . The differential phase shift modulation scheme is sometimes operated at a low data rate to guarantee more accurate error-free operation, but this limits the amount of data that can be transmitted during a predetermined period.

Accordingly, it is an object of the present invention to provide a system that is particularly suitable for use in a receiving communication terminal in the power line communication scheme, using a uniquely combined and controlled minimum operation, with optimum performance as well as simple and reliable operation. To provide a synchronous detector that performs

In view of the above object, the present invention provides a synchronization detector for a data bit signal modulating a plurality of square and pulse signals derived from a binary phase-shifted carrier wave that is particularly suitable for use in a power line carrier communication method, the square and sampling the pulse signal and generating a plurality of polarity sample bits having any of two binary logic states corresponding to a square and a first level and a second level of the pulse signal, wherein a predetermined equal plurality of groups of the sample bits are an apparatus for causing periodic occurrences during each data bit period, and a plurality of predetermined equal groups in response to a plurality of groups having a plurality of first vector component signals having, for each group, an indication of a relative phase angle at a fundamental frequency. a device for generating a reference vector component signal; a device for generating a plurality of reference vector component signals in response to a plurality of predetermined equal groups having an indication of a relative phase angle at the fundamental frequency; a phase detector for generating a plurality of correlation signals in response to each phase comparison of the plurality of first vector component signals and the plurality of reference vector component signals; and a phase detector output summing circuit for selectively adding the plurality of correlation signals in response to a phase comparison of the plurality of first vector component signals generated from each of the groups.

The present invention also provides the above-described synchronous detector for the power line carrier communication method for performing synchronous phase shift modulated carrier data transmission, wherein the power line carrier communication method is installed in a signal communication relationship with a plurality of power line conductors to perform phase-modulated binary A power line combiner for transmitting a carrier wave having data, and a receiver for receiving a carrier signal from the power line combiner, wherein the receiver includes a carrier wave and a high pass filter for attenuating power frequencies transmitted through a plurality of power line conductors together with the carrier wave a band filter having a center frequency substantially equal to a predetermined frequency of <RTI ID=0.0>a</RTI>

According to the present invention, a synchronization detector is provided for detecting a plurality of binary data symbols, the plurality of binary data symbols having a binary 1 data bit equal to the normal phase of the carrier and 180° phase shift of the carrier, i.e. , is represented by a binary "0" data bit equivalent to the inverse phase as a progressive carrier wave. A phase-modulated carrier wave is a phase-inverted or equi-phase-shifted one, which is severely constrained at the receiver to produce a rectangular carrier signal with phase-coded dipole data bits, the phase-coded The bipolar data bits have a data bit period that defines a predetermined data rate, i.e., a data simple period, and these data bits are synchronized with the sending and signal so as to be integrally related to the frequency of the sending wave signal. In the receiver, opposing states, ie levels, of tightly constrained broadcast wave signals are sampled at a sampling pulse rate in which the ratio of the sampling rate to the transmission frequency is not an integer. Given that they consist of equally spaced polarity sample signals, they represent the phase of one cycle of the half-speed wave during equal carriers and segments of the carrier data bit period. Each group of a plurality of sample signals is aberrationally stored such that a binary phase coded signal representing the phase image of the carrier in each data bit segment is formed. For example, four 8 foot phase coded video signals may be generated during each data bit period. Because the binary states of adjacent bits in a phase coded video signal are inverted when they represent the polarity crossing of the carrier signal, a bit shift is a zero crossing or a polarity shift, and hence the difference between the carrier and the signal during sampling of one carrier data bit segment. It represents the phase inversion in one complete cycle.

A zero-crossing detector determines the relative position and direction of bit transitions in the image signals by associating the phase coded image signals with corresponding sample coefficients. The first memorized vector signals exhibit a different relative phase angle of one cycle at a fundamental frequency equal to the carrier frequency, but independent of the actual received carrier frequency. The vector signal that is then memorized represents a relative phase angle of 2 cycles at twice the carrier frequency, i.e., the second harmonic frequency, but this is also independent of the actual received carrier frequency. The detected zero-crossing sample coefficients establish a corresponding relative phase angle represented by correspondingly selected ones of the memorized fundamental vector signal and the second harmonic vector signal. One representation of the eight different relative phase indications of each of the first vector signal and the second vector signal corresponds to each of the eight bit cells in the binary image signal when zero crossing can be detected. The two groups of memorized vector signals contain digital values of an in-phase I component and a quarter-phase Q component defining each of the eight fundamental frequency vectors V, and each of the eight second harmonic frequency vectors V2 Includes digital values of the in-phase I2 component and the quarter-phase Q2 component. Accordingly, the I, Q, I2 and Q2 component signals are selected from two vector lookup tables as binary representations of quarter-phase components. In addition, these component signals are added separately so that a mood frequency relative phase angle indication Vi and a second harmonic relative phase angle indication V2i are derived for each phase coded video signal derived from sampling individual carrier segments.

The second harmonic vector component is digitally integrated over a predetermined number of carrier segments, i.e., the corresponding phase image signal, such that the second harmonic vector average signal V2avg is generated. The second harmonic vector average signal V2avg is used to detect a strong second harmonic energy component in a received carrier as a standard of carrier detection and to provide a reference phase angle vector signal VR at the same time. The reference phase angle vector signal VR is expressed by an in-phase IR component and a quarter-phase QR component obtained by vectorically dividing a 12 avg component and a Q2 avg component representing the second harmonic vector average signal by two. The basic vector Vi is expressed by an Ii component and a Qi component for each phase-coded video signal of one carrier segment. Each of the Ii component and Qi component, and IR component and QR component signals is applied to a phase detector, the output of the detector being in response to any of the opposing data bit phase states of the carrier segments, positive or negative correlation of the detector input When the relationship is high, it is a correlation signal ±M with a large relative value and positive or negative polarity.

Since for each data bit period there are four phase detector output correlation signals corresponding to four carrier segments, the sum of the four phase detector scramble ±M correlation signal groups is synchronized when they are derived from the associated data bit period. do. In addition, the code polarity of the four correlation sum signal M-SUM is correlated with the binary logic state of the received broadcast data bit represented by the sum of each of the four correlation signals, that is, the polarity. Synchronization of the synchronization detector with each outgoing data bit is provided by the processing of the data bits of the procedural part by the synchronization detector during each data transmission performed by the carrier. The adhesive part contains a predetermined number of data bits in which "1" and "0" appear agitatingly used for synchronization, followed by data bits in which two consecutive "1s" appear, raising the ambiguity of its polarity. used to make it ±M correlation signals are sequentially stored, different groups of four correlation signals are added, and the added M-SUM values are compared to determine the synchronization of the bits. Following the bit synchronization, a separate operation of correlating the sign of the sum of the correlation signals with the binary logic state "I" or "0" of each carrier data bit is required. When receiving two successive polarity indication bits in the prefix, their known states are compared with the sign of two successive sums (M-SUM) of four ±M correlation signals. The data bit sign correlator correlates the sign of the correlation sum with the binary logical state of the received data bits, resulting in a data bit logical state matching the received carrier data bit logical state at the output of the synchronous detector. Thus, the synchronous detector output selector produces a reproduced data bit for each data bit that phase modulates the received carrier.

Accordingly, a feature of the present invention is a synchronous detector of a communication system in which a synchronous phase shift transmits a modulated carrier wave through a plurality of power line conductors of the power system. A single segment vector of a reference vector signal provided by an averaged relative phase angle vector signal representing the summed vector values of a predetermined number of carrier segments preceding deriving a relative phase angle vector signal from each of a plurality of segments of a carrier data bit period. Synchronization detection is provided by correlating the signal and then adding the correlation signals to each received carrier data bit period and a small synchronization relationship. Another feature of the present invention resides in providing a fixed phase angle indication of a receiving carrier by generating corresponding vector signals derived from a plurality of sampling periods, each of which corresponds to a plurality of segments of the received carrier. The carrier segments are sampled by an equal number of polarized sampling pulses with a rate that is not multiplicative with the carrier frequency. The second harmonic vector signal of a predetermined number of carrier segments without changing the sampling pulse frequency to perform synchronous detection and without generating any reference phase angle signals generated by time-consuming frequency control of the local oscillator. It is another feature of the present invention to provide a reference phase angle vector signal derived from calculating an average representation of the set.

In addition, according to another feature of the present invention, a fundamental frequency and a doubling frequency, each of which corresponds to eight relative zero crossings detected in the phase-coded binary image signal of one carrier segment within each data bit period. A synchronous detector is provided which has a stored component signal value representing the relative phase angle in (prescribes one of the phase angle indications). The signal value of the double frequency vector component is applied to the digital integrator so that their values are summed over several data periods, and at the same time, average representations of the second harmonic vector signal are derived, so that the presence of a carrier is detected; At the same time, an averaged reference vector signal generated from several data bits generated in the past is generated for correlation with vector signals representing each coded binary image signal at the same time. According to another feature, it is to provide bit synchronization between the phase-modulated carrier data bit periods without changing the sampling pulse rate, that is, the sampling pulse frequency. To this end, a plurality of groups of polarized sample bit signals occurring at 45° shifted phase angles of spaced cycles of a multi-carrier segment are sequentially stored and the relative phase angle vector of each group of sample signals corresponding to the referenced phase angle vector Phase detection of the indication, then storing the sum of the absolute values of the plurality of correlation signals and sequentially detecting the sum of the maximum absolute values of the correlation signals, so that the grouped sequence of the correlation signal synchronized with the received carrier data bit period is indicated do. The synchronization of the data bits is initially established so that ambiguity of the polarity of the data bits can be raised by detecting the same sign of the correlated signal synthesis produced by two consecutive polarity indicating data bits received during the prefix of the carrier data transmission. is set

1 shows a communication diagnosis station 10 having a receiver 12 installed between the power line carrier input line 13 and the synchronous detector 14 of the present invention. Prior to explaining the synchronous detector 14 having the input selector 15 , the present invention will be understood through the description of the characteristics of the communication signal processed by the receiver 12 and the synchronous detector 14 . The communication terminal 10 is, in one preferred embodiment, connected to a coupler 16 , which is arranged to be in signal communication with at least one of the power line conductors 18 . The power line conductor 18 is typically used by a power company to supply 60 Hz power to a power consumption desired location where the communication terminal 10 is installed. The combiner 16 responds to a power line carrier wave 20 that is transmitted through the power line conductor 18 and is to be received at the receiver 12 . The carrier wave 20 contains data information to be forged modulated and transmitted to be reproduced by the sync detector 14 of the present invention. As is well known, the transmission wave 20 is transmitted in the power line communication method, and in addition to the carrier wave and power of 60 Hz, interference noise and foreign signals of various frequencies are also transmitted. Because of the distribution transformers and related distributors such as power compensating capacitors, in the distribution system including the power line conductors 18, various random attenuation characteristics and impedance characteristics are also exhibited at the carrier frequency in question.

The synchronous detector 14 operates in a communication method with a synchronous phase shift modulated carrier in which a single sinusoidal carrier frequency or binary data modulation phase inversion of a beep is performed. The carrier wave waveform indicated by the example code 22 in FIG. 1 is a phase inversion modulated with a bipolar binary data bit message symbol included during data transmission to be received from the communication terminal 10, and thus is on the power conductor 18. It is a de facto ideal representation of the carrier wave 20 . Each data bit is coded to be zero or a nominal carrier frequency or 180° phase inversion of the carrier frequency, and then these data bits are synchronized to the carrier frequency. Thus, identical carrier data bit periods are provided that contain the same number of cycles of the carrier such that a given data rate is defined. Although the data bit rate is synchronized to the carrier wave, neither the data bit rate nor the carrier frequency need be synchronized to the power frequency or other synchronizing frequency or signal source for the operation of the synchronizing detector 14 according to the present invention; It is also not necessary to have any predetermined high frequency or quasi-harmonic frequency relationship. As an example, a preferred range of carrier frequencies is 9 KHz. to 15 KHz, and an example of a carrier frequency used herein is 1 KHz. Once the carrier frequency and data bit rate are known at the synchronous detector 14, a unique arrangement is provided for the synchronous detector, as will be described below.

The general requirements of the receiver 12 and the synchronous detector 14 are to detect the presence of a carrier waveform 22 in the carrier wave 20 on the power line conductor 18 and to measure the phase of the carrier wave with respect to a predetermined reference phase. correlating the transmitted polarity or binary logic state of each carrier data bit, and providing synchronization of the start and end of each message symbol or data bit period thereof. In order to meet the above requirements, the receiver 12 is adapted to discriminate the frequency of the carrier waveform 22 in the presence of noise representative of the transmission of 60 Hz power and externally induced noise of the power line conductor 18 . A high-pass filter 24 is provided to initially reject the 60 Hz power frequency and pass the center frequency in question. The signal conditioning processor 26 filters, adjusts, and amplifies the received signal to generate a substantially single-frequency carrier waveform 22 having phase-modulation coded binary data information. The signal conditioning processor 26 typically includes a low-pass filter to remove high frequencies slightly higher than the carrier frequency and a diode clipper to remove severe noise impulses. Also, the band filter provided by the signal conditioning processor 26 has a bandwidth of about 400 Hz and a center frequency of 12.5 KHz in a preferred embodiment. Thus, the output of the signal conditioning processor 26 is a sinusoidal carrier wave as initially transmitted or injected into the power line conductor 18 in the presence of low noise. The zero reference axis 27 represents the positive cycle and the negative cycle of the sinusoidal carrier waveform 22 . The reproduced carrier waveform 22 is applied to a hard limiter 28, where it is amplified and at the same time is strictly limited between about 5V (direct current) and the ground potential so that it is generated as a rectangular carrier signal 30, and is generated as a synchronous detector. (14) is applied to the input line (15). The instantaneous high level state and the sequential low level state of the carrier signal 30 correspond to the respective positive and negative half cycles of the carrier waveform 22 . In the carrier signal 30, the entirety of the phase-inverted modulated data information for initially modulating the carrier signal frequency and the phase characteristic of the carrier is produced. The transition of the carrier signal 30 between the high voltage level and the low voltage level, side and column voltage levels is the passage of the carrier waveform 22 between the positive half cycle (positive phase) and the negative half cycle (negative phase), that is, the zero reference. It corresponds to the intersection on the axis 27 .

The synchronous detector 14 divides and processes the carrier signal 30 into predetermined and n segments, and these segments (FIG. 3) are sampled by the operation of the synchronous detector 14 to generate binary image signals Si. From these segments, a phase image, that is, a phase reproduction, is derived for processing the phase angle characteristic. When the synchronization of the synchronization detector 14 for synchronization operation is viewed in a broad sense, the polarity samples of each carrier wave segment are converted into relative phase angles represented by vector signals at the fundamental frequency and double frequency of the carrier wave. A vector signal of double frequency is averaged over several carrier segments so that a reference for phase detection of a vector signal representing a single segment is provided, and at the same time as a standard for the presence or absence of a carrier second harmonic for carrier detection. Criteria for use should be provided.

Correlation signals derived from the phase detector, which will be described later, are added, compared and processed, so that synchronization of carriers, synchronization of data bits and resolution of polarity ambiguity of data bits are achieved, and reproduced on the output line 33 of synchronization detector 14 A binary data signal 32 is generated. The binary numbers "I" and "0" of the binary data signal 32 represent binary data information as included in the transmitted carrier information. Binary numbers "I" and "0" in the binary data signal 32 represent binary data information as included in the transmitted carrier information. Two data signals 32 are applied to logic circuits 34 and 35 for their intended use. These logic circuits 34 and 35 have functions as generally described in U.S. Patent No. 4130874, and the communication terminal 10 is a load used for remote meter reading and remote load control at all consumption desired locations. A plurality of selectable address formats for the power line communication method when the control station type is for the load control station.

Fig. 2 shows a detailed functional block diagram of the synchronous detector 14, which is described in relation to the operation of processing the signals and vectors shown in Figs. Graph A in FIG. 3 is a graph of the logical state of the binary baseband data signal 36 before modulation as shown in the carrier waveform 22. FIG. The transmission start portion of each carrier is shown between the time points TO and T2 and includes a prefix consisting of 11 data bits. These 11 data bits consist of 9 data bits alternating "0" and "I" to provide a bit for synchronization followed by two consecutive "1s" followed by two data bits for polarity indication. contains data bits. At time point T2 at the end of the prefix, the message portion of data transfer is started. The full length of the message part consists of about 50 to 60 data bits in its typical example. A binary base bend data signal 36 is generated at a transmitter (not shown) and is used to phase shift the nominal carrier frequency to generate a phase modulated carrier wave.

Graph B of FIG. 3 exemplifies one carrier data bit period from time TO to T1 in the carrier signal 30 . Each identical carrier data period begins and ends at the point where a phase inversion occurs when the binary state of the data bit, i.e., the logic state, changes from the logical state of the preceding data bit. The initial portion of the prefix contains data bits whose polarity is alternately changed to establish synchronization in the synchronization detector 14, as will be apparent from the description below. The above-described four carrier segments are included during each data bit period as divided into time points TO, TTO-1, TO-2, TO-3 and T1. The carrier wave segment is actually formed after a polarity sampling operation is performed and a predetermined number of polarity samples are accumulated in the synchronous detector 14 . A sampled carrier segment usually does not coincide with the beginning of a data bit period, but is shown to coincide for simplicity of description and relationship of carrier segments and data bit periods (which is equivalent to four carrier segments). Graph C of FIG. 3 shows one carrier segment in graph B. This is defined by eight samples generated by the sampling pulse 37 supplied to the synchronous detector 14 shown in FIG. The frequency fs of the sampling pulse 37 is actually lower than the carrier frequency fc, and in one preferred embodiment is determined by an fs/fc ratio of 8/(8N ±1). (where N is an integer). It is important that the ratio fs/fc is not some integer, but need not necessarily be an integer ±1/8, such that each group of 8 samples will gradually sample a meaningful cycle period of the carrier. When N=5, the sampling rate occurs every 5.1/8 cycle of the carrier signal 30, effectively sampling every full cycle of the carrier signal, i.e., every 45° of 360°, but with a low sample rate, i.e. fs is sampled at a sampling rate of 2,439 Hz. In the case of 4 carrier segments per data bit period, there are 32 sampling pulses for each data bit, which is equivalent to a data bit rate of 76.2 bits per second. The above-described sampling rate occurs with 16 carrier cycles occurring during each data bit period shown among the groups of body 3 diagrams and 41 carrier cycles occurring during each sub data bit segment. Samples of the carrier signal 30 are used to represent the zero crossing of the carrier waveform 22, which defines its phase angle, and hence the standard of the phase modulated data information.

Description of the general characteristics of the carrier signal 30 applied to the input line 15 of the synchronous detector 14 is given with reference to FIG. FIG. 2 shows a polarity sampling circuit 38 for receiving a carrier signal 30 . The polarity sampling of the carrier signal 30 is controlled by the sampling pulse 37 supplied from the sampling pulse clock oscillator 40 . Sampling pulses 37 are also supplied to other parts of the synchronous detector for tie and synchronous control of the synchronous detector.

The high and low levels of the carrier signal 30 are sampled with each occurrence of a sampling pulse 37, causing a series of binary polarity indicating sample signals 43 to be generated. The positive polarity and negative polarity of the carrier wave are expressed in the sample signal 43 as bits of "1" bits or "0" bits, respectively. The bits of the sample signal 43 are sequentially stored in the storage tester of 8 stages, i.e., 8-bit cells, shown as the image signal memory 44 in FIG. When a group of 8-bit sample signals 43 is stored, one phase-coded binary signal is generated and set, which is generated during sampling of one carrier segment so that effective sampling of one cycle of the carrier is completed. do. Any bit transition between the sample bit "1" and the sample bit "0" represents the zero crossing of the carrier waveform 22 between sample times. A phase coded binary signal is denoted by Si, which is a temporarily fixed, stationary image of a carrier segment. Therefore, when the recognized bits are different in the data word defining the binary image signal Si, zero crossing or phase inversion is indicated, which is caused by the bit cell position of the bit transition in the data word register defining the binary image signal Si. is displayed Each of the sample bit positions in the binary image signal Si is represented by a sampling pulse 37 from 7 to 0 corresponding to the most significant bit (MSB) to the least significant bit (LSB) of the binary register, or the same 8 coefficients of the number of bit cells. do. The sample bits of the binary image signal Si detect eight coefficients of the sampling pulse and also a zero-crossing detector 46 that detects whether the transition is positive or negative, that is, whether the transition is from "0" to "1" or from "1" to "0". ) and compared to determine adjacent bit transitions.

FIG. 4 shows the above-described sampling processor, and before explaining the remaining part of the synchronization detector 14 as shown in FIG. The signal 48 shown in FIG. 4 is an imaginary waveform, ie, an example waveform, of one cycle of the carrier signal 30 sampled during the eight sampling pulses of each carrier segment. As described above, a carrier cycle of 41 occurs during eight sample times, i.e., a period of coefficients 7 to 0 shown as progressively smaller numbers above the virtual waveform 48. The first polarity sample is shown at factor 7, which is negative and is stored as bit "0" in the phase coded exemplary image signal (Si: 50) bit cell b7.

Sequentially occurring -,-, +, +. It is stored as bit 00111100 at the position of b0. 8 bit positions of the video signal (Si: 50) and 8 sample coefficients are identified by numbers 7, 6, 5, 4, 3, 2, 1, 0. The transition between coefficients 6 and 5 and the transition between coefficients 2 and 1 shown in FIG. 4 are detected because they are outputs of a zero-crossing detector 46, which will be described later. An example of the output of the zero-crossing detector 46 is shown in Fig. 4, where +5 denotes a positive transition at a factor of 5, and -1 denotes a negative transition at a factor of 1. An example signal in graph II of FIG. 7 is a coded identical representation of an image signal (Si: 50) having (+5, -1), at the output of the zero-crossing detector 46 upon detection of the displayed zero-crossing sample coefficient. . Graph VII of FIG. 7 shows an exemplary binary complementary signal of opposite polarity to that shown in Graph III, in which case the corresponding Si signal (not shown) is +,+,-,-,-,-,+, + Indicates a polarity sample signal and has negative transition at coefficient 5 and positive transition at coefficient 1. In an ideal error-free state, the example signals of graphs III and VIII of FIG. 7 can be generated among the transport and segment of data bits coded in the transmission time region of the same carrier. The sampling process in the synchronous detector 14 just described is continuous, so that the zero harmonic representations of the video signals Si are continuously processed without interruption. The stationary-phase indication of the received carrier segment is effectively achieved by the above-described sampling and zero-cross detection.

Returning to FIG. 2 again, the illustrated relative phase angle vector memory 60 receives the output of the zero bridge detector 46 . The relative phase angle vector memory 60 is in phase with eight octagonal vectors V having a fundamental frequency equal to the frequency of the received carrier wave and a double frequency having twice the frequency of the received carrier wave, that is, a second harmonic vector V2. Substantially comprises component I and quarter-phase component Q. The output of the zero bridge detector 46 is the relative phase angle vector memory 60 . is applied to the that digital signals of the V vector and V2 vector represented by the corresponding in-phase and quarter-phase components of the stored vectors are generated. do. One result to be achieved by the output of the relative phase angle vector memory 60 is a phase angle vector signal representing or corresponding to the relative phase angle of each zero crossing of the carrier wave segment, as represented by the binary image signal Si. is provided, and the phase angle vector signals Vi and V2i are established from all zero crossings of the binary image signal Si. Thus, the phase angle vector signals Vi and V2i represent the relative phase angles at the fundamental frequency and the second harmonic frequency for each carrier segment for further signal processing in the synchronous detector 14, as will be described below. . Various phase angles, referred to herein as phase angles, are either by one vector having a certain magnitude and angle in the polar coordinate system, or as two vector components in the Cartesian coordinate system called in-phase components and quarter-phase components herein. is expressed It should be noted that particularly important in the present invention is the phase angle information expressed by the vector described above.

The stored values of the vectors V and V2 are equivalent for any frequency value fc of the received transmission frequency, although those vectors are described as related to the fundamental and second harmonic frequencies of the carrier wave. As long as the sampling frequency fs coincides with the carrier frequency of 12.5 KHz. described above as an example, those vectors are valid for the synchronous operation. The phase angle vector signal Vi obtained for each carrier segment will provide a consistent relative phase value reference indication from time to time as long as groups of eight sampling pulses actually accurately and repeatedly sample one complete cycle of the carrier signal 30 . Vectors V and V2 are said to relate to "relative" phase angles because the start of the sampling process is unknown and randomly initiated at some instant or phase angle of the carrier signal 30 . Thus, the cyclic group of the 8-bit polarity sample signal 43 is converted into a corresponding relative phase angle represented by any phase angle vector signal Vi and V2i, which is the sum of the stored vector values, so that an arbitrary phase angle reference indication is provided. do. The specific phase angle value of both vectors is not critical, rather, that both vectors that are completely equal or substantially equal are generated for a carrier segment of one carrier databit polarity or substantially equal or approximately equal 180° shifted. It is important that both vectors are generated for carrier segments of reverse carrier bit polarity. Although the description here relates to the virtually error-free operation, the approximation method, comparison technique, and measured averaging and addition operation included in the function of the synchronous detector 14 are ideal signal conditions as typically seen in the power line carrier communication method. It is noted that it will optimally do an accurate reproduction of the outgoing data bits and their polarities, as long as they adapt to errors and deviations from .

Since the phase of the second harmonic does not change when the phase of the nominal carrier frequency is inverted due to the inverted phase coding of the data bits of "1" and "0", the double frequency, i.e. the vector V2 of the second harmonic, occurs before It is used to generate a reference vector VR for an extremely large number of carrier segments. The second harmonic vector V2 rotates 2 cycles when the vector V rotates 1 cycle, so that the 360° phase of V2 occurs at 180° phase of V but is the same as it occurs at 0° phase of V. The above description is exemplified in Figs. 5A, 5B, 6A and 6B. The second harmonic vector V2 is used to perform the carrier detection function. The detection of the carrier is done by measuring the spectral energy density distributed in the band filter that reproduces the carrier for processing by the synchronous detector 14. The detection of the spectral energy density is effected by a second harmonic vector V2 that substantially doubles the frequency of the input carrier, and the synchronous detector filters to measure the component of the second harmonic that is very close to the expected carrier frequency.

Thus, the use of a corresponding fundamental vector signal and a second harmonic vector signal representing the phase angles detected during the carrier and segment avoids processing the total number of incoming data signals, and is commonly used in many conventional synchronous detectors and harmonics. Having a locally generated reference signal source is avoided.

Reference to the graphs of FIGS. 5A and 5B is an additional explanation of the above, these graphs showing in-phase components I and 1 of the fundamental vector V stored in the relative phase angle vector memory 60 shown in FIG. Representative values of /4 phase component Q are shown. To the extent these vectors are referred to herein as describing the synchronous detector 14, they are located on the I reference axis and Q reference axis at 0° and 90° respectively, so that representation of the vector as having a length and an angle is avoided. It is represented by two 90° components with weighted values corresponding to their lengths. An approximation is also used so that the components corresponding to a certain vector are specified, as described below. The vector V rotated counterclockwise by an angle θ starting from the 0° axis in FIG. 5a and represented by numbers 0 to 7 is the in-phase component I and the quarter-phase in the corresponding graph of FIG. 5b. Correspondingly defined by one of the weighted values of -4, -3, -, +3 and +4 for component Q. By connecting the I and Q values, a pseudo sine wave and a pseudo cosine wave are generated. In this case, I equals pseudo Vcosθ, Q equals pseudo Vsinθ, which are in fact transformations from polar to rectangular coordinates. The two pseudosinusoids described above are shown in Fig. 5b as relative phase angles spaced 45[deg.] with respect to eight vector axes shown as 7 to 0 of V. The vector axes 7 to 0 in FIG. 5b are shown with respect to the I reference axis and the Q reference axis of 0° and 90°, respectively. Thus, vector 7 can be defined by I and Q components where I is +3 and Q is -3. Vector 7 is shown as extending at -45° from the fourth quadrant of FIG. 5A. Correspondingly, the vector 6 is defined by the in-phase component I and the quarter-phase component Q when I = +4 and Q = 0. Vector 6 is shown coincident with the I reference axis of 0°. The two numbers in parentheses of the vectors in Fig. 5a are the weighted values of the I and Q components of the related vectors taken from the graph of the two pseudosinusoids shown in Fig. 5b. Therefore, (3, -3) represents vector 7, and (4, 0) represents vector 6. These values are approximations of true sinusoids, but they simplify the memory of the vectors to a satisfactory level. The vector component values specified in parentheses of each vector in FIG. 5a are the relative phase angle vector memory 60 ) is remembered in Thus, within parentheses of the vector 7,6,5,4,3,2,1,0 the respective weighted values 3,4,3,0,-3,-4,-3 and 0 of the in-phase component I and 0 and The respective weighted values -3,0,3,4,3,0,-3 of the quarter-phase component Q are specified.

Figures 6a and 6b show twice the relative phase angle as represented by two pseudo-sinusoids I2 and Q2 with cycles of twice the frequency compared to the single reference frequency cycle of I and Q shown in Figure 5b. A frequency vector, that is, a second harmonic vector V2 is shown. 7 to 0 of the corresponding vector V2 are shown along the same vertical axis reference lines in Figs. The related values of I2 and QW in Fig. 6b are considered as pseudocosmic and sinusoidal components of V2 rotated by a single 2θ cycle as follows. I2 equals pseudo V2sinθ and Q2 equals pseudo V2cosθ, which also define the transformation from polar to rectangular coordinates. The corresponding second harmonic vector V2 is shown in Fig. 6a with an in-phase component I2 axis and a quarter-phase component Q2 axis of 0° and 90°, respectively. The vectors 7,6,5,4,3,2,1,0 of the second harmonic vector V2 represent the respective weighted values 0,1,0,-1,0,1,0,-1 of the in-phase component I2. and respective weighted values -1,0,1,0,-1,1,0 of the quarter-phase component Q2. The second harmonic vector V2 advances 720° every 360° of the fundamental vector shown in FIGS. 5A and 5B.

The zero-crossing detector 46 shown in FIG. 2 is a relative phase angle vector memory 60 having first and second lookup tables containing the weighted values of I and Q, and I2 and Q2, respectively, as described above. It has an output applied to The polarity bit transitions are the corresponding eight sample coefficients of the phase coded binary image signal Si which will produce the corresponding in-phase component I or I2 and quarter-phase component Q or Q2 of the fundamental vector V and the second harmonic vector V2, respectively. It is shown in Figure 7 by

Thus, in the example shown in Fig. 4, the transitions of +5 and -1 have two I components of +3 and -3 and two I components of +3 and -3 and two I components of +3 and -3. We will generate two sets of four vector component values with a Q component. The sum of the in-phase component I value and the quarter-phase component Q value is obtained by adding the I component values to each other and the Q component values to each other, and negation of the respective I and Q component values for negative transitions. obtained for each phase-coded signal representing one carrier and segment by taking. Accordingly, the Ii component of the exemplary image signal (Si:50) having a transition at the coefficient 5 and the coefficient 1 of FIG. 4 is equal to +3-3(-3)=+6, and the Qi component is +3(-3) ) = +6. The Ii and Qi components are the values (6,6) at +45° between the 0° reference axis of Ii and the 90° reference axis of Qi (these are not shown, but equal to twice the vector value shown in FIG. 5). ) of the synthetic vector Vi(Ii,Qi). A further explanation with respect to FIG. 7 is shown below how to convert the zero crossing to the corresponding individual I, Q, I2 and Q2 component values.

By taking the corresponding I2 component value and Q2 component value for each zero-crossing, and finding a corresponding vector from the sample coefficients of bits having a certain transition in the binary image signal Si, the second harmonic vector V2 is also zero-crossed. It is determined from the outputs of the detector 46 . Therefore, in the example of Fig. 4, since the two values of I2 from the bit sample transitions at coefficient 5 and coefficient 1 are respectively equal to 0, their sum is obtained in the adding circuit 62, and the resulting I 2i value is 0. becomes equal to Two Q2 values are added to Q2i of the binary image signal Si. Q2's coefficient 5 and coefficient 1 are each +1, so Q2i is equal to +2. Synthetic vector V2i is not shown in Fig. 6a but matches vector 5 shown in Fig. 6a. Therefore, the ideal I2i component and Q2i component of the synthetic vector V2i are two hundred of the components shown in Fig. 6A. The phase angle vector signal V2i (I2i, Q2i) of the second harmonic vector is applied to the digital integrator 64 . Digital integrator 64, in one preferred embodiment, performs low-pass filter operation with a predetermined time constant equal to four data bit periods, i.e., 16 carrier segments. The I2i component value and the Q2i component value for the phase angle vector signal V2i of each new binary immortal signal Si are the 15 preceding V2i such that the average of the sum of the augmented values at or near the second harmonic of the received carrier is developed. It is effectively integrated at the value (I2i, Q2i). Accordingly, the digital integrator 64 is of a so-called "accumulator" type that provides smooth output values by performing a low-pass, wave action. Note that after at least four carrier segments have been processed, the polarities of the fundamental vectors V and Vi are inverted during the sync data bits of the data transfer prefix. Conversely, since the I2 component value and the Q2 component value have the same polarity as described above, the values of the same sign will continuously contribute to the average outputs of the weighted sum of the digital integrator 64 . For Figure 4, for the example carrier segment described above, the V2i values of I2i = 0 and Q2i = +2 rise towards the average value of the ideal V2avg weighted sum of Iavg = 0 and Qavg = +32 by error-free operation. is integrated This creates V2avg along the 90° reference axis of FIG. The output of the digital integrator 64 is an I2avg component and a Q2avg component having an average value of the weighted sum derived over the varying totals of the 16 binary image signals Si (which is equivalent to 4 data bit periods).

The values of the I2avg and Q2avg components for the eight vectors 7 to 0 of V2avg are 16 times the I2i and Q2i component values corresponding to the second harmonic vector V2i (which are twice the values shown in FIG. 6), so theoretically For error-free operation, the values of I2avg are 0, +32, 0,+32,-32,0,-32,0+31,0,-32, respectively, and the values of Q2avg are -32,0,+ respectively. It becomes 32,-,=32,0,+32,0. It is noted that the above-mentioned numerical value is an average value of the weighted sum for providing the relative phase angle vector indication, and the synchronization detector 14 may use other values having corresponding weighted values. In addition, in actual operation, the above-mentioned theoretical value is not generated, and the actual V2avg vector signal is generated within the plane shown in FIG. 11A or the relevant plane of FIG. 6, but with an I2avg reference axis of ±0° and ±90 ° does not coincide with any of the Q2avg reference axes.

The carrier detector 66 has means for calculating the magnitude of the vector or the RMS value of the V2avg vector from the I2avg value and the Q2avg value generated by the digital integrator 64 . Since the carrier detector 66, in one preferred embodiment, also responds substantially to a predetermined threshold established for noise-related operation, when the RMS value of the Vavg vector is calculated and exceeds the predetermined threshold, The carrier detection logic signal CD is supplied to the output line 67 of the carrier detector 66 .

When the I2avg component and the Q2avg component are used to detect the carrier, it is necessary to convert the average vector component of the weighted sum into a reference phase angle vector VR (having an IR component and a QR component) in the vector angle calculator 70 . For illustrative purposes, the theoretical values for the I2avg component and the Q2avg component described above have corresponding second harmonic vector V2i angles as shown as the I2 component and Q2 component of V2 in FIG. 6A. A vector value Vvg divided by approximately half an angle is calculated to generate a VR as described below with respect to FIGS. 11A and 11B, where the actual V2avg vector is in the 360° plane of FIG. 11A. In the theoretical example of I2i and Q2i, the values of the IR component and the QR component of the corresponding reference vector VR are shown in FIG. The 1R component is always set to positive in calculating the half vector angle value from the V2avg vector value I2avg vector component values I2avg and Q2avg, and the IR component and QR component are the IR reference axes taken along the 0° axis as shown. It is selected to occur in the first upper limit and the fourth upper limit shown in FIGS. 8 and 11 as well. The quarter-phase reference axis QR of 90° is shown at +90° from the reference axis IR of 0°. The theoretical values for the IR component and QR component of the theoretical VR vectors 7,6,5,4,3,2,1 and 0 in FIG. 8 are the theoretical I2avg and It is shown as calculated from the Q2avg component. Therefore, the theoretical VR vectors 7 to 0, respectively, +32, +32. Generates QR component values of 32, 0, +32, +32. Because of the reciprocity that can occur in the half-angle division of vectors, a correction is made when the Q2avg component passes 180° if the corresponding QR component can vary between ±90°; It will be described later in conjunction with the description of FIG. 11B. An important feature of the present invention is that the IR component value is always positive.

The vector angle divider 70 generates a reference phase angle vector VR on its output side, which reference phase angle vector VR is expressed by the values of the IR component and the QR component, and the values of these IR and QR components are the values of the V2i vector component. It is made based on the average values of the above weighted sum of the preceding 16 values. The phase detector 76 receives the Ii component value and the Qi component value of the synthesis vector Vi for the single binary image signal Si of one carrier segment, and also receives the IR component value and the QR component value of the reference vector VR. When each component of the positive input is individually multiplied, (Ii X IR) + (Qi X QR) is generated in the output line 78 . That is, in the output signal 78 of the phase detector 76, the correlation between the phase angle vector Vi(Ii, Qi) and the reference phase angle vector VR(IR, QR) is generated. The ±M correlation signal 77 on the output line 78 is represented by +M or -M, each of which indicates the relative phase angle of the phase angle vector Vi(Ii, Qi) is the reference phase angle vector VR(IR). , QR) provides a standard of the same polarity or reverse polarity by in-phase or opposite-phase to the reference phase angle indication.

The correlation signal 77 has a large numerical value and a + or - sign in a small error operation, so that the component representations of the phase angle vectors Vi and VR, that is, the positive and negative correlations of the phase detector inputs, are precisely in phase relationship in phase. and it is clearly provided that it is completely in an ideal topological relationship.

Fig. 7 is a graph of eight phase-coded ideal image signals Si having eight different phase relationships, each of which has two different zero crossings. In graph III of FIG. 7 and in E shown in FIG. 4, the ideal correlation signal 77 is calculated in the satellite detector 76 as will be described later. The Ii component value and the Qi component value are +6 and +6 as generated by the sum of the two vector component values as described above. Ii X IR is (6 X 32) =192. Qi X QR is (6 X 32) = 192, and the M-correlation signal value is +142. In the graphs I, II, III, IV, V, VII, and VIII of the graphs I, II, III, IV, V, VII, and VIII of Fig. 7, the calculation of the analogous form for the image signals Si is the value of the ±M correlation signal 77 +384, +256, +384, +256, will generate -384 and -256 respectively. It is also noted that these values are any weighted values that may vary by individual selection of weighted values for the vector component values described above. In one preferred embodiment, the correlation signal 77, which is the output of the phase detector 76, is a data word formed by a binary number consisting of an 8-bit signal in two's complement. Accordingly, the most significant bit (MSB) b7 of the data word signal of the correlation signal is logical "1" or "0" with respect to the negative (-) signal and the positive (+) signal of the ±M correlation signal 77 .

The following description will describe the phase angle vector Vi(Ii, Qi) derived from each carrier segment for the reference vector VR(IR, QR) derived from the average of 16 weighted sums of the second harmonic vector signal V2i(I2i, Q2i). ) and a method of performing carrier detection and phase detection of each binary image signal Si. Therefore, their values actually vary slightly with each new vector signal V2i (I2i, Q2i). The correlation signal 77 of the satellite detector 76 is fed to the phase detector output summing circuit 84 so that the sum of the four correlation signals 77 corresponding to the sampled carrier segments included during the carrier data bit period being processed is provided. must be combined by The operation of the data bit synchronization circuit 86 generates appropriate groups of four correlation signals 77 such that they form the combined sequence of the correlation signals 77 . The phase detector output summing circuit 84 generates a correlation sum (±M-SUM) signal 87 that is the algebraic sum, that is, the integrated and weighted sum of the four correlation signals 77 for an appropriate group. Further, when the four correlation signals 77 in the correct sequence are synchronized with the carrier data bit period, the data bit logic state is correlated with the sign of the correlation sum signal 87, so that the The sign must correspond to the binary logic states "1" and "0" of the data bits transmitted on the carrier wave.

The data bit for duality indication at the end of the data transmission prefix is used for the operation of the data bit code correlator 92, which will be described later. Each correlation signal 77 is applied to a phase detector output summing circuit 84 having four memory registers connected in an annular shape. The phase detector output summing circuit 84 causes the correlation signal 77 to be sequentially stored in its storage register after receiving the carrier detection signal CD. When each correlation signal 77 is applied to the memory register, its correlation signal 77 is added logarithmically with the preceding three correlation signals 77, and the resultant ±M-SUM signal 87 is M - Stored in the SUM memory 88. The M-SUM memory 88 also has four storage registers connected in an annular shape, and these registers are the absolute values of the four ±M-SUM correlation sum signals 87 generated by the phase detector output summing circuit 84, i.e. , receive an unsigned value and accumulate it. When the four storage registers in the M-SUM memory reach their maximum values, the reset operation for the counter controller in the data bit synchronization circuit 86 is started. Whenever the M-SUM signal in the M-SUM memory 88 is higher than the preceding M-SUM signal, a reset operation is started. Each time the M-SUM signal in the M-SUM memory 88 is higher than the preceding M-SUM signal, a reset operation is performed, as a result, after reception of several correlation sum signals 87, the four correlation signals 87 are A plurality of groups formed are detected. These groups produce maxima when added to each other. Then, the bit synchronization is set and stored by the sequence counter in the M-SUM memory 88 as will be described later. After the maximum value of the absolute sum of the correlation sum signal 87 reaches a predetermined threshold, the bit synchronization process is terminated. This bit synchronization operation is performed within 4 to 5 prefix data bits after carrier detection.

The sign of the M-SUM signal 87 corresponding to the data bit period is located in the data bit sign correlator 92 because it is synchronized with each associated received data bit period. When the two polarity indicating data bits of the prefix are received, the signs of the two corresponding M-SUM signals 87 are compared, and if the signs of both M-SUM signals are positive, the data bit sign correlator 92 The M-SUM output stored in the M-SUM memory 88 is inverted and sent to the data output circuit 96. When the polarities of the two M-SU signals are both negative (-), the data bit sign correlator 92 does not invert the output of the M-SUM memory 88 to the data output circuit 96 . As an example, two M-SUM signals 87 are selected to have theoretical signal values of -192 and -19 when two polarity indication data bits are generated and each of them is "1". Accordingly, the data bit sign correlator 92 inverts the signs of all subsequent M-SUM signals, causing the data output circuit 96 to generate the binary data output signal 32 . The binary data output signal 32 is "1" and "0" respectively when the +M-SUM signal and the -M-SUM signal are generated in the data output circuit 96. Accordingly, the data output signal 32 of the synchronous detector 14 is on top of the baseband binary-coded data bits in the received carrier wave. In a typical example, the data output signal 32 is not generated until the prefix ends (which indicates the start of the information transfer portion of the wave transmission message).

9A, 9B and 9C are detailed block diagrams of the synchronous detector 14 generally shown in the block diagram of FIG. It corresponds to one embodiment of the invention. The microprocessor-based method of FIG. 12 includes a 6,800 series microcomputer system 108 commercially available from Motorola Semiconductor Manufacturing Company. The usage and description of the microcomputer system 108 are described in Motorola's M6,800 microprocessor application manual and M6,800 programming standard manual (, 68PRMD) issued in November 1976. In FIG. 12, the CPU 110 has a structure as generally shown in U.S. Patent No. 4,145,761, and operates according to the contents of the above-mentioned publication in order to perform signal processing of carrier synchronization detection as will be described later. can do. The ROM 112 has a program memory, in which an operation instruction of a pre-programmed sequence is stored in the program memory to perform the operations described herein. The RAM 114 has a plurality of 8-bit (bits b7 to b0) address memory registers for read/write, and these address memory registers are used for signal processing for performing a novel operation of the synchronous detector 14. Provides binary data storage. The timer module 116 for crystal-controlled oscillation has a programmable double divider, and the programmable double divider provides a clock oscillator 40, which generates sampling pulses ( 37) is internally related as a synchronous relationship with the carrier frequency fc as described above. The sampling pulse 37 is selectively applied to the NMI input line 120 of the CPU 110 through the plurality of data I/O ports 118 . The timer module 116 also provides a timing control signal for timing the operation of the CPU 110 .

The plurality of carrier signals 30 are applied from the receiver 12 to one of the plurality of data I/O ports 118 in the CPU 110 . The present invention relies on the method and result and novel arithmetic functions described in detail herein rather than program operations in a specific order as used in a plurality of instructions to be programmed in the ROM 112 . Each of the plurality of stretching processes and operations as described during the description of FIGS. 9a, 9b and 9c according to the description given with respect to FIGS. 1 and 2 is a separate logic as well understood by those skilled in the art. It may be formed as a circuit component.

Certain types of memory masters are cited in the descriptions with respect to FIGS. 9a, 9b and 9b, and these memory registers are to be installed in the RAM 114 and are apparent from the following description. The address selectable data arresters described below have data and signal values as used to operate the synchronous detector in the following discussion of FIGS. 9A-9C.

The sampling pulse counter registers 126 (FIG. 9A) each count eight sampling pulses in the manner of a modulo-8 ring counter by subtracting from a count of 7 to a count of 0 when the sampling pulse 37 is generated. The count of the sampling pulse counter register 12 is decremented to 0, and the output CP comes out, indicating that the eight polarity samples of the carrier signal 30 are complete.

The binary image signal Si counter register 128 (FIG. 9a) counts each group consisting of four binary image signals Si phase-coded in the manner of modulo-4 counter by decreasing the coefficient 3 to the coefficient 0. do. The sampling pulse counter register 126 reaches a count of 0, and the count content of the Si counter register 128 is decremented by one count. When the Si counter register 128 reaches the coefficient 0, the output Cis indicates that four binary image signals Si are detected and four carrier segments equal to one data bit period are sampled.

The data bit counter register 130 (FIG. 9A) counts a plurality of data bits in the prefix after the carrier wave is detected and the maximum count is 5. The coefficient 5 is reduced to the level 1, so that a delay for determining the bit synchronization with the carrier data non-special period is made before starting the data bit code correlation operation. The data bit sign correlation operation is initiated by the output Cdbl before the tenth and eleventh two "I" data bits provide the aforementioned polarity indication of the prefix. Upon completion of the data bit sign correlation operation, the data bit counter register 130 is decremented when it has a negative value, indicating that the bit synchronization and data bit sign correlation operations are complete.

The total sequence counter register (132: Fig. 9a) counts from the count 0 to the count 3 in the manner of the Domulo-4 counter, and each increase the coefficient.

The register 128 indicates which of the four correlation values M is the start of the data bit, which is shown by the example symbol 88 in FIGS. 2 and 9C and is added with the M-SUM value during the bit operation described later .

The current phase-coded binary image signal Si register (FIG. 9A) acts as a shift register currently being accumulated, causing a plurality of polarity-indicating sample signals 43 to form, in which the sample signals 43 are transferred to the carrier signal 30 ) because it occurs simultaneously with each of the sampling pulse times. Loading the 8 sample bits into the register allows the binary image signal Si to be defined, which is the phase representation of the quarter segment of the carrier data bit period.

The last Si register 136 is a temporary memory of the last 8 sample bits loaded into the current Si register 134 . The bit cell position in the last Si register 136 corresponds to the corresponding sample coefficient to indicate the logical transition of the bit and the zero crossing of the carrier signal, the sample coefficient.

The preceding last Si register 138 (FIG. 9A) is a temporary storage of a binary image signal preceding the binary image signal Si currently stored in the last Si register 136. As shown in FIG. The least significant bit b0 position in the succeeding last Si register 138 is compared with the most significant bit b7 position for detection of a bit transition occurring at the most significant bit b7 position in the SI register 136 .

Base vector V(I,Q) lookup table register 60-1: Fig. 9a shows up to 8 for each I-component and Q-component corresponding to the approximate weighted approximate weighted values shown in Figs. 5A and 5B. Remember binary values.

The second harmonic vector V2 (I2, Q2) condition table register 60-2 (Fig. 9A) contains eight binary values for the I2 component and the Q2 component corresponding to the approximate weighted values shown in Figs. 7A and 6B. remember

The Ii register 140 and the Qi register 142 (FIG. 9A) are the sum of the I component values and the Q component values derived from detecting the zero crossing of each binary image signal Si generated for each carrier segment. remember

I2i register 144 and Q2i register 146 (Fig. 9a) store the sum of the I2 component values and Q2 component values derived from detecting the zero crossing of the image signals Si, 2 generated for the carrier segments. do.

I2avg register 148 and Q2avg register 150 (Fig. 9b) store 16 weighted sum average vector component values of I2avg and Q2avg in the exact two binary numbers resulting from the digital integration operation. 15/16 of each of the I2i component and Q2i values are summed over the time constant of the binary image signal Si, and these are added to the current I2i and Q2i vector component values, respectively.

The values of the I2avg register 148 and the Q2avg register 150 change slowly during the actual operation of the synchronous detector 14, as a result, abrupt changes in I2i and Q2i precede the measurement of the second harmonic component of the received carrier. The weighted sum average value does not change abruptly.

The Q2avg register (156: Fig. 9b) stores the binary number of the preceding higher-order byte of Q2avg and compares it with the binary number of the current preceding higher-order byte of Q2avg, so that the dominance in each division of the vector is removed. It is used to measure whether Q2avg changes on the -180° reference axis.

The IR register 158 and the QR register 160 (FIG. 9B) store the binary values of the IR component and QR component of the reference vector VR generated by vector angle division.

The V(I,Q) lookup register 60-1 (FIG. 9A) has eight weighted values for each of the I2 component and the Q2 component as shown in FIGS. 5A and 5B.

The V2(I2, Q2) lookup register 60-2 (FIG. 9A) has eight weighted values for each of the I2 component and the Q2 component as shown in FIGS. 6A and 6B.

The flip-flop 1 register 162 is a flag register, and stores "1" or "0" for adjusting the sign change of the Q2avg vector component for a plurality of changes traversing the -180 DEG reference axis during vector angle division. The logic state of the flip-flop 1 register 162 allows the vector calculation to be corrected for the ambiguity of the vector division by inverting the sign of the correlation signal of the phase detector 76 .

The threshold value register 163 (FIG. 9B) stores a certain threshold value for the carrier detection operation. The threshold is set as a predetermined level compared with the effective value of V2avg to start the carrier detection signal CD.

The phase detector output (M) storage register 164 (FIG. 9B) stores the correlation signal 77 output from the phase detector 76. This is the correlation of vectors Vi and VR determined by the sum of the signed quadrature multiplications of I × IR + Q × QR for each binary image signal Si. A batt in the phase detector output storage register 164 is a signed binary number in 2's complement, and a sign and a magnitude indicating the correlation between positive and negative are provided.

The current M-SUM register 172 (FIG. 9c) stores the current M-SUM signal 87, which contains the four correlation signals 77 from the phase detector 76. ) has the sign and magnitude of the binary value of the sum.

It stores the sign and magnitude of the last M-SUM value stored in the last M-SUM register 174, which is used for the data bit sign correlation operation in the current M-SUM register 172 and the last M-SUM value. The most significant bit b7 of the register 174, that is, the sub-bit is for comparison.

The M-SUM storage register 176 (FIG. 9c) stores the sign and magnitude values of the current correlation sum signal 87 derived from the four storage registers 181 to 184. During the bit synchronization operation, the sum value of each of the four consecutive correlation signals 77 is converted into an absolute value to be compared, resulting in synchronization with the carrier data bit period for establishment of bit synchronization such as M-SUM.

The flip-flop 2 register 178 (FIG. 9c) is a flag register, and is a flag register for consecutive 2 of four correlation signals 77; A 1 or 0 corresponding to the known 1 of the two polarity indication data bits of the transmitted prefix with a group of positive and negative M-SUM signals 87. remember

M memory 1 register 181, M memory 2 register 182, M memory 3 register 183, and M memory 4 register 184 (FIG. 9c) are the values of the last four correlation signals 77. Since they occur sequentially among the detector output storage registers 164, they are storage registers for sequentially storing their values. The sum of these four storage register values provides the proper value of the M-SUM signal 87 after bit synchronization.

M-SUM memory/register (185), M-SUM memory 2 register (186). The M-SUM storage 3 register 187 and the M-SUM storage 4 register 188 are storage registers from which successive M-SUM signals 87 from the four storage registers 181,182, 183 and 184 are sequentially loaded. The binary values in the storage registers 185 to 188 are absolute values rather than signed values. Among the storage registers 185 to 188, the storage register having the largest M-SUM signal value is detected to indicate a corresponding M-SUM signal group consisting of a plurality of correlation signals 77. As shown in FIG. The plurality of correlation signals 77 correspond to data bit periods as detected during the data bit synchronization operation.

The maximum M-SUM storage register 190 (Fig. 9c) stores the sum of the accumulated maximum absolute M-SUM values that emerge when summing the four successive correlation signals 77. The maximum M-SUM value corresponds to the maximum value in one of the storage registers 185 to 188. This maximum value has the highest value to be continuously accumulated among the above-described one storage registers. When a predetermined threshold value is reached among the maximum M-SUM storage registers 190, the data bit synchronization operation is stopped.

Referring to Figs. 9A and 12, which show the synchronous operation of the synchronous detector 14, these synchronous operations are based on the above-described relationship and characteristics of the phase angle vector component and the carrier signal shown in Figs. Includes a general description of the For this reason, it has a series of operations as controlled by the program command data stored in the ROM 112 while using the RAM 114, which will be described later. Accordingly, the carrier signal 30 is shown in FIG. 9A as being applied to the polarity sampling circuit 38 . The sampling pulse 37 is applied from the clock oscillator 40 as described above, so that the polarity sampling operation of the reception input to the synchronous detector 14 is provided. The sampling operation continues regardless of whether a carrier is received or not. 12, the plurality of carrier signals 30 are the most significant bit b of the microcomputer system 108.⁷It is applied to the data I/O port 118 . The sampling pulse 37 is generated at the main frequency fs programmed by the oscillation timer 116 and is applied to the NMI input line. The CPU 110 starts the NMI routine so that the voltage level at bit b7 of the data I/O port 118 is detected.

The program operation sequence of the CPU 110 starts the main operation sequence, where the signal applied to the I/O bit b7 input line is detected at the start value of each sampling pulse. The high voltage state and the low voltage state generate the corresponding sample signal 43 of "I" or "0", respectively. A plurality of bit samples are set at the first stage, that is, the least significant bit b0 position of the current Si register 134 in FIG. 9A configured as shown in FIG. The sampling pulse counter register 126 is decremented by 1, and the main piece sequence is made valid by the other input applied to the NMI input line of the CPU 110 by terminating the standby state for the other sampling pulse 37. The above-described operation sequence is repeated with each of the sampling pulses decrementing the sampling pulse counter register 126 . When the sampling pulse counter register 126 reaches the count 0, the operation sequence serially transfers the binary data in the current Si register 134 to the last Si register 136 . The coefficient of the Si counter register 128 is decreased, so that it is displayed that one binary image signal Si has been completely received and stored in the preceding last Si register 138. At this point in time, the preceding last signal Si becomes the next signal to the last signal Si stored in the preceding last Si register 138 and the last signal Si stored in the last Si register 136, The current Si register 134 will decimate a plurality of sample bits to derive a new signal Si from the next 8 sample bits.

The above-described sampling operation is performed regardless of whether the carrier waveform 22 shown in FIG. 1 is being received or not. Noise and other line vibrations cause high-level and low-level signals to be generated on the input line 15 in a random order. This causes random "1" and "0" to be generated in the sampling signal 43 . These will be compared for zero crossings, and their corresponding I, Q, I2 and Q2 relative phase angle vector component values are generated and added so that Ii, Qi, I2i and Q2i for each group of 8 sample beaks will cause it to be created. Synchronous detector 14 will not reach carrier detection state, where digital integrators 64-1 and 64-2 (9B) randomly provide weighted sum average values of positive and negative I2avg and Q2avg As a result, the V2avg vector RMS value will not reach the carrier detection threshold in the threshold register 163 to initiate the carrier detection signal CD. Accordingly, the following description of FIGS. 9A, 9B, and 11 will describe the synchronous detector 14 for generating the carrier signal 30 by phase-modulating the received carrier. is to receive

As long as the calculated RMS value of V2avg is lower than the carrier detection threshold, the registers of the synchronous detector 14 are restored to their initial settings, which are, for example, the Ii, Qi, I2i and Q2i registers 140, 142, 144 and 146. ) is reset, that is, by setting it to zero, and setting the counter registers 126, 128, 130 and 132 to the initial coefficients. The operation of the zero-crossing detector 46 is performed by the bit transition comparison coefficient circuit 200 (FIG. 9A), and the content of the preceding last Si register 138 is loaded into the accumulator A of the CPU 110. It starts by doing

The address of the first register of the RAN 114 in the lookup table for I and Q in the V(I, Q) lookup register 60-1 and I2 and Q2 in the V2(I2, Q2) lookup register 60-2 An offset coefficient of +7 that determines the address of the first register of the RAN 114 in the lookup table for is loaded into the index register. The eight weights stored in the RAM registers for I, Q, I2 and Q2 have been described in connection with the description of FIGS. The first address of the V(I, Q) lookup register 60-1 and the V2(I2, Q2) lookup register 60-2 corresponds to a sample count equivalent to 7 in FIGS. 5A and 5B. The last Si register 136 may store a binary value as shown in FIG. 3 for illustrative purposes. In order to compare adjacent "1" and "0" in the last Si register 136, the most significant bit b7 corresponding to the sample coefficient 7 is the last Si register 138 preceded by "1" or "0" is checked to see if it is equal to the least significant bit of The contents of the last Si register 136 are loaded into the temporary register of the RAM 114, and then the last Si register 136 is shifted by one bit to the adjacent contiguous as initially stored in the last Si register 136. Allows bits to be compared individually. Comparison is performed by the exclusive OR instruction conditional on the most significant bit b7 of both registers, and the result of the exclusive OR becomes "0" or "1" indicating that adjacent bits are different or equal. If the polarities of the sample bits in the signal Si are the same, the last Si register 136 is sequentially shifted to the left in a left rotation operation, and the preceding content of the last Si register 136 is loaded into the temporary register so that two adjacent The polarities of the sample bits are sequentially checked. Whenever two adjacent sample bits of a register are equal, the index register is a vector corresponding to the next sample count by addressing the lookup tables of I, Q, I2 and Q2 when the next adjacent sample bits are different and indicate a zero crossing. The component values are decremented to be output. The above zero-crossing operation is controlled at the machine clock frequency of the CPU 110 and occurs extremely rapidly between the gampling times of the sampling pulses 37 . The indexed addressing mode is used to specify the RAM addresses of I, Q I2 and Q2 and decrement the index register, where each of the 8 bits of the exclusive OR is checked for each signal Si and as a counter. This is done after the sample coefficients of the bit samples in each signal Si are matched with the corresponding I, Q, I2 and Q2 vector table values using the index register.

As an example described above, when the polarities of adjacent bits of the last Si register 136 are different as in the positions of sample coefficients 5 and 1 in FIG. 2) is selected. To read the I2 and Q2 vector components, the address of the lookup register 60-2 is determined by adding offset bits 10 and 11 to the address of the lookup register 60-1, which are I and Q and I2 and Let Q2 be created. After each transition determination of the sample bit, the polarity of the sample bit being compared is checked whether the polarity is negative and whether there is a negative bit sample transition. If it is a negative bit transition, the lookup table values for I and Q are negated, which is indicated by the sign inverter 204 and (Fig. 9a). The values of I and Q are applied to the Ii register 140 and the Qi register 142, respectively, and are added by the addition circuit 61 of FIG. The values of I2 and Q2 are directly accumulated in I2i registers 144 and Q2i registers 146, respectively. Therefore, by the above operation, the zero-crossing detection operation output functionally generates two sorts, one of which is a sample coefficient of a bit transition in the binary image signal Si, and the corresponding V(I, Q) and V2(I2, Q2) also indicate the direction of the transition by indicating the polarity correlated with the same coefficient to produce a lookup table value.

As described above, the index register of CPU 110 is decremented after each exclusive OR sample bit comparison operation, and if it is not zero, the above process is repeated. If the index register is equal to I and Q register address-1 in the look-up table, the zero-crossing detection operation for 8 sample bits of each binary image signal Si is finished, and the value in the last Si register 136 is Si transferred to the register. At this time, the sum of I and Q for the binary image signal Si derived from the 8 sample bits is obtained in the Ii register 140 and the Qi register 142 . Similarly, according to the above-described operation sequence, the sum of I2 and Q2 as selected from the second harmonic vector component lookup table is accumulated in the I2i register 144 and the Q2i register 146 having the I2i component and the Q2i component.

Referring to Fig. 9b, in which the signal processing described above will be generated by an initial carrier data transmission including a prefix, I2i and Q2i vector components are applied to the digital integrators 64-1 and 64-2 to detect the carrier wave. do. These digital integrators perform the low-pass filter operation and the leakage integration operation as described above to generate a weighted sum average second harmonic vector V2avg(I2avg, Q2avg) established over a carrier segment time constant of 61. The results of the digital integrators 64-1 and 64-2 are obtained in the I2avg register 148 and the Q2avg register 150 described above. The exact Ii and positive integrals of the signal Si of 16 are calculated by an approximation in which the present values of I2avg and Q2avg are substituted by the present values of I2i and Q2i plus 15/16 of the preceding I2avg and Q2avg component values. The I2i Q2i component value applied to the digital integrator typically consists of a long string of signed 8-bit binary data values with the same weighted number, such as +2, -2, or 0, with a noise-free carrier input. Therefore, in the ideal state, the I2avg and Q2avg weighted sum average values measured by the digital integrators (64-1) and (64-2) are 0, +32 or -32 for the weighted component values of I2avg and Q2avg described above. have an order

In one operation mode, the operations of the digital integrators 64-1 and 64-2 are performed in the CPU 110 by a so-called time constant operation sequence. According to the time constant operation sequence, the new value of I2 is placed in the first temporary register of RAM 114, and the contents of the high-order byte and low-order byte of I2avg are placed in respective accumulators A and B of the CPU. The values in these accumulators A and B are divided by two by four successive arithmetic shift operations to produce a value equal to 1/16 of the original value.

The index register of the CPU is used as a counter by setting it to a factor of 4, and the contents of the accumulators A and B are loaded into the first and second date and time registers. The contents of the two exact numbers of accumulators A and B are divided by two by their respective arithmetic shift operations, and the index register is decremented by one coefficient until its coefficient reaches zero. Accordingly, the content remaining in accumulators A and B becomes 1/16 of the original I2avg value loaded into the grout. The higher-order byte is stored as the new approximation divided by the sixteenth value of I2avg (I2avg/16), and the lower-order byte is stored as the remainder of the division by 16. The contents of accumulators A and B are subtracted from the contents of the first and second date and time registers. These temporary registers contain the values of the high-order byte and the low-order byte of the I2avg component value, to generate 15/16 values of the preceding and I2avg values. The new I2i component value of the third temporary register in the RAM 114 is added to the operation described last, and is approximately equal to 15/16 of the I2i component value and the last I2avg value added among the new high-order byte and low-order byte data words. causes a new I2avg component value to be created in The new values in accumulators A and B are loaded into the two RAM registers of the I2avg register 148, and the higher order byte provides the I2avg component that is also used in the sync detector 14. The above operation is repeated to derive the appropriate Q2avg component value, so that each new value of its new Q2i value plus 15/16 of the last Q2avg value is stored in the I2avgRK I2avg register 148, and so on. It is written to the Q2avg register 150 .

As described above, since ambiguity occurs during vector division, the sign of the new Q2avg must be checked so that ambiguity due to vector division is avoided.

The Q2avg component value actually passes through the ±180° reference axis. Therefore, the above-described operation sequence continues the subsequent calculation of the new Q2avg component value, so that it is determined whether I2avg is greater than 0, that is, whether it is a positive number in the sign comparator 210 (FIG. 9B). is stored, and if negative, the preceding Q2avg component value in the contents of the Q2avg register 156 is stored again. If the sign polarity of the selected Q2avg component value and the current Q2avg component value are different, the result obtained by dividing the two reference phase angle vectors VR(IR, QR) is calculated by the vector angle divider 70 (Fig. 9b). When derived from the values of I2avg and Q2avg, the flag bit indicates that the binary state of the flip-flop 1 register 162 is complemented, as indicated by the output line 212 from the sign comparator 210 (Fig. 9b). it is set to

Although the operation results of the digital integrators 64-1 and 64-2 have been described so far, the operation of the carrier detector 66 shown in FIG. 2 will be described below. The carrier detector 66 includes a V2avg vector calculation circuit 220 and a threshold comparator 224 as shown in FIG. 9B. The carrier detection operation is accomplished by calculating the effective RMS value of the vector expressed by the component values of I2avg and Q2avg or the size of the vector. The calculated V2avg value is an approximation of the square root of the sum of the squares of the absolute values of I2avg and Q2avg, so that the measured value of the V2avg vector can be effectively measured. This approximation is done by taking the absolute value of the larger of the I2avg and Q2avg component values and adding half the absolute value of the smaller one. The above-described operation is performed by loading the Q2avg and I2avg component values into the accumulators A and B. The absolute value of the contents of accumulators A and B is performed by negating their contents if it is judged that their contents are negative. The contents of accumulator B are compared with the contents of accumulator A to determine whether it is greater or not. If it is greater, the contents of accumulator A are divided by 2, if not large, the contents of accumulator B are divided by 2 lose After this, the contents of accumulators A and B are added to each other. It is worth noting that in this operation, only the higher-order bytes of the I2avg and Q2avg component values are processed, resulting in an approximation of V2avg.

The calculated V2avg value from the V2avg vector calculation circuit 220 is compared with the content value of the threshold value register 163 . This value is a 4-bit binary number equivalent to a number about base 10 of about 9 or 10. The threshold value is about 1/3 of the theoretical approximate maximum value of 32 ideally reached by the digital direct operation described above. If the approximate VI2avg vector value is lower than the threshold value in the threshold value comparator 224, the carrier detection state is not reached. The plurality of bit sync counter registers and storage registers currently set the M-SUM storage register 172 to 0, set the data bit counter register 130 to 4, and set the maximum M-SUM storage register 190 to 0. Initial setting again by setting the M storage registers 181 to 184 and the M-SUM storage registers 185 to 188 to 0 and clearing the register for generating the carrier detection signal CD to 0. If the single computed V2avg vector value is greater than the threshold in the threshold comparator 224, the carrier detection signal CD is set to provide a logical indication of carrier detection for the reception of a plurality of carrier signals 30. The carrier detection signal CD MDL "1" also causes the above registers to perform a bit synchronization operation, which will be described later.

Referring to the vector angle divider 70 of FIG. 9B, the IR component and the QR component of the reference phase angle vector VR are calculated by the half angle division operation expressed by the vector angle divider. As described above with respect to the description of FIG. 8, the component values of IR and QR are calculated from the I2avg and Q2avg vector component values. In this case, the phase angle of the vector V2avg(I2avg , Q2avg ) will lie in the range between -180° and +180° or the actual one carrier and segment represented by the number in Fig. 11a, and the VR(IR, QR) vector is The first upper limit and the fourth upper limit, and the eight 45° segments represented by the numbers in FIG. 11b are preselected. The 45° segment is a half-angle segment corresponding to the eighth segment of the equal sign of FIG. 11B. The V2avg(I2avg, Q2avg) vector is halved so that the equivalent angle of the VR(IR, QR) vector emerges from the I2avg and Q2avg components, and the calculated angles and magnitudes of the I2avg and Q2avg component values of the resulting component values. Provides IR and QR component values as found from the information. Also, as described below, the IR and QR values are in the range of 0 to 32. Thus, the reference vectors VR(IR, QR) are in the -180° plain and +180° planes of FIGS. 8 and 11b.

The vector division operation sequence of the CPU 110 calculates the half frequency or half the angle of the V2avg (I2avg, Q2avg) vector located in the plane of the circle divided into 8 equal segments shown in FIG. It provides an approximation to generate the corresponding opiate vector. The order of calculation of the vector divider 70 begins by taking the I2avg component and the Q2avg component, and actually defining the corresponding V2avg vector, and then determining which octal segment in Fig. 11a it is in. The component values of I2avg and Q2avg are loaded from I2avg register 148 and Q2avg register 150 into accumulators A and B, respectively. The first decision step in the operation sequence is to compare whether the value of Q2avg in accumulator B is greater than the content of I2avg in accumulator A. is in a semicircular plane consisting of If Q2avg is greater than I2avg, the content of accumulator B is negated, and a separate decision is made to determine whether the newly negated content of accumulator B is greater than that of accumulator A, so that the vector V2avg is divided into eight segments and or and is determined. In this case, if so, the IR component is equivalent to the contents of accumulator A, and the QR component is equivalent to half of the negated value of accumulator B. Accordingly, the approximate half-angle of the I2avg component defining the V2avg vector in the eighth segments 1 and 8 in Fig. 11a is converted into the approximate IR and QR components defining the VR factor in the segments 1 and 8 in Fig. 11a. If, by the latter comparison of accumulators B and A, it is determined that the negated Q2vag component value of accumulator B is greater than the I2avg content of accumulator A, the contents of accumulator A are divided by 2, and the IR component is the contents of accumulator A and accumulator B It is equal to the sum of the contents of , and the QR component is equal to the value obtained by subtracting the contents of accumulator B from the contents of accumulator A. Accordingly, the vector V2avg (I2avg, Q2avg) is in the eighth segment and in Fig. 11a, and is converted into the approximate IR and QR components defining the VR vector in the segments and in Fig. 11b.

If it is judged by the original comparison that the content of the Q2avg value of accumulator B is greater than the content of I2avg of accumulator A, the V2avg vector is in the semi-carrier plane including segments , , and in Fig. 11a. The I2avg component value of accumulator A is negated, and the content of the Q2avg value of accumulator B is compared to determine whether it is greater than the content of the newly negated I2avg value of accumulator A. If the Q2avg value is larger, the angle of Q2avg and the I2avg value content of accumulator A in the eight segments and becomes equal to the content of accumulator A -1/2, and the IR component is the content of accumulator B and the content of accumulator A It is set equal to the sum of the contents, and the QR component is equal to the contents of accumulator B minus the contents of accumulator A. Accordingly, the approximate IR and QR component values of the corresponding VR vectors are defined in the segments 2 and 3 in Fig. 11B. If the results of the last comparison judge that the content of the Q2avg component of accumulator B is greater than the content of the I2avg component of accumulator A, the angle of V2avg is within segments and (adjacent to the +90° axis and -90° axis). and whether the content of the Q2avg component of accumulator B is greater than 0, if so, it is judged by the last comparison that the QR component is the same as the content of accumulator A and the IR component is not greater than 0 , the contents of the accumulator ADML SODYD ALC accumulator B are negated, and the QR component defines the approximate IR and QR components in the segment the same as the contents of the accumulator A. The values determined as described above for the IR component and QR component are transmitted from the accumulator A or B to the IR register 158 and the QR register 160 shown in FIG. 9B.

As is clear from the description given above with respect to Fig. 9b, the phase angle vector Vi(Ii, Qi) is derived from a single binary image signal Si, and the reference vector VR(IR, QR) is 16 binary image signals Si respond to the weighted sum average of The Ii component and the IR component are applied to a multiplier 216, and the Qi component and the QR component are applied to a multiplier 218, which multipliers are in the phase detector 76 described above. Quadrant multiplication loads the contents of the Ii register 140 into the accumulator A and the IR register 158 into the accumulator B, so that the Ii component and the IR component are multiplied by multiplying the contents of these accumulators. This is done in the gold CPU 110 . The progress of the multiplication is loaded into the temporary register of the RAM. Similarly, the contents of the Qi register 142 and the QR register 160 are loaded into accumulators A and B, respectively, and multiplied, and the result is stored in either of the accumulators A and B, and Ii X the small date and time of the IR multiplication It is transferred from the register to the remainder of the multiplier. The sum of the two accumulators A and B is obtained by adding the contents of the two multipliers in the addition circuit 248 . The contents of the addition result by the addition circuit 248 are passed or inverted by the code inverter 244 in the case of the same code under the control of the flip-flop 1 register 162 to cause the correlation signal 77 to be generated. . The correlation signal (77) is stored in the phase detector output storage register (164). The correlation signal 77 of +M or -M in the output line 250 is in phase (180°) with the reference vector VR(IR, QR) and the vector Vi (Ii, Qi) as described above. It is a 2-bit data word signal having the above-mentioned sign having a relatively large numerical value.

How is a binary image signal Si composed of a single carrier and segment converted into a relative phase angle vector Vi(Ii, Qi) representing a partial measurement value of the phase-modulated carrier data bits, and representing a carrier segment of four carrier data bits How the reference vector VR signal and the Vi signal derived by the effective smooth filtering of the phase angle are correlated has been described above. The remainder of the synchronization detector 14 is shown in Fig. 9c, which properly matches the correlated signals 77:±M, the output from the phase detector 76, for each carrier segment so that the synchronization of the data bits is determined. It shows the operation of grouping, then resolving the ambiguity of the data bit code and correlating it so that the logical state of the data bit signal is reproduced. It is assumed that the initial operation of the synchronization detector 14 has already detected a carrier, and that the carrier detection logic signal CD has already been started before synchronization of the data bits. The data bit counter register 130 of FIG. 9A starts counting from a factor of 5 during the time following the carrier detection noise signal CD, and is decremented by 1 for every 32 sampling pulses included in the carrier data bits. Thus, the above-described correlation signal 77 shown on output line 250 in FIG. 9C is binary data signed in two's complement, the magnitude of which is scaled for proper handling within CPU 110. and is related to the above-described outlier for the purpose of explanation. In order to explain the operation of FIG. 9C, each of the plurality of correlation signals 77 output from the phase detector 76 is represented by a sign of + or - prefixed to the signal M as described above. A plurality of correlation signals (±M) are sequentially loaded into the M memory registers 181 to 184. The contents of these M registers are added to each new correlation signal 77 output from the phase detector 76, and the resulting M-SUM is stored in the M-SUM register 176. When adding the contents of the four M storage registers 181 to 184, the index register in the CPU 110 is used as a counter and a pointer to the RAM addresses of the M storage registers 181 to 184. The value of the first ±M correlation signal 7 from the M memory 1 register 181 is loaded into the accumulator A, and the content value of the accumulator A is added to the value of the following ±M correlation signal 77. Each addition operation decrements the index counter until the addresses of all M storage registers 181 to 184 are determined and their sum is stored in the M-SUM register 176.

The contents of the M-SUM register 176 are loaded into the accumulator A and the absolute value of the M-SUM is obtained by the M-SUM absolute value circuit 256 . The absolute value of M-SUM is loaded into one of the M-SUM storage registers 185 to 188. These M-SUM storage registers 185 to 188 are respectively loaded with new values of the M-SUM signals 8, so that after the first group of four ±M correlation signals 77, each correlation signal is M It is stored in one of the storage registers 181 to 184, and is stored in the four M-SUM storage registers 185 to 188 as the M-SUM value increases after the sum of absolute values is added to the preceding total sum of absolute values. make it possible Also using the index register addressing mode in the CPU 110, one M-SUM storage register having the maximum value among the M-SUM storage registers 185 to 188 is determined by the maximum M-SUM comparator 190, The sum sequence counter register 132 shown in Fig. 9a is initially set to a coefficient of 0, and then is incremented by one by a new coefficient for the new binary image signals Si, and when the coefficient 0 is reached, one carrier data bit indicates the end of The operation of setting the sum sequence counter register 132 to 0 is performed by the maximum M-SUM comparator 190 sending a logic signal to the reset input line of the sum sequence counter register 132 through the reset logic gate 266. is shown

The reset logic gate 266 is enabled by the output of the three-dimensional value comparator 268 . As described above, the solid value comparator 268 disables the resetting of the sum sequence counter register 132 after a predetermined threshold value of the solid value register 270 is reached. Accordingly, several data bit periods after the transmission wave detection are available for data bit synchronization.

The sum sequence counter register 132 is in a synchronous count cycle, and is continuously incremented from a count 0 to a count 3 for each group consisting of four ±M correlation signals 77 . The coefficients 0 to 3 are offset from the four coefficients of the Si counter register 128 .

10 is a diagram for another ion diagram for the synchronous operation of data bits. marked, the corresponding absolute value of the M-SUM signal 87 is stored in the M-SUM storage registers 185-188. The reason is that a series of values of the +M and -M correlation signals 77 from the phase detector output attempted in the third row from the top of FIG. 10 occurring at time points T1 to T10 are processed. The time graph of FIG. 10 also shows "1", "0" and "1" of the carrier data bits, which are +M or -M at the corresponding time points in some exemplary modes of operation of the synchronous detector 14. A corresponding time graph of the coefficient Cis of the Si counter register 128 and the coefficient Css of the total sequence counter register 132 is also shown in FIG. 10 .

Each of the M storage registers 181 to 184 and the M-SUM storage register 185 to 188 receives the initial value underlined in Fig. 10, and then continues with the same value during the subsequent three times of the stored value of the register. do. At the time point T1, the associated +M value is loaded into the M memory register 181 . The sum of the preceding three register values will be zero so that the M-SUM value M of FIG. 1 is loaded into the M-SUM storage register 185 . Since this is the first maximum it is loaded into the maximum M-SUM comparator 190 and the sum sequence counter register 132 is reset. At another time point T6, a -M value is loaded into the storage register 182 instead of the +M value loaded at the time point T2. The M-SUM value at time point T6 has 4M as a signed absolute sum of ±M occurring at time points T6, T5, T4, and T3, which is added to the sum of 2M stored in the memory register 186, so that a new The maximum M-SUM of 6M is to be provided at this point T6. Therefore, if the sum sequence counter register 132 is not reset, it will be reset at time T6, and the value of the maximum M-SUM storage register 260 will be equal to the value of the storage register 186 . As is apparent from comparing the 2nd and 3rd rows from the top of Fig. 10 with the count of 0 of the sum sequence counter register 132, the correlation signal 77 of four equal signs +M or -M is one carrier data bit. Grouped as a period, the M-SUM value generated at the count 0 of the comprehensive sequence counter register 132 is the ±M-SUM correlation sum signal 87 for f data bits, and the count 0 marks the end of the data bit period. indicates. Therefore, whenever the count 0 of the signal Css from the sum sequence register 132 starts, the M-SUM signal is put into the storage register 186 . The ±1 relative values for the unit values of +M and -M in Fig. 10 are actually approximate, since, when exemplifying a plurality of M-SUM values, their respective large positive or negative values. It can be seen that the memory register 186 has a size that increases more rapidly than the other three memory registers 185, 187, and 188. The above operation continues until the maximum M-SUM reaches a predetermined threshold as shown in threshold comparator 268 . This terminates the synchronization of the data bits, which occurs prior to the data bits of the tenth and eleventh carrier prefixes being processed for polarity indication.

As described above, the data bit counter register 130 is decremented by a factor of one, during which time synchronization of data bits is achieved, and the current Si register 134 is fixed to establish synchronization of data bits; Each suitable group of four ±M correlation signals 77 is followed so that the ±M-SUM value of the correlation sum signal 87 contained in one data bit is defined.

The operation of the data bit encoding image 92 will be described with reference to FIG. 9c. As described above, at the beginning of the program operation sequence in the CPU 110, it is determined whether or not the count of the data bit counter register 130 reaches zero by following the Si counter register 128 and reaching a decision range. If it is judged that the single coefficient has not reached zero, the above-described operation sequence is performed among the preceding five data bits of the prefix following the detection of the carrier so that the carrier is synchronized by the generation of the binary image signal Si. and also allows the synchronization of data bits to be established as described above. If the count of the denitor bit counter register 130 reaches the count 0 through the count 1 indicated by Cdbl, the sign of the contents of the current M-SUM register 172 and the last M-SUM register 174 A sequence of comparison operations for comparing the sign of the content with the sign of the last M-SUM register 172 content is enabled. These M-SUM registers 172 and 174 store the M-SUM of the last two data bits received. Since these M-SUMs are signed binary numbers, the most significant bit (MSB) b7 of each of the M-SUM registers 172 and 174 is compared to determine if they are equal, to indicate the two double polarities of the prefix. The data bit indicates that the tenth data bit and the eleventh data bit have been reached. If both signs are the same, they are effective to operate the flip-flop top 2 register 178 . Logic gate 274-1 responds to the gate enable signal Cdcl, which is started when data bit counter register 130 reaches count 1, the two bits 7 sign bit of M-SUM registers 172 and 174. Indicates gating of values. Two common sign bits are stored in the M-SUM registers 172 and 174, and the flip-flop two registers 178 are set to the same state as the logic state of the common sign bit. The data bit-sign correlator 92 determines the high-level and low-level logic states of the binary data signal 32 in which the sign of the correlation sum signal 87 occurs when data bits of 1 and 0 occur in the received carrier segment. make it happen for sure.

If both M-SUM sign bits are negative, that is, "1", flip-flop 2 register 178 is set to "1". If both M-SUM sign bits are positive, that is, "0" indicates that MSB b7="0"), flip-flop 2 register 178 is set to "0", and the current M-SUM register is Output from 172 provides positive, i.e., data bit "1" polarity to output line 32 as is the case among current M-SUM registers 172. The sign comparator 274-2 starts the reset logic gate 274-3 so that the data bit counter register 130 is decremented, and as a result, the data bit counter 130 is set to a value and It indicates that the eleventh data bit has been processed, indicates that the data bit synchronization and data bit sign correlation operations have been completed, and indicates that each other bit of the transmitted data and the transmitted data is part of the message data bit information to be received. Accordingly, the data bit counter register 130 is also used as the sync detector status flag register. The initial synchronization state of the synchronization detector is fixed and is also preserved over the processing period of the remaining message data transmitted to the synchronization detector.

When the data output circuit 96 is provided in the microcomputer system 108 during the reception of the carrier wave modulated message data, the carrier wave signal 30 is sampled as described above, so that one carrier wave segment and one data bit period are Eight sample bits representing one waveform sample derived from the transmitted wave signal 30 occurring during /4 are defined. A corresponding relative phase angle vector Vi(Ii, Qi) is generated for each of a group consisting of 8 sample bits and a reference vector VR(IR, QR) is generated during the period of 16 carrier segments, resulting in the occurrence of these carrier segments. It changes gradually according to the deviation or change of the phase angle vector display. The output line 78 of the phase detector 76 has a ±M correlation signal 77 for each of the generated phase angle vectors Vi(Ii, Qi), as controlled by the sum sequence counter register 132. It starts to add up with the carrier bit. The flip-flop 2 register 178 is fixed throughout the received data message so that the sign of the correlation sum signal 87 is correlated with the phases of "1" and "0" of the data bits in the carrier message data. . Accordingly, the sign of the correlation sum signal 87 provides high-level and low-level binary states in the synchronously detected data signal for "1" and "0" of each data bit received.

In order to perform the data mitt correlation operation as described above, the CPU 110 checks the sum sequence counter register 132, and a negative value is a mode for the synchronization detector 14 to process the message data bits to the output line. indicates that The signed M-SUM signal 87 in the current M-SUM register 172 is loaded into the accumulator B of the CPU 110 . The logic state of the flip-flop 2 register 78 is checked by being set in the M-SUM signal at the time of the polarity indication bit. If the sign logic state of the M-SUM signal 87 and the flip-flop 2 register 178 are different, the contents of the accumulator B are complemented, and if they are identical, the contents of the accumulator B do not change. This provides the equivalent logical state of the exclusive OR state during databit sign correlation for the two's complement signed binary dataword of the current M-SUM register 172. Accordingly, the most significant bit b7 of the M-SUM signal 87 generates a binary state in the binary data signal 32 . The data I/O port 118 is initially set to output the binary data signal 32 to the output line 36, so that "1" on the input line to the data I/O port 118 is the binary data signal. (32) causes a high-level state. Accordingly, the high voltage state and the low voltage state in the output line 36 are MSB b7 of the M-SUM signal 87, that is, the respective sign bit "0" when the flip-top 2 register 178 is set to "0". and "1". This is done in the microcomputer system 108 .

The abnormal operation of the synchronous detector 14 has been described in terms of an ideal error-free operation in fact. In practical operation, the non-noise of the frequency shift of the sampling pulse 37 with respect to the phase of the received carrier in the carrier signal 30 sometimes produces phase changes among the group of sample bit signals derived from the relevant carrier segment, so that the carrier wave Segments cannot always result in 4 bit samples "0" and 4 bit samples "1" for each segment as shown in FIG. For example, 5 or 6 certain sample bit polarities and 3 or 2 different sample bit polarities may occur in one group of 8 sample bits forming the binary image signal Si. Accordingly, the relative phase angle vector Vi(Ii, Qi) signal represents a phase angle vector of in-phase or inverse phase (180°) with respect to the preceding Vi(Ii, Qi) signal. The preceding Vi(IR, QR) signal coincides with the reference vector represented by the VR(IR, QR) signal or the vector of the inverse phase. The ±M correlation signal 77 from the phase detector 76 has a very small sign value of the same sign polarity of another ±M correlation signal 77 of the same data bit or a large sign value of the opposite polarity.

The effect on the VR(IR, QR) vector signal is minor because each new binary image signal Si only contributes to 1/16 of the (VR(IR, QR) signal. Even if the correlation signal 77 has an opposite sign to the other three ±M correlation signals related to the same data bit, the three correlation signals of the common code and the code matching the binary logic state of the detected related broadcast data bits are The sign of the numerical value obtained from trailing the appended ±M -SUM signal 77 is provided to the detected polarity synchronous detector 14 indicating the associated logical state of the received carrier data bits. Although this description is an example of compensation for an erroneous change in the ±M correlation signal 77, the synchronous detector 14 receives the VR(IR,QR) signal as the changing angle indication of the sampling period and carrier of the sampling pulse 37. By slowly changing it, the audience ±M correlation signal 77 having a ±M -SUM value of the correlation sum signal 87 is continuously generated, which is a mutual inverse representing 1 and 0 data bit information. Shows a high degree of correlation with one of the carrier states of polarity. The end of the carrier data transmission is detected in the synchronization detector 14 by the carrier detection loss, which causes the carrier detection logic signal to be reset to "0". The above-described storage register and counter register controlled by the carrier detection logic signal are reset, and the synchronous detector 14 successively samples the receiver output so that another carrier transmission is detected, and at the same time, the above-described initial setting synchronous operation, the sign The correlation operation and the data synchronization detection operation are repeated.