Island matrixed gallium nitride microwave and power switching transistors

ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates generally to gallium nitride transistors, and more particularly to methods for improving performance and improving yields related thereto.

Gallium nitride materials include gallium nitride and alloys thereof such as aluminum gallium nitride, indium gallium nitride, and aluminum indium gallium nitride. These materials are semiconductor compounds with a relatively wide, direct bandgap that allows high-energy electronic transitions to occur. Gallium nitride materials have many attractive properties, including high electron mobility, the ability to efficiently emit blue light, and the ability to transmit signals at high frequencies, among others. Accordingly, gallium nitride materials are being investigated in a number of microelectronic applications such as transistors and optoelectronic devices.

Despite the attractive properties described above, there are many challenges associated with developing devices based on gallium nitride materials. For example, it can be difficult to grow high quality gallium nitride materials on certain substrates, particularly silicon, due to differences in properties (eg, lattice constant and coefficient of thermal expansion) between gallium nitride and substrate materials. Additionally, it has been challenging to form gallium nitride materials that meet the cost requirements for specific applications.

High and medium power gallium nitride microwave transistors are currently available, all types using multifinger structures. Some power switching devices described in the research literature also use multifinger structures. Alternative novel matrix island based structures are shown herein, which provide significant advantages for all switching applications. Following implementation of all power transistors, the structures are optimized for grounded source circuit applications where it is desirable to minimize the inductance and resistance of the source connection. To this end, transistors typically consist of a series of via connections that subtend the entire vertical structure. Those that typically use through-substrate via connections are difficult to manufacture and control. To reach an area where fewer large vias can be fabricated, an air bridge would have to be constructed from each of the source connections. See, eg, US Pat. No. 7,352,016 B2. However, air bridges are a source of manufacturing and handling problems.

U.S. Patent 7,550,821 B2 (Shibata et al.) discloses a nitride semiconductor with an air bridge removed. A plurality of first electrodes and a plurality of second electrodes are formed (spaced from each other) on an active region in the nitride semiconductor layer (formed on the major surface of the substrate). An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings for individually exposing the first electrodes, and has a planarized upper surface. The first electrode pad is formed in a region above the active region in the interlayer insulating film, and is electrically connected to the exposed first electrode through individual openings. Source-substrate contacts (short vias) are disposed adjacent to the active region and directly connected to the source electrode, but there is a disadvantage of increasing the area within the multi-finger structure. Therefore, the nitride semiconductor device of Shibata et al. is also limited by the high on-resistance typical of power switching transistors using conventional multi-finger structures.

U.S. Patent 7,250,641 B2 (Saito et al.) discloses a silicon substrate, a first aluminum gallium nitride layer formed as a channel layer on the silicon substrate in an island shape, and a first conductivity type or i- on the first aluminum gallium nitride layer A nitride semiconductor device comprising a second aluminum gallium nitride layer formed of a tangible barrier layer is disclosed. The islands disclosed herein are completely isolated from each other with no common gate electrode between them, so each island is a separate device. The embodiments disclosed by Saito et al. (eg, as in FIG. 1 ) require a juxtaposition of three source electrodes island-to-island. The island concept disclosed by Saito et al. only provides for the separation of isolated devices, ie there is no intrinsic mode of operation induced between the islands.

The novel topology described herein eliminates the source connecting air bridge and allows the gate electrode to be tracked in up to two additional directions, resulting in a 1.5 to 5 fold reduction in on-resistance compared to conventional multifinger structures. cause In this way, the large area requirement of the ladder (or multi-finger structure) is eliminated.

Some examples of the present invention may be based on relatively complex silicon-based templates. However, with the new island-based surface topology, this greatly simplifies the costly gallium nitride device processing steps.

<p>The invention will be first described in terms of its overall form, and then its implementation in terms of specific design will be described hereinafter. These examples are intended to explain the principles of the invention and methods of its practice.</p><p>The present invention eliminates air bridges that are well known to make power transistor fabrication and handling difficult. Both the old gallium arsenide devices and the new gallium nitride devices suffer from yield losses. The present invention provides a topology in which one implementation uses multiple small short vias making an air bridge or through-substrate source electrode via connection mechanism unnecessary. The source and drain are fabricated to consist of only islands downsized enough to allow positioning of the ball grid and/or via grid within the respective source and drain. By this unique means, the air bridge as well as the couplings are eliminated.</p><p>According to one aspect of the present invention, a substrate, a nitride semiconductor layer formed on a major surface of the substrate, and a nitride semiconductor layer spaced apart from each other to be alternately arranged to create a two-dimensional active region within all feasible regions of the nitride semiconductor layer. A plurality of first island electrodes and a plurality of second island electrodes are formed in the region between each first island electrode and each second island electrode on the nitride semiconductor layer, and serve as a gate electrode of a multi-island field effect transistor. a plurality of strip electrodes each having a plurality of strip electrodes, each of which is one of a drain electrode or a source electrode of a field effect transistor, and a plurality of strip electrodes each having a source electrode and a ball connection on the surface of each drain electrode A nitride semiconductor device comprising a ball connection is provided. The substrate is conductive, and the ball connections on the surface of each source electrode can be replaced by vias. The ball joint is preferably formed of gold, while the nitride semiconductor layer is preferably a hetero layer consisting of a layer of undoped gallium nitride under a layer of undoped aluminum gallium nitride.</p><p>Each of the island electrodes preferably has a rectangular shape, or preferably a triangular shape. Alternatively, the islands may be a combination of various variations of polygonal shape allowing for drain/source juxtaposition. Each gate electrode is preferably attached to the gate pad using a low resistance means such as but not limited to a metal strap. Additionally, the nitride semiconductor device may further include one or more epitaxial layers between the substrate and the nitride semiconductor layer. Each epitaxial layer is lightly doped. Field plates may be embedded in the epitaxial layers.</p><p>In the present invention, the source island electrodes are always arranged in parallel with the drain island electrodes, and there is always a gate therebetween.</p><p>If it is desired to use an insulating substrate, the via can be removed and replaced by the same ball grid used for the drain island. If the islands are tetragonal with two-fold or four-fold symmetry, respectively, this allows the gate to run in two directions, and if the islands are triangular the gate can run in three directions. Consequently, the gate track can be much larger for a given dice size. The multi-finger structure may be eliminated, and an island may be formed with only the source and drain.</p><p>The island topologies disclosed herein, preferably triangular or rectangular island structures, offer many advantages over conventional multifinger or interdigitated structures. This island topology results in a non-transistor resistance of less than 70% of that achieved by an equivalent area multifinger layout. More significantly, the overall effective device area ratio is 3-5 times superior due to the reduced face interconnect and pad requirements.</p><p>The present invention provides a device having a large gate width (or "Wg") within a given active region. In certain exemplary embodiments, the topology provides a significant increase in current handling capability per unit device area overall and not just within the active area. Additionally, a simple process for fabricating GaN semiconductor devices of extreme capability is provided.</p><p>Another inventive aspect of the invention relates to the design of field plates embedded in various epitaxial layers. Since a silicon conductive substrate will cause an unwanted increase in the capacitance of the active region, epitaxial layers of lightly doped single, double, or series (lightly doped) intrinsic silicon material can be grown on the substrate. The thickness of this layer or of these layers may be variable, and an embedded conductive layer or series of layers may be inserted to act as an embedded field plate. Multiple field plates of various sizes and shapes may be introduced. These field plates increase the maximum voltage the transistor can withstand by reducing the peak electric field near the gate edge in parallel with the drain. Additionally, these field plates can be arranged to provide a very uniform distribution of electrical stress between the gate edge and the drain edge. Independent and exceptional linear or very high voltage devices can be manufactured. The novel perpendicular epitaxial silicon-based structure may also assist with problems related to mechanical stress caused by the difference between the thermal expansion of silicon and gallium nitride.</p><p>The foregoing and other aspects of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings.</p><p>Where ranges of values are recited in this specification, sub-ranges therein are intended to be included within the scope of the invention unless otherwise indicated. When features are due to one or another variant of the invention, unless otherwise indicated, these features apply to all other variants of the invention provided these features are consistent with or compatible with such other variants. it is intended to be</p><p>The foregoing is provided by way of example only and should not be construed as limiting the present invention. Many obvious modifications are possible without departing from the spirit and scope of the invention.</p>

1 shows a plan view of an example of a prior art building block structure; 2 shows a plan view of an embodiment of the present invention. Fig. 3 shows a cross-sectional view taken along line I-I' in Fig. 2; Fig. 4 shows a top view of the embodiment shown in Fig. 2; 5 shows a plan view of a second embodiment of the present invention. 6 shows a plan view of a third embodiment of the present invention. Fig. 7 shows the packaging of the embodiment shown in Fig. 4;

DETAILED DESCRIPTION In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof and which schematically show specific embodiments in which the invention may be practiced. In the drawings, like reference numbers indicate substantially similar elements in various directions. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. As used in the detailed description that follows, the terms wafer template and substrate include any structure having an exposed surface on which the circuit structure of the present invention is formed. The term substrate or template is understood to include semiconductor wafers. The term substrate or template is also used to refer to the semiconductor structure being processed and may include other layers already constructed thereon. Wafers, templates and substrates include doped and undoped semiconductors, epitaxial semiconductor layers supported by base semiconductors or insulators, as well as other semiconductor structures well known to those skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the material referred to as a conductor. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the invention is defined solely by the appended claims, along with the full scope of equivalents given therein.

The accompanying drawings are conceptual and are not drawn to scale. For the sake of clarity, not all components in each figure are assigned a name. All patent applications and patents incorporated herein by reference are hereby incorporated by reference in their entirety. In case of conflict, this specification, including definitions, will control.

The field of the present invention relates generally to high and medium power gallium nitride transistors. More particularly, the present invention relates to transistors operating at high temperatures with thermal gradients that impair performance of large gallium nitride devices. The connection system for each source and/or drain includes a separate heat sink. Since all large gallium nitride transistors have multiple source/drain electrodes, the concept described compensates for each source and drain connection being resistively and thermally isolated depending on the specific location of these connections in the overall complex structure of the transistor. allow it to be

When the base substrate is heavily doped, small, short vias can provide a low resistance connection to the backside of the wafer. The wafer doping level can be selected to tailor the resistance according to the specific needs of any type of transistor. Highly doped wafers allow the formation of positive temperature coefficient resistors that operate reliably over a temperature range extending up to 600°K. plus temperature coefficient is 10E16cm^-3 to 10E18cm^-3 Using a wafer doping level of between 0.11% per °K and 1.1% per °K can be selected. Small, short vias may vary in length, depth and/or width to provide appropriate compensation.

Alternatively, if short-term operation at very high temperatures (above 600°K) and very good performance is desired, the resistor temperature coefficients may be selected to reach at least 10% of their room temperature value. Operation in this alternative mode would confront the natural tendency of gallium nitride devices to degrade their performance at higher temperatures. The transition temperature from a positive temperature coefficient to a negative temperature coefficient may be selected between 600°K and 900°K. Although this negative temperature coefficient of resistance is generally not useful, it is possible to use gold or other suitable dopant to achieve a negative temperature coefficient. New structures and layouts can be used and suitably employed to provide series source resistors with negative temperature coefficients. Thus, it is possible to fabricate a gallium nitride transistor based on the concept proposed herein that exhibits very stable performance over a wide temperature range from less than 300°K to over 600°K. A very simple bias method and very stable, linear performance can be obtained. However, device design difficulties culminate in balancing the positive effect of reducing source resistance against the decreasing performance of conventional intrinsic gallium nitride transistors with increasing temperature.

In addition to the novel lateral topological contributions described above, the vertical arrangement described herein has an aspect that significantly contributes to the performance of the fabricated transistors. Heavily doped substrates are known to have disadvantages related to drain-source and channel-source capacitances. This high capacitance results from the fact that the substrate acts as one plate of the capacitor. To mitigate this effect, very lightly doped substrates have conventionally been used. However, some designs described herein require a heavily doped bulk substrate. To reduce the capacitive effect, another aspect of the vertical structure proposed herein includes novelly a series of epitaxial or very lightly doped epitaxial layers grown on the substrate in such a way that an ideal interfacial structure is maintained. Process steps involving an epitaxial layer or layers are important because subsequent process steps involve difficulties associated with great difficulty in terms of the coefficient of expansion and lattice constant (17%) between gallium nitride and silicon. The present invention provides a strained layer super lattice capable of assisting the further growth of a GaN/AlGaN heterolayer. A high quality GaN/AlGaN heterolayer can be grown across an epitaxial layer or layers by interposing a GaN AIN superlattice over an AIN buffer layer grown directly on the epitaxial layer or layers. The epitaxial layer or layers may be grown to extend over a thickness range of, for example, 3-20 μm. When microwave transistors are fabricated, smaller capacitances are preferred, as smaller capacitances can be selected as part of the required matching network. However, this will require the capacitance to be minimal and the required epitaxial layer thickness to be maximal. The 20 μm dimension can be extended to further reduce the capacitance.

It is known that it is important to reduce the electric field stress at the gate edge. It has become common practice to extend the drain side of the gate edge over SiN or other surface passivation. In some implementations, devices with a drain-gate spacing of 2.5 μm have a surface field plate extending 1.0 μm from the gate to the drain. This extension results in unwanted gate-drain feedback capacitance. This significantly reduces the gain of the device. An alternative concept involves a metal field plate coupled to the source and disposed over the gate. The novel proposed structure described herein employs a source connected to a buried layer extending under the gate to the opposite (or behind) gate edge of the drain. An additional gain in field stress reduction results from the conductive substrate beneath the epitaxial layer. When several are used, each or any epitaxial layer includes a buried layer that acts as a field plate under the gate. The buried field plate or combination of plates and a conductive substrate alleviates the absolute need for a field plate provided on a metal surface. The combination of the surface field plate and the proposed buried field plate will provide very high breakdown voltage performance. If the epitaxial layer is thin, it is possible that the buried layer field plate is not required, which simplifies the process. A choice can be made between a reduction in drain-source capacitance or alternatively a reduction in field stress, resulting in an ideal epitaxial thickness for each transistor application.

The reduced peak electric field for the transistor device of the present invention compared to a simple transistor device results from reduced field crowding at the drain side of the gate electrode. This reduction contributes to the single or combined effect of the novel field plate acting to provide the same or additional stress reduction that the surface field plate provides. Stress reduction results in improved electrical performance characteristics, including increased operating voltage and/or reduced gate leakage current.

Gallium nitride has a different crystal structure from silicon, and when the gallium nitride structure is formed on a silicon substrate, dislocation may occur. Defects and dislocations in the vicinity of the active region can severely impair device performance. Due to the novel layout style of the proposed devices, it is possible to electrically isolate defective individual transistors and remove them from the main structure. One or both of the gate connection or the drain connection of the defective device may be disconnected. In the particular case of normally-off transistors, simply disconnecting the gate electrode may be sufficient. The disconnect mechanism may be based on a fuse or laser methodology. It may additionally be necessary to ground the gate electrode to the source electrode due to leakage current or the involved capacitive coupling. Metal-to-metal short circuits can be achieved with high-energy lasers.

In the conventional design used in the prior art ( FIG. 1 ), the source electrode 100 is connected to the source pad 130 by an air bridge 125 , which is further connected by a large via 135 . do. As shown, the drain electrode 120 is connected to the common drain pad 105 , and the gate electrode 110 is connected to the common gate pad 115 . In this schematic unit cell, 10 gate electrodes are connected to the gate pad, and 5 drain electrodes are connected to the drain pad. In addition, the opposite via needs to be connected to the back surface (not shown) of the substrate. In this case, the area required for the nitride semiconductor device is about three times larger than the area of the active region 130 (where the source, drain, and electrodes are located). Although it is possible to reduce the size of the electrode pad, this size reduction of the electrode pad is limited in terms of yield.

Figure 2 shows a unique topology in which adjacent positioning of substrate contacts (short vias) does not compromise the active area density. In this topology, since the gate runs in two dimensions, the gate width can be increased significantly for a given active area. There is no limit to the on-resistance that can be achieved by this topology, except for breakdown voltage and line width limits. Here, each source electrode 100 is accompanied by a via 111 , and each source electrode 100 is surrounded by an adjacent drain electrode 120 . Each drain electrode 120 is accompanied by a drain bump 105, which is a conventional ball usually made of gold. The gate electrode is shown at 110 , which is connected to the gate strap 175 by a contact 106 . The gate strap 175 is also connected with the gate pad 115 . In this way, each island electrode has its own pad, thereby reducing the overall device size. The island or tile shown in FIG. 2 is an embodiment of an overall shape in which source and drain electrodes are necessarily alternated in a two-dimensional topology. The source electrode 100 and the drain electrode 120 are preferably formed of titanium and aluminum. The gate electrode 110 is preferably formed of palladium.

FIG. 3 shows a cross-sectional view taken along II of FIG. 2 . A substrate 155 preferably made of silicon forms a base, on which successive insulating epitaxial layers 150 , 145 , 140 are stacked. A buffer layer 135 is deposited on the epitaxial layer 140 , and an undoped gallium nitride layer 130 is deposited thereon. A final undoped layer of aluminum gallium nitride 125 is deposited over layer 120 . Within the three epitaxial layers 150 , 145 , 140 are two field plates 160 , 165 , which are conductive in nature. They are preferably formed from impurities of silicon. The source electrode is shown at 110 , with vias 111 thereon, and the drain electrode is shown at 120 . The gate electrode 110 is seated between the source electrode 100 and the drain electrode 120 , and an oxide layer 170 , preferably silicon nitride, is disposed thereon. A gate strap 175 is shown on top of the layer 170 .

The rectangular equivalent shown in FIG. 2 can be replaced with a tetragonal shape without losing the advantages mentioned. The rectangle can be rotated, for example an alternative use of the rectangle is shown in FIG. 5 .

This two-dimensional tiled layout shown in Figures 4 and 5 is very advantageous as it allows for increased gate width. In both Figures 4 and 5, the source electrode and via are shown at 110 and 111, respectively, and the drain electrode and ball connection are shown at 120 and 105, respectively. The gate runs in both directions. However, since some active region is lost at the transition between individual island devices, the useful active gate width is not doubled. Indeed, when compared to the multifinger device layout, the island topologies of Figures 4 and 5 were found to provide 1.5 to 1.7 times the gate width. The on-resistance of these devices is proportionally lower.

It is possible to also improve the gate width by splicing the gate in three directions. This is shown in the island layout of FIG. 6 using a unique equilateral triangular island. However, the triangle may be of any configuration, and the concept of gates in three directions is not limited to the convenient equilateral triangle layout shown. In practice, this layout also provides approximately 1.5 to 1.7 times the gate width obtained by using prior art interlocking (or multi-finger) structures. As shown in FIG. 2 , the via 111 is positioned on the source electrode 100 , and the ball connection part 105 is on the top of the drain electrode 120 . The fuse/anti-fuse 106 serves to connect the gate electrode 110 to the gate strap 175 , and the gate strap 175 is connected to the gate pad 175 .

Based on the design rule of 0.5 μm gate length and 2.5 μm drain-source spacing, the active area is 7.5 mm 2 and the individual gate widths are 7.5 m with interdigitation 0.7 m, rectangular island, 1.1 m, and triangular island 1.1 m. μm drain/source features are present. Thus, a GaN transistor with a 1.4 m gate width can be fabricated using a die size of less than 3 mm x 3 mm. Such a device would have an on-resistance of 10 to 15 microohms and would be able to switch 100 amps.

The island topology allows the space between active devices to be used as connection points. By using a low unit resistance gate strap 175, the problem of metal gate resistance can be eliminated. By displacing the strap from the gate as it transits through the active gate-drain channel region, the strap can be positioned to act as an auxiliary field plate. This is shown in FIGS. 2 and 3 .

To use only the straps to connect good functional individual cells, the contacts 106 at the gate corners can be used. Yield improvement is also possible by isolating individual drains by removal or absence of gold bumps. Thus, even in the presence of large defect densities, it is possible to fabricate a viable functional device using the layout shown in FIG. 2 .

It is shown in Figs. 2, 4, 5 and 6 that a conventional bond or package is not provided. An alternative advantageous packaging technique is shown in cross section in FIG. 7 . The absence of the air bridge allows the die 200 to be eutectically coupled to the copper/source heatsink clip 210 (via eutectic coupling 205 ). This can be inverted to allow the gold bump gate 215 and drain 220 connections to be made directly to the copper tracks 225 on a multichip assembly. This arrangement significantly reduces the overall area of the mounted device and reduces the inductance of the drain and source connections compared to a package using wire bonding.

Alternatively, all heat dissipation could be removed via copper tracks on the board, and the copper/source heatsink clips could be removed. To achieve this result, the drain, source, and gate connections all have gold bumps, and via connections and insulating high-resistance substrates are not used.

It is common practice to thin the wafers of power RF devices to about 450 μm to 150 μm to lower thermal resistance. In the packaged device shown in FIG. 7, the dice are thinned to 50 μm to achieve low series resistance to the source connection. The package shown in Figure 7 is used to mechanically strengthen the dice and obtain a low inductance connection to the source.

The foregoing constitutes a description of specific embodiments indicating how the invention may be applied and used. These embodiments are exemplary only. In view of its broadest and more specific aspects, the invention is further described and defined in the claims that follow.