Semiconductor device, and display device and electronic device having the same

A semiconductor device, and a display device and an electronic device having the semiconductor device TECHNICAL FIELD

The present invention relates to a semiconductor device. In particular, the present invention relates to a shift register constructed using transistors. Further, the present invention relates to a display device including a semiconductor device, and an electronic device including the display device.

In recent years, since large-sized display devices, such as a liquid crystal television, are increasing, display devices, such as a liquid crystal display device and a light emitting device, are being actively developed. In particular, a technique for forming a driver circuit (hereinafter referred to as an internal circuit) including a pixel circuit and a shift register circuit, etc. on the same substrate by using a transistor formed of an amorphous semiconductor on an insulator is effective in reducing power consumption and cost. Because it contributes greatly, it is being actively developed. The internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter referred to as an external circuit) disposed outside the insulator via an FPC or the like, and its operation is controlled.

Further, as an internal circuit formed on an insulator, a shift register circuit constructed using a transistor made of an amorphous semiconductor has been devised (see Document 1: PCT International Publication No. 95/31804).

However, since the shift register circuit has a period in which the output terminal is in a floating state, noise is likely to occur in the output terminal. Due to the noise generated at this output terminal, a malfunction of the shift register circuit occurs.

To solve the above problem, a shift register circuit in which the output terminal is not brought into a floating state has been devised. This shift register circuit operates by so-called static driving (see Document 2: Japanese Patent Application Laid-Open No. 2004-78172).

The shift register circuit disclosed in Document 2 can realize static driving. Accordingly, in this shift register circuit, since the output terminal is not in a floating state, noise generated at the output terminal can be reduced.

In the shift register circuit disclosed in Document 2, its operation period is divided into a selection period for outputting one selection signal and a non-selection period for outputting a non-selection signal, and most of these operation periods are the non-selection period. becomes this In the non-selection period, a low potential is supplied to the output terminal through the transistor. That is, the transistor for supplying a low potential to this output terminal is turned on for most of the operation period of the shift register circuit.

It is known that the characteristics of a transistor manufactured using an amorphous semiconductor deteriorate depending on the time the transistor is turned on and the potential applied to the transistor. Among them, the threshold voltage shift at which the threshold voltage of the transistor rises becomes conspicuous when the characteristics of the transistor deteriorate. This threshold voltage shift is one of the major causes of malfunction of the shift register circuit.

In view of the above problems, the present invention provides a shift register circuit capable of suppressing deterioration of transistors with little noise even in the non-selection period, a semiconductor device or display device including the shift register circuit, and the display device An object of the present invention is to provide an electronic device comprising a.

In the present invention, the transistor included in the semiconductor device is not always turned on, and deterioration of the characteristics of the transistor is suppressed.

A semiconductor device according to an aspect of the present invention includes a first transistor, a second transistor, a third transistor, an inverter, a first wiring, a second wiring, and a third wiring, wherein the first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, a gate terminal of the first transistor is electrically connected to a first terminal of the inverter, and a second transistor a first terminal of the second transistor is electrically connected to the second wiring, a gate terminal of the second transistor is electrically connected to a second terminal of the third transistor, and a first terminal of the third transistor is electrically connected to the third wiring, and , a gate terminal of the third transistor is electrically connected to a second terminal of the inverter, and a gate terminal of the first transistor is electrically connected to a transistor for placing the gate terminal of the first transistor in a floating state.

A semiconductor device according to an aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first wiring, a second wiring, a third wiring, and a fourth wiring, , a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a gate terminal of the first transistor is electrically connected to a second terminal of the fourth transistor. electrically connected to the gate terminal, a first terminal of the second transistor electrically connected to the second wiring, a gate terminal of the second transistor electrically connected to a second terminal of the third transistor, and a second terminal of the third transistor The first terminal is electrically connected to the third wiring, the gate terminal of the third transistor is electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, and the first terminal of the fourth transistor is electrically connected to the second terminal electrically connected to the wiring, and a first terminal of the fifth transistor is electrically connected to the fourth wiring; The gate terminal of the fifth transistor is electrically connected to the fourth wiring, and the gate terminal of the first transistor is electrically connected to the transistor for putting the gate terminal of the first transistor in a floating state.

A semiconductor device according to an aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first wiring, a second wiring, a third wiring, a fourth wiring , and a fifth wire, wherein a first terminal of the first transistor is electrically connected to the first wire, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and the first transistor a gate terminal of the fourth transistor is electrically connected to a gate terminal of the fourth transistor and a second terminal of the sixth transistor, a first terminal of the second transistor is electrically connected to a second wiring, and a gate terminal of the second transistor is electrically connected to the third electrically connected to a second terminal of the transistor, a first terminal of the third transistor is electrically connected to a third wiring, and a gate terminal of the third transistor is electrically connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor is electrically connected to, and a first terminal of the fourth transistor is electrically connected to a second wiring, a first terminal of the fifth transistor is electrically connected to the fourth wiring, a gate terminal of the fifth transistor is electrically connected to the fourth wiring, and a first terminal of the sixth transistor is electrically connected to the fourth wiring; A gate terminal of the sixth transistor is electrically connected to the fifth wiring.

A semiconductor device according to an aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first wiring, a second wiring, and a third wiring. , a fourth wire, and a fifth wire, wherein a first terminal of the first transistor is electrically connected to the first wire, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and , the gate terminal of the first transistor is electrically connected to the gate terminal of the fourth transistor, the second terminal of the sixth transistor, and the second terminal of the seventh transistor, and the first terminal of the second transistor is electrically connected to the second wiring , a gate terminal of the second transistor is electrically connected to a second terminal of the third transistor and a gate terminal of the seventh transistor, and a first terminal of the third transistor is electrically connected to a third wiring, The gate terminal of the third transistor is electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, the first terminal of the fourth transistor is electrically connected to the second wiring, and the second terminal of the fifth transistor is electrically connected to the second terminal. The first terminal is electrically connected to the fourth wiring, the gate terminal of the fifth transistor is electrically connected to the fourth wiring, the first terminal of the sixth transistor is electrically connected to the fourth wiring, and the gate of the sixth transistor is electrically connected to the fourth wiring. A terminal is electrically connected to the fifth wiring, and a first terminal of the seventh transistor is electrically connected to the second wiring.

A semiconductor device according to an aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first wiring, and a second wiring. , a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring, wherein a first terminal of the first transistor is electrically connected to the first wiring, and a second terminal of the first transistor is connected to the second transistor. electrically connected to the second terminal, the gate terminal of the first transistor being electrically connected to the gate terminal of the fourth transistor, the second terminal of the sixth transistor, the second terminal of the seventh transistor, and the second terminal of the eighth transistor connected, a first terminal of the second transistor electrically connected to the second wiring, a gate terminal of the second transistor electrically connected to a second terminal of the third transistor and a gate terminal of the seventh transistor, and a third transistor The first terminal of the is electrically connected to the third wiring, The gate terminal of the third transistor is electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, the first terminal of the fourth transistor is electrically connected to the second wiring, and the first terminal of the fifth transistor is electrically connected to the second terminal of the fifth transistor. The first terminal is electrically connected to the fourth wiring, the gate terminal of the fifth transistor is electrically connected to the fourth wiring, the first terminal of the sixth transistor is electrically connected to the fourth wiring, and the gate of the sixth transistor is electrically connected to the fourth wiring. a terminal electrically connected to the fifth wiring, a first terminal of the seventh transistor electrically connected to the second wiring, a first terminal of the eighth transistor electrically connected to the second wiring, and a gate of the eighth transistor A terminal is electrically connected to the sixth wiring.

In addition, in the present invention, the ratio (W/L) of the channel length (L) to the channel width (W) of the fourth transistor is the ratio (W) of the channel length (L) to the channel width (W) of the fifth transistor /L) may be 10 times or more.

Further, in the present invention, the first transistor and the third transistor may have the same conductivity type.

Further, in the present invention, the first transistor and the fourth transistor may be an n-channel transistor or a p-channel transistor.

Further, in the present invention, a capacitor electrically connected between the second terminal of the first transistor and the gate terminal of the first transistor may be provided.

Further, in the present invention, a capacitance (capacitance) may be formed by using a MOS transistor instead of the capacitor.

Further, in the present invention, the capacitor includes a first electrode, a second electrode, and an insulator held between the first electrode and the second electrode, wherein the first electrode is a semiconductor layer, and the second electrode is a gate wiring layer and the insulator may be a gate insulating film.

Further, in the present invention, a clock signal may be supplied to the first wiring and an inverted clock signal 180 degrees out of phase with the clock signal may be supplied to the third wiring.

A display device according to an aspect of the present invention includes a plurality of pixels and a driving circuit, each of the plurality of pixels is controlled by the driving circuit, and the driving circuit always includes a plurality of transistors and each of the plurality of transistors. It contains a circuit that prevents it from being turned on.

Further, in the present invention, the driving circuit may include the semiconductor device described above.

Further, in the present invention, each of the plurality of pixels includes at least one transistor, and the transistor included in each of the plurality of pixels and the transistor included in the driving circuit may have the same conductivity type.

Further, in the present invention, each of the plurality of pixels and the driving circuit may be formed on the same substrate.

Also, the display device of the present invention may be applied to an electronic device.

As described above, in the present invention, in order to keep the second transistor and the seventh transistor from being always on, the on or off of the second transistor and the seventh transistor is controlled by the signal supplied to the third wiring.

Further, in order to prevent the second transistor from turning on when the first transistor is turned on, the third transistor is turned off by connecting the gate terminal of the first transistor to the gate terminal of the second transistor via an inverter. If the second transistor is turned off before the third transistor is turned off, the second transistor remains off. Therefore, the first wiring and the second wiring do not conduct through the first transistor and the second transistor.

Further, when the potential of the first wiring changes when the first transistor is on and the second transistor is off, the potential of the second terminal of the first transistor also changes. At this time, when the gate terminal of the first transistor is in a floating state, the potential of the gate terminal of the first transistor is simultaneously changed by capacitive coupling of the capacitor. Here, when the potential of the gate terminal of the first transistor changes to a value equal to or greater than or equal to the sum of the potential of the first wiring and the threshold voltage of the first transistor, the first transistor is continuously turned on. As described above, the present invention also has a function of turning on the first transistor to set the first terminal and the second terminal of the first transistor to the same potential even when the potential of the first wiring changes.

In addition, the switch described herein may use, for example, an electrical switch or a mechanical switch. That is, any element can be used as long as it can control the flow of current, and the switch is not limited to a specific one. For example, it may be a transistor, a diode (eg, a PN junction diode, a PIN junction diode, a Schottky diode, a diode-connected transistor, etc.), or a logic circuit combining them. Therefore, when a transistor is used as a switch, since the transistor operates as a simple switch, the polarity (conduction type) of the transistor is not particularly limited. However, when a small off current is desired, it is preferable to use a transistor of a polarity with a small off current. Examples of the transistor having a low off-state current include a transistor having an LDD region, a transistor having a multi-gate structure, and the like. Further, when the potential of the source terminal of the transistor operating as a switch is close to the low-potential power supply (eg, Vss, GND, or 0 V), an n-channel transistor is used, and conversely, the potential of the source terminal It is preferable to use a p-channel transistor when is close to the high-potential power supply (eg, Vdd). This is because, since the absolute value of the voltage between the gate and the source of the transistor can be increased, it is easy to operate when functioning as a switch. Further, a CMOS switch may be formed by using both an n-channel transistor and a p-channel transistor.

In addition, in this invention, the description "connected" is synonymous with the description "connected electrically". Accordingly, other elements or switches may be interposed between the elements.

In addition, a display device, a display device that is a device having a display device, a light emitting device, and a light emitting device that is a device having a light emitting device may use various types and may include various devices. For example, an EL element (for example, an organic EL element, an inorganic EL element, or an EL element containing both organic and inorganic substances), an electron emitting element, a liquid crystal element, electronic ink, etc. A changing display medium can be applied. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron emission element, there are a field emission display (FED), a surface-conduction electron-emitter display (SED), etc., and a liquid crystal element. As a display device using , there is a liquid crystal display, and as a display device using electronic ink, there is an electronic paper.

In addition, in the present invention, there is no limitation on the type of transistor that can be applied, and a thin film transistor (TFT) using a non-single crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate , MOS transistors, junction transistors, bipolar transistors, transistors using compound semiconductors such as ZnO or a-InGaZnO, transistors using organic semiconductors or carbon nanotubes, and other transistors can be applied. There is no limitation on the kind of substrate on which the transistor is formed, and the transistor can be disposed on a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, or the like.

Further, as already described, various types of transistors may be used in the present invention, and such transistors may be formed on various types of substrates. Therefore, all of the circuits may be formed on a glass substrate, may be formed on a plastic substrate, may be formed on a single crystal substrate, may be formed on an SOI substrate, or may be formed on any other substrate. Alternatively, some of the circuits may be formed on a certain substrate, and another portion of the circuits may be formed on another substrate. That is, it is not necessary that all of the circuits are formed on the same substrate. For example, a part of the circuit may be formed using a transistor on a glass substrate, the other part of the circuit may be formed on a single crystal substrate, and the IC chip may be connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed circuit board.

In addition, the structure of a transistor is not specifically limited. For example, a multi-gate structure having two or more gates may be used, and a structure in which gate electrodes are disposed above and below a channel may be used, a structure in which a gate electrode is disposed above a channel may be used, and a structure in which a gate electrode is disposed above and below the channel may be used. A structure in which gate electrodes are disposed, a forward staggered structure, an inverted staggered structure may be used, and a structure in which the channel region is divided into a plurality of regions may be used, and the divided regions may be connected in parallel or in series, may have a structure, a source electrode or a drain electrode may be superimposed on the channel (or a part thereof), and an LDD (Lightly Doped Drain) region may be provided.

In addition, in this specification, it shall be assumed that 1 pixel represents the minimum unit of an image. Therefore, in the case of a full-color display device comprising color elements of R (red), G (green), and B (blue), one pixel means a dot of a color element of R, a dot of a color element of G, and B (blue). shall be composed of dots of color elements of

In addition, in the present specification, that the pixels are arranged in a matrix means not only the case where the pixels are arranged in a so-called grid pattern combining vertical stripes and horizontal stripes, but also three color elements (e.g., RGB ), a case in which dots of three color elements are arranged in a so-called delta pattern is also included. Further, the size of the light emitting region may be different for each dot of the color element.

A transistor is an element having at least three terminals: a gate, a drain, and a source, and has a channel region between the drain region and the source region. Here, since the source region and the drain region of the transistor change depending on the structure and operating conditions of the transistor, it is difficult to limit which one is the source region or the drain region. Accordingly, in this specification, one of the regions functioning as the source region and the drain region is denoted as a first terminal, and the other region is denoted as a second terminal.

In addition, as used herein, a semiconductor device refers to a device having a circuit including a semiconductor element (eg, a transistor or a diode). Moreover, the overall device which can function by using semiconductor characteristics may be sufficient. In addition, a display device refers to a display panel itself formed on the same substrate as a peripheral driving circuit in which a plurality of pixels including display elements such as liquid crystal elements and EL elements formed on a substrate drive those pixels, as well as flexible printed circuits ( FPC) and printed wiring boards (PWBs) are also included. Incidentally, the light emitting device refers to a display device using a self-emission type display element such as an EL element or an element used for an FED.

In the semiconductor device of the present invention, a transistor whose on/off is controlled by a signal supplied to the third wiring may be turned on at regular time intervals. By doing so, the transistor of the shift register circuit using the semiconductor device of the present invention is not always turned on during the non-selection period, so that the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit using the semiconductor device of the present invention is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit using the semiconductor device of the present invention can suppress noise generated at the output terminal.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows Embodiment 1. FIG.

Fig. 2 is a timing chart showing Embodiment 1;

Fig. 3 is a diagram showing the first embodiment;

Fig. 4 is a diagram showing the first embodiment.

Fig. 5 is a diagram showing the first embodiment;

Fig. 6 is a diagram showing the first embodiment;

Fig. 7 is a diagram showing the first embodiment;

Fig. 8 is a diagram showing the first embodiment;

Fig. 9 is a diagram showing the first embodiment;

Fig. 10 is a diagram showing the first embodiment;

Fig. 11 is a diagram showing the first embodiment;

12 is a timing chart showing Embodiment 1;

Fig. 13 is a diagram showing the first embodiment;

Fig. 14 is a diagram showing the first embodiment;

Fig. 15 is a diagram showing the first embodiment;

Fig. 16 is a diagram showing the first embodiment;

Fig. 17 is a diagram showing a second embodiment;

18 is a timing chart showing Embodiment 2;

Fig. 19 is a timing chart showing Embodiment 2;

Fig. 20 is a diagram showing a third embodiment;

Fig. 21 is a diagram showing a third embodiment;

Fig. 22 is a diagram showing a third embodiment;

Fig. 23 is a diagram showing a third embodiment;

Fig. 24 is a diagram showing a third embodiment;

Fig. 25 is a diagram showing a third embodiment;

Fig. 26 is a diagram showing a third embodiment;

Fig. 27 is a diagram showing a third embodiment;

Fig. 28 is a diagram showing a third embodiment;

Fig. 29 is a diagram showing a third embodiment;

Fig. 30 is a diagram showing a third embodiment;

Fig. 31 is a diagram showing a third embodiment;

Fig. 32 is a diagram showing a third embodiment;

Fig. 33 is a diagram showing a third embodiment;

Fig. 34 is a diagram showing a third embodiment;

Fig. 35 is a diagram showing a third embodiment;

Fig. 36 is a diagram showing a third embodiment;

Fig. 37 is a diagram showing a third embodiment;

Fig. 38 is a diagram showing a third embodiment;

Fig. 39 is a diagram showing a third embodiment;

Fig. 40 is a diagram showing a third embodiment;

Fig. 41 is a diagram showing a third embodiment;

Fig. 42 is a diagram showing a third embodiment;

Fig. 43 is a diagram showing a third embodiment;

Fig. 44 is a diagram showing a third embodiment;

45 is a diagram showing a third embodiment;

Fig. 46 is a diagram showing a third embodiment;

Fig. 47 is a diagram showing a third embodiment;

Fig. 48 is a diagram showing a third embodiment;

Fig. 49 is a diagram showing a third embodiment;

Fig. 50 is a diagram showing a third embodiment;

Fig. 51 is a diagram showing a third embodiment;

52 is a diagram showing a third embodiment;

Fig. 53 is a diagram showing a third embodiment;

Fig. 54 is a diagram showing a third embodiment;

Fig. 55 is a diagram showing a third embodiment;

Fig. 56 is a diagram showing a third embodiment;

Fig. 57 is a diagram showing a third embodiment;

58 is a diagram showing a third embodiment;

59 is a diagram showing a third embodiment;

Fig. 60 is a diagram showing a third embodiment;

Fig. 61 is a diagram showing a third embodiment;

Fig. 62 is a diagram showing a third embodiment;

Fig. 63 is a diagram showing a third embodiment;

Fig. 64 is a diagram showing a third embodiment;

Fig. 65 is a diagram showing a third embodiment;

Fig. 66 is a diagram showing a third embodiment;

Fig. 67 is a diagram showing a third embodiment;

Fig. 68 is a diagram showing a third embodiment;

Fig. 69 is a diagram showing a third embodiment;

70 is a diagram showing a third embodiment;

Fig. 71 is a diagram showing a third embodiment;

Fig. 72 is a diagram showing a third embodiment;

Fig. 73 is a diagram showing a third embodiment;

Fig. 74 is a diagram showing a third embodiment;

Fig. 75 is a diagram showing a third embodiment;

Fig. 76 is a diagram showing a third embodiment;

Fig. 77 is a diagram showing a third embodiment;

Fig. 78 is a diagram showing a third embodiment;

Fig. 79 is a diagram showing a third embodiment;

Fig. 80 is a diagram showing a third embodiment;

Fig. 81 is a diagram showing a third embodiment;

Fig. 82 is a diagram showing a third embodiment;

Fig. 83 is a diagram showing a third embodiment;

Fig. 84 is a diagram showing a third embodiment;

Fig. 85 is a diagram showing a third embodiment;

Fig. 86 is a diagram showing a third embodiment;

Fig. 87 is a diagram showing a third embodiment;

Fig. 88 is a diagram showing a fourth embodiment;

Fig. 89 is a diagram showing a fourth embodiment;

Fig. 90 is a diagram showing a fourth embodiment;

Fig. 91 is a diagram showing a fourth embodiment;

Fig. 92 is a view showing the first embodiment;

Fig. 93 is a view showing the first embodiment;

Fig. 94 is a diagram showing the first embodiment;

Fig. 95 is a view showing Example 2;

96 is a diagram showing Example 3;

97 is a view showing Example 3;

98 is a diagram showing Example 3;

Fig. 99 is a view showing a third embodiment;

100(A) and 100(B) are views showing a fourth embodiment;

101(A) and 101(B) are views showing a fourth embodiment;

102(A) and 102(B) are views showing a fourth embodiment;

103(A) and 103(B) are views showing a fourth embodiment;

104(A) to 104(C) are views showing a fourth embodiment;

Fig. 105 is a diagram showing a fourth embodiment;

106(A) and 106(B) are views showing the fourth embodiment;

107(A) and 107(B) are views showing the fourth embodiment;

108(A) and 108(B) are views showing the fourth embodiment;

109(A) and 109(B) are views showing the fourth embodiment;

110(A) and 110(B) are views showing the fourth embodiment;

111(A) and 111(B) are views showing a fourth embodiment;

Fig. 112 is a diagram showing a seventh embodiment;

Fig. 113 is a view showing a seventh embodiment;

114(A) and 114(B) are diagrams showing Example 7;

115(A) and 115(B) are views showing a seventh embodiment;

Fig. 116 is a diagram showing a sixth embodiment;

117(A) to 117(H) are diagrams showing Example 7;

Fig. 118 is a view showing a third embodiment;

Fig. 119 is a diagram showing a third embodiment;

Fig. 120 is a view showing Example 3;

121 is a view showing Example 3;

Fig. 122 is a diagram showing a fourth embodiment;

Fig. 123 is a diagram showing a fifth embodiment;

Fig. 124 is a diagram showing a third embodiment;

Fig. 125 is a diagram showing a third embodiment;

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated with reference to drawings by embodiment and an Example. However, it will be readily apparent to those skilled in the art that the present invention can be practiced in many other embodiments and that various changes can be made in form and details thereof without departing from the spirit and scope of the present invention. Therefore, this invention is limited to the description of embodiment and an Example and is not interpreted.

[Embodiment 1]

1 shows one form of a flip-flop circuit 10 included in a shift register circuit of the present invention . The shift register circuit of the present invention has a flip-flop circuit 10 in multiple stages. The flip-flop circuit 10 shown in FIG. 1 includes a transistor 11 , a transistor 12 , a transistor 13 , a transistor 14 , a transistor 15 , a transistor 16 , a transistor 17 , and a transistor 18 . , and a capacitor 19 having two electrodes. However, the capacitor 19 is not necessarily required if the gate capacitance of the transistor 12 can be used as the capacitor 19 .

As shown in the flip-flop circuit 10, the gate terminal of the transistor 11 is connected to the input terminal IN1, the first terminal of the transistor 11 is connected to the first power supply, and the second terminal of the transistor 11 is connected to the first power supply. Two terminals are connected to the gate terminal of the transistor 12 , the second terminal of the transistor 14 , the gate terminal of the transistor 15 , the second terminal of the transistor 17 , and the second electrode of the capacitor 19 . . A first terminal of transistor 15 is connected to a second power supply, and a second terminal of transistor 15 is connected to a second terminal of transistor 16 and a gate terminal of transistor 18 . A gate terminal and a first terminal of the transistor 16 are connected to a first power supply. A first terminal of the transistor 18 is connected to the input terminal IN3 , and a second terminal of the transistor 18 is connected to a gate terminal of the transistor 13 and a gate terminal of the transistor 14 . A first terminal of the transistor 13 is connected to a second power source, and a second terminal of the transistor 13 is connected to a first electrode of the capacitor 19 , a second terminal of the transistor 12 , and an output terminal OUT. connected. A first terminal of the transistor 12 is connected to the input terminal IN2. A first terminal of the transistor 14 is connected to a second power supply. A gate terminal of the transistor 17 is connected to the input terminal IN4 , and a first terminal of the transistor 17 is connected to a second power supply.

Further, in the flip-flop circuit 10 , the second terminal of the transistor 11 , the gate terminal of the transistor 12 , the second terminal of the transistor 14 , the gate terminal of the transistor 15 , and the second terminal of the transistor 17 . The second terminal and the node of the second electrode of the capacitor 19 are denoted by N1. The node of the second terminal of the transistor 15 , the second terminal of the transistor 16 , and the gate terminal of the transistor 18 is denoted by N2 . A node of the gate terminal of the transistor 13 , the gate terminal of the transistor 14 , and the second terminal of the transistor 18 is denoted by N3 .

Further, a power supply potential VDD is supplied to the first power supply, and a power supply potential VSS is supplied to the second power supply. A potential difference (VDD-VSS) between the power supply potential VDD of the first power supply and the power supply potential VSS of the second power supply corresponds to the power supply voltage of the flip-flop circuit 10 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

Further, a control signal is supplied to each of the input terminals IN1 to IN4. Also, the output terminal OUT outputs an output signal. The output signal of the flip-flop circuit 10 of the previous stage is supplied as a control signal to the input terminal IN1. The output signal of the flip-flop circuit 10 of the next stage is supplied as a control signal to the input terminal IN4.

Further, each of the transistors 11 to 18 is an n-channel transistor. However, each of the transistors 11 to 18 may be a p-channel transistor.

Next, the operation of the flip-flop circuit 10 shown in Fig. 1 will be described using the timing chart shown in Fig. 2 . FIG. 2 is a timing chart of a control signal supplied to each of the input terminals IN1 to IN4 shown in FIG. 1, an output signal output from the output terminal OUT, and potentials of the nodes N1 to N3. The timing chart shown in Fig. 2 is divided into periods T1 to T4 for convenience.

Further, in the period after the period T4, the period T3 and the period T4 are sequentially repeated. In Fig. 2, period T1 is defined as a selection preparation period, period T2 is defined as a selection period, and period T3 and period T4 are defined as non-selection periods. That is, one selection preparation period, one selection period, and a plurality of non-selection periods are sequentially repeated.

In addition, in the timing chart shown in FIG. 2, each of a control signal and an output signal has two values. That is, each of these signals is a digital signal, and one of the potentials of the digital signal is VDD (hereinafter also referred to as potential VDD or H level) which is the same potential as the power source potential of the first power source when the digital signal is an H signal. When the digital signal is an L signal, it is VSS (hereinafter also referred to as potential VSS or L level) which is the same potential as the power source potential of the second power source.

3 to 6 show the connection state of the flip-flop circuit 10 corresponding to the operation in the period T1 to T4, respectively.

In addition, in FIGS. 3 to 6 , a transistor indicated by a solid line indicates an ON state, and a transistor indicated by a dotted line indicates an OFF state. The wiring indicated by the solid line indicates that it is connected to the power supply or the input terminal, and the wiring indicated by the dotted line indicates that it is not connected to the power supply or the input terminal.

Next, the operation for each period will be described with reference to Figs.

First, the operation of the flip-flop circuit 10 in the period T1 will be described with reference to FIG. 3 . 3 is a diagram showing the connection state of the flip-flop circuit 10 in the period T1.

In the period T1, the input terminal IN1 is at the H level, and the transistor 11 is turned on. The input terminal IN4 becomes L level, and the transistor 17 is turned off. Since the node N3 is maintained at the VSS obtained in a period T3 to be described later, the transistor 14 is turned off. The node N1 is electrically connected to the first power supply through the transistor 11, and the potential of the node N1 rises to become Vn11. When the node N1 becomes Vn11, the transistor 11 is turned off. Here, Vn11 is a value (VDD-Vth11) obtained by subtracting the threshold voltage Vth11 of the transistor 11 from the power supply potential VDD. In addition, Vn11 is a potential at which the transistor 12 and the transistor 15 can be turned on.

When the potential of the node N1 becomes Vn11, the transistor 11 is turned off, and the transistor 12 and the transistor 15 are turned on. The node N2 is electrically connected to the second power source through the transistor 15 and to the first power source through the transistor 16 , and the potential of the node N2 rises to Vn21. Here, Vn21 is determined by the operating points of the transistor 16 and the transistor 15 . In addition, the transistor 15 and the transistor 16 constitute an inverter using the two transistors. Accordingly, when an H-level signal is input to the gate terminal (node N1) of the transistor 15, an L-level signal is input to the node N2. Here, Vn21 is a potential at which the transistor 18 can be turned off. Therefore, even when the input terminal IN3 is at H level, since the transistor 18 is off, the node N3 can be held at VSS. Since the input terminal IN2 becomes L level and the output terminal OUT is electrically connected to the input terminal IN2 through the transistor 12, the potential of the output terminal OUT becomes VSS.

Since the potential of the node N2 is Vn21 and the transistor 18 is off, the node N3 is held at VSS, and the transistor 13 and the transistor 14 are turned off.

By the above operation, in the period T1, the transistor 12 is turned on and the output terminal OUT is brought to the L level. Also, since the transistor 11 is off, the node N1 is placed in a floating state.

Next, the operation of the flip-flop circuit 10 in the period T2 will be described with reference to FIG. 4 is a diagram showing the connection state of the flip-flop circuit 10 in the period T2.

In the period T2, the input terminal IN1 is at the L level, and the transistor 11 is off. The input terminal IN4 remains at the L level, and the transistor 17 is off. Therefore, the node N1 continues to be in the floating state from the period T1, and maintains the potential Vn11 in the period T1.

Since the potential of the node N1 is maintained at Vn11, the transistor 12 is on. Then, the input terminal IN2 becomes H level. Then, since the output terminal OUT is electrically connected to the input terminal IN2 via the transistor 12, the potential of the output terminal OUT rises from VSS. The potential of the node N1 is changed to Vn12 by capacitive coupling of the capacitor 19, thereby maintaining the ON state of the transistor 12. A so-called bootstrap operation is performed. As a result, the potential of the output terminal OUT rises to the same potential as VDD, which is the potential of the input terminal IN2. Further, Vn12 is a value equal to or greater than the sum of the potential VDD and the threshold voltage Vth12 of the transistor 12 .

Even when the potential of the node N1 becomes Vn12, the transistor 15 remains on. Therefore, the potential of the node N2 and the potential of the node N3 become the same potential as the potential in the period T1.

By the above operation, in the period T2, the potential of the floating node N1 is raised by the bootstrap operation, and the transistor 12 is continuously turned on. Accordingly, the potential of the output terminal OUT is set to VDD, and the output terminal OUT is set to the H level.

Next, the operation of the flip-flop circuit 10 in the period T3 will be described with reference to FIG. 5 . Fig. 5 is a diagram showing the connection state of the flip-flop circuit 10 in the period T3.

In the period T3, the input terminal IN1 remains at the L level, and the transistor 11 is off. The input terminal IN4 goes to the H level, and the transistor 17 is turned on. Then, the node N1 is electrically connected to the second power source through the transistor 17, so that the potential of the node N1 becomes VSS.

The potential of the node N1 becomes VSS, and the transistor 12 and the transistor 15 are turned off. Since the node N2 is electrically connected to the first power supply through the transistor 16, the potential of the node N2 rises to become Vn22. Here, Vn22 is a value (VDD-Vth16) obtained by subtracting the threshold voltage Vth16 of the transistor 16 from the power supply potential VDD. Also, Vn22 is a potential that can turn on the transistor 18 .

When the potential of the node N2 becomes Vn22, the transistor 18 is turned on. And since the input terminal IN3 is at H level, the node N3 is electrically connected to the input terminal IN3 via the transistor 18, and the potential of the node N3 becomes Vn31. Here, Vn31 is a value (Vn22-Vth18) obtained by subtracting the threshold voltage Vth18 of the transistor 18 from Vn22, which is the potential of the node N2. Further, Vn31 corresponds to a value (VDD-Vth16-Vth18) obtained by subtracting the threshold voltage Vth16 of the transistor 16 and the threshold voltage Vth18 of the transistor 18 from the power supply potential VDD. Incidentally, Vn31 is a potential at which the transistor 13 and the transistor 14 can be turned on.

When the potential of the node N3 becomes Vn31, the transistor 13 is turned on. And, since the output terminal OUT is electrically connected to the second power supply through the transistor 13 , the potential of the output terminal OUT becomes VSS.

By the above operation, in the period T3, VSS is supplied to the node N1, and the transistor 12 and the transistor 15 are turned off. Further, the node N3 is set to H level, and the transistor 13 and the transistor 14 are turned on. Accordingly, the potential of the output terminal OUT is set to VSS, and the output terminal OUT is set to the L level.

Next, the operation of the flip-flop circuit 10 in the period T4 will be described with reference to FIG. 6 . 6 is a diagram showing the connection state of the flip-flop circuit 10 in the period T4.

In the period T4, the input terminal IN3 becomes L level, and the potential of the node N3 becomes VSS. Accordingly, the transistor 13 and the transistor 14 are turned off. The input terminal IN4 goes to L level to turn off the transistor 17 . Accordingly, the node N1 is in a floating state, and the potential of the node N1 is maintained at VSS.

Since the potential of the node N1 remains at VSS, the transistor 12 and the transistor 15 remain off. Thus, node N2 remains at Vn22 and transistor 18 remains on.

Since the transistor 12 and the transistor 13 are off, the output terminal OUT is in a floating state. Accordingly, the potential of the output terminal OUT is maintained at VSS.

By the above operation, in the period T4 , the potential of the output terminal OUT is maintained at VSS, and the transistor 13 and the transistor 14 can be turned off. As described above, since the transistors 13 and 14 are not always turned on, deterioration of the characteristics of the transistors 13 and 14 can be suppressed.

The relationship between the period T1 to the period T4 will be described. The period following period T1 is period T2, the period following period T2 is period T3, and the period following period T3 is period T4. Here, the period following the period T4 is the period T1 or the period T3. That is, the period following the period T4 becomes the period T1 when the input terminal IN1 is at the H level, and becomes the period T3 when the input terminal IN1 remains at the L level. Further, when the period T3 is the period following the period T4, the input terminal IN4 remains at the L level and the transistor 17 remains off.

Here, the functions of the transistors 11 to 18 and the capacitor 19 will be described below.

The transistor 11 has a function as a switch for selecting whether to connect or not connect the first power supply and the node N1 according to a control signal supplied to the input terminal IN1 . In the period T1, the transistor 11 has a function of supplying the power supply potential VDD to the node N1 and turning off when the potential of the node N1 becomes Vn11.

In addition, the transistor 11 has a function of putting the node N1 in a floating state (floating state) according to a control signal supplied to the input terminal IN1 . In the period T1 and period T2, the transistor 11 has a function of turning off when the potential of the node N1 becomes Vn11 or higher.

The transistor 12 has a function as a switch for selecting whether to connect or not connect the input terminal IN2 and the output terminal OUT according to the potential of the node N1. In the period T1, the transistor 12 has a function of supplying VSS to the output terminal OUT. In the period T2, the transistor 12 has a function of supplying VDD to the output terminal OUT.

The transistor 13 has a function as a switch for selecting whether or not to connect the second power source and the output terminal OUT according to the potential of the node N3 . In the period T3, the transistor 13 has a function of supplying the power supply potential VSS to the output terminal OUT.

The transistor 14 has a function as a switch that selects whether or not to connect the second power supply and the node N1 according to the potential of the node N3. In the period T3, the transistor 14 has a function of supplying the power supply potential VSS to the node N1.

The transistor 15 has a function as a switch for selecting whether to connect or not connect the second power source to the node N2 according to the potential of the node N1 . In the period T1 and period T2, the transistor 15 has a function of supplying the power supply potential VSS to the node N2.

The transistor 16 has a function as a diode with an input terminal connected to the first power supply and an output terminal connected to a node N2.

The transistor 17 has a function as a switch for selecting whether to connect or not connect the second power supply and the node N1 according to a control signal supplied to the input terminal IN4 . In the period T3 after the period T2, the transistor 17 has a function of supplying the power supply potential VSS to the node N1.

The transistor 18 has a function as a switch that selects whether or not to connect the input terminal IN3 and the node N3 according to the potential of the node N2. In period T3, transistor 18 has a function of supplying VDD to node N3. Also, in the period T4, the transistor 18 has a function of supplying VSS to the node N3.

The capacitor 19 has a function of changing the potential of the node N1 according to the potential of the output terminal OUT. In the period T2, the capacitor 19 has a function of raising the potential of the node N1 by raising the potential of the output terminal OUT.

As described above, in the flip-flop circuit 10 shown in FIG. 1 , the transistor 13 and the transistor 14 are turned on in the period T3 and turned off in the period T4, so that the transistor 13 and the transistor ( 14) can be avoided from being always on. Accordingly, deterioration in characteristics of the transistors 13 and 14 can be suppressed. Accordingly, in the flip-flop circuit 10 shown in FIG. 1 , malfunction due to deterioration in characteristics of the transistors 13 and 14 can also be suppressed.

Further, when the transistor 13 and the transistor 14 are turned on, the power supply potential VSS is supplied to the output terminal OUT and the node N1. Accordingly, in the flip-flop circuit 10 shown in FIG. 1 , the power supply potential VSS can be supplied to the output terminal OUT and the node N1 at regular time intervals, so that the output terminal OUT and the node N1 It is possible to reduce the fluctuation of the electric potential.

Further, since the flip-flop circuit 10 shown in Fig. 1 is all constituted by n-channel transistors, amorphous silicon can be used as the semiconductor layer, and the manufacturing process can be simplified. Therefore, reduction in manufacturing cost and improvement of product yield can be aimed at. Moreover, it becomes possible to create a large-sized display panel. Further, by using the flip-flop circuit of the present invention, the life of the semiconductor device can be prolonged even when a transistor made of amorphous silicon, which tends to deteriorate in characteristics, is used.

Further, in the period T1 to the period T4, an element such as a transistor or a switch may be provided in the flip-flop circuit 10 so as to satisfy the states of Figs. 3 to 6, respectively.

In addition, the capacitor 19 is preferably formed using a gate wiring layer and a semiconductor layer. The gate wiring layer and the semiconductor layer are stacked with a gate insulating film interposed therebetween. Since the film thickness of the gate insulating film is much thinner than that of other insulating layers such as an interlayer film, the capacitor has a small area and a large capacity when the gate insulating film is used as an insulator.

In addition, it is preferable that the size (W/L) of the transistor 15 is larger than the size of the transistor 16 . Here, W represents the channel width of the transistor, and L represents the channel length of the transistor. When the transistor 15 is turned on, the potential of the node N2 is determined by the operating points of the transistor 15 and the transistor 16 . That is, if the size of the transistor 15 is not sufficiently larger than the size of the transistor 16 , the potential of the node N2 increases, so that the transistor 18 cannot be turned off. Therefore, in order to turn off the transistor 18 , the size of the transistor 15 needs to be sufficiently larger than the size of the transistor 16 .

In addition, the size of the transistor 15 is preferably 4 or more times the size of the transistor 16, more preferably 10 times or more. When the power supply voltage is low, the size ratio of the transistor 15 to the transistor 16 may be about 4:1, but when the power supply voltage is high, the size ratio needs to be about 10:1.

Here, when a level shift circuit or the like is connected to the output terminal OUT of the flip-flop circuit 10, the size ratio of the transistor 15 to the transistor 16 is preferably 4:1 or more. This is because the amplitude voltage of the output signal of the flip-flop circuit 10 increases by a level shift circuit or the like, and the flip-flop circuit 10 operates at a low power supply voltage in many cases.

Alternatively, when the level shift circuit or the like is not connected to the output terminal OUT of the flip-flop circuit 10, the size ratio of the transistor 15 to the transistor 16 is preferably 10:1 or more. This is because the output signal of the flip-flop circuit 10 is applied to any operation without a level shift, and the flip-flop circuit 10 operates at a high power supply voltage in many cases.

In addition, each of the power source potential and the control signal potential may be any potential as long as the on/off of the target transistor can be controlled.

For example, the power supply potential VDD may be higher than the H level potential of the control signal. This is because the potential of the node N3 is Vn31 (VDD-Vth16-Vth18), and as the power supply potential VDD increases, the potential Vn31 of the node N3 also increases. Therefore, even if the threshold voltages of the transistors 13 and 14 are high due to deterioration of the characteristics of the transistors 13 and 14, the transistors 13 and 14 can be reliably turned on. .

The power supply potential VDD may be lower than the H level potential of the control signal as long as the on/off of each transistor can be controlled.

In addition, the capacitor 19 is not necessarily required as long as the gate capacitance (parasitic capacitance) between the gate terminal and the second terminal of the transistor 12 is sufficiently large.

For example, as in the flip-flop circuit 70 of FIG. 7 , the capacitor 19 may not be connected. Accordingly, since the number of elements in the flip-flop circuit 70 is one less than the number of elements in the flip-flop circuit 10, each element can be arranged at a high density in the flip-flop circuit 70.

Further, as another example, as in the flip-flop circuit 100 of FIG. 10 , a capacitor may be formed using the transistor 101 . This is because, when the transistor 101 is on, the gate capacitance of the transistor 101 sufficiently functions as a capacitor.

Further, in the period T1 and period T2 (during the bootstrap operation), since the transistor 101 is on, a channel region is formed in the transistor 101 , and the transistor 101 functions as a capacitor. On the other hand, in the period T3 and period T4 (when the bootstrap operation is not being performed), since the transistor 101 is off, a channel region is not formed in the transistor 101 , so that the transistor 101 is a capacitor. It does not function as a capacitor, or it functions as a small capacitor.

Here, by forming a capacitor using the transistor 101 as in the flip-flop circuit 100 of FIG. 10 described above, the transistor 101 functions as a capacitor only when necessary (periods T1 and T2). and does not function as a capacitor at unnecessary times (periods T3 and T4), so that the flip-flop circuit 100 is less likely to malfunction due to changes in potentials of the node N1 and the output terminal OUT. .

Also, the transistor 101 has the same polarity as the transistor 12 .

Further, the first terminal of the transistor 11 may be connected anywhere in the period T1 and the period T2 as long as the node N1 can be placed in a floating state.

For example, as in the flip-flop circuit 80 of FIG. 8 , the first terminal of the transistor 11 may be connected to the input terminal IN1 . This is because even when the first terminal of the transistor 11 is connected to the input terminal IN1, the node N1 can be placed in a floating state in the periods T1 and T2.

In addition, in the flip-flop circuit 10 of FIG. 1 , when the potential of the input terminal IN1 changes, noise is generated in the first power supply due to parasitic capacitance between the first terminal and the gate terminal of the transistor 11 . do. Also, when a current is supplied to the node N1 from the first power supply by turning on/off the transistor 11 , noise is generated in the first power supply due to a voltage drop caused by the current. Such noise is caused by a change in the potential of the input terminal IN1.

Here, by connecting like the flip-flop circuit 80 of FIG. 8 described above, the noise described above can be suppressed. In addition, by suppressing noise from the first power supply, other circuits using the first power supply can operate stably.

In addition, the other circuit using the first power supply corresponds to an inverter circuit connected to the output terminal OUT of the flip-flop circuit 80 , a level shift circuit, a latch circuit, a PWC circuit, or the like.

In addition, as the transistor 16, any element can be used as long as it can constitute an inverter circuit together with the transistor 15. As shown in FIG. The transistor 16 does not necessarily have rectification, and any element can be used as long as it generates a voltage through which a current flows.

For example, as in the flip-flop circuit 90 of FIG. 9 , a resistor element (resistor) 91 may be connected instead of the transistor 16 . This is because, even if the resistor element 91 is connected instead of the transistor 16, the inverter circuit can be configured using the resistor element 91 and the transistor 15.

Also, when the transistor 15 is off, the potential of the node N2 becomes VDD, which is the same potential as the potential of the first power supply. In addition, the potential of the node N3 at this time becomes a value (VDD-Vth18) obtained by subtracting the threshold voltage Vth18 of the transistor 18 from the power supply potential VDD.

Here, by using the resistor element 91 instead of the transistor 16 as in the flip-flop circuit 90 of FIG. 9 described above, even if the threshold voltage of each transistor is increased due to characteristic deterioration, the node N2 Since the potential of VDD becomes VDD, and the potential of the node N3 is only lower than VDD by the threshold voltage Vth18 of the transistor 18, the transistor 13 and the transistor 14 can be easily turned on.

Further, although a control signal is supplied to each of the input terminal IN1, the input terminal IN2, the input terminal IN3, and the input terminal IN4, the present invention is not necessarily limited to this.

For example, a power supply potential VDD or a power supply potential VSS may be supplied to each of the input terminal IN1, the input terminal IN2, the input terminal IN3, and the input terminal IN4, Alternatively, another potential may be supplied.

In addition, although the first terminal of the transistor 11 and the first terminal of the transistor 16 are connected to the first power supply, the present invention is not necessarily limited to this.

For example, the first terminal of the transistor 11 and the first terminal of the transistor 16 may be respectively connected to different power sources. At this time, it is preferable that the potential of the power source connected to the first terminal of the transistor 16 is higher than the potential of the power source connected to the first terminal of the transistor 11 .

As another example, a control signal may be supplied to each of the first terminal of the transistor 11 and the first terminal of the transistor 16 .

In addition, although the first terminal of the transistor 13, the first terminal of the transistor 14, and the first terminal of the transistor 17 are connected to the second power supply, the present invention is not necessarily limited to this.

For example, the first terminal of the transistor 13 , the first terminal of the transistor 14 , and the first terminal of the transistor 17 may be respectively connected to different power sources.

As another example, a control signal may be supplied to each of the first terminal of the transistor 13 , the first terminal of the transistor 14 , and the first terminal of the transistor 17 .

Although the flip-flop circuit 10 shown in Fig. 1 is all configured using n-channel transistors, all may be configured using p-channel transistors. Here, Fig. 11 shows a flip-flop circuit in the case where all of the p-channel transistors are used.

Fig. 11 shows one form of a flip-flop circuit 110 included in the shift register circuit of the present invention. The shift register circuit of the present invention has a plurality of flip-flop circuits (110). The flip-flop circuit 110 shown in FIG. 11 includes a transistor 111 , a transistor 112 , a transistor 113 , a transistor 114 , a transistor 115 , a transistor 116 , a transistor 117 , and a transistor 118 . , and a capacitor 119 having two electrodes. However, the capacitor 119 is not necessarily required when the capacitor 119 can be substituted for the gate capacitance of the transistor 112 .

As shown in the flip-flop circuit 110 , the gate terminal of the transistor 111 is connected to the input terminal IN1 , the first terminal of the transistor 111 is connected to the first power supply, and the second terminal of the transistor 111 is connected to the first power supply. two terminals are connected to a gate terminal of transistor 112 , a second terminal of transistor 114 , a gate terminal of transistor 115 , a second terminal of transistor 117 , and a second electrode of capacitor 119 . . A first terminal of transistor 115 is connected to a second power source, and a second terminal of transistor 115 is connected to a second terminal of transistor 116 and a gate terminal of transistor 118 . A gate terminal and a first terminal of the transistor 116 are connected to a first power supply. A first terminal of the transistor 118 is connected to the input terminal IN3 , and a second terminal of the transistor 118 is connected to a gate terminal of the transistor 113 and a gate terminal of the transistor 114 . A first terminal of the transistor 113 is connected to a second power source, and a second terminal of the transistor 113 is connected to a first electrode of the capacitor 119 , a second terminal of the transistor 112 , and an output terminal OUT. connected. A first terminal of the transistor 112 is connected to the input terminal IN2. A first terminal of the transistor 114 is connected to a second power supply. A gate terminal of the transistor 117 is connected to the input terminal IN4 , and a first terminal of the transistor 117 is connected to a second power supply.

In the flip-flop circuit 110 , the second terminal of the transistor 111 , the gate terminal of the transistor 112 , the second terminal of the transistor 114 , the gate terminal of the transistor 115 , and the second terminal of the transistor 117 . The second terminal and the node of the second electrode of the capacitor 119 are denoted by N1. The node of the second terminal of the transistor 115 , the second terminal of the transistor 116 , and the gate terminal of the transistor 118 is denoted by N2 . A node of the gate terminal of the transistor 113 , the gate terminal of the transistor 114 , and the second terminal of the transistor 118 is denoted by N3 .

In addition, the power supply potential VSS is supplied to the first power supply, and the power supply potential VDD is supplied to the second power supply. A potential difference (VDD-VSS) between the power supply potential VSS of the first power supply and the power supply potential VDD of the second power supply corresponds to the power supply voltage of the flip-flop circuit 110 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

Further, a control signal is supplied to each of the input terminals IN1 to IN4. Also, the output terminal OUT outputs an output signal. The output signal of the flip-flop circuit 110 of the previous stage is supplied to the input terminal IN1 as a control signal, and the output signal of the flip-flop circuit 110 of the next stage is supplied to the input terminal IN4 as a control signal.

Further, each of the transistors 111 to 118 is a p-channel transistor. However, each of the transistors 111 to 118 may be an n-channel transistor.

Next, the operation of the flip-flop circuit 110 shown in Fig. 11 will be described using the timing chart shown in Fig. 12 . FIG. 12 is a timing chart of a control signal supplied to each of the input terminals IN1 to IN4 shown in FIG. 11, an output signal output from the output terminal OUT, and potentials of the nodes N1 to N3. In addition, as for the timing of the control signal and the output signal, the H level and the L level are inverted from that in the case where the flip-flop circuit is both composed of n-channel transistors (Fig. 1). In addition, the timing chart shown in FIG. 12 is divided into period T1 - period T4 for convenience.

In addition, in the period after the period T4, the period T3 and the period T4 are sequentially repeated. 12, a period T1 is defined as a selection preparation period, a period T2 is defined as a selection period, and a period T3 and a period T4 are defined as a non-selection period. That is, one selection preparation period, one selection period, and a plurality of non-selection periods are sequentially repeated.

Further, in the timing chart shown in Fig. 12, each of the control signal and the output signal is a digital signal having two values. One of the two values of the digital signal is VDD (hereinafter also referred to as potential (VDD) or H level), which is the same potential as the power source potential of the second power source when the digital signal is an H signal, and among the two values of the digital signal The other is VSS (hereinafter also referred to as potential VSS or L level), which is the same potential as the power source potential of the first power source when the digital signal is an L signal.

Next, the operation of the flip-flop circuit 110 for each period will be described.

First, the operation of the flip-flop circuit 110 in the period T1 will be described.

In the period T1, the input terminal IN1 goes to the L level to turn on the transistor 111, and the input terminal IN4 goes to the H level to turn the transistor 117 off. Since the node N3 is maintained at the VDD obtained in a period T3 to be described later, the transistor 114 is turned off. The node N1 is electrically connected to the first power supply through the transistor 111 , and the potential of the node N1 decreases to become Vn11. When the node N1 becomes Vn11, the transistor 111 is turned off. Here, Vn11 is a value (VSS+|Vth111|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth111) of the transistor 111 . In addition, Vn11 is a potential at which the transistor 112 and the transistor 115 can be turned on.

When the potential of the node N1 becomes Vn11, the transistor 111 is turned off, and the transistor 112 and the transistor 115 are turned on. The node N2 is electrically connected to the second power source through the transistor 115 and to the first power source through the transistor 116 , and the potential of the node N2 becomes Vn21. Here, Vn21 is determined by the operating points of the transistor 116 and the transistor 115 . In addition, the transistor 115 and the transistor 116 constitute an inverter using the two transistors. Accordingly, when the L level signal is input to the gate terminal (node N1) of the transistor 115, the H level signal is input to the node N2. Here, Vn21 is a potential at which the transistor 118 can be turned off. Accordingly, since the transistor 118 is off even when the input terminal IN3 is at L level, the node N3 can be maintained at VDD. Since the input terminal IN2 is at H level and the output terminal OUT is electrically connected to the input terminal IN2 through the transistor 112 , the potential of the output terminal OUT becomes VDD.

Since the potential of the node N2 is Vn21 and the transistor 118 is off, the node N3 is held at VDD, and the transistor 113 and the transistor 114 are turned off.

By the above operation, in the period T1 , the transistor 112 is turned on and the output terminal OUT is at the H level. Also, since the transistor 111 is off, the node N1 is in a floating state.

Next, the operation of the flip-flop circuit 110 in the period T2 will be described.

In the period T2, the input terminal IN1 is at the H level, and the transistor 111 is off. The input terminal IN4 remains at the H level, and the transistor 117 is off. Accordingly, the node N1 continues to be in the floating state from the period T1, and maintains the potential Vn11 in the period T1.

Since the potential of the node N1 is maintained at Vn11, the transistor 112 is on. Then, the input terminal IN2 becomes H level. Then, since the output terminal OUT is electrically connected to the input terminal IN2 through the transistor 112, the potential of the output terminal OUT decreases from VDD. The potential of the node N1 is changed to Vn12 by the capacitive coupling of the capacitor 119, so that the on state of the transistor 112 is continuously maintained. A so-called bootstrap operation is performed. As a result, the potential of the output terminal OUT decreases to the same potential as VSS, which is the potential of the input terminal IN2. In addition, Vn12 is a value equal to or less than a value (VSS-|Vth112|) obtained by subtracting the absolute value of the threshold voltage Vth112 of the transistor 112 from the potential VSS. Since the input terminal IN2 is at L level and the output terminal OUT is electrically connected to the input terminal IN2 through the transistor 112 , the potential of the output terminal OUT becomes VSS.

Even when the potential of the node N1 becomes Vn12, the transistor 115 remains on. Accordingly, the potential of the node N2 and the potential of the node N3 become the same potential as in the period T1.

By the above operation, in the period T2, the potential of the floating node N1 is lowered by the bootstrap operation, so that the output terminal OUT is set to VSS.

Next, the operation of the flip-flop circuit 110 in the period T3 will be described.

In the period T3, the input terminal IN1 remains at the H level, and the transistor 111 is off. The input terminal IN4 becomes L level to turn on the transistor 117 . Then, the node N1 is electrically connected to the second power source through the transistor 117 , and the potential of the node N1 becomes VDD.

The potential of the node N1 becomes VDD, and the transistor 112 and the transistor 115 are turned off. Since the node N2 is electrically connected to the first power supply through the transistor 116, the potential of the node N2 decreases to become Vn22. Here, Vn22 is a value (VSS+|Vth116|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth116) of the transistor 116 . Also, Vn22 is a potential that can turn on the transistor 118 .

When the potential of the node N2 becomes Vn22, the transistor 118 is turned on. And, since the input terminal IN3 is at L level, the node N3 is electrically connected to the input terminal IN3 via the transistor 118, and the potential of the node N3 becomes Vn31. Here, Vn31 is a value (Vn22+|Vth118|) that is the sum of the absolute value of the threshold voltage Vth118 of the transistor 118 and Vn22 which is the potential of the node N2. In addition, Vn31 is a value (VSS+) that is the sum of the absolute value of the power source potential VSS and the threshold voltage Vth116 of the transistor 116 and the absolute value of the threshold voltage Vth118 of the transistor 118 . Vth116+Vth118). In addition, Vn31 is a voltage that can turn on the transistor 113 and the transistor 114 .

When the potential of the node N3 becomes Vn31, the transistor 113 is turned on. And, since the output terminal OUT is electrically connected to the second power source through the transistor 113 , the potential of the output terminal OUT becomes VDD.

By the above operation, in the period T3 , VDD is supplied to the node N1 to turn off the transistor 112 and the transistor 115 . Further, the node N3 is brought to the L level to turn on the transistors 113 and 114 . Accordingly, the potential of the output terminal OUT becomes VDD, so that the output terminal OUT has the H level.

Next, the operation of the flip-flop circuit 110 in the period T4 will be described.

In the period T4, the input terminal IN3 becomes H level, and the potential of the node N3 becomes VDD. Accordingly, the transistor 113 and the transistor 114 are turned off. The input terminal IN4 becomes H level to turn off the transistor 117 . Accordingly, the node N1 is in a floating state, and the potential of the node N1 is maintained at VDD.

Since the potential of the node N1 remains at VDD, the transistor 112 and the transistor 115 remain off. Thus, node N2 remains at Vn22 and transistor 118 remains off.

Since the transistor 112 and the transistor 113 are off, the output terminal OUT is in a floating state. Accordingly, the potential of the output terminal OUT is maintained at VDD.

By the above operation, in the period T4 , the potential of the output terminal OUT is maintained at VDD, so that the transistors 113 and 114 can be turned off. As described above, since the transistors 113 and 114 are not always turned on, deterioration of the characteristics of the transistors 113 and 114 can be suppressed.

The relationship between the period T1 to the period T4 will be described. The period following period T1 is period T2, the period following period T2 is period T3, and the period following period T3 is period T4. Here, the period following the period T4 is the period T1 or the period T3. That is, the period following the period T4 becomes the period T1 when the input terminal IN1 is at the L level, and becomes the period T3 when the input terminal IN1 remains at the H level. In addition, when the period T3 is the period following the period T4, the input terminal IN4 remains at the H level and the transistor 117 remains off.

Here, the transistors 111 to 118 and the capacitor 119 have the same functions as the transistors 11 to 18 and the capacitor 19 shown in FIG. 1, respectively.

As described above, in the flip-flop circuit 110 shown in FIG. 11 , the transistor 113 and the transistor 114 are turned on in the period T3 and turned off in the period T4, so that the transistor 113 and the transistor 114 are turned off in the period T4. It can be avoided that (114) is always on. Accordingly, deterioration in characteristics of the transistors 113 and 114 can be suppressed. Accordingly, in the flip-flop circuit 110 shown in FIG. 11 , malfunction due to deterioration of the characteristics of the transistors 113 and 114 can also be suppressed.

Further, when the transistors 113 and 114 are turned on, the power supply potential VDD is supplied to the output terminal OUT and the node N1. Accordingly, in the flip-flop circuit 110 shown in Fig. 11, the power supply potential VDD can be supplied to the output terminal OUT and the node N1 at regular time intervals, so that the output terminal OUT and the node N1 are connected to each other. It is possible to reduce the fluctuation of the electric potential.

In addition, in the flip-flop circuit 110 shown in Fig. 11, polysilicon can be used for the semiconductor layer, so that the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield. In addition, since the characteristics of polysilicon are not easily deteriorated, the lifetime of the semiconductor device can be longer than in the case where amorphous silicon is used for the semiconductor layer. Further, by using the flip-flop circuit of the present invention, the lifetime of the semiconductor device can be further extended. In addition, since the mobility of the transistor using polysilicon is high, the flip-flop circuit 110 can operate at high speed.

In addition, the capacitor 119 is preferably formed using a gate wiring layer and a semiconductor layer. The gate wiring layer and the semiconductor layer are laminated with a gate insulating film interposed therebetween. Since the film thickness of the gate insulating film is much thinner than that of other insulating layers such as an interlayer film, the capacitor has a small area and a large capacity when the gate insulating film is used as an insulator.

In addition, the size (W/L) of the transistor 115 is preferably larger than the size of the transistor 116 . Here, W represents the channel width of the transistor, and L represents the channel length of the transistor. When the transistor 115 is on, the potential of the node N2 is determined by the operating points of the transistor 115 and the transistor 116 . That is, if the size of the transistor 115 is not sufficiently larger than the size of the transistor 116 , the potential of the node N2 increases, so that the transistor 118 cannot be turned off. Therefore, in order to turn off the transistor 118 , the size of the transistor 115 needs to be sufficiently larger than the size of the transistor 116 .

In addition, the size of the transistor 115 is preferably 4 or more times the size of the transistor 116 , and more preferably 10 times or more. When the power supply voltage is low, the size ratio of the transistor 115 to the transistor 116 may be about 4:1, but when the power supply voltage is high, the size ratio of the transistor 115 to the transistor 116 needs to be about 10:1 there is

Here, when a level shift circuit or the like is connected to the output terminal OUT of the flip-flop circuit 110, the size ratio of the transistor 115 to the transistor 116 is preferably 4:1 or more. This is because, in many cases, the amplitude voltage of the output signal of the flip-flop circuit 110 is increased by a level shift circuit or the like, and the flip-flop circuit 110 operates at a low power supply voltage.

Alternatively, when the level shift circuit or the like is not connected to the output terminal OUT of the flip-flop circuit 110 , the size ratio of the transistor 115 to the transistor 116 is preferably 10:1 or more. This is because, in many cases, the output signal of the flip-flop circuit 110 is applied to any operation without a level shift, and the flip-flop circuit 110 operates at a high power supply voltage.

In addition, each of the power source potential and the control signal potential may be any potential as long as the on/off of the target transistor can be controlled.

For example, the power supply potential VSS may be a potential lower than the L level potential of the control signal. This is because the potential of the node N3 is Vn31 (VSS+|Vth16|+|Vth18|), and when the power supply potential VSS becomes low, the potential Vn31 of the node N3 also decreases. Therefore, even if the threshold voltages of the transistors 113 and 114 are lowered due to deterioration of the characteristics of the transistors 113 and 114, the transistors 113 and 114 are reliably turned on. can

Further, the power supply potential VSS may be a potential higher than the L level potential of the control signal as long as the on/off of each transistor can be controlled.

Further, the capacitor 119 is not necessarily required as long as the gate capacitance (parasitic capacitance) between the gate terminal and the second terminal of the transistor 112 is sufficiently large.

For example, as in the flip-flop circuit 130 of FIG. 13 , the capacitor 119 may not be connected. Accordingly, since the number of elements of the flip-flop circuit 130 is one less than the number of elements of the flip-flop circuit 110 , each element can be arranged at a high density in the flip-flop circuit 130 .

As another example, as in the flip-flop circuit 160 of FIG. 16 , a capacitor may be formed using the transistor 161 . This is because, when the transistor 161 is on, the gate capacitance of the transistor 161 sufficiently functions as a capacitor.

In addition, since the transistor 161 is on in the period T1 and period T2 (during the bootstrap operation), a channel region is formed in the transistor 161 , and the transistor 161 functions as a capacitor. On the other hand, since the transistor 161 is off in the period T3 and period T4 (when the bootstrap operation is not being performed), a channel region is not formed in the transistor 101, and the transistor 161 is used as a capacitor. Either it does not function, or it functions as a small capacitor.

Here, as in the flip-flop circuit 160 of FIG. 16 described above, by forming a capacitor using the transistor 161, the transistor 161 is used as a capacitor only when necessary (periods T1 and T2). Since it functions and does not function as a capacitor when it is unnecessary (periods T3 and T4), the flip-flop circuit 160 is prevented from malfunctioning due to changes in the potentials of the node N1 and the output terminal OUT. becomes difficult

Also, the transistor 161 has the same polarity as the transistor 112 .

Further, the first terminal of the transistor 111 may be connected anywhere in the period T1 and period T2, as long as the node N1 can be placed in a floating state.

For example, as in the flip-flop circuit 140 of FIG. 14 , the first terminal of the transistor 111 may be connected to the input terminal IN1 . This is because even when the first terminal of the transistor 111 is connected to the input terminal IN1, the node N1 can be placed in a floating state in the periods T1 and T2.

In addition, in the flip-flop circuit 110 of FIG. 11 , when the potential of the input terminal IN1 changes, noise is generated in the first power supply due to a parasitic capacitance between the first terminal and the gate terminal of the transistor 111 . do. Also, when a current is supplied from the first power supply to the node N1 by turning on/off the transistor 111 , noise is generated in the first power supply due to a voltage drop caused by the current. Such noise is caused by a change in the potential of the input terminal IN1.

Here, by connecting as in the flip-flop circuit 140 of FIG. 14 described above, the noise described above can be suppressed. In addition, since the noise of the first power supply is suppressed, other circuits using the first power supply can operate stably.

In addition, the other circuit using the first power supply corresponds to an inverter circuit connected to the output terminal OUT of the flip-flop circuit 140 , a level shift circuit, a latch circuit, a PWC circuit, or the like.

In addition, as long as the transistor 116 can form an inverter circuit together with the transistor 115 , any element can be used. The transistor 116 does not necessarily have rectification, and any device that generates a voltage when current flows may be used.

For example, as in the flip-flop circuit 150 of FIG. 15 , a resistor element (resistor) 151 may be connected instead of the transistor 116 . This is because, even if the resistor element 151 is connected instead of the transistor 116 , the inverter circuit can be configured using the resistor element 151 and the transistor 115 .

Also, when the transistor 115 is off, the potential of the node N2 becomes VSS, which is the same potential as the potential of the first power supply. In addition, the potential of the node N3 at this time becomes a value (VSS+|Vth118|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth118 of the transistor 118 .

Here, as in the flip-flop circuit 150 of FIG. 15 described above, by using the resistance element 151 instead of the transistor 116, even if the threshold voltage of each transistor increases due to characteristic deterioration, the node ( Since the potential of N2 becomes VSS and the potential of the node N3 only becomes higher than VSS by the threshold voltage Vth118 of the transistor 118, the transistor 113 and the transistor 114 can be easily turned on. have.

Further, although a control signal is supplied to each of the input terminal IN1, the input terminal IN2, the input terminal IN3, and the input terminal IN4, the present invention is not necessarily limited to this.

For example, a power supply potential VDD or a power supply potential VSS may be supplied to each of the input terminal IN1, the input terminal IN2, the input terminal IN3, and the input terminal IN4, Alternatively, another potential may be supplied.

In addition, although the first terminal of the transistor 111 and the first terminal of the transistor 116 are connected to the first power supply, the present invention is not necessarily limited to this.

For example, the first terminal of the transistor 111 and the first terminal of the transistor 116 may be respectively connected to different power sources. In this case, the potential of the power source connected to the first terminal of the transistor 116 is preferably higher than the potential of the power source connected to the first terminal of the transistor 111 .

As another example, a control signal may be supplied to each of the first terminal of the transistor 111 and the first terminal of the transistor 116 .

In addition, although the first terminal of the transistor 113, the first terminal of the transistor 114, and the first terminal of the transistor 117 are connected to the second power supply, the present invention is not necessarily limited to this.

For example, the first terminal of the transistor 113 , the first terminal of the transistor 114 , and the first terminal of the transistor 117 may be respectively connected to different power sources.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor of the shift register circuit of the present invention is turned on at regular time intervals, thereby supplying the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Embodiment 2]

In this embodiment, the configuration of the shift register circuit of the present invention will be described.

Fig. 17 shows one embodiment of the shift register circuit of the present invention. The shift register circuit shown in FIG. 17 includes a plurality of flip-flop circuits 171 , a control signal line 172 , a control signal line 173 , and a control signal line 174 .

As shown in the shift register circuit of Fig. 17, the input terminal IN1 of each flip-flop circuit 171 is connected to the output terminal OUT of the flip-flop circuit 171 in the previous stage. The output terminal OUT is connected to the input terminal IN1 of the flip-flop circuit 171 of the next stage, the input terminal IN4 of the flip-flop circuit 171 of the previous stage, and the output terminal SRout of the shift register circuit. have. In addition, the input terminal IN1 of the flip-flop circuit 171 of the first stage is connected to the control signal line 172 . In addition, the input terminal IN4 of the flip-flop circuit 171 of the last stage is connected to the power supply. In the flip-flop circuit 171 of the odd stage, the input terminal IN2 is connected to the control signal line 173 , and the input terminal IN3 is connected to the control signal line 174 . On the other hand, in the flip-flop circuit 171 of the even stage, the input terminal IN2 is connected to the control signal line 174 , and the input terminal IN3 is connected to the control signal line 173 .

In addition, as the flip-flop circuit 171, the same thing as the flip-flop circuit shown in Embodiment 1 can be used.

In addition, as the input terminals IN1 to IN4 and the output terminal OUT of the flip-flop circuit 171, the same ones as those described in the first embodiment can be used.

In addition, the output terminal SRout of the first stage of the shift register circuit of the present invention is denoted by SRout1, the output terminal SRout of the second stage is denoted by SRout2, and the output terminal SRout of the third stage is denoted by SRout3. , the output terminal SRout of the fourth stage is denoted as SRout4, and the output terminal SRout of the nth stage is denoted as SRoutn.

In addition, in the flip-flop circuit 171, a power supply and a power supply line are not shown for convenience. For the power supply and the power supply line, the first power supply and the second power supply described in the first embodiment can be used. Accordingly, the potential difference (VDD-VSS) between the power source potential VDD of the first power source and the power source potential VSS of the second power source corresponds to the power source voltage of the flip-flop circuit 171 .

Further, a control signal SSP, a control signal CK, and a control signal CKB are supplied to the control signal line 172 to the control signal line 174, respectively. In addition, the output signals of the flip-flop circuits 171 of the first to fourth stages and the nth stage are supplied to the output terminals SRout1 to SRout4 and the output terminals SRoutn of the shift register circuit, respectively.

Next, the operation of the shift register circuit shown in Fig. 17 will be described using the timing chart shown in Fig. 18 . Fig. 18 shows the control signal SSP, the control signal CK, and the control signal CKB respectively supplied to the control signal lines 172 to 174, and the output signals of the output terminals SRout1 to SRout4 and the output terminals SRoutn. timing chart is shown. In addition, the timing chart shown in FIG. 18 is divided into period T0 - period T5, period Tn, and period (Tn+1) for convenience.

18 is a timing chart when an n-channel transistor is used as the transistor of the flip-flop circuit 171. As shown in FIG. That is, FIG. 18 is a timing chart when the flip-flop circuit shown in FIGS. 1 and 7 to 10 is used as the flip-flop circuit 171 .

In the timing chart shown in Fig. 18, each of the control signal and the output signal is a digital signal having two values as in the first embodiment.

The operation of the shift register circuit shown in FIG. 17 will be described with reference to FIG. 18 .

First, the operation of the shift register circuit in the period T0 will be described. In the period T0, the control signal SSP is at the H level, the control signal CK is at the L level, and the control signal CKB is at the H level.

In the flip-flop circuit 171 of the first stage, the input terminal IN1 becomes the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input terminal IN4 becomes the H level. becomes L level. Accordingly, the output terminal OUT becomes L level. This state is the same as that of the timing chart in the period T1 shown in FIG. 2 .

In the flip-flop circuit 171 of odd-numbered stages except for the first stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input The terminal IN4 goes to the L level. Accordingly, the output terminal OUT becomes L level. This state is the same as that of the timing chart in the period T3 shown in FIG.

In the flip-flop circuit 171 of the even stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes the L level. It becomes L level. Accordingly, the output terminal OUT becomes L level. This state is the same as that of the timing chart in the period T4 shown in FIG.

In this way, all the output terminals SRout of the shift register circuit are at the L level.

Next, the operation of the shift register circuit in the period T1 will be described. In the period T1, the control signal SSP becomes the L level, the control signal CK becomes the H level, and the control signal CKB becomes the L level.

In the flip-flop circuit 171 of the first stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes the L level. remains at L level. Accordingly, the output terminal OUT becomes H level. This state is the same as that of the timing chart in the period T2 shown in FIG.

In the flip-flop circuit 171 of the second stage, the input terminal IN1 becomes the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input terminal IN4 becomes the H level. remains at L level. Accordingly, the output terminal OUT remains at the L level. This state is the same as that of the timing chart in the period T1 shown in FIG.

In the flip-flop circuit 171 of odd stages except for the first stage, the input terminal IN1 remains at the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input The terminal IN4 remains at the L level. Accordingly, the output terminal OUT remains at the L level. This state is the same as that of the timing chart in the period T4 shown in FIG.

In the flip-flop circuit 171 of the even stage except for the second stage, the input terminal IN1 remains at the L level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input The terminal IN4 remains at the L level. Accordingly, the output terminal OUT remains at the L level. This state is the same as that of the timing chart in the period T3 shown in FIG.

In this way, the output terminal SRout1 of the shift register circuit becomes the H level, and the other output terminal SRout remains at the L level.

Next, the operation of the shift register circuit in the period T2 will be described. In the period T2, the control signal SSP becomes the L level, the control signal CK becomes the L level, and the control signal CKB becomes the H level.

In the flip-flop circuit 171 of the first stage, the input terminal IN1 remains at the L level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the L level, and the input terminal IN4 remains at the L level. becomes H level. Accordingly, the output terminal OUT becomes L level. This state is the same as that of the timing chart in the period T3 shown in FIG.

In the flip-flop circuit 171 of the second stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes the L level. remains at L level. Accordingly, the output terminal OUT becomes H level. This state is the same as that of the timing chart in the period T2 shown in FIG.

In the flip-flop circuit 171 of the third stage, the input terminal IN1 becomes the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input terminal IN4 becomes the H level. remains at L level. Accordingly, the output terminal OUT remains at the L level. This state is the same as that of the timing chart in the period T1 shown in FIG.

In the flip-flop circuit 171 of odd stages excluding the first stage and the third stage, the input terminal IN1 remains at the L level, the input terminal IN2 becomes the L level, and the input terminal IN3 is at the H level. , and the input terminal IN4 remains at the L level. Accordingly, the output terminal OUT remains at the L level. This state is the same as that of the timing chart in the period T3 shown in FIG.

In the flip-flop circuit 171 of the even stage except the second stage, the input terminal IN1 remains at the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input The terminal IN4 remains at the L level. Accordingly, the output terminal OUT remains at the L level. This state is the same as that of the timing chart in the period T4 shown in FIG.

In this way, the output terminal SRout1 of the shift register circuit becomes the L level, the output terminal SRout2 becomes the H level, and the other output terminal SRout remains at the L level.

Similarly in the subsequent period, the output terminal SRout3 of the shift register circuit becomes H level in the period T3, the output terminal SRout4 of the shift register circuit becomes the H level in the period T4, and the output terminal SRout4 of the shift register circuit becomes H level in the period T5. In , the output terminal SRout5 of the fifth stage of the shift register circuit becomes H level, and in the period Tn, the output terminal SRoutn of the nth stage of the shift register circuit becomes H level. In this way, the output terminals of the shift register circuit become H level sequentially for only one period. In addition, one period corresponds to the half period of the control signal CK or the control signal CKB.

By the above operation, the output terminal SRout of the shift register circuit shown in Fig. 17 can be set to H level one by one. Further, by using the flip-flop circuit shown in Embodiment 1 as the flip-flop circuit 171, the flip-flop circuit shown in Fig. 17 is less prone to malfunction due to deterioration of transistor characteristics, and noise of the output signal is reduced.

18 shows a timing chart when the transistor of the flip-flop circuit 171 is an n-channel transistor, while FIG. 19 shows a timing chart when the transistor of the flip-flop circuit 171 is a p-channel transistor. That is, FIG. 19 is a timing chart in the case where the flip-flop circuit shown in FIGS. 11 and 13 to 16 is used as the flip-flop circuit 171 .

Next, the operation of the shift register circuit shown in FIG. 17 will be described using the timing chart shown in FIG. FIG. 19 shows the control signal SSP, the control signal CK, and the control signal CKB respectively supplied to the control signal lines 172 to 174 shown in FIG. 17, and the output terminals SRout1 to SRout4 and the output terminals SRoutn. shows the timing chart of the output signal of In addition, the timing chart shown in FIG. 19 is divided into period T0 - period T5, period Tn, and period (Tn+1) for convenience. As for the timing of the control signal and the output signal, the H level and the L level are inverted from that in the case where the flip-flop circuit 171 is both composed of n-channel transistors (Fig. 18).

Moreover, in the timing chart shown in FIG. 19, each of a control signal and an output signal is a digital signal which has the same two-valued as in Embodiment 1. FIG.

The operation of the shift register circuit shown in FIG. 17 will be described with reference to FIG.

First, the operation of the shift register circuit in the period T0 will be described. In the period T0, the control signal SSP becomes the L level, the control signal CK becomes the H level, and the control signal CKB becomes the L level.

In the flip-flop circuit 171 of the first stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes the L level. becomes H level. Accordingly, the output terminal OUT becomes H level. This state is the same as that of the timing chart in the period T1 shown in Fig. 12 .

In the flip-flop circuit 171 of odd-numbered stages except for the first stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input The terminal IN4 goes to the H level. Accordingly, the output terminal OUT becomes H level. This state is the same as that of the timing chart in the period T2 shown in FIG.

In the flip-flop circuit 171 of the even stage, the input terminal IN1 becomes the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input terminal IN4 becomes the H level. H level. Accordingly, the output terminal OUT becomes H level. This state is the same as that of the timing chart in the period T4 shown in FIG.

In this way, all the output terminals SRout of the shift register circuit are at the H level.

Next, the operation of the shift register circuit in the period T1 will be described. In the period T1, the control signal SSP goes to the H level, the control signal CK goes to the L level, and the control signal CKB goes to the H level.

In the flip-flop circuit 171 of the first stage, the input terminal IN1 becomes the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input terminal IN4 becomes the H level. remains at H level. Accordingly, the output terminal OUT becomes L level. This state is the same as that of the timing chart in the period T2 shown in FIG.

In the flip-flop circuit 171 of the second stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes the L level. remains at H level. Accordingly, the output terminal OUT remains at the H level. This state is the same as that of the timing chart in the period T1 shown in Fig. 12 .

In the flip-flop circuit 171 of odd stages except for the first stage, the input terminal IN1 remains at the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input The terminal IN4 remains at the H level. Accordingly, the output terminal OUT remains at the H level. This state is the same as that of the timing chart in the period T4 shown in FIG.

In the flip-flop circuit 171 of the even stage except for the second stage, the input terminal IN1 remains at the H level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input The terminal IN4 remains at the H level. Accordingly, the output terminal OUT remains at the H level. This state is the same as that of the timing chart in the period T3 shown in Fig. 12 .

In this way, the output terminal SRout1 of the shift register circuit becomes the L level, and the other output terminals SRout remain at the H level.

Next, the operation of the shift register circuit in the period T2 will be described. In the period T2, the control signal SSP becomes the H level, the control signal CK becomes the H level, and the control signal CKB becomes the L level.

In the flip-flop circuit 171 of the first stage, the input terminal IN1 remains at the H level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes L level. Accordingly, the output terminal OUT becomes H level. This state is the same as that of the timing chart in the period T3 shown in Fig. 12 .

In the flip-flop circuit 171 of the second stage, the input terminal IN1 becomes the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input terminal IN4 becomes the H level. remains at H level. Accordingly, the output terminal OUT becomes L level. This state is the same as that of the timing chart in the period T2 shown in FIG.

In the flip-flop circuit 171 of the third stage, the input terminal IN1 becomes the L level, the input terminal IN2 becomes the H level, the input terminal IN3 becomes the L level, and the input terminal IN4 becomes the L level. remains at H level. Accordingly, the output terminal OUT remains at the H level. This state is the same as that of the timing chart in the period T1 shown in Fig. 12 .

In the flip-flop circuit 171 of odd stages except for the first stage and the third stage, the input terminal IN1 remains at the H level, the input terminal IN2 becomes the H level, and the input terminal IN3 is at the L level. , and the input terminal IN4 remains at the H level. Accordingly, the output terminal OUT remains at the H level. This state is the same as that of the timing chart in the period T3 shown in Fig. 12 .

In the flip-flop circuit 171 of the even stage except the second stage, the input terminal IN1 remains at the H level, the input terminal IN2 becomes the L level, the input terminal IN3 becomes the H level, and the input The terminal IN4 remains at the H level. Accordingly, the output terminal OUT remains at the H level. This state is the same as that of the timing chart in the period T4 shown in FIG.

In this way, the output terminal SRout1 of the shift register circuit becomes the H level, the output terminal SRout2 becomes the L level, and the other output terminals SRout remain at the H level.

Similarly in the subsequent period, the output terminal SRout3 of the shift register circuit becomes L level in the period T3, the output terminal SRout4 of the shift register circuit becomes the L level in the period T4, and the output terminal SRout4 of the shift register circuit becomes the L level in the period T5. In , the output terminal SRout5 of the fifth stage of the shift register circuit is at the L level, and in the period Tn, the output terminal SRoutn of the nth stage of the shift register circuit is at the L level. In this way, the output terminals of the shift register circuit are sequentially brought to the L level only for one period. In addition, one period corresponds to the half period of the control signal CK or the control signal CKB.

By the above operation, the output terminal SRout of the shift register circuit shown in Fig. 17 can be set to L level one by one. Further, by using the flip-flop circuit shown in Embodiment 1 as the flip-flop circuit 171, the flip-flop circuit shown in Fig. 17 is less prone to malfunction due to deterioration of transistor characteristics, and noise of the output signal is reduced.

Further, the flip-flop circuit 171 may be any flip-flop circuit as long as it can supply a selection signal to the output terminals SRout of the shift register circuit sequentially from the first stage.

Also, the output terminal OUT of the flip-flop circuit 171 may be connected to the output terminal SRout of the shift register circuit through any device or circuit. Certain elements and circuits correspond to logic circuits such as inverter circuits, buffer circuits, NAND circuits, NOR circuits, tristate buffer circuits, and PWC circuits, switches, resistor elements, capacitors, and other elements. In addition, various circuits can be configured by combining these elements or circuits.

In addition, although a control signal is supplied to each of the control signal lines 172 to 174, the present invention is not necessarily limited to this.

For example, a power supply potential VDD may be supplied to each of the control signal lines 172 to 174, a power supply potential VSS may be supplied, or another potential may be supplied.

In addition, although the control signal CK is supplied to the control signal line 173 and the control signal CKB is supplied to the control signal line 174, the present invention is not necessarily limited to this.

For example, the control signal CK may be supplied to the control signal line 173 and an inverted signal of the control signal CK may be supplied to the control signal line 174 via an inverter circuit. Alternatively, an inverted signal of the control signal CKB may be supplied to the control signal line 173 via an inverter circuit, and the control signal CKB may be supplied to the control signal line 174 . Further, this inverter circuit is preferably formed on the same substrate as the shift register circuit.

In addition, although the input terminal IN4 of the flip-flop circuit 171 of the last stage is connected to a power supply, this invention is not necessarily limited to this.

For example, the input terminal IN4 of the flip-flop circuit 171 of the last stage may be connected to any one of the control signal lines 172 to 174, may be connected to another control signal, or may be connected to the flip-flop circuit of the other stage. It may be connected to the output terminal OUT of (171).

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor of the shift register circuit of the present invention is turned on at regular time intervals, thereby supplying a power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Embodiment 3]

In this embodiment, a configuration example in the case where the flip-flop circuit described in Embodiment 1 and the shift register circuit described in Embodiment 2 are used as a part of the driving circuit will be described.

A configuration example of a driving circuit applicable to the gate driver will be described with reference to FIGS. 20 to 27 . However, the driving circuits of FIGS. 20 to 27 can be applied to any circuit configuration as well as the gate driver.

20 shows one embodiment of the gate driver of the present invention. The gate driver of the present invention includes a shift register circuit 200 and a buffer circuit 201 .

As shown in the gate driver of FIG. 20 , the output terminal SRout of the shift register circuit 200 is connected to the output terminal GDout of the gate driver via the buffer circuit 201 .

Note that the shift register circuit 200 is the same as that described in the second embodiment.

The output terminals SRout1 to SRout4 and the output terminals SRoutn of the shift register circuit 200 are the same as those described in the second embodiment.

In addition, the output terminal GDout of the first stage of the gate driver of the present invention is denoted by GDout1, the output terminal GDout of the second stage is denoted by GDout2, and the output terminal GDout of the third stage is denoted by GDout3. and the output terminal GDout of the nth stage is denoted as GDoutn.

In addition, the buffer circuit 201 includes a logic circuit such as an inverter circuit, a buffer circuit, a NAND circuit, a NOR circuit, a tristate buffer circuit, and a PWC circuit, a switch, a resistor element, a capacitor, or other elements. In addition, various circuits can be configured by combining these elements and circuits.

In addition, in the gate driver of Fig. 20, power supply lines and control signal lines are not shown for convenience.

Further, when the shift register circuit 200 is configured using an n-channel transistor, it is preferable that the buffer circuit 201 is also configured using an n-channel transistor. When the shift register circuit 200 is configured using a p-channel transistor, the buffer circuit 201 is also preferably configured using a p-channel transistor.

Further, when the shift register circuit 200 is configured using an n-channel transistor, the output signal of the shift register circuit 200 is the same as that of the timing chart of FIG. When the shift register circuit 200 is configured using a p-channel transistor, the output signal of the shift register circuit 200 is the same as that of the timing chart of FIG.

Here, a specific configuration example of the buffer circuit 201 will be described. 21 to 27 show a configuration example of a gate driver including a buffer circuit. However, the buffer circuit 201 is not limited to the configuration of Figs.

Fig. 21 specifically shows one embodiment of a gate driver including the buffer circuit of the present invention. The gate driver of FIG. 21 includes a shift register circuit 200 and a buffer circuit 210 . The buffer circuit 210 includes an inverter circuit 211A of a first stage and an inverter circuit 211B of a second stage.

As shown in the gate driver of FIG. 21 , the output terminal SRout of the shift register circuit 200 is connected to the output terminal GDout of the gate driver via the buffer circuit 210 .

The connection relationship of the buffer circuit 210 will be described. The input terminal IN of the inverter circuit 211A is connected to the output terminal SRout of the shift register circuit 200, and the output terminal OUT of the inverter circuit 211A is connected to the input terminal IN of the inverter circuit 211B. ) is connected to The output terminal OUT of the inverter circuit 211B is connected to the output terminal GDout of the gate driver. That is, in the buffer circuit 210, two inverter circuits 211A and 211B are connected in series for each output terminal SRout of the shift register circuit 200 in each stage.

The operation of the gate driver of FIG. 21 in the case where the output terminal SRout is at the H level and when the output terminal SRout is at the L level will be described respectively.

First, a case in which the output terminal SRout is at the H level will be described. Since the output terminal SRout is connected to the output terminal GDout through the two inverter circuits 211A and 211B, the output terminal GDout becomes H level.

Next, the case where the output terminal SRout is at the L level will be described. Since the output terminal SRout is connected to the output terminal GDout via the two inverter circuits 211A and 211B, the output terminal GDout becomes L level.

By the above operation, when the output terminal SRout becomes the H level, the output terminal GDout becomes the H level. Also, when the output terminal SRout becomes the L level, the output terminal GDout becomes the L level.

In addition, since the inverter circuits 211A and 211B have a rectifying action, it is possible to suppress the noise of the output terminal SRout from affecting the output terminal GDout of the gate driver.

In the buffer circuit 210, two inverter circuits 211A and 211B are connected in series, but a plurality of inverter circuits 211 may be connected in series. For example, when an odd number of inverter circuits 211 are connected in series, the output terminal GDout has a level opposite to that of the output terminal SRout. When an even number of inverter circuits 211 are connected in series, the output terminal GDout is at the same level as the output terminal SRout.

In the buffer circuit 210, two inverter circuits 211A and 211B are connected in series, but a plurality of inverter circuits 211 may be connected in parallel. In this way, since the current density of the inverter circuits 211A, 211B becomes small, deterioration in characteristics of the elements constituting the inverter circuits 211A, 211B can be suppressed.

22 specifically shows another form of a gate driver including a buffer circuit of the present invention. The gate driver of FIG. 22 includes a shift register circuit 200 , a buffer circuit 220 , and a control signal line 222 . The buffer circuit 210 has a NAND circuit 221 .

As shown in the gate driver of FIG. 22 , the output terminal SRout of the shift register circuit 200 is connected to the output terminal GDout of the gate driver via the buffer circuit 220 .

The connection relationship of the buffer circuit 220 will be described. The input terminal IN1 of the NAND circuit 221 is connected to the control signal line 222 , the input terminal IN2 of the NAND circuit 221 is connected to the output terminal SRout of the shift register circuit 200 , The output terminal OUT of the circuit 221 is connected to the output terminal GDout of the gate driver.

In addition, an enable signal En is supplied to the control signal line 222 . The enable signal En is a digital signal.

The operation of the gate driver in Fig. 22 in the case where the control signal line 222 is at the H level and the case where the output terminal SRout is at the H level and the case where the output terminal SRout is at the L level will be described, respectively.

First, a case in which the control signal line 222 is at the H level and the output terminal SRout is at the H level will be described. The input terminal IN1 of the NAND circuit 221 goes to the H level, and the input terminal IN2 of the NAND circuit 221 goes to the H level. Accordingly, the output terminal OUT of the NAND circuit 221 becomes L level, and therefore the output terminal GDout of the gate driver becomes L level.

Next, the case where the control signal line 222 is at the H level and the output terminal SRout is at the L level will be described. The input terminal IN1 of the NAND circuit 221 goes to the H level, and the input terminal IN2 of the NAND circuit 221 goes to the L level. Accordingly, the output terminal OUT of the NAND circuit 221 becomes H level, and therefore the output terminal GDout of the gate driver becomes H level.

Next, the case where the control signal line 222 is at the L level and the output terminal SRout is at the H level will be described. The input terminal IN1 of the NAND circuit 221 goes to the L level, and the input terminal IN2 of the NAND circuit 221 goes to the H level. Accordingly, the output terminal OUT of the NAND circuit 221 becomes H level, and therefore the output terminal GDout of the gate driver becomes H level.

Next, the case where the control signal line 222 is at the L level and the output terminal SRout is at the L level will be described. The input terminal IN1 of the NAND circuit 221 goes to the L level, and the input terminal IN2 of the NAND circuit 221 goes to the L level. Accordingly, the output terminal OUT of the NAND circuit 221 becomes H level, and therefore the output terminal GDout of the gate driver becomes H level.

Through the above operation, when the control signal line 222 is at the H level, when the output terminal SRout is at the H level, the output terminal GDout of the gate driver becomes the L level, and when the output terminal SRout is at the L level, the output terminal GDout becomes the L level. The output terminal GDout of the gate driver becomes H level. When the control signal line 222 is at the L level, the output terminal GDout of the gate driver is at the H level regardless of the potential of the output terminal SRout.

As such, the output signal of the gate driver may be arbitrarily changed by the enable signal En. In the gate driver of Fig. 22, so-called pulse width control (PWC) can be performed.

Here, the pulse width control is performed using the fact that the output terminal GDout becomes the H level regardless of the potential of the output terminal SRout when the enable signal En is at the L level. That is, even when the output signal of the shift register circuit 200 has a pulse width (period) of any L level, by setting the enable signal En to the L level, the output signal can be shortened.

Further, although the NAND circuit 221 has two input terminals, if the output signal of the shift register circuit 200 is supplied to any one of the input terminals, the number of input terminals of the NAND circuit 221 may be any number. good. If there are a plurality of input terminals of the NAND circuit 221 , the buffer circuit 220 may more accurately control the output signal of the gate driver.

Also, as in the buffer circuit 240 of FIG. 24 , the output terminal SRout may be connected to the input terminal IN2 of the NAND circuit 221 via the inverter circuit 211 . In this case, when the control signal line 222 is at the H level, when the output terminal SRout is at the H level, the output terminal GDout of the gate driver becomes the H level, and when the output terminal SRout is at the L level, The output terminal GDout of the gate driver is at L level. When the control signal line 222 is at the L level, the output terminal GDout of the gate driver is at the H level regardless of the potential of the output terminal SRout.

Also, as in the buffer circuit 260 of FIG. 26 , the output terminal OUT of the NAND circuit 221 may be connected to the output terminal GDout of the gate driver via the inverter circuit 211 . In this case, when the control signal line 222 is at the H level, when the output terminal SRout is at the H level, the output terminal GDout of the gate driver becomes the H level, and when the output terminal SRout is at the L level, The output terminal GDout of the gate driver is at L level. When the control signal line 222 is at the L level, the output terminal GDout of the gate driver is at the L level regardless of the potential of the output terminal SRout.

In addition, although the enable signal En is supplied to the control signal line 222, the present invention is not limited to this.

For example, another control signal may be supplied to the control signal line 222 .

As another example, power may be supplied to the control signal line 222 .

23 specifically shows another form of a gate driver including a buffer circuit of the present invention. The gate driver of FIG. 23 includes a shift register circuit 200 , a buffer circuit 230 , and a control signal line 222 . The buffer circuit 230 has a NOR circuit 231 .

As shown in the gate driver of FIG. 23 , the output terminal SRout of the shift register circuit 200 is connected to the output terminal GDout of the gate driver via the buffer circuit 230 .

The connection relationship of the buffer circuit 230 will be described. The input terminal IN1 of the NOR circuit 231 is connected to the control signal line 222 , the input terminal IN2 of the NOR circuit 231 is connected to the output terminal SRout of the shift register circuit 200 , and the NOR The output terminal OUT of the circuit 231 is connected to the output terminal GDout of the gate driver.

In addition, an enable signal En is supplied to the control signal line 222 .

The operation of the gate driver in Fig. 23 when the control signal line 222 is at the H level and at the L level, and when the output terminal SRout of the shift register circuit 200 is at the H level and at the L level Each is explained.

First, the case where the control signal line 222 is at the H level and the output terminal SRout of the shift register circuit 200 is at the H level will be described. The input terminal IN1 of the NOR circuit 231 becomes H level, and the input terminal IN2 of the NOR circuit 231 becomes H level. Accordingly, the output terminal OUT of the NOR circuit is at the L level, and thus the output terminal GDout of the gate driver is at the L level.

Next, the case where the control signal line 222 is at the H level and the output terminal SRout of the shift register circuit 200 is at the L level will be described. The input terminal IN1 of the NOR circuit 231 becomes H level, and the input terminal IN2 of the NOR circuit 231 becomes L level. Accordingly, the output terminal OUT of the NOR circuit is at the L level, and thus the output terminal GDout of the gate driver is at the L level.

Next, the case where the control signal line 222 is at the L level and the output terminal SRout of the shift register circuit 200 is at the H level will be described. The input terminal IN1 of the NOR circuit 231 becomes the L level, and the input terminal IN2 of the NOR circuit 231 becomes the H level. Accordingly, the output terminal OUT of the NOR circuit is at the L level, and thus the output terminal GDout of the gate driver is at the L level.

Next, the case where the control signal line 222 is at the L level and the output terminal SRout of the shift register circuit 200 is at the L level will be described. The input terminal IN1 of the NOR circuit 231 becomes the L level, and the input terminal IN2 of the NOR circuit 231 becomes the L level. Accordingly, since the output terminal OUT of the NOR circuit becomes H level, the output terminal GDout of the gate driver becomes H level.

By the above operation, when the control signal line 222 is at the H level, the output terminal GDout of the gate driver becomes the L level regardless of the potential of the output terminal SRout. When the control signal line 222 is at the L level, when the output terminal SRout is at the H level, the output terminal GDout of the gate driver becomes the L level, and when the output terminal SRout is at the L level, the output of the gate driver The terminal GDout becomes H level.

As such, the output terminal GDout of the gate driver may be arbitrarily changed by the enable signal En. In the gate driver of Fig. 23, so-called pulse width control (PWC) can be performed.

Here, the pulse width control is performed using that the output terminal GDout becomes the L level regardless of the potential of the output terminal SRout when the enable signal En is at the H level. That is, no matter what H level pulse width (period) the output signal of the shift register circuit 200 has, by setting the enable signal En to H level, the output signal can be shortened.

Further, although the NOR circuit 231 has two input terminals, any number of input terminals of the NOR circuit 231 may be provided if the output signal of the shift register circuit 200 is supplied to any one of the input terminals. When there are a plurality of input terminals of the NOR circuit 231 , the buffer circuit 230 may more accurately control the output signal of the gate driver.

Also, as in the buffer circuit 250 of FIG. 25 , the output terminal SRout of the shift register circuit 200 may be connected to the input terminal IN2 of the NOR circuit 231 via the inverter circuit 211 . In this case, when the control signal line 222 is at the H level, the output terminal GDout of the gate driver becomes the L level regardless of the potential of the output terminal SRout. When the control signal line 222 is at the L level, the output terminal GDout of the gate driver becomes the H level when the output terminal SRout is at the H level, and the output terminal GDout of the gate driver becomes the H level when the output terminal SRout is at the L level. GDout) becomes L level.

Also, as in the buffer circuit 270 of FIG. 27 , the output terminal OUT of the NOR circuit 231 may be connected to the output terminal GDout of the gate driver via the inverter circuit 211 . In this case, when the control signal line 222 is at the H level, the output terminal GDout of the gate driver becomes the H level regardless of the potential of the output terminal SRout. When the control signal line 222 is at the L level, when the output terminal SRout is at the H level, the output terminal GDout of the gate driver becomes the H level, and when the output terminal SRout is at the L level, the output of the gate driver The terminal GDout outputs an L level signal.

Here, a configuration example applicable to the inverter circuit 211 will be described.

28 shows one form of the inverter circuit 211 . The inverter circuit 280 of FIG. 28 includes a transistor 281 and a transistor 282 .

As shown in the inverter circuit 280 of FIG. 28 , the first terminal of the transistor 281 is connected to the second power supply, and the second terminal of the transistor 281 is connected to the second terminal and the output terminal ( OUT), and the gate terminal of the transistor 281 is connected to the input terminal IN. A first terminal of the transistor 282 is connected to a first power supply, and a gate terminal of the transistor 282 is connected to a first power supply.

Further, a power supply potential VDD is supplied to the first power supply, and a power supply potential VSS is supplied to the second power supply. A potential difference (VDD-VSS) between the power source potential VDD of the first power source and the power source potential VSS of the second power source corresponds to the power source voltage of the inverter circuit 280 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

In addition, a digital control signal is supplied to the input terminal IN. Also, the output terminal OUT outputs an output signal.

In addition, each of the transistors 281 and 282 is an n-channel transistor.

The operation of the inverter circuit 280 in FIG. 28 in the case where the input terminal IN is at the H level and when the input terminal IN is at the L level will be described respectively.

First, a case in which the input terminal IN is at the H level will be described. When the input terminal IN goes to the H level, the transistor 281 is turned on. The output terminal OUT is electrically connected to the second power source through the transistor 281 , and is electrically connected to the first power source through the transistor 282 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 281 and the transistor 282 , and the output terminal OUT becomes L level.

Next, the case where the input terminal IN is at L level will be described. When the input terminal IN goes to the L level, the transistor 281 is turned off. The output terminal OUT is electrically connected to the first power supply through the transistor 282 , and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT becomes a value (VDD-Vth282) obtained by subtracting the threshold voltage Vth282 of the transistor 282 from the power supply potential VDD, and the output terminal OUT becomes H level.

In addition, the transistor 282 does not have to have rectification, and any element can be used as long as it generates a voltage when a current flows. For example, as in the inverter circuit 320 of FIG. 32 , the resistor 321 may be connected instead of the transistor 282 .

Here, the functions of the transistor 281 and the transistor 282 will be described below.

The transistor 281 has a function as a switch for selecting whether to connect or not connect the second power source and the output terminal OUT according to the potential of the input terminal IN. When the input terminal IN is at the H level, the transistor 281 has a function of supplying the power supply potential VSS to the output terminal OUT.

The transistor 282 functions as a diode.

29 shows another form of the inverter circuit 211 . The inverter circuit 290 of FIG. 29 has a transistor 291 , a transistor 292 , a transistor 293 , and a capacitor 294 having two electrodes. Also, the capacitor 294 is not necessarily required.

As shown in the inverter circuit 290 of FIG. 29 , the first terminal of the transistor 291 is connected to the second power supply, and the second terminal of the transistor 291 is the second terminal of the transistor 292 and the capacitor 294 . ) and the output terminal OUT, and the gate terminal of the transistor 291 is connected to the input terminal IN. A first terminal of transistor 292 is connected to a first power supply, and a gate terminal of transistor 292 is connected to a second terminal of transistor 293 and a first electrode of capacitor 294 . A first terminal of the transistor 293 is connected to a first power supply, and a gate terminal of the transistor 293 is connected to a first power supply.

In addition, the first power source, the second power source, the input terminal IN, and the output terminal OUT may be the same as those of FIG. 28 .

Further, each of the transistors 291 to 293 is an n-channel transistor.

The operation of the inverter circuit 290 in Fig. 29 in the case where the input terminal IN is at the H level and when the input terminal IN is at the L level will be described respectively.

First, a case in which the input terminal IN is at the H level will be described. When the input terminal IN goes to the H level, the transistor 291 is turned on. The potential of the gate terminal of the transistor 292 becomes a value (VDD-Vth293) obtained by subtracting the threshold voltage Vth293 of the transistor 293 from the power supply potential VDD, and the transistor 292 is turned on. Also, the gate terminal of the transistor 292 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 291 and electrically connected to the first power source through the transistor 292 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 291 and the transistor 292 , and the output terminal OUT becomes L level.

Next, the case where the input terminal IN is at L level will be described. When the input terminal IN goes to the L level, the transistor 291 is turned off. The potential of the gate terminal of the transistor 292 becomes a value (VDD-Vth293) obtained by subtracting the threshold voltage Vth293 of the transistor 293 from the power supply potential VDD, and the transistor 292 is turned on. Also, the gate terminal of the transistor 292 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 292 , and the potential of the output terminal OUT rises. The potential of the gate terminal of the transistor 292 rises to a value greater than or equal to the sum of the power supply potential VDD and the threshold voltage Vth292 of the transistor 292 according to the capacitive coupling of the capacitor 294, and the transistor 292 ) remains on. A so-called bootstrap operation is performed. Accordingly, the potential of the output terminal OUT at this time becomes VDD, and the output terminal OUT becomes H level.

As described above, in the inverter circuit 290 of FIG. 29 , the H-level potential of the output terminal OUT may be raised to the power supply potential VDD of the first power supply by the bootstrap operation.

In addition, the circuit configuration of the inverter circuit 290 of FIG. 29 is not limited to the circuit configuration of FIG. 29 as long as the bootstrap operation can be performed when the input terminal IN is at L level. When the input terminal IN is at the H level, a potential may be supplied to the gate terminal of the transistor 292 .

For example, as in the inverter circuit 330 of FIG. 33 , a transistor 331 may be added. This is because the potential of the output terminal OUT can be set to VSS when the output terminal OUT is at the L level. That is, since the transistor 331 is turned on when the input terminal IN is at the H level, the gate terminal of the transistor 292 becomes the L level. Then, the transistor 292 is turned off, and the output terminal OUT is electrically connected to only the second power source through the transistor 291 .

Also, the transistor 331 is an n-channel transistor.

As another example, as in the inverter circuit 360 of FIG. 36 , the first terminal of the transistor 293 may be connected to the input terminal INb. This is because the potential of the output terminal OUT can be set to VSS when the output terminal OUT is at the L level. That is, when the input terminal IN is at the H level, since the input terminal INb is at the L level, the gate terminal of the transistor 292 becomes the L level. Then, the transistor 292 is turned off, and the output terminal OUT is electrically connected to only the second power source through the transistor 291 .

In addition, an inverted signal of the signal of the input terminal IN is supplied to the input terminal INb. Also, a method of generating a signal supplied to the input terminal INb will be described.

For example, as shown in FIG. 124 , a signal from the input terminal IN may be supplied to the input terminal INb via the inverter circuit 1241 . In addition, as the inverter circuit 1241, the inverter circuit shown in Figs. 28 to 35 can be applied.

In addition, the inverted signal of the signal of the input terminal IN is not necessarily supplied to the input terminal INb. Hereinafter, the signal supplied to the input signal INb will be described.

For example, when the input terminal IN is connected to the output terminal SRoutn of the n-th stage, the input terminal INb may be connected to the output terminal SRoutn-1 of the n-th stage.

As another example, when the input terminal IN is connected to the output terminal SRoutn of the n-th stage, the input terminal INb may be connected to the output terminal SRoutn+1 of the n-th stage.

As another example, when the input terminal IN is connected to the output terminal SRout of the nth stage, the input terminal INb may be connected to the node N2 of the flip-flop circuit of the nth stage. This is because, in the non-selection period, the potential of the node N2 of the flip-flop circuit is inverted with the potential of the output terminal SRout, so the potential of the node N2 of the flip-flop circuit can be used as an inversion signal. . Accordingly, by supplying the potential of the node N2 of the flip-flop circuit to the input terminal INb of the inverter circuit 360, an inverter circuit for generating an inverted signal becomes unnecessary.

As another example, when a control signal (digital value) is supplied to the input terminal INb, the inverter circuit of FIG. 36 may operate as a tristate buffer circuit. This is because when the input terminal IN goes to the L level and the input terminal INb goes to the L level, the transistors 291 and 292 are turned off, and the output terminal OUT is not connected to any power supply. Because. Accordingly, the inverter circuit 360 may have a function as a tristate buffer circuit or an inverter circuit.

As such, a signal may be supplied to the input terminal INb of the inverter circuit 360 in various ways.

Below, the application example of FIG. 29 is further demonstrated.

As another example, as in the inverter circuit 390 of FIG. 39 , the first terminal and the gate terminal of the transistor 293 are connected to the input terminal INb, and a transistor 391 may be added. This is because, when the output terminal OUT is at the L level, the potential of the output terminal OUT can be set to VSS. That is, when the input terminal INb is at the L level, the gate terminal of the transistor 292 is at the L level. Then, the transistor 292 is turned off, and the output terminal OUT is electrically connected to only the second power source through the transistor 291 .

In addition, as the capacitor 294, any element can be used as long as it has a capacitive element. For example, instead of the capacitor 294 , as in the inverter circuit 300 of FIG. 30 , the inverter circuit 340 of FIG. 34 , the inverter circuit 370 of FIG. 37 , and the inverter circuit 400 of FIG. 40 . The transistor 301 , the transistor 341 , the transistor 371 , and the transistor 401 may be connected, respectively.

In addition, the capacitor 294 is not necessarily required as long as the capacitance between the second terminal and the gate terminal of the transistor 292 is sufficiently large. For example, as in the inverter circuit 310 of FIG. 31 , the inverter circuit 350 of FIG. 35 , the inverter circuit 380 of FIG. 38 , and the inverter circuit 410 of FIG. 41 , the capacitor 294 is connected. you don't have to

Here, the functions of the transistors 291 to 293 , the transistor 301 , the transistor 331 , the transistor 341 , and the capacitor 294 will be described below.

The transistor 291 has a function as a switch for selecting whether or not to connect the second power source and the output terminal OUT according to the potential of the input terminal IN. When the input terminal IN is at the H level, the transistor 291 has a function of supplying the power supply potential VSS to the output terminal OUT.

The transistor 292 has a function as a switch for selecting whether or not to connect the first power supply and the output terminal OUT.

The transistor 293 functions as a diode. In addition, the transistor 293 has a function of placing the gate terminal of the transistor 292 in a floating state.

The transistor 301 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 292 . When the input terminal IN is at the L level, the transistor 301 has a function of raising the potential of the gate terminal of the transistor 292 .

The transistor 331 has a function as a switch for selecting whether to connect or not connect the second power supply and the gate terminal of the transistor 292 according to the potential of the input terminal IN.

The transistor 341 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 292 . When the input terminal IN is at the L level, the transistor 341 has a function of raising the potential of the gate terminal of the transistor 292 by raising the potential of the output terminal OUT.

The capacitor 294 has a function for changing the potential of the gate terminal of the transistor 292 according to the potential of the output terminal OUT. When the input terminal IN is at the L level, the capacitor 294 has a function of raising the potential of the gate terminal of the transistor 292 by raising the potential of the output terminal OUT.

In this way, in the inverter circuits of Figs. 28 to 41, when the H level signal is output, the potential of the output terminal OUT can be freely changed by changing the power supply potential VDD. That is, the inverter circuits in Figs. 28 to 41 can operate not only as an inverter circuit, but also as a level shift circuit.

In Figs. 28 to 41, all inverter circuits configured using n-channel transistors have been described, but all of the inverter circuits may be configured using p-channel transistors. Here, the inverter circuits all constructed using p-channel transistors are shown in FIGS. 58 to 71.

58 shows one form of the inverter circuit 211. As shown in FIG. The inverter circuit 580 in FIG. 58 includes a transistor 581 and a transistor 582 .

As shown in the inverter circuit 580 of FIG. 58 , the first terminal of the transistor 581 is connected to the second power supply, and the second terminal of the transistor 581 is connected to the second terminal and the output terminal ( OUT), and the gate terminal of the transistor 581 is connected to the input terminal IN. A first terminal of the transistor 582 is connected to a first power supply, and a gate terminal of the transistor 582 is connected to a first power supply.

In addition, the power supply potential VSS is supplied to the first power supply, and the power supply potential VDD is supplied to the second power supply. A potential difference (VDD-VSS) between the power source potential VSS of the first power source and the power source potential VDD of the second power source corresponds to the power source voltage of the inverter circuit 580 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

In addition, a digital control signal is supplied to the input terminal IN. Also, the output terminal OUT outputs an output signal.

In addition, each of the transistors 581 and 582 is a p-channel transistor.

The operation of the inverter circuit 580 in Fig. 58 in the case where the input terminal IN is at the H level and when the input terminal IN is at the L level will be described respectively.

First, a case in which the input terminal IN is at the H level will be described. When the input terminal IN goes to the H level, the transistor 581 is turned off. The output terminal OUT is electrically connected to the first power supply through the transistor 582 , and the potential of the output terminal OUT decreases. At this time, the potential of the output terminal OUT becomes a value (VSS+Vth582|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth582 of the transistor 582, and the output terminal OUT ) becomes L level.

Next, the case where the input terminal IN is at L level will be described. When the input terminal IN goes to the L level, the transistor 581 is turned on. The output terminal OUT is electrically connected to the second power source through the transistor 581 and electrically connected to the first power source through the transistor 582 , so that the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 581 and the transistor 582 , and the output terminal OUT becomes H level.

In addition, the transistor 582 does not need to have rectification, and any element can be used as long as it generates a voltage when current flows. For example, as in the inverter circuit 620 of FIG. 62 , the resistor 621 may be connected instead of the transistor 582 .

Here, the functions of the transistor 581 and the transistor 582 will be described below.

The transistor 581 has a function as a switch for selecting whether to connect or not connect the second power source and the output terminal OUT according to the potential of the input terminal IN. When the input terminal IN is at the L level, the transistor 581 has a function of supplying the power supply potential VDD to the output terminal OUT.

The transistor 582 has a function as a diode.

59 shows another form of the inverter circuit 211 . The inverter circuit 590 shown in Fig. 59 includes a transistor 591, a transistor 592, a transistor 593, and a capacitor 594 having two electrodes. Also, the capacitor 594 is not necessarily required.

As shown in the inverter circuit 590 of FIG. 59 , the first terminal of the transistor 591 is connected to the second power supply, and the second terminal of the transistor 591 is the second terminal of the transistor 592 and the capacitor 594 . ), and is connected to the output terminal OUT, and the gate terminal of the transistor 591 is connected to the input terminal IN. A first terminal of transistor 592 is connected to a first power supply, and a gate terminal of transistor 592 is connected to a second terminal of transistor 593 and a first electrode of capacitor 594 . A first terminal of the transistor 593 is connected to a first power supply, and a gate terminal of the transistor 593 is connected to a first power supply.

In addition, the first power supply, the second power supply, the input terminal IN, and the output terminal OUT may be the same as those shown in FIG. 58 .

Further, each of the transistors 591 to 593 is a p-channel transistor.

The operation of the inverter circuit 590 in FIG. 59 in the case where the input terminal IN is at the H level and when the input terminal IN is at the L level will be described respectively.

First, a case in which the input terminal IN is at the H level will be described. When the input terminal IN goes to the H level, the transistor 591 is turned off. The potential of the gate terminal of the transistor 592 becomes a value (VSS+|Vth593|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth593) of the transistor 593, and the transistor 592 is turned on Also, the gate terminal of the transistor 592 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 592 , so that the potential of the output terminal OUT is lowered. The potential of the gate terminal of the transistor 592 is a value obtained by subtracting the absolute value (Vth592|) of the threshold voltage (Vth592) of the transistor 592 from the power supply potential (VSS) according to the capacitive coupling of the capacitor 594 ( VSS-|Vth592|) or less, and the transistor 592 continues to be on. A so-called bootstrap operation is performed. Accordingly, the potential of the output terminal OUT at this time becomes VSS, and the output terminal OUT becomes the L level.

Next, the case where the input terminal IN is at L level will be described. When the input terminal IN goes to the L level, the transistor 591 is turned on. The potential of the gate terminal of the transistor 592 becomes a value (VSS+Vth593|) that is the sum of the power supply potential (VSS) and the absolute value (|Vth593|) of the threshold voltage of the transistor 593, and the transistor ( 592) is turned on. Also, the gate terminal of the transistor 592 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 591 and electrically connected to the first power source through the transistor 592 , and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 591 and the transistor 592 , and the output terminal OUT becomes H level.

As described above, in the inverter circuit 590 of FIG. 59 , the L level potential of the output terminal OUT may be lowered to the power supply potential VSS of the first power supply by the bootstrap operation.

In addition, the circuit configuration of the inverter circuit 590 of FIG. 59 is not limited to the circuit configuration of FIG. 59 as long as the bootstrap operation can be performed when the input terminal IN is at the H level. When the input terminal IN is at the L level, a potential may be supplied to the gate terminal of the transistor 592 .

For example, as in the inverter circuit 630 of FIG. 63 , a transistor 631 may be added. This is because, when the output terminal OUT is at the H level, the potential of the output terminal OUT can be set to VDD. That is, since the transistor 631 is turned on when the input terminal IN is at the L level, the gate terminal of the transistor 592 becomes the H level. Then, the transistor 592 is turned off, and the output terminal OUT is electrically connected only to the second power source through the transistor 591 .

Also, the transistor 631 is a p-channel transistor.

As another example, as in the inverter circuit 660 of FIG. 66 , the first terminal of the transistor 593 may be connected to the input terminal INb. This is because, when the output terminal OUT is at the H level, the potential of the output terminal OUT can be set to VDD. That is, when the input terminal IN is at the L level, since the input terminal INb is at the H level, the gate terminal of the transistor 592 becomes the H level. Then, the transistor 592 is turned off, and the output terminal OUT is electrically connected only to the second power source through the transistor 591 .

In addition, an inverted signal of the signal of the input terminal IN is supplied to the input terminal INb. In addition, as the input terminal INb, the same thing as the input terminal INb of FIG. 36 can be used.

For example, as shown in FIG. 125 , a signal input to the input terminal IN may be supplied to the input terminal INb via the inverter circuit 1251 . Note that, as the inverter circuit 1251, the inverter circuits shown in Figs. 58 to 65 can be applied.

36 shows that the inverter circuit 360 also functions as a tristate buffer circuit by supplying a control signal to the input terminal INb. Here, the inverter circuit 660 shown in Fig. 66 can similarly function as a tristate buffer circuit by supplying a control signal to the input terminal INb. That is, when the input terminal IN goes to the H level and the input terminal INb goes to the H level, the transistor 591 and the transistor 592 are turned off, and the output terminal OUT is not connected to any power supply. , the inverter circuit 660 may function as a tristate buffer circuit.

Below, the application example of FIG. 59 is further demonstrated.

As another example, as in the inverter circuit 690 of FIG. 69 , the first terminal and the gate terminal of the transistor 593 are connected to the input terminal INb, and a transistor 631 may be added. This is because, when the output terminal OUT is at the H level, the potential of the output terminal OUT can be set to VDD. That is, when the input terminal INb is at the H level, the gate terminal of the transistor 592 is at the H level. Then, the transistor 592 is turned off, and the output terminal OUT is electrically connected only to the second power source through the transistor 591 .

In addition, as the capacitor 594, any element can be used as long as it has a capacitive element. For example, as in the inverter circuit 600 of FIG. 60 , the inverter circuit 640 of FIG. 64 , the inverter circuit 670 of FIG. 67 , and the inverter circuit 700 of FIG. 70 , instead of the capacitor 594 . The transistor 601 , the transistor 641 , the transistor 671 , and the transistor 701 may be connected respectively.

Further, the capacitor 594 is not necessarily required as long as the capacitance between the second terminal and the gate terminal of the transistor 592 is sufficiently large. For example, as in the inverter circuit 610 of FIG. 61 , the inverter circuit 650 of FIG. 65 , the inverter circuit 680 of FIG. 68 , and the inverter circuit 710 of FIG. 71 , the capacitor 594 is connected. you don't have to

Here, the functions of the transistors 591 to 593 , the transistor 601 , the transistor 631 , the transistor 641 , and the capacitor 594 will be described below.

The transistor 591 has a function as a switch that determines whether or not to connect the second power source and the output terminal OUT according to the potential of the input terminal IN. When the input terminal IN is at the L level, the transistor 591 has a function of supplying the power supply potential VDD to the output terminal OUT.

The transistor 592 has a function as a switch for determining whether or not to connect the first power supply and the output terminal OUT.

The transistor 593 functions as a diode. In addition, the transistor 593 has a function of putting the gate terminal of the transistor 592 in a floating state.

The transistor 601 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 592 . When the input terminal IN is at the H level, the transistor 601 has a function of lowering the potential of the gate terminal of the transistor 592 .

The transistor 631 has a function as a switch that determines whether or not to connect the second power source and the gate terminal of the transistor 592 according to the potential of the input terminal IN. When the input terminal IN is at the L level, the transistor 631 has a function of supplying the power supply potential VDD to the gate terminal of the transistor 592 .

The transistor 641 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 592 . When the input terminal IN is at the L level, the capacitor 594 has a function of lowering the potential of the gate terminal of the transistor 592 by the fall of the potential of the output terminal OUT.

The capacitor 594 has a function for changing the potential of the gate terminal of the transistor 592 according to the potential of the output terminal OUT. When the input terminal IN is at the H level, the capacitor 594 has a function of lowering the potential of the gate terminal of the transistor 592 by the fall of the potential of the output terminal OUT.

In this way, the inverter circuits of FIGS. 58 to 71 can freely change the potential of the output terminal OUT by changing the power supply potential VSS when outputting the L level signal. That is, the inverter circuits of FIGS. 58 to 71 can operate not only as an inverter circuit, but also as a level shift circuit.

Here, some configuration examples applicable to the NAND circuit 221 will be described.

42 shows one form of the NAND circuit 221 . The NAND circuit 420 of FIG. 42 includes a transistor 421 , a transistor 422 , and a transistor 423 .

As shown in the NAND circuit 420 of FIG. 42 , a first terminal of the transistor 421 is connected to a second power source, a second terminal of the transistor 421 is connected to a first terminal of the transistor 422 , The gate terminal of the transistor 421 is connected to the input terminal IN1. A second terminal of the transistor 422 is connected to the first terminal and the output terminal OUT of the transistor 423 , and a gate terminal of the transistor 422 is connected to the input terminal IN2 . A second terminal of the transistor 423 is connected to the first power supply, and a gate terminal of the transistor 423 is connected to the first power supply.

Further, a power supply potential VDD is supplied to the first power supply, and a power supply potential VSS is supplied to the second power supply. A potential difference (VDD-VSS) between the power source potential VDD of the first power source and the power source potential VSS of the second power source corresponds to the power source voltage of the NAND circuit 420 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

In addition, a digital control signal is supplied to each of the input terminal IN1 and the input terminal IN2 . Also, the output terminal OUT outputs an output signal.

Further, each of the transistors 421 to 423 is an n-channel transistor.

The operation of the NAND circuit 420 in Fig. 42 in the case where the input terminal IN1 is at the H level and the L level, and when the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 421 is turned on. When the input terminal IN2 becomes H level, the transistor 422 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 421 and the transistor 422 , and is electrically connected to the first power source through the transistor 423 , so that the potential of the output terminal OUT is is lowered At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 421 , the transistor 422 , and the transistor 423 , and the output terminal OUT becomes L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 421 is turned on. When the input terminal IN2 becomes L level, the transistor 422 is turned off.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 423 , and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT becomes a value (VDD-Vth423) obtained by subtracting the threshold voltage Vth423 of the transistor 423 from the power supply potential VDD, and the output terminal OUT becomes H level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 421 is turned off. When the input terminal IN2 becomes H level, the transistor 422 is turned on.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 423 , and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT becomes a value (VDD-Vth423) obtained by subtracting the threshold voltage Vth423 of the transistor 423 from the power supply potential VDD, and the output terminal OUT becomes H level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 421 is turned off. When the input terminal IN2 becomes L level, the transistor 422 is turned off.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 423 , and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT becomes a value (VDD-Vth423) obtained by subtracting the threshold voltage Vth423 of the transistor 423 from the power supply potential VDD, and the output terminal OUT becomes H level.

In addition, the transistor 423 does not need to have rectification, and any element can be used as long as it generates a voltage when current flows. For example, as in the NAND circuit 460 of FIG. 46 , a resistor element 461 may be connected instead of the transistor 423 .

Here, the functions of the transistors 421 to 423 will be described below.

The transistor 421 has a function as a switch that determines whether or not to connect the second power source and the first terminal of the transistor 422 according to the potential of the input terminal IN1 .

The transistor 422 has a function as a switch that determines whether or not to connect the second terminal of the transistor 421 and the output terminal OUT according to the potential of the input terminal IN2 .

The transistor 423 has a function as a diode.

43 shows another form of the NAND circuit 221 . The NAND circuit 430 of FIG. 43 includes a transistor 431 , a transistor 432 , a transistor 433 , a transistor 434 , and a capacitor 435 .

As shown in the NAND circuit 430 of FIG. 43 , the first terminal of the transistor 431 is connected to a second power supply, the second terminal of the transistor 431 is connected to the first terminal of the transistor 432 , A gate terminal of the transistor 431 is connected to the input terminal IN1 . A second terminal of the transistor 432 is connected to a second terminal of the transistor 433 , a second electrode of the capacitor 435 , and an output terminal OUT, and a gate terminal of the transistor 432 is connected to an input terminal IN2 . is connected to A first terminal of the transistor 433 is connected to a first power supply, and a gate terminal of the transistor 433 is connected to a second terminal of the transistor 434 and a first electrode of the capacitor 435 . A first terminal of the transistor 434 is connected to a first power supply, and a gate terminal of the transistor 434 is connected to a first power supply.

In addition, the first power source, the second power source, the input terminal IN1 , the input terminal IN2 , and the output terminal OUT may be the same as those shown in FIG. 42 .

Further, each of the transistors 431 to 434 is an n-channel transistor.

The operation of the NAND circuit 430 in Fig. 43 in the case where the input terminal IN1 is at the H level and the L level, and the case where the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 431 is turned on. When the input terminal IN2 becomes H level, the transistor 432 is turned on. The potential of the gate terminal of the transistor 433 becomes a value (VDD-Vth434) obtained by subtracting the threshold voltage Vth434 of the transistor 434 from the power supply potential VDD, and the transistor 433 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 431 and the transistor 432 , and is electrically connected to the first power source through the transistor 433 , so that the potential of the output terminal OUT is is lowered At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 431 , the transistor 432 , and the transistor 433 , and the output terminal OUT becomes the L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 431 is turned on. When the input terminal IN2 becomes L level, the transistor 432 is turned off. The potential of the gate terminal of the transistor 433 becomes a value (VDD-Vth434) obtained by subtracting the threshold voltage Vth434 of the transistor 434 from the power supply potential VDD, and the transistor 433 is turned on. Also, the gate terminal of the transistor 433 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 433 , and the potential of the output terminal OUT rises. The potential of the gate terminal of the transistor 433 increases to a value greater than or equal to the sum of the power supply potential VDD and the threshold voltage Vth433 of the transistor 433 according to the capacitive coupling of the capacitor 435 , ) remains on. A so-called bootstrap operation is performed. At this time, the potential of the output terminal OUT becomes VDD, and the output terminal OUT becomes H level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 431 is turned off. When the input terminal IN2 becomes H level, the transistor 432 is turned on. The potential of the gate terminal of the transistor 433 becomes a value (VDD-Vth434) obtained by subtracting the threshold voltage Vth434 of the transistor 434 from the power supply potential VDD, and the transistor 433 is turned on. Also, the gate terminal of the transistor 433 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 433 , and the potential of the output terminal OUT rises. The potential of the gate terminal of the transistor 433 increases to a value greater than or equal to the sum of the power supply potential VDD and the threshold voltage Vth433 of the transistor 433 according to the capacitive coupling of the capacitor 435 , ) remains on. A so-called bootstrap operation is performed. Accordingly, the potential of the output terminal OUT at this time becomes VDD, and the output terminal OUT becomes H level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 431 is turned off. When the input terminal IN2 becomes L level, the transistor 432 is turned off. The potential of the gate terminal of the transistor 433 becomes a value (VDD-Vth434) obtained by subtracting the threshold voltage Vth434 of the transistor 434 from the power supply potential VDD, and the transistor 433 is turned on. Also, the gate terminal of the transistor 433 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 433 , and the potential of the output terminal OUT rises. The potential of the gate terminal of the transistor 433 increases to a value greater than or equal to the sum of the power supply potential VDD and the threshold voltage Vth433 of the transistor 433 according to the capacitive coupling of the capacitor 435 , ) remains on. A so-called bootstrap operation is performed. Accordingly, the potential of the output terminal OUT at this time becomes VDD, and the output terminal OUT becomes H level.

As described above, in the NAND circuit 430 of FIG. 43 , the H-level potential of the output terminal OUT may be raised to the power supply potential VDD of the first power supply by the bootstrap operation.

Further, the circuit configuration of the NAND circuit 430 in Fig. 43 is. If the bootstrap operation can be performed when the input terminal IN1 or the input terminal IN2 is at the L level, the circuit configuration of FIG. 43 is not limited. When the input terminal IN1 and the input terminal IN2 are at the H level, a potential may be supplied to the gate terminal of the transistor 433 .

For example, as in the NAND circuit 470 of FIG. 47 , a transistor 471 and a transistor 472 may be added. This is because, when the output terminal OUT is at the L level, the potential of the output terminal OUT can be set to VSS. That is, since the transistor 471 and the transistor 472 are turned on when the input terminal IN1 and the input terminal IN2 are at the H level, the gate terminal of the transistor 433 becomes the L level. Then, the transistor 433 is turned off, and the output terminal OUT is electrically connected to only the second power source through the transistor 431 and the transistor 432 .

Also, the transistors 471 and 472 are n-channel transistors, respectively.

In addition, as the capacitor 435, any element may be used as long as it has a capacitive element. For example, as in the NAND circuit 440 of FIG. 44 and the NAND circuit 480 of FIG. 48, the transistor 441 and the transistor 481 may be connected instead of the capacitor 435, respectively.

Further, the capacitor 435 is not necessarily required as long as the capacitance between the second terminal and the gate terminal of the transistor 433 is sufficiently large. For example, as in the NAND circuit 450 of FIG. 45 and the NAND circuit 490 of FIG. 49, the capacitor 435 may not be connected.

Here, the functions of the transistors 431 to 434 , the transistor 441 , the transistor 471 , the transistor 472 , the transistor 481 , and the capacitor 435 will be described below.

The transistor 431 has a function as a switch that determines whether or not to connect the second power supply and the first terminal of the transistor 432 according to the potential of the input terminal IN1 .

The transistor 432 has a function as a switch that determines whether to connect or not connect the second terminal of the transistor 432 and the output terminal OUT according to the potential of the input terminal IN2 .

The transistor 433 has a function as a switch that determines whether or not to connect the first power supply and the output terminal OUT.

The transistor 434 has a function as a diode. In addition, the transistor 434 has a function of putting the gate terminal of the transistor 433 in a floating state.

The transistor 441 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 433 . When the input terminal IN1 or the input terminal IN2 is at the L level, the transistor 441 has a function of raising the potential of the gate terminal of the transistor 433 .

The transistor 471 has a function as a switch that determines whether or not to connect the second power supply and the first terminal of the transistor 472 according to the potential of the input terminal IN1 .

The transistor 472 has a function as a switch that determines whether or not to connect the first terminal of the transistor 471 and the gate terminal of the transistor 433 according to the potential of the input terminal IN2 .

The transistor 481 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 433 . When the input terminal IN1 or the input terminal IN2 is at the L level, the transistor 441 has a function of raising the potential of the gate terminal of the transistor 433 .

The capacitor 435 has a function for changing the potential of the gate terminal of the transistor 433 according to the potential of the output terminal OUT. When the input terminal IN1 or the input terminal IN2 is at the L level, the capacitor 435 has a function of raising the potential of the gate terminal of the transistor 433 .

In this way, in the NAND circuits of Figs. 42 to 49, the potential of the output terminal OUT can be freely changed by changing the power supply potential VDD when outputting an H-level signal. That is, the NAND circuits in Figs. 42 to 49 can operate not only as an inverter circuit but also as a level shift circuit.

42 to 49, the NAND circuits configured using n-channel transistors are all described. However, all of the NAND circuits may be configured using p-channel transistors. Here, NAND circuits all constructed using p-channel transistors are shown in Figs.

80 shows another form of the NAND circuit 221 . The NAND circuit 800 of FIG. 80 includes a transistor 801 , a transistor 802 , and a transistor 803 .

As shown in the NAND circuit 800 of FIG. 80 , the first terminal of the transistor 801 is connected to the second power supply, and the second terminal of the transistor 801 is the second terminal of the transistor 802 and the transistor 803 . ) and the output terminal OUT, and the gate terminal of the transistor 801 is connected to the input terminal IN1. A first terminal of the transistor 802 is connected to a second power supply, and a gate terminal of the transistor 802 is connected to an input terminal IN2 . A first terminal of the transistor 803 is connected to a first power supply, and a gate terminal of the transistor 803 is connected to a first power supply.

In addition, the power supply potential VSS is supplied to the first power supply, and the power supply potential VDD is supplied to the second power supply. A potential difference (VDD-VSS) between the power source potential VSS of the first power source and the power source potential VDD of the second power source corresponds to the power source voltage of the NAND circuit 800 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

In addition, a digital control signal is supplied to each of the input terminal IN1 and the input terminal IN2. Also, the output terminal OUT outputs an output signal.

Further, each of the transistors 801 to 803 is a p-channel transistor.

The operation of the NAND circuit 800 in Fig. 80 in the case where the input terminal IN1 is at the H level and the L level, and the case where the input terminal IN2 is at the H level and the L level, respectively, will be described. .

First, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 801 is turned off. When the input terminal IN2 becomes H level, the transistor 802 is turned off.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 803, and the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT becomes a value (VSS+Vth803|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth803 of the transistor 803, and the output terminal OUT ) becomes L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 801 is turned off. When the input terminal IN2 becomes L level, the transistor 802 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power supply via the transistor 802 and electrically connected to the first power supply via the transistor 803 , so that the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 802 and the transistor 803 , and the output terminal OUT becomes H level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 801 is turned on. When the input terminal IN2 becomes H level, the transistor 802 is turned off.

Accordingly, the output terminal OUT is electrically connected to the second power supply via the transistor 801 and electrically connected to the first power supply via the transistor 803 , so that the potential of the output terminal OUT rises. The potential of the output terminal OUT at this time is determined by the operating points of the transistor 801 and the transistor 803, so that the output terminal OUT is at the H level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 801 is turned on. When the input terminal IN2 becomes L level, the transistor 802 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 801 , electrically connected to the second power source through the transistor 802 , and electrically connected to the first power source through the transistor 803 . connected, and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 801 , the transistor 802 , and the transistor 803 , and the output terminal OUT becomes H level.

In addition, the transistor 803 does not need to have rectification, and any element can be used as long as it generates a voltage when current flows. For example, as in the NAND circuit 840 of FIG. 84, the resistor 841 may be connected instead of the transistor 803.

Here, the functions of the transistors 801 to 803 will be described below.

The transistor 801 has a function as a switch that determines whether or not to connect the second power supply and the output terminal OUT according to the potential of the input terminal IN1 . When the input terminal IN1 is at the L level, the transistor 801 has a function of supplying the power supply potential VDD to the output terminal OUT.

The transistor 802 has a function as a switch that determines whether or not to connect the second power supply and the output terminal OUT according to the potential of the input terminal IN2 . When the input terminal IN2 is at the L level, the transistor 802 has a function of supplying the power supply potential VDD to the output terminal OUT.

The transistor 803 functions as a diode.

81 shows another form of the NAND circuit 221 . The NAND circuit 810 of FIG. 81 includes a transistor 811 , a transistor 812 , a transistor 813 , a transistor 814 , and a capacitor 815 .

As shown in the NAND circuit 810 of FIG. 81 , the first terminal of the transistor 811 is connected to the second power supply, and the second terminal of the transistor 811 is the second terminal of the transistor 812 and the transistor 813 . ), is connected to the first electrode of the capacitor 815 , and the gate terminal of the transistor 811 is connected to the input terminal IN1 . A first terminal of the transistor 812 is connected to the second power supply, and a gate terminal of the transistor 812 is connected to the input terminal IN2 . A first terminal of the transistor 813 is connected to a first power supply, and a gate terminal of the transistor 813 is connected to a second terminal of the transistor 814 and a second electrode of the capacitor 815 . A first terminal of the transistor 814 is connected to a first power supply, and a gate terminal of the transistor 814 is connected to a first power supply.

In addition, the first power source, the second power source, the input terminal IN1 , the input terminal IN2 , and the output terminal OUT may be the same as those shown in FIG. 80 .

Further, each of the transistors 811 to 814 is a p-channel transistor.

The operation of the NAND circuit 810 in Fig. 81 in the case where the input terminal IN1 is at the H level and the L level, and when the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 811 is turned off. When the input terminal IN2 becomes H level, the transistor 812 is turned off. The potential of the gate terminal of the transistor 813 becomes a value (VSS+|Vth(814)|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth814 of the transistor 814, and the transistor (813) is turned on. Also, the gate terminal of the transistor 813 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 813 , and the potential of the output terminal OUT is lowered. The potential of the gate terminal of the transistor 813 is a value obtained by subtracting the absolute value of the threshold voltage Vth813 of the transistor 813 from the power supply potential VSS according to the capacitive coupling of the capacitor 815 (VSS-|Vth813| ), and the transistor 813 continues to be on. A so-called bootstrap operation is performed. At this time, the potential of the output terminal OUT becomes VSS, and the output terminal OUT becomes L level.

Next, the case where the input terminal IN is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 811 is turned off. When the input terminal IN2 becomes L level, the transistor 812 is turned on. The potential of the gate terminal of the transistor 813 becomes a value (Vss+|Vth814|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth814) of the transistor 814, and the transistor 813 is turned on Also, the gate terminal of the transistor 813 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 812 and electrically connected to the first power source through the transistor 813 , so that the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 812 and the transistor 813 , and the output terminal OUT is at the H level.

Next, the case where the input terminal IN is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 811 is turned on. When the input terminal IN2 becomes H level, the transistor 812 is turned off. The potential of the gate terminal of the transistor 813 becomes a value (Vss+Vth(814)|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth814 of the transistor 814 , the transistor (813) is turned on. Also, the gate terminal of the transistor 813 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power supply via the transistor 811 and electrically connected to the first power supply via the transistor 813 , so that the potential of the output terminal OUT increases. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 811 and the transistor 813 , and the output terminal OUT becomes H level.

Next, the case where the input terminal IN is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 811 is turned on. When the input terminal IN2 becomes L level, the transistor 812 is turned on. The potential of the gate terminal of the transistor 813 becomes a value (Vss+Vth(814)|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth814 of the transistor 814 , the transistor (813) is turned on. Also, the gate terminal of the transistor 813 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 811 , electrically connected to the second power source through the transistor 812 , and electrically connected to the first power source through the transistor 813 . connected, and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 811 , the transistor 812 , and the transistor 813 , and the output terminal OUT becomes H level.

As described above, in the NAND circuit 810 of FIG. 81 , the L-level potential of the output terminal OUT can be lowered to the power supply potential VSS of the first power supply by the bootstrap operation.

In addition, the circuit configuration of the NAND circuit 810 in FIG. 81 is not limited to the circuit configuration in FIG. 81 as long as the bootstrap operation can be performed when the input terminal IN1 and the input terminal IN2 are at H level. When the input terminal IN1 or the input terminal IN2 is at the L level, a potential may be supplied to the gate terminal of the transistor 813 .

For example, as in the NAND circuit 850 of FIG. 85, a transistor 851 and a transistor 852 may be added. This is because the potential of the output terminal OUT can be set to VDD when the output terminal OUT is at the H level. That is, since the transistor 851 or the transistor 852 is turned on when the input terminal IN1 or the input terminal IN2 is at the L level, the gate terminal of the transistor 813 becomes the H level. Then, the transistor 813 is turned off, and the output terminal OUT is electrically connected only to the second power source through the transistor 811 or the transistor 812 .

In addition, each of the transistors 851 and 852 is a p-channel transistor.

In addition, as the capacitor 815, any element can be used as long as it has a capacitive element. For example, as in the NAND circuit 820 of FIG. 82 and the NAND circuit 860 of FIG. 86, the transistor 821 and the transistor 861 may be connected instead of the capacitor 815, respectively.

Further, the capacitor 815 is not necessarily required as long as the capacitance between the second terminal and the gate terminal of the transistor 813 is sufficiently large. For example, as in the NAND circuit 830 of FIG. 83 and the NAND circuit 870 of FIG. 87, the capacitor 815 may not be connected.

Here, the functions of the transistors 811 to 814 , the transistor 821 , the transistor 851 , the transistor 852 , the transistor 861 , and the capacitor 815 will be described below.

The transistor 811 has a function as a switch that determines whether or not to connect the second power source and the output terminal OUT according to the potential of the input terminal IN1 . When the input terminal IN1 is at the L level, the transistor 811 has a function of supplying the power supply potential VDD to the output terminal OUT.

The transistor 812 has a function of a switch that determines whether or not to connect the second power source and the output terminal OUT according to the potential of the input terminal IN2 . When the input terminal IN2 is at the L level, the transistor 812 has a function of supplying the power supply potential VDD to the output terminal OUT.

The transistor 813 has a function as a switch for determining whether or not to connect the first power supply and the output terminal OUT.

The transistor 814 has a function as a diode. In addition, the transistor 814 has a function of putting the gate terminal of the transistor 813 in a floating state.

The transistor 821 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 813 . When the input terminal IN1 and the input terminal IN2 are at the H level, the transistor 821 has a function of lowering the potential of the gate terminal of the transistor 813 .

The transistor 851 has a function as a switch that determines whether or not to connect the second power source and the gate terminal of the transistor 813 according to the potential of the input terminal IN1 . When the input terminal IN1 is at L level, the transistor 851 has a function of supplying the power supply potential VDD to the gate terminal of the transistor 813 .

The transistor 852 has a function as a switch that determines whether or not to connect the second power source and the gate terminal of the transistor 813 according to the potential of the input terminal IN2 . When the input terminal IN2 is at L level, the transistor 852 has a function of supplying the power supply potential VDD to the gate terminal of the transistor 813 .

The transistor 861 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 813 . When the input terminal IN1 and the input terminal IN2 are at the H level, the transistor 861 has a function of lowering the potential of the gate terminal of the transistor 813 .

The capacitor 815 has a function for changing the potential of the gate terminal of the transistor 813 according to the potential of the output terminal OUT. When the input terminal IN1 or the input terminal IN2 is at the H level, the capacitor 815 has a function of lowering the potential of the gate terminal of the transistor 813 .

In this way, in the NAND circuits of Figs. 81 to 87, the potential of the output terminal OUT can be freely changed by changing the power supply potential VSS when outputting the L-level signal. That is, the NAND circuits in Figs. 81 to 87 can operate not only as NAND circuits, but also as level shift circuits.

Here, some structural examples applicable to the NOR circuit 231 will be described.

50 shows one form of the NOR circuit 231 . The NOR circuit 500 of FIG. 50 includes a transistor 501 , a transistor 502 , and a transistor 503 .

As shown in the NOR circuit 500 of FIG. 50 , the first terminal of the transistor 501 is connected to the second power supply, and the second terminal of the transistor 501 is the second terminal of the transistor 502 and the transistor 503 . ) and the output terminal OUT, and the gate terminal of the transistor 501 is connected to the input terminal IN1. A first terminal of the transistor 502 is connected to a second power supply, and a gate terminal of the transistor 502 is connected to an input terminal IN2 . A first terminal of the transistor 503 is connected to a first power supply, and a gate terminal of the transistor 503 is connected to a first power supply.

Further, a power supply potential VDD is supplied to the first power supply, and a power supply potential VSS is supplied to the second power supply. A potential difference (VDD-VSS) between the power supply potential VDD of the first power supply and the power supply potential VSS of the second power supply corresponds to the power supply voltage of the NOR circuit 500 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

In addition, a digital control signal is supplied to each of the input terminal IN1 and the input terminal IN2. Also, the output terminal OUT outputs an output signal.

Further, each of the transistors 501 to 503 is an n-channel transistor.

The operation of the NOR circuit 500 of FIG. 50 in the case where the input terminal IN1 is at the H level and the L level, and the case where the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 501 is turned on. When the input terminal IN2 becomes H level, the transistor 502 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power supply via the transistor 501 and the transistor 502 , and electrically connected to the first power supply via the transistor 503 , so that the potential of the output terminal OUT is is lowered The potential of the output terminal OUT at this time is determined by the operating points of the transistor 501, the transistor 502, and the transistor 503, and the output terminal OUT is at the L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 501 is turned on. When the input terminal IN2 becomes L level, the transistor 502 is turned off.

Accordingly, the output terminal OUT is electrically connected to the second power supply via the transistor 501 and electrically connected to the first power supply via the transistor 503 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 501 and the transistor 503, so that the output terminal OUT is at the L level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 501 is turned off. When the input terminal IN2 becomes H level, the transistor 502 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power supply via the transistor 502 and electrically connected to the first power supply via the transistor 503 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT is determined by the operating points of the transistors 502 and 503, so that the output terminal OUT is at L level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 501 is turned off. When the input terminal IN2 becomes L level, the transistor 502 is turned off.

Accordingly, the output terminal OUT is electrically connected to the first power supply via the transistor 503, and the potential of the output terminal OUT rises. At this time, the potential of the output terminal OUT becomes a value (VDD-Vth503) obtained by subtracting the threshold voltage Vth503 of the transistor 503 from the power supply potential VDD, and the output terminal OUT becomes H level.

In addition, the transistor 503 does not need to have rectification, and any element can be used as long as it generates a voltage when a current flows. For example, as in the NOR circuit 540 in FIG. 54 , a resistor 541 may be connected instead of the transistor 503 .

Here, the functions of the transistors 501 to 503 will be described below.

The transistor 501 has a function as a switch for selecting whether to connect or not connect the second power source and the output terminal OUT according to the potential of the input terminal IN1 .

The transistor 502 has a function as a switch that selects whether or not to connect the second power source and the output terminal OUT according to the potential of the input terminal IN2 .

The transistor 503 functions as a diode.

51 shows another form of the NOR circuit 231 . The NOR circuit 510 of FIG. 51 includes a transistor 511 , a transistor 512 , a transistor 513 , a transistor 514 , and a capacitor 515 having two electrodes.

As shown in the NOR circuit 510 of FIG. 51 , the first terminal of the transistor 511 is connected to the second power supply, and the second terminal of the transistor 511 is the second terminal of the transistor 512 and the transistor 513 . ), the second electrode of the capacitor 515 , and the output terminal OUT, and the gate terminal of the transistor 511 is connected to the input terminal IN1 . A first terminal of the transistor 512 is connected to the second power supply, and a gate terminal of the transistor 512 is connected to the input terminal IN2 . A first terminal of the transistor 513 is connected to a first power supply, and a gate terminal of the transistor 513 is connected to a second terminal of the transistor 514 and a first electrode of the capacitor 515 . A first terminal of the transistor 514 is connected to a first power supply, and a gate terminal of the transistor 514 is connected to a first power supply.

In addition, the first power source, the second power source, the input terminal IN1 , the input terminal IN2 , and the output terminal OUT may be the same as those of FIG. 50 .

Further, each of the transistors 511 to 514 is an n-channel transistor.

The operation of the NOR circuit 510 of FIG. 51 in the case where the input terminal IN1 is at the H level and the L level, and the case where the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 511 is turned on. When the input terminal IN2 becomes H level, the transistor 512 is turned on. The potential of the gate terminal of the transistor 513 becomes a value (VDD-Vth514) obtained by subtracting the threshold voltage Vth514 of the transistor 514 from the power supply potential VDD, and the transistor 513 is turned on. Also, the gate terminal of the transistor 513 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 511 and the transistor 512 , and is electrically connected to the first power source through the transistor 513 , so that the potential of the output terminal OUT is is lowered At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 511 , the transistor 512 , and the transistor 513 , and the output terminal OUT becomes the L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 511 is turned on. When the input terminal IN2 becomes L level, the transistor 512 is turned off. The potential of the gate terminal of the transistor 513 becomes a value (VDD-Vth514) obtained by subtracting the threshold voltage Vth514 of the transistor 514 from the power supply potential VDD, and the transistor 513 is turned on. Also, the gate terminal of the transistor 513 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 511 and electrically connected to the first power source through the transistor 513 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 511 , the transistor 512 , and the transistor 513 , and the output terminal OUT becomes L level.

Next, the case where the input terminal IN is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 511 is turned off. When the input terminal IN2 becomes H level, the transistor 512 is turned on. The potential of the gate terminal of the transistor 513 becomes a value (VDD-Vth514) obtained by subtracting the threshold voltage Vth514 of the transistor 514 from the power supply potential VDD, and the transistor 513 is turned on. Also, the gate terminal of the transistor 513 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 512 and electrically connected to the first power source through the transistor 513 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 511 , the transistor 512 , and the transistor 513 , and the output terminal OUT becomes L level.

Next, the case where the input terminal IN is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 511 is turned off. When the input terminal IN2 becomes L level, the transistor 512 is turned off. The potential of the gate terminal of the transistor 513 becomes a value (VDD-Vth514) obtained by subtracting the threshold voltage Vth514 of the transistor 514 from the power supply potential VDD, and the transistor 513 is turned on. Also, the gate terminal of the transistor 513 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 513 , and the potential of the output terminal OUT rises. The potential of the gate terminal of the transistor 513 increases to a value equal to or greater than the sum of the power supply potential VDD and the threshold voltage Vth513 of the transistor 513 according to the capacitive coupling of the capacitor 515 , ) remains on. A so-called bootstrap operation is performed. At this time, the potential of the output terminal OUT becomes VDD, and the output terminal OUT becomes H level.

As described above, in the NOR circuit 510 of FIG. 51 , the potential of the output terminal OUT can be increased from the H level to the power supply potential VDD of the first power supply by the bootstrap operation.

In addition, the NOR circuit 510 of FIG. 51 is not limited to the circuit configuration of FIG. 51 as long as it can perform a bootstrap operation when the input terminal IN1 and the input terminal IN2 are at L level. When the input terminal IN1 or the input terminal IN2 is at the H level, a potential may be supplied to the gate terminal of the transistor 513 .

For example, like the NOR circuit 550 in FIG. 55 , a transistor 551 and a transistor 552 may be added. This is because, when the output terminal OUT is at the L level, the potential of the output terminal OUT can be set to VSS. That is, when either or both of the input terminal IN1 and the input terminal IN2 are at the H level, either or both of the transistor 551 and the transistor 552 are turned on, so that the The gate terminal goes to L level, then the transistor 513 is turned off, and the output terminal OUT is electrically connected only to the second power supply via either or both of the transistor 511 and the transistor 512 . Because.

In addition, each of the transistors 551 and 552 is an n-channel transistor.

In addition, as the capacitor 515, any element can be used as long as it has a capacitive element. For example, as in the NOR circuit 520 of FIG. 52 and the NOR circuit 560 of FIG. 56 , the transistor 521 and the transistor 561 may be connected instead of the capacitor 515 , respectively.

In addition, the capacitor 515 is not necessarily required as long as the capacitance between the second terminal and the gate terminal of the transistor 513 is sufficiently large. For example, as in the NOR circuit 530 of FIG. 53 and the NOR circuit 570 of FIG. 57 , the capacitor 515 may not be connected.

Here, the functions of the transistors 511 to 514 , the transistor 521 , the transistor 551 , the transistor 552 , the transistor 561 , and the capacitor 515 will be described below.

The transistor 511 has a function as a switch for selecting whether or not to connect the second power source and the output terminal OUT according to the potential of the input terminal IN1 . When the input terminal IN1 is at the H level, the power supply potential VSS is supplied to the output terminal OUT.

The transistor 512 has a function as a switch for selecting whether to connect or not connect the second power source and the output terminal OUT according to the potential of the input terminal IN2 . When the input terminal IN2 is at the H level, the power supply potential VSS is supplied to the output terminal OUT.

The transistor 513 has a function as a switch for selecting whether or not to connect the first power supply and the output terminal OUT.

The transistor 514 has a function as a diode. In addition, the transistor 514 has a function of putting the gate terminal of the transistor 513 in a floating state.

The transistor 521 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 513 . When the input terminal IN1 and the input terminal IN2 are at L level, the transistor 521 has a function of raising the potential of the gate terminal of the transistor 513 .

The transistor 551 has a function as a switch for selecting whether to connect or not connect the second power supply and the gate terminal of the transistor 513 according to the potential of the input terminal IN1 . When the input terminal IN1 is at the H level, the transistor 551 has a function of supplying the power supply potential VSS to the gate terminal of the transistor 513 .

The transistor 552 has a function as a switch for selecting whether to connect or not connect the second power supply and the gate terminal of the transistor 513 according to the potential of the input terminal IN2 . When the input terminal IN2 is at the H level, the transistor 552 has a function of supplying the power supply potential VSS to the gate terminal of the transistor 513 .

The transistor 561 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 513 . When the input terminal IN1 and the input terminal IN2 are at L level, the transistor 561 has a function of raising the potential of the gate terminal of the transistor 513 .

The capacitor 515 has a function for changing the potential of the gate terminal of the transistor 513 according to the potential of the output terminal OUT. When the input terminal IN1 and the input terminal IN2 are at L level, the capacitor 515 has a function of raising the potential of the gate terminal of the transistor 513 .

In this way, in the NOR circuits of Figs. 50 to 57, the potential of the output terminal OUT can be freely changed by changing the power supply potential VDD when outputting the H level signal. That is, each of the NOR circuits in FIGS. 50 to 57 may operate not only as an inverter circuit but also as a level shift circuit.

Although the case where all of the NOR circuits in FIGS. 50 to 57 are configured using n-channel transistors has been described, all of the NOR circuits may be configured using p-channel transistors. Here, Figs. 72 to 79 show inverter circuits in the case where all of them are configured using p-channel transistors.

72 shows another form of the NOR circuit 231 . The NOR circuit 720 of FIG. 72 includes a transistor 721 , a transistor 722 , and a transistor 723 .

As shown in the NOR circuit 720 of FIG. 72 , the first terminal of the transistor 721 is connected to the second power supply, the second terminal of the transistor 721 is connected to the first terminal of the transistor 722 , The gate terminal of the transistor 721 is connected to the input terminal IN1. A second terminal of the transistor 722 is connected to the second terminal and the output terminal OUT of the transistor 723 , and a gate terminal of the transistor 722 is connected to the input terminal IN2 . A first terminal of the transistor 723 is connected to a first power supply, and a gate terminal of the transistor 723 is connected to a first power supply.

In addition, the power supply potential VSS is supplied to the first power supply, and the power supply potential VDD is supplied to the second power supply. A potential difference (VDD-VSS) between the power supply potential VSS of the first power supply and the power supply potential VDD of the second power supply corresponds to the power supply voltage of the NOR circuit 720 . In addition, the power supply potential VDD is a potential higher than the power supply potential VSS.

In addition, a control signal is supplied to each of the input terminal IN1 and the input terminal IN2. Also, the output terminal OUT outputs an output signal.

Further, each of the transistors 721 to 723 is a p-channel transistor.

The operation of the NOR circuit 720 in Fig. 72 in the case where the input terminal IN1 is at the H level and the L level, and the case where the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 721 is turned off. When the input terminal IN2 becomes H level, the transistor 722 is turned off.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 723 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT becomes a value (VSS+Vth723|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth723 of the transistor 723, and the output terminal OUT ) becomes L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 721 is turned off. When the input terminal IN2 becomes L level, the transistor 722 is turned on.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 723 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT becomes a value (VSS+Vth723|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth723 of the transistor 723, and the output terminal OUT ) becomes L level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 721 is turned on. When the input terminal IN2 becomes H level, the transistor 722 is turned off.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 723 , so that the potential of the output terminal OUT is lowered. At this time, the potential of the output terminal OUT becomes a value (VSS+Vth723|) that is the sum of the absolute value of the power supply potential VSS and the threshold voltage Vth723 of the transistor 723, and the output terminal OUT ) becomes L level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 721 is turned on. When the input terminal IN2 becomes L level, the transistor 722 is turned on.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 721 and the transistor 722 , and is electrically connected to the first power source through the transistor 723 , so that the potential of the output terminal OUT is is rising At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 721 , the transistor 722 , and the transistor 723 , and the output terminal OUT becomes H level.

In addition, the transistor 723 does not need to have rectification, and any element can be used as long as it generates a voltage when current flows. For example, like the NOR circuit 760 of FIG. 76 , a resistor 761 may be connected instead of the transistor 723 .

Here, the functions of the transistors 721 to 723 will be described below.

The transistor 721 has a function as a switch that selects whether or not to connect the second power source and the first terminal of the transistor 722 according to the potential of the input terminal IN1 .

The transistor 722 has a function as a switch for selecting whether or not to connect the second terminal and the output terminal OUT of the transistor 721 according to the potential of the input terminal IN2 .

The transistor 723 has a function as a diode.

73 shows another form of the NOR circuit 231 . The NOR circuit 730 of FIG. 73 includes a transistor 731 , a transistor 732 , a transistor 733 , a transistor 734 , and a capacitor 735 having two electrodes.

As shown in the NOR circuit 730 of FIG. 73 , the first terminal of the transistor 731 is connected to the second power supply, the second terminal of the transistor 731 is connected to the first terminal of the transistor 732 , The gate terminal of the transistor 731 is connected to the input terminal IN1. A second terminal of the transistor 732 is connected to a second terminal of the transistor 733 , a second electrode of the capacitor 735 , and an output terminal OUT, and a gate terminal of the transistor 732 is connected to an input terminal IN2 is connected to A first terminal of the transistor 733 is connected to a first power supply, and a gate terminal of the transistor 733 is connected to a second terminal of the transistor 734 and a first electrode of the capacitor 735 . A first terminal of the transistor 734 is connected to a first power supply, and a gate terminal of the transistor 734 is connected to a first power supply.

In addition, the first power source, the second power source, the input terminal IN1 , the input terminal IN2 , and the output terminal OUT may be the same as those in FIG. 72 .

In addition, each of the transistors 731 to 734 is a p-channel transistor.

The operation of the NOR circuit 730 of FIG. 73 in the case where the input terminal IN1 is at the H level and the L level, and the case where the input terminal IN2 is at the H level and the L level will be described, respectively. .

First, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes H level, the transistor 731 is turned off. When the input terminal IN2 becomes H level, the transistor 732 is turned off. The potential of the gate terminal of the transistor 733 is the sum of the absolute values of the power supply potential VSS and the threshold voltage Vth734 of the transistor 734 (VSS+|Vth734|), and the transistor 733 is turned on. do. Also, the gate terminal of the transistor 733 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 733 , so that the potential of the output terminal OUT is lowered. The potential of the gate terminal of the transistor 733 is a value (VSS-|Vth733| ), and the transistor 733 continues to be on. A so-called bootstrap operation is performed. At this time, the potential of the output terminal OUT becomes VSS, and the output terminal OUT becomes L level.

Next, the case where the input terminal IN1 is at the H level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes H level, the transistor 731 is turned off. When the input terminal IN2 becomes L level, the transistor 732 is turned on. The potential of the gate terminal of the transistor 733 becomes a value (VSS+|Vth734|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth734) of the transistor 734, and the transistor 733 is turned on Also, the gate terminal of the transistor 733 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 733 , so that the potential of the output terminal OUT is lowered. The potential of the gate terminal of the transistor 733 is a value (VSS-|Vth733| ), and the transistor 733 continues to be on. A so-called bootstrap operation is performed. At this time, the potential of the output terminal OUT becomes VSS, and the output terminal OUT becomes L level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the H level will be described. When the input terminal IN1 becomes L level, the transistor 731 is turned on. When the input terminal IN2 becomes H level, the transistor 732 is turned off. The potential of the gate terminal of the transistor 733 becomes a value (VSS+|Vth734|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth734) of the transistor 734, and the transistor 733 is turned on Also, the gate terminal of the transistor 733 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the first power supply through the transistor 733 , so that the potential of the output terminal OUT is lowered. The potential of the gate terminal of the transistor 733 is a value (VSS-|Vth733| ), and the transistor 733 continues to be on. A so-called bootstrap operation is performed. At this time, the potential of the output terminal OUT becomes VSS, and the output terminal OUT becomes L level.

Next, the case where the input terminal IN1 is at the L level and the input terminal IN2 is at the L level will be described. When the input terminal IN1 becomes L level, the transistor 731 is turned on. When the input terminal IN2 becomes L level, the transistor 732 is turned on. The potential of the gate terminal of the transistor 733 becomes a value (VSS+|Vth734|) that is the sum of the absolute value of the power supply potential (VSS) and the threshold voltage (Vth734) of the transistor 734, and the transistor 733 is turned on Also, the gate terminal of the transistor 733 is in a floating state.

Accordingly, the output terminal OUT is electrically connected to the second power source through the transistor 731 and the transistor 732 , and is electrically connected to the first power source through the transistor 733 , so that the potential of the output terminal OUT is is rising At this time, the potential of the output terminal OUT is determined by the operating points of the transistor 731 , the transistor 732 , and the transistor 733 , and the output terminal OUT becomes H level.

As described above, in the NOR circuit 730 of FIG. 73 , the potential of the output terminal OUT may be lowered from the L level to the power supply potential VSS of the first power supply by the bootstrap operation.

In addition, the NOR circuit 730 of FIG. 73 is not limited to the circuit configuration of FIG. 73 as long as it can perform a bootstrap operation when the input terminal IN1 or the input terminal IN2 is at H level. When the input terminal IN1 and the input terminal IN2 are at the L level, a potential may be supplied to the gate terminal of the transistor 733 .

For example, as in the NOR circuit 770 of FIG. 77 , a transistor 771 and a transistor 772 may be added. This is because, when the output terminal OUT is at the H level, the potential of the output terminal OUT can be set to VDD. That is, when the input terminal IN1 and the input terminal IN2 are at the L level, the transistor 771 and the transistor 772 are turned on, so that the gate terminal of the transistor 733 is at the H level, and then the transistor ( This is because 733 is turned off, and the output terminal OUT is electrically connected only to the second power source through the transistor 731 or the transistor 732 .

In addition, each of the transistors 771 and 772 is a p-channel transistor.

In addition, as the capacitor 735, any element can be used as long as it has a capacitive element. For example, as in the NOR circuit 740 of FIG. 74 and the NAND circuit 780 of FIG. 78 , the transistor 741 and the transistor 781 may be respectively connected instead of the capacitor 735 .

Further, the capacitor 735 is not necessarily required as long as the capacitance between the second terminal and the gate terminal of the transistor 733 is sufficiently large. For example, as in the NOR circuit 750 of FIG. 75 and the NOR circuit 790 of FIG. 79, the capacitor 735 may not be connected.

Here, the functions of the transistors 731 to 734 , the transistor 741 , the transistor 771 , the transistor 772 , the transistor 781 , and the capacitor 735 will be described below.

The transistor 731 has a function as a switch that selects whether or not to connect the second power source and the first terminal of the transistor 732 according to the potential of the input terminal IN1 .

The transistor 732 has a function as a switch that selects the second terminal and the output terminal OUT of the transistor 731 according to the potential of the input terminal IN2 .

The transistor 733 has a function as a switch for selecting whether or not to connect the first power supply and the output terminal OUT.

The transistor 734 has a function as a diode. In addition, the transistor 734 has a function of putting the gate terminal of the transistor 733 in a floating state.

The transistor 741 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 733 . When either or both of the input terminal IN1 and the input terminal IN2 are at the H level, the transistor 741 has a function of lowering the potential of the gate terminal of the transistor 733 .

The transistor 771 has a function as a switch for selecting whether to connect or not to connect the second power supply and the first terminal of the transistor 772 according to the potential of the input terminal IN1 .

The transistor 772 has a function as a switch for selecting whether or not to connect the first terminal of the transistor 771 and the gate terminal of the transistor 733 according to the potential of the input terminal IN2 .

The transistor 781 has a function as a capacitor connected between the output terminal OUT and the gate terminal of the transistor 733 . When either or both of the input terminal IN1 and the input terminal IN2 are at the H level, the transistor 781 has a function of lowering the potential of the gate terminal of the transistor 733 .

The capacitor 735 has a function for changing the potential of the gate terminal of the transistor 733 according to the potential of the output terminal OUT. When either or both of the input terminal IN1 and the input terminal IN2 are at L level, the capacitor 735 has a function of lowering the potential of the gate terminal of the transistor 733 .

In this way, in the NOR circuit of Figs. 73 to 78, when the L level signal is output, the potential of the output terminal OUT can be freely changed by changing the power supply potential VSS. That is, each of the NOR circuits in FIGS. 73 to 78 may operate not only as an inverter circuit but also as a level shift circuit.

Further, since the circuit configurations of Figs. 28 to 87 are used as the inverter circuit 211, the NAND circuit 221, and the NOR circuit 231, the margin for operating the shift register circuit 200 becomes large. . This is because, in the inverter circuit 211 , the NAND circuit 221 , and the NOR circuit 231 , the gate terminal of one transistor is connected to the output terminal SRout. Accordingly, since the load capacitance of the output terminal SRout becomes small, the margin for operating the shift register circuit 200 can be increased.

Further, the inverter circuit, NAND circuit, and NOR circuit shown in Figs. 28 to 87 are each constituted by using transistors of the same polarity. Therefore, if the polarity of these transistors is the same as that of other transistors on the same substrate, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

In addition, although the power supply potential VDD or the power supply potential VSS is supplied to the 1st power supply and the 2nd power supply shown in FIGS. 28-87, this invention is not necessarily limited to this.

For example, different potentials may be supplied to each of the first power supply and the second power supply in FIGS. 28 to 87 .

As another example, a control signal may be supplied to each of the first power supply and the second power supply in FIGS. 28 to 87 .

Further, although a control signal is supplied to each of the input terminals in Figs. 28 to 87, the present invention is not necessarily limited to this.

For example, a power supply voltage may be supplied to the input terminals of FIGS. 28 to 87 .

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor of the shift register circuit of the present invention is turned on at regular time intervals, thereby supplying a power supply potential to the output terminal. Accordingly, the output terminal of the shift register circuit is supplied with a power supply potential through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, this shift register circuit can suppress generation of noise at the output terminal.

[Embodiment 4]

In this embodiment, a configuration different from the driving circuit described in Embodiment 3 will be described.

As a driving circuit, a configuration example applicable to a source driver will be described with reference to FIGS. 88 to 91 . The driving circuits in Figs. 88 to 91 can be applied to any circuit configuration as well as the source driver.

88 shows one form of the source driver of the present invention. The source driver of the present invention includes a shift register circuit 880, a plurality of switches SW, and a video signal line 881 .

As shown in the source driver in Fig. 88, the video signal line 881 is connected to the first terminal of the switch SW, and the second terminal of the switch SW is connected to the output terminal SDout. The control terminal of the switch SW is connected to the output terminal SRout of the shift register circuit 880 .

Note that the shift register circuit 880 is similar to that described in the second embodiment. Note that the gate driver described in Embodiment 3 may be applied to the shift register circuit 880 .

Note that the output terminals SRout1 to SRout4 and the output terminals SRoutn of the shift register circuit 880 may be the same as those described in the second embodiment.

Further, in the source driver of the present invention, the output terminal SDout of the first stage is the output terminal SDout1, the output terminal SDout of the second stage is the output terminal SDout2, and the output terminal of the third stage is the output terminal SDout2. Let SDout be the output terminal SDout3, and the output terminal SDout of the n-th stage will be the output terminal SDoutn.

In addition, in the source driver of FIG. 88, the power supply line and the control signal line are not shown for convenience.

Incidentally, when the shift register circuit 880 is configured using an n-channel transistor, the output signal of the shift register circuit 880 is the same as the timing chart of FIG. When the shift register circuit 880 is configured using a p-channel transistor, the output signal of the shift register circuit 880 is the same as the timing chart of FIG.

In addition, a video signal is supplied to the video signal line 881 . The video signal may be a current or a voltage, may be an analog signal, or may be a digital signal. The video signal is preferably an analog voltage. This is because many external circuits are for liquid crystal display devices. That is, if the video signal is an analog voltage, an existing inexpensive circuit can be used as an external circuit.

The operation of the source driver in Fig. 88 when the output terminal SRout of the shift register circuit 880 is at the H level and at the L level will be described, respectively.

For convenience, it is assumed that the switch SW in Fig. 88 is turned on when the control terminal is at the H level, and is turned off when the control terminal is at the L level. Of course, the switch SW may be turned off when the control terminal is at the H level, and may be turned on when the control terminal is at the L level.

First, a case in which the output terminal SRout is at the H level will be described. When the output terminal SRout of the shift register circuit becomes H level, the switch SW is turned on. When the switch SW is turned on, the video signal line 881 is connected to the output terminal SRout of the source driver via the switch SW.

Accordingly, since the output terminal SDout of the source driver has the same potential or the same current as the video signal line 881, the source driver outputs the video signal.

Next, the case where the output terminal SRout is at the L level will be described. When the output terminal SRout of the shift register circuit becomes L level, the switch SW is turned off. When the switch SW is turned off, the video signal line 881 is not connected to the output terminal SRout of the source driver.

Therefore, since the output terminal SDout of the source driver is not affected by the potential of the video signal line 881, the source driver does not output the video signal.

As described in Embodiment 2, when the shift register circuit 880 is constituted by an n-channel transistor, the shift register circuit 880 goes to H level sequentially from the output terminal SRout1. That is, the switch SW shown in Fig. 88 is sequentially turned on from the switch SW1 (in the first column), and the output terminal SDout of the source driver is sequentially turned on from the output terminal SDout1 (in the first column). The same potential or the same current as the signal.

In addition, the video signal is changed whenever the shift register circuit 880 outputs the H level signal, so that the source driver shown in Fig. 88 can sequentially output different video signals from the output terminal SDout1.

In addition, each output terminal SRout of the shift register circuit 880 controls one switch, but the present invention is not necessarily limited to this. Each output terminal SRout of the shift register circuit 880 may control a plurality of switches SW. In that case, a plurality of video signal lines may be provided, and each may be connected to the first terminal of the switch SW.

For example, as in the source driver of Fig. 89, one output terminal SRout of the shift register circuit 880 may control the three switches SW. Because the video signal line 891, the video signal line 892, and the video signal line 893 are connected to the first terminals of the three switches, the three output terminals SDout of the source driver can simultaneously output the video signal. because there is Therefore, since the operating frequency of the shift register circuit 880 can be lowered, the power consumption of the shift register circuit 880 is suppressed.

In addition, as the switch SW, an electrical switch or a mechanical switch can be used, for example. That is, as long as it can control the flow of current, it is not limited to a specific thing. A transistor may be sufficient, a diode may be sufficient, and a logic circuit combining them may be sufficient. Therefore, when a transistor is used as a switch, since the transistor operates as a simple switch, the polarity (conduction type) of the transistor is not particularly limited. However, when it is desirable to have a small off-state current, it is preferable to use a transistor having a polarity toward the small off-current. As the transistor with a small off-state current, there are a transistor having an LDD region, a transistor having a multi-gate structure, and the like. In addition, when operating in a state where the potential of the source terminal of the transistor operating as a switch is close to the low-potential power supply (Vss, GND, 0 V, etc.), it is preferable to use an n-channel transistor, and conversely, the source of the transistor It is preferable to use a p-channel transistor when the terminal is operated in a state where the potential is close to the high-potential power supply (Vdd, etc.). This is because, since the absolute value of the gate-source voltage can be increased, it is easy to operate when functioning as a switch. Further, a CMOS switch may be formed using both an n-channel transistor and a p-channel transistor.

For example, as in the source driver of FIG. 90 , the transistor 901 may be connected as a switch SW. On/off of the transistor 901 is controlled by the shift register circuit 880 . When the transistor 901 is turned on, the output terminal SDout of the source driver outputs a video signal.

Also, the transistor 901 is an n-channel transistor.

Further, the transistor 901 functions as a switch for selecting whether or not to connect the video signal line 881 and the output terminal SDout of the source driver according to the potential of the output terminal SRout of the shift register circuit 880. have When the output terminal SRout of the shift register circuit 880 is at the H level, the transistor 901 supplies a video signal to the output terminal SDout of the source driver.

In addition, the shift register circuit 880 at this time is preferably configured using an n-channel transistor. If the shift register circuit 880 is configured using an n-channel transistor, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

As another example, as in the source driver of FIG. 91 , the transistor 911 may be connected as a switch SW. On/off of this transistor 911 is controlled by a shift register circuit 880 . When the transistor 911 is turned on, the output terminal SDout of the source driver circuit outputs a video signal.

Also, the transistor 911 is a p-channel transistor.

Further, the transistor 911 functions as a switch for selecting whether or not to connect the video signal line 881 and the output terminal SDout of the source driver according to the potential of the output terminal SRout of the shift register circuit 880. have When the output terminal SRout of the shift register circuit 880 is at the L level, the transistor 911 supplies the video signal to the output terminal SDout of the source driver.

In addition, the shift register circuit 880 at this time is preferably configured using a p-channel transistor. If the shift register circuit 880 is configured using a p-channel transistor, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor of the shift register circuit of the present invention is turned on at regular time intervals to supply the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Embodiment 5]

In this embodiment, the layout diagram of the flip-flop circuit shown in Embodiment 1 is demonstrated.

FIG. 122 shows a layout diagram of the flip-flop circuit 10 shown in FIG.

The layout diagram of the flip-flop circuit shown in FIG. 122 shows a case where the flip-flop circuit is configured using a transistor made of amorphous silicon.

The flip-flop circuit of FIG. 122 includes a power supply line 12201, a control line 12202, a control line 12203, a control line 12204, a control line 12205, a power supply line 12206, an output terminal 12207, and a transistor. 11 , a transistor 12 , a transistor 13 , a transistor 14 , a transistor 15 , a transistor 16 , a transistor 17 , and a transistor 18 .

Further, reference numeral 12208 denotes a semiconductor layer, 12209 denotes a gate electrode and a gate wiring layer, 12210 denotes a second wiring layer, and 12211 denotes a contact layer.

The connection relationship of the flip-flop circuit shown in FIG. 122 is demonstrated. As shown in the flip-flop circuit 10, the gate terminal of the transistor 11 is connected to the input terminal IN1, the first terminal of the transistor 11 is connected to the first power supply, and the second terminal of the transistor 11 is connected to the first power supply. two terminals are connected to the gate terminal of the transistor 12 , the second terminal of the transistor 14 , the gate terminal of the transistor 15 , the second terminal of the transistor 17 , and the second electrode of the capacitor 19 . . A first terminal of transistor 15 is connected to a second power supply, and a second terminal of transistor 15 is connected to a second terminal of transistor 16 and a gate terminal of transistor 18 . A gate terminal and a first terminal of the transistor 16 are connected to a first power supply. A first terminal of the transistor 18 is connected to the input terminal IN3 , and a second terminal of the transistor 18 is connected to a gate terminal of the transistor 13 and a gate terminal of the transistor 14 . A first terminal of the transistor 13 is connected to a second power source, and a second terminal of the transistor 13 is connected to a first electrode of the capacitor 19 , a second terminal of the transistor 12 , and an output terminal OUT. connected. A first terminal of the transistor 12 is connected to the input terminal IN2. A first terminal of the transistor 14 is connected to a second power supply. A gate terminal of the transistor 17 is connected to the input terminal IN4 , and a first terminal of the transistor 17 is connected to a second power supply.

Also, the transistors 11 to 18 in FIG. 122 correspond to the transistors 11 to 18 in FIG. 1, respectively. The control line 12204, the control line 12202, the control line 12203, and the control line 12205 in FIG. 122 correspond to the input terminals IN1 to IN4 in FIG. 1, respectively. The output terminal 12207 corresponds to the output terminal OUT of FIG. 1 .

In addition, in the layout diagram of the flip-flop circuit of FIG. 122, the shape of the channel region of the transistor 15 is U-shaped. Also, as described above, the size of the transistor 15 needs to be large. Therefore, as in the transistor 15 of FIG. 122 , by making the channel region U-shaped, the transistor 15 can have a small area and the size (or W/L ratio) of the transistor 15 can be increased. .

Further, the wiring widths of the control line 12202 and the control line 12203 are larger than that of the power supply line 12201 . In the flip-flop circuit of Fig. 122, a larger current or voltage is supplied to the flip-flop circuit by the control line 12202 and the control line 12203 than the power supply line 12201. Therefore, if the wiring widths of the control line 12202 and the control line 12203 are large, the influence of the voltage drop of the control line 12202 and the control line 12203 can be reduced.

In addition, although the flip-flop circuit of FIG. 122 is comprised using the transistor made of amorphous silicon, this invention is not limited to this.

For example, as in the flip-flop circuit of FIG. 123, the flip-flop circuit may be configured using a polysilicon transistor.

Here, a case in which the flip-flop circuit is constructed using a polysilicon transistor will be described.

The flip-flop circuit of FIG. 123 includes a power supply line 12201, a control line 12202, a control line 12203, a control line 12204, a control line 12205, a power supply line 12206, an output terminal 12207, and a transistor. 11 , a transistor 12 , a transistor 13 , a transistor 14 , a transistor 15 , a transistor 16 , a transistor 17 , and a transistor 18 .

Further, reference numeral 12208 denotes a semiconductor layer, 12209 denotes a gate electrode and a gate wiring layer, 12210 denotes a second wiring layer, and 12211 denotes a contact layer.

The connection relationship of the flip-flop circuit shown in FIG. 123 is demonstrated. As shown in the flip-flop circuit 10, the gate terminal of the transistor 11 is connected to the input terminal IN1, the first terminal of the transistor 11 is connected to the first power supply, and the second terminal of the transistor 11 is connected to the first power supply. two terminals are connected to the gate terminal of the transistor 12 , the second terminal of the transistor 14 , the gate terminal of the transistor 15 , the second terminal of the transistor 17 , and the second electrode of the capacitor 19 . . A first terminal of transistor 15 is connected to a second power supply, and a second terminal of transistor 15 is connected to a second terminal of transistor 16 and a gate terminal of transistor 18 . A gate terminal and a first terminal of the transistor 16 are connected to a first power supply. A first terminal of the transistor 18 is connected to the input terminal IN3 , and a second terminal of the transistor 18 is connected to a gate terminal of the transistor 13 and a gate terminal of the transistor 14 . A first terminal of the transistor 13 is connected to a second power source, and a second terminal of the transistor 13 is connected to a first electrode of the capacitor 19 , a second terminal of the transistor 12 , and an output terminal OUT. connected. A first terminal of the transistor 12 is connected to the input terminal IN2. A first terminal of the transistor 14 is connected to a second power supply. A gate terminal of the transistor 17 is connected to the input terminal IN4 , and a first terminal of the transistor 17 is connected to a second power supply.

Further, a power supply line 12201 , a control line 12202 , a control line 12203 , a control line 12204 , a control line 12205 , a power supply line 12206 , an output terminal 12207 , a transistor 11 , a transistor (12), the transistor 13, the transistor 14, the transistor 15, the transistor 16, the transistor 17, and the transistor 18 can use the same ones as those of FIG.

In addition, as the semiconductor layer 12208, the gate wiring layer 12209 (gate electrode layer), the 2nd wiring layer 12210, and the contact layer 12211, the thing similar to that of FIG. 122 can be used.

In addition, in the layout diagram of the flip-flop circuit of FIG. 123, the gate terminal of the transistor 13 and the gate terminal of the transistor 14 are connected to each other via the second wiring layer 12210, so that the gate wiring layer 12209 can be shortened. can It is known that when the gate wiring layer 12209 is long, electrostatic breakdown is likely to occur through the gate wiring layer 12209 in the manufacturing process of the semiconductor device. Accordingly, by connecting the gate terminal of the transistor 13 and the gate terminal of the transistor 14 to each other through the second wiring layer 12210 , electrostatic breakdown through the gate wiring layer 12209 can be suppressed. In addition, by suppressing electrostatic breakdown, advantages such as improvement in product yield, improvement in productivity, and long life of the semiconductor device are obtained.

Also, the transistor 15 has a plurality of channel regions. By dividing the channel region into a plurality of regions in this way, heat generation of the transistor 15 can be reduced, and deterioration of the characteristics of the transistor 15 can be suppressed.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor of the shift register circuit of the present invention is turned on at regular time intervals, thereby supplying a power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 1]

In this embodiment, the configuration of a display device, a gate driver, a source driver, and the like will be described. Further, the semiconductor device of the present invention can be applied to a part of a gate driver or a source driver.

92 shows one form of a display device to which the present invention is applied. The display device 920 to which the present invention is applied has a pixel region 921 , a gate driver 922 , a control signal line 923 , and an FPC 926 . The pixel region 921 includes a pixel, and the pixel includes a display element and a circuit for controlling the display element.

In FIG. 92 , the FPC 926 is connected to the control signal line 923 and the source signal line 924 , and the gate driver 922 is connected to the control signal line 923 and the gate signal line 925 .

In addition, as the gate driver 922, the same one as described in Embodiment 3 can be used.

In addition, the number of gate drivers 922 may be one or more.

As described above, a display device, which is a device having a display element, or a light emitting device, which is a device having a light emitting device, may use various shapes or may have various elements. For example, an EL element (an organic EL element, an inorganic EL element, or an EL element containing an organic material and an inorganic material), an electron emitting element, a liquid crystal element, an electronic ink, etc., a display medium whose contrast is changed by an electric or magnetic action can be applied. Further, as a display device using an EL element, there is an EL display, and as a display device using an electron emission element, there are a field emission display (FED), a surface-conduction electron-emitter display (SED), etc., and a liquid crystal element. As a display device using , there is a liquid crystal display, and as a display device using electronic ink, there is an electronic paper.

An operation of the display device 920 will be briefly described.

The gate driver 922 sequentially outputs a selection signal to the pixel region 921 through the gate signal line 925 . An external circuit sequentially outputs a video signal to the pixel region 921 via the FPC 926 and the source signal line 924 . The external circuit is not shown. In the pixel region 921, an image is displayed by controlling the light state according to a video signal.

Further, a control signal is supplied to the control signal line 923 from an external circuit, and the gate driver 922 is controlled by the control signal. For example, as the control signal, a start pulse, a clock signal, an inverted clock signal, and the like are used.

Note that the video signal may be an input of a voltage value or an input of a current value. For example, when a liquid crystal element is used as the display element, the video signal is preferably an input of a voltage value. This is because, in the liquid crystal element, the tilt of the liquid crystal element is controlled by an electric field, and thus can be easily controlled by a video signal having a voltage value.

In addition, a digital value may be sufficient as a video signal, and an analog value may be sufficient as it. For example, when a liquid crystal element is used as the display element, the video signal is preferably an analog value. This is because the response speed of the liquid crystal element is slow, and the liquid crystal element can be controlled by supplying a video signal of an analog value only once in one frame period.

In addition, although the FPC 926 is constituted by one FPC 926, the present invention is not necessarily limited to this. The FPC 926 may be divided into a plurality of FPCs.

For example, as in the display device 920 of FIG. 93 , the FPC 926 may be divided into three. This is because, even when the display device is large or the number of connections between the FPC 926 and the display device 920 is large, the existing FPC and the existing FPC crimping device can be used, thereby reducing the manufacturing cost. . In addition, when the connection between the FPC 926 and the display device 920 fails, only the FPC 926 in which the connection has failed needs to be replaced, so that the manufacturing cost can be reduced.

Also, a video signal can be output to the pixel region 921 through any circuit and any element.

For example, as shown in FIG. 94 , the video signal may be output to the pixel region 921 via the signal line control circuit 941 . This is because, if the signal line control circuit 941 has various functions, the configuration of the external circuit becomes simple, so that the cost of the display device as a whole can be reduced. Also, the number of connections between the FPC 926 and the display device 920 can be significantly reduced.

In addition, a video signal and a control signal are supplied to the signal line control circuit 941 by a control signal line 942 .

As described above, various configurations can be applied to the display device of the present invention.

In addition, in this embodiment, although the structure of various display apparatuses was shown, the structure of the display apparatus of this invention is not limited to these display apparatuses.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the gate driver and the source driver provided with the shift register circuit of the present invention supply the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 2]

Next, a specific configuration of the signal line control circuit 941 described in the first embodiment will be described.

In addition, as the signal line control circuit 941, the source driver described in Embodiment 4 can be applied.

Fig. 95 shows an embodiment of a signal line control circuit 941 different from the source driver described in the fourth embodiment. The signal line control circuit 950 of FIG. 95 has a plurality of switches SW.

As shown in Fig. 95, the video signal line 954 is connected to the first terminal of the switch SW1, the first terminal of the switch SW2, and the first terminal of the switch SW3. The second terminal of the switch SW1 is connected to the source signal line 955 , the second terminal of the switch SW2 is connected to the source signal line 956 , and the second terminal of the switch SW3 is connected to the source signal line 957 . is connected to The control terminal of the switch SW1 is connected to the control signal line 951, the control terminal of the switch SW2 is connected to the control signal line 952, and the control terminal of the switch SW3 is connected to the control signal line 953. have. Further, the video signal line 954, the control signal line 951, the control signal line 952, and the control signal line 953 are connected to an external circuit via the FPC.

Further, the control signal A is supplied to the control signal line 951 , the control signal B is supplied to the control signal line 952 , and the control signal C is supplied to the control signal line 953 . A video signal is supplied to the video signal line 954 .

As already described, as the switches SW1 to SW3, for example, an electrical switch or a mechanical switch can be used. That is, the switch may be one that can control the flow of current, and is not limited to a specific one. A transistor may be sufficient, a diode may be sufficient, and a logic circuit combining them may be sufficient. Therefore, when a transistor is used as a switch, since the transistor operates as a simple switch, the polarity (conduction type) of the transistor is not particularly limited. However, when it is desirable to have a small off-state current, it is preferable to use a transistor having a polarity with a small off-current. As a transistor with a small off-state current, a transistor having an LDD region, a transistor having a multi-gate structure, or the like can be used. Further, when operating in a state where the potential of the source terminal of the transistor operating as a switch is close to the low-potential power supply (Vss, GND, 0 V, etc.), it is preferable to use an n-channel transistor, and conversely, the source terminal of the transistor It is preferable to use a p-channel transistor when operating in a state where the potential of is close to the high-potential power supply (Vdd, etc.). This is because the transistor can easily function as a switch because the absolute value of its gate-source voltage can be increased. Further, a CMOS switch may be formed using both an n-channel transistor and a p-channel transistor.

The operation of the signal line control circuit 950 in Fig. 95 will be described.

The control signal A, the control signal B, and the control signal C are signals for sequentially turning on the switch SW1, the switch SW2, and the switch SW3. The value of the video signal is changed according to the on/off state of the switch SW1, the switch SW2, and the switch SW3.

First, the switch SW1 is turned on by the control signal A. At this time, the switch SW2 is turned off by the control signal B, and the switch SW3 is turned off by the control signal C. As shown in FIG. Accordingly, the video signal is supplied to the source signal line 955 through the video signal line 954 and the switch SW1. At this time, since the switch SW2 and the switch SW3 are off, the video signal is not supplied to the source signal line 956 and the source signal line 957 .

Next, the switch SW2 is turned on by the control signal B. At this time, the switch SW1 is turned off by the control signal A, and the switch SW3 is turned off by the control signal C. As shown in FIG. Accordingly, the video signal is supplied to the source signal line 956 through the video signal line 954 and the switch SW2. At this time, since the switch SW1 and the switch SW3 are off, the video signal is not supplied to the source signal line 955 and the source signal line 957 .

Next, the switch SW3 is turned on by the control signal C. FIG. At this time, the switch SW1 is turned off by the control signal A, and the switch SW3 is turned off by the control signal B. Accordingly, the video signal is supplied to the source signal line 957 through the video signal line 954 and the switch SW3. At this time, since the switch SW1 and the switch SW2 are off, the video signal is not supplied to the source signal line 955 and the source signal line 956 .

By the above operation, a video signal is supplied to three lines: a source signal line 955 , a source signal line 956 , and a source signal line 957 using one video signal line 954 . That is, since the number of video signal lines 954 becomes 1/3 of the number of source signal lines, the number of connections between the FPC and the display device is greatly reduced. Accordingly, the probability of connection failure between the FPC and the display device is greatly reduced.

In addition, although the signal line control circuit 950 of FIG. 95 has three switches SW, this invention is not limited to this. The switch SW is not limited. The number of control signals needs to be changed corresponding to the number of switches SW. For example, when the number of switches SW is four, the number of control signals is four.

Further, the signal line control circuit 950 in Fig. 95 may have a period in which all of the switches SW1 to SW3 are not turned on. This is because image defects such as crosstalk can be suppressed. That is, when a new video signal is supplied to the source signal line, the potential of the source signal line does not change immediately. This is because, in some cases, the influence of the previous potential remains on the source signal line, so that image defects such as crosstalk occur. This period is a preparation period for writing the next row.

Further, the control signal A, the control signal B, and the control signal C may be supplied by the shift register circuit of the second embodiment. At this time, the shift register circuit includes three or more flip-flop circuits. The shift register circuit preferably has three or more flip-flop circuits and five or less flip-flop circuits.

In addition, in the display device 920 , by forming the signal line control circuit 950 on the same substrate, the number of connections between the FPC and the display device 920 can be further reduced.

As described above, various signal line control circuits can be used in the display device of the present invention.

In addition, although various signal line control circuits are shown in this embodiment, the signal line control circuits applicable to the display device of the present invention are not limited to these signal line control circuits.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the signal line control circuit including the shift register circuit of the present invention supplies the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 3]

Next, the specific configuration of the pixel described in the first embodiment will be described.

96 shows one form of a pixel. The pixel 960 of FIG. 96 includes a transistor 961 , a liquid crystal element 962 having two electrodes, and a capacitor 963 having two electrodes.

As shown in the pixel 960 of FIG. 96 , the first terminal of the transistor 961 is connected to the source signal line 924 , and the second terminal of the transistor 961 is the first electrode of the liquid crystal element 962 and the capacitor It is connected to the first electrode of 963 , and the gate terminal of the transistor 961 is connected to the gate signal line 925 . The second electrode of the liquid crystal element 962 is a counter electrode 964 . A second electrode of the capacitor 963 is connected to the common line 965 .

In addition, a video signal is supplied to the source signal line 924 and a selection signal is supplied to the gate signal line 925 . In addition, the source signal line 924 and the gate signal line 925 can use the same ones as those in the first embodiment.

Further, a common potential is supplied to the common line 965 , and a substrate potential is supplied to the counter electrode 964 . The common potential and the substrate potential are constant potentials.

Also, the transistor 961 is an n-channel transistor.

The operation of the pixel 960 in Fig. 96 when the selection signal is supplied to the gate signal line 925 (H level) and when the selection signal is not supplied (L level) will be described respectively. In addition, a period in which the selection signal is supplied to the gate signal line 925 is referred to as a first period, and a period in which the selection signal is not supplied is referred to as a second period.

First, the first period will be described. The gate signal line 925 goes to the H level, and the transistor 961 turns on. The source signal line 924 is electrically connected to the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 , and the potential of the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 . becomes the same potential as the potential of the source signal line 924 .

Here, the potential of the source signal line 924 is the potential corresponding to the video signal.

The light transmittance of the liquid crystal element 962 is determined by the potential corresponding to the video signal. The capacitor 963 holds a potential corresponding to the video signal.

Next, the second period will be described. The gate signal line 925 goes to the L level, and the transistor 961 turns off. The source signal line 924 is not electrically connected to the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 . Accordingly, since the potential corresponding to the previously input video signal is maintained as the potential of the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963, the light transmittance of the liquid crystal element 962 is also maintained.

Here, the functions of the transistor 961 and the capacitor 963 will be described below.

The transistor 961 is a switch for selecting whether or not to connect the source signal line 924 to the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 according to the potential of the gate signal line 925 . has a function as In the first period, the transistor 961 has a function of supplying a video signal to the pixel 960 .

The capacitor 963 has a function of holding a video signal. In the first period, a video signal is supplied to the capacitor 963, and the capacitor 963 has a function of holding the video signal. In the second period, the capacitor 963 has the function of holding the video signal until the next first period.

In this way, the pixel 960 may be actively driven. In addition, if the other transistors on the same substrate as the pixel 960 are n-channel transistors, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

The second electrode of the capacitor 963 may be connected anywhere as long as the second electrode of the capacitor 963 is maintained at a constant potential during the operation period of the pixel 960 . For example, the second electrode of the capacitor 963 may be connected to the gate signal line 925 of the previous row. This is because the common line 965 is not needed and the aperture ratio of the pixel 960 is increased.

In addition, although a constant potential is supplied to the counter electrode 964, the present invention is not limited thereto. For example, when the pixel 960 is driven by inversion, the potential of the counter electrode 964 may be changed corresponding to the inversion driving. At this time, when the video signal has a positive potential, the potential of the counter electrode 964 becomes a negative potential. Further, when the video signal has a negative potential, the potential of the counter electrode 964 becomes a positive potential.

Although the case where the pixel in FIG. 96 is configured using an n-channel transistor has been described, it may be configured using a p-channel transistor. Here, FIG. 120 shows a pixel configured using a p-channel transistor.

120 shows one form of a pixel. The pixel 1200 of FIG. 120 includes a transistor 1201 , a liquid crystal element 962 having two electrodes, and a capacitor 963 having two electrodes.

As shown in the pixel 1200 of FIG. 120 , the first terminal of the transistor 1201 is connected to the source signal line 924 , and the second terminal of the transistor 1201 is the first electrode of the liquid crystal element 962 and the capacitor 963 is connected to the first electrode, and the gate terminal of the transistor 1201 is connected to the gate signal line 925 . The second electrode of the liquid crystal element 962 is a counter electrode 964 . A second electrode of the capacitor 963 is connected to the common line 965 .

In addition, a video signal is supplied to the source signal line 924 and a selection signal is supplied to the gate signal line 925 . In addition, the source signal line 924 and the gate signal line 925 can use the same ones as those in the first embodiment.

Further, a common potential is supplied to the common line 965 , and a substrate potential is supplied to the counter electrode 964 . The common potential and the substrate potential are constant potentials.

Further, the liquid crystal element 962 , the capacitor 963 , the counter electrode 964 , and the common line 965 may use the same ones as those of FIG. 96 .

Also, the transistor 1201 is a p-channel transistor.

The operation of the pixel 1200 of FIG. 120 when the selection signal is supplied to the gate signal line 925 (L level) and when the selection signal is not supplied (H level) will be described respectively. In addition, a period in which the selection signal is supplied to the gate signal line 925 is referred to as a first period, and a period in which the selection signal is not supplied is referred to as a second period.

First, the first period will be described. The gate signal line 925 goes to the L level, and the transistor 1201 turns on. The source signal line 924 is electrically connected to the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 , and the potential of the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 . becomes the same potential as the potential of the source signal line 924 .

Here, the potential of the source signal line 924 is the potential corresponding to the video signal.

The light transmittance of the liquid crystal element 962 is determined by the potential corresponding to the video signal. The capacitor 963 holds a potential corresponding to the video signal.

Next, the second period will be described. The gate signal line 925 goes to the H level, and the transistor 1201 turns off. The source signal line 924 is not electrically connected to the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963 . Accordingly, since the potential corresponding to the previously input video signal is maintained as the potential of the first electrode of the liquid crystal element 962 and the first electrode of the capacitor 963, the light transmittance of the liquid crystal element 962 is also maintained.

Here, the functions of the transistor 1201 and the capacitor 963 will be described below.

The transistor 1201 is a switch for selecting whether or not to connect the source signal line 924 to the first terminal of the liquid crystal element 962 and the first electrode of the capacitor 963 according to the potential of the gate signal line 925 . has a function as In the first period, the transistor 1201 has a function of supplying a video signal to the pixel 1200 .

In this way, the pixel 1200 may be actively driven. In addition, if the other transistors on the same substrate as the pixel 1200 are p-channel transistors, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

Further, the second electrode of the capacitor 963 may be connected anywhere as long as the second electrode of the capacitor 963 is maintained at a constant potential during the operation period of the pixel 1200 . For example, the second electrode of the capacitor 963 may be connected to the gate signal line 925 of the previous row. This is because the common line 965 is not needed and the aperture ratio of the pixel 1200 is increased.

In addition, although a constant potential is supplied to the counter electrode 964, the present invention is not limited thereto. For example, when the pixel 1200 is driven by inversion, the potential of the counter electrode 964 may be changed corresponding to the inversion driving. At this time, when the video signal has a positive potential, the potential of the counter electrode 964 becomes a negative potential. Further, when the video signal has a negative potential, the potential of the counter electrode 964 becomes a positive potential.

97 shows another form of a pixel. A pixel 970 of FIG. 97 includes a transistor 971 , a transistor 972 , a display element 973 having two electrodes, and a capacitor 974 having two electrodes.

As shown in the pixel 970 of FIG. 97 , the first terminal of the transistor 971 is connected to the source signal line 924 , and the second terminal of the transistor 971 is the gate terminal of the transistor 972 and the capacitor 974 . ), and a gate terminal of the transistor 971 is connected to a gate signal line 925 . The second electrode of the capacitor 974 is connected to the power supply line 976 . A first terminal of the transistor 972 is connected to the power supply line 976 , and a second terminal of the transistor 972 is connected to a first electrode of the display element 973 . The second electrode of the display element 973 is a common electrode 975 .

In addition, a video signal is supplied to the source signal line 924 and a selection signal is supplied to the gate signal line 925 . In addition, the source signal line 924 and the gate signal line 925 can use the same ones as those in the first embodiment.

Further, an anode potential is supplied to the power supply line 976 , and a cathode potential is supplied to the common electrode 975 . Also, the anode potential is a higher potential than the cathode potential.

Further, each of the transistors 971 and 972 is an n-channel transistor.

The operation of the pixel 970 in Fig. 97 when the selection signal is supplied to the gate signal line 925 (H level) and when not supplied (L level) will be described respectively. In addition, a period in which the selection signal is supplied to the gate signal line 925 is referred to as a first period, and a period in which the selection signal is not supplied is referred to as a second period.

First, the first period will be described. The gate signal line 925 goes to the H level, and the transistor 971 is turned on. The source signal line 924 is electrically connected to the gate terminal of the transistor 972 and the first electrode of the capacitor 974, and the potential of the gate terminal of the transistor 972 and the first electrode of the capacitor 974 is the source signal line ( 924) becomes the same potential.

Here, the potential of the source signal line 924 is the potential corresponding to the video signal.

The current value of the transistor 972 is determined by the potential difference (Vgs) between the potential corresponding to the video signal and the potential of the second terminal of the transistor 972 , and the same current as the transistor 972 is supplied to the display element 973 . flows In this case, the operating points of the transistor 972 and the display element 973 need to be set in the saturation region. In this way, the current value of the display element 973 can be freely determined by the video signal.

Further, when the operating points of the transistor 972 and the display element 973 are set in the linear region, the first electrode of the display element 973 is electrically connected to the power supply line 976 via the transistor 972, and the power supply A voltage approximately equal to the potential of the line 976 is applied to the first electrode of the display element 973 . In addition, it is advantageous to set the operating points of the transistor 972 and the display element 973 in the linear region, because the current value of the transistor 972 is not affected by the characteristic deviation and deterioration of the transistor 972 . because it doesn't

Next, a case in which the selection signal is not supplied to the gate signal line 925 will be described. The gate signal line 925 goes to the L level, and the transistor 971 is turned off. The source signal line 924 is not electrically connected to the second terminal of the transistor 972 . Accordingly, since the potential corresponding to the previously input video signal is maintained as the potential of the second terminal of the transistor 972, the Vgs of the transistor 972 is maintained as it is. Accordingly, the current value of the display element 973 is also maintained as it is.

Here, the functions of the transistor 971 , the transistor 972 , and the capacitor 974 will be described below.

The transistor 971 functions as a switch for selecting whether or not to connect the source signal line 924 to the gate terminal of the transistor 972 and the first electrode of the capacitor 974 according to the potential of the gate signal line 925 . have In the first period, the transistor 971 has a function of supplying a video signal to the pixel 970 .

The transistor 972 has a function as a driving transistor that supplies a current or a voltage to the display element 973 according to the potential of the gate terminal of the transistor 972 and the first electrode of the capacitor 974 . Further, when the operating points of the transistor 972 and the display element 973 are set in the saturation region, the transistor 972 has a function as a current source for supplying a current to the display element 973 . In addition, when the operating points of the transistor 972 and the display element 973 are set in the linear region, the transistor 972 determines whether or not to connect the power supply line 976 and the first electrode of the display element 973 . It has a function as a switch to select.

Capacitor 974 has a function of holding a video signal. In the first period, a video signal is supplied to a capacitor 974, and the capacitor 974 has a function of holding the video signal. In the second period, the capacitor 974 has the function of holding the video signal until the next first period.

In this way, the pixel 970 may be actively driven. In addition, if the other transistors on the same substrate as the pixel 970 are n-channel transistors, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

In addition, the second electrode of the capacitor 974 may be connected anywhere as long as the second electrode of the capacitor 974 is held at a constant potential during the operation period of the pixel 970 . For example, the second electrode of the capacitor 974 may be connected to the gate signal line 925 of the previous row.

As another example, as in the pixel 980 of FIG. 98 , the second electrode of the capacitor 974 may be connected to the second terminal of the transistor 972 . This is because, since the potential of the gate terminal of the transistor 972 changes according to the change in the potential of the second terminal of the transistor 972, a more accurate current is supplied to the display element. That is, when the potential of the second terminal of the transistor 972 fluctuates, the potential of the gate terminal of the transistor 972 simultaneously fluctuates according to the capacitive coupling of the capacitor 974 . A so-called bootstrap operation is performed.

Although the case where all of the pixels in Fig. 97 are configured using n-channel transistors has been described, all of the pixels may be configured using p-channel transistors. Here, Fig. 121 shows a pixel in the case where all of the p-channel transistors are used.

121 shows another form of a pixel. The pixel 1210 of FIG. 121 includes a transistor 1211 , a transistor 1212 , a two-electrode display element 973 , and a two-electrode capacitor 974 .

As shown in the pixel 1210 of FIG. 121 , the first terminal of the transistor 1211 is connected to the source signal line 924 , and the second terminal of the transistor 1211 is the gate terminal of the transistor 1212 and the capacitor 974 . ), and a gate terminal of the transistor 1211 is connected to a gate signal line 925 . The second electrode of the capacitor 974 is connected to the power supply line 976 . A first terminal of the transistor 1212 is connected to the power supply line 976 , and a second terminal of the transistor 1212 is connected to a first electrode of the display element 973 . The second electrode of the display element 973 is a common electrode 975 .

In addition, a video signal is supplied to the source signal line 924 and a selection signal is supplied to the gate signal line 925 . In addition, the source signal line 924 and the gate signal line 925 can use the same ones as those in the first embodiment.

Further, an anode potential is supplied to the power supply line 976 , and a cathode potential is supplied to the common electrode 975 . Also, the anode potential is a potential higher than the cathode potential.

In addition, the display element 973, the capacitor 974, the common electrode 975, and the power supply line 976 can use the same thing as those in FIG.

In addition, each of the transistors 1211 and 1212 is a p-channel transistor.

The operation of the pixel 1210 in FIG. 121 when the selection signal is supplied to the gate signal line 925 (L level) and when not supplied (H level) will be described respectively. In addition, a period in which the selection signal is supplied to the gate signal line 925 is referred to as a first period, and a period in which the selection signal is not supplied is referred to as a second period.

First, the first period will be described. The gate signal line 925 goes to the L level, and the transistor 1211 is turned on. The source signal line 924 is electrically connected to the gate terminal of the transistor 1212 and the first electrode of the capacitor 974, and the potential of the gate terminal of the transistor 1212 and the first electrode of the capacitor 974 is the source signal line ( 924) becomes the same potential.

Here, the potential of the source signal line 924 is the potential corresponding to the video signal.

The current value of the transistor 1212 is determined by the potential difference (Vgs) between the potential corresponding to the video signal and the potential of the power supply line 976 , and the same current flows through the display element 973 . In this case, the operating points of the transistor 1212 and the display element 973 need to be set in the saturation region. In this way, the current value of the display element 973 can be freely determined by the video signal.

Further, when the operating points of the transistor 1212 and the display element 973 are set in the linear region, the first electrode of the display element 973 is electrically connected to the power supply line 976 via the transistor 1212 to display The potential of the first electrode of the element 973 is applied. In addition, it is advantageous that the operating points of the transistor 1212 and the display element 973 are set in the linear region, because the current value of the transistor 1212 is not affected by the characteristic deviation and deterioration of the transistor 1212 . am.

Next, a case in which the selection signal is not supplied to the gate signal line 925 will be described. The gate signal line 925 goes to the H level, and the transistor 1211 is turned off. The source signal line 924 is not electrically connected to the second terminal of the transistor 1212 . Accordingly, since the potential corresponding to the previously input video signal is maintained as the potential of the second terminal of the transistor 1212, Vgs of the transistor 1212 is maintained as it is. Accordingly, the current value of the display element 973 is also maintained as it is.

Here, the functions of the transistor 1211 and the transistor 1212 will be described below.

The transistor 1211 functions as a switch for selecting whether or not to connect the source signal line 924 to the gate terminal of the transistor 1212 and the first terminal of the capacitor 974 according to the potential of the gate signal line 925 . have In the first period, the transistor 1211 has a function of supplying a video signal to the pixel 1210 .

The transistor 1212 has a function as a driving transistor that supplies a current or a voltage to the display element 973 according to the potential of the gate terminal of the transistor 1212 and the second electrode of the capacitor 974 . Further, when the operating points of the transistor 1212 and the display element 973 are set in the saturation region, the transistor 1212 has a function as a current source for supplying a current to the display element 973 . In addition, when the operating points of the transistor 1212 and the display element 973 are set in the linear region, the transistor 1212 determines whether or not to connect the power supply line 976 and the first electrode of the display element 973 . It has a function as a switch to select.

In this way, the pixel 970 may be actively driven. In addition, if the other transistors on the same substrate as the pixel 970 are n-channel transistors, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

Further, the second electrode of the capacitor 974 may be connected anywhere as long as the second electrode of the capacitor 974 is maintained at a constant potential during the operation period of the pixel 1210 . For example, the second electrode of the capacitor 974 may be connected to the gate signal line 925 of the previous row.

99 shows another form of a pixel. The pixel 990 of FIG. 99 includes a transistor 991 , a transistor 992 , a transistor 993 , a two-electrode display element 973 , and a two-electrode capacitor 994 .

As shown in the pixel 990 of FIG. 99 , the first terminal of the transistor 991 is connected to the source signal line 924 , and the second terminal of the transistor 991 is the second terminal of the transistor 992 and the capacitor ( It is connected to the first electrode of 994 and the first electrode of the display element 973 . A first terminal of the transistor 992 is connected to a power supply line 995 , and a gate terminal of the transistor 992 is connected to a second terminal of the transistor 993 and a second electrode of the capacitor 994 . A first terminal of the transistor 993 is connected to a gate signal line 925 , and a gate terminal of the transistor 993 is connected to a power supply line 995 . The second electrode of the display element 973 is a common electrode 975 .

In addition, a video signal is supplied to the source signal line 924 and a selection signal is supplied to the gate signal line 925 . Also, the source signal line 924 and the gate signal line 925 can be the same as those in the first embodiment .

Also, the video signal is an analog current.

Further, a control potential is supplied to the power supply line 995 and a negative potential is supplied to the common electrode. In addition, the control potential changes according to the operation of the pixel 990 .

In addition, as the display element 973 and the common electrode 975, the same ones as those in FIG. 97 can be used.

Further, each of the transistors 991 to 993 is an n-channel transistor.

The operation of the pixel 990 in Fig. 99 when the selection signal is supplied to the gate signal line 925 (H level) and when not supplied (L level) will be described respectively. In addition, a period in which the selection signal is supplied to the gate signal line 925 is referred to as a first period, and a period in which the selection signal is not supplied is referred to as a second period.

First, the first period will be described. The gate signal line 925 goes to the H level, and the transistor 991 and the transistor 993 are turned on. A first terminal and a gate terminal of the transistor 992 are electrically connected via a transistor 993, and the transistor 992 is diode-connected. Further, the source signal line 924 is electrically connected to the second terminal of the transistor 992 , the first electrode of the capacitor 994 , and the first electrode of the display element 973 .

At this time, the potential of the power supply line 995 is set so that the potential of the first electrode of the display element 973 is lower than the potential of the common electrode 975 .

For the video signal, an analog current flowing from the power supply line 995 through the transistor 992 and the transistor 991 to the source signal line 924 is supplied to the pixel 990 . Then, a current such as a video signal is supplied to the transistor 992 . Since the transistor 992 is diode-connected, the voltage Vgs between the first terminal and the gate terminal of the transistor 992 at that time is held in the capacitor 994 .

In addition, since the potential of the first electrode of the display element 973 is lower than the potential of the common electrode, the display element 973 does not emit light.

Next, the second period will be described. The gate signal line 925 goes to the L level, and the transistor 991 and the transistor 993 are turned off. The first terminal and the gate terminal of the transistor 992 are not electrically connected through the transistor 993, and the transistor 992 is not diode-connected. In addition, the source signal line 924 is not electrically connected to the second terminal of the transistor 992 , the first electrode of the capacitor 994 , and the first electrode of the display element 973 .

At this time, the potential of the power supply line 995 is set so that the potential of the first electrode of the display element 973 is higher than the potential of the common electrode 975 .

The capacitor 994 holds a voltage at which the transistor 992 supplies a current such as a video signal. When the potential of the power supply line 995 rises, the potential of the first electrode of the capacitor 994 also rises. Here, the potential of the gate terminal of the transistor 992 rises by capacitive coupling of the capacitor 994, and Vgs of the transistor 992 is maintained as it is. Accordingly, the display element 973 is supplied with a current such as a video signal.

Here, the functions of the transistors 991 to 993 and the capacitor 994 will be described below.

The transistor 991 connects the source signal line 924 to the second terminal of the transistor 992 , the first electrode of the capacitor 994 , and the first electrode of the display element 973 according to the potential of the gate signal line 925 . It has a function as a switch to select whether to connect to or not to connect to. In the first period, the transistor 991 has a function of supplying a video signal to the pixel 990 .

The transistor 992 functions as a current source for supplying a current to the display element 973 according to potentials of the gate terminal of the transistor 992 , the second terminal of the transistor 993 , and the second electrode of the capacitor 994 . have

The transistor 993 has a function as a switch for selecting whether to connect or not connect the first terminal of the transistor 992 and the gate terminal of the transistor 992 . In the first period, the transistor 993 has a function of making the transistor 992 diode-connected.

The capacitor 994 has a function of changing the potential of the gate terminal of the transistor 992 in accordance with the potential of the first electrode of the display element 973 . In the second period, the capacitor 994 has a function of raising the potential of the gate terminal of the transistor 992 by raising the potential of the first electrode of the display element 973 .

In this way, the pixel 990 may be actively driven. In addition, if the other transistors on the same substrate as the pixel 990 are n-channel transistors, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

118 shows another form of a pixel. A pixel 1180 of FIG. 118 includes a transistor 1181 , a transistor 1182 , a transistor 1183 , a transistor 1184 , a two-electrode display element 973 , and a two-electrode capacitor 974 . Have.

As shown in the pixel 1180 of FIG. 118 , the first terminal of the transistor 1181 is connected to the source signal line 924 , and the second terminal of the transistor 1181 is the second terminal of the transistor 1182 , the transistor ( It is connected to the gate terminal of 1183 , the gate terminal of the transistor 1184 , and the second electrode of the capacitor 974 , and the gate terminal of the transistor 1181 is connected to the gate signal line 925 . A first terminal of the transistor 1182 is connected to a first terminal of the transistor 1183 , and a gate terminal of the transistor 1182 is connected to a gate signal line 925 . A second terminal of the transistor 1183 is connected to a second terminal of the transistor 1184 and a first electrode of the display element 973 . A first terminal of the transistor 1184 is connected to a power supply line 976 . The second electrode of the capacitor 974 is connected to the power supply line 976 . The second electrode of the display element 973 is a common electrode 975 .

In addition, a video signal is supplied to the source signal line 924 and a selection signal is supplied to the gate signal line 925 . In addition, the source signal line 924 and the gate signal line 925 can use the same ones as those in the first embodiment.

Also, the video signal is an analog current.

Further, an anode potential is supplied to the power supply line 976 , and a cathode potential is supplied to the common electrode 975 . Also, the anode potential is a potential higher than the cathode potential.

In addition, the display element 973, the common electrode 975, and the power supply line 976 can use the same ones as in FIG.

Also, the transistors 1181 to 1184 are n-channel transistors, respectively.

The operation of the pixel 1180 of FIG. 118 when the selection signal is supplied to the gate signal line 925 (H level) and when the selection signal is not supplied (L level) will be described respectively. In addition, a period in which the selection signal is supplied to the gate signal line 925 is referred to as a first period, and a period in which the selection signal is not supplied is referred to as a second period.

First, the first period will be described. The gate signal line 925 goes to the H level, and the transistor 1181 and the transistor 1182 are turned on. A first terminal and a gate terminal of the transistor 1183 are electrically connected via a transistor 1182 , and the transistor 1183 is diode-connected. Further, the source signal line 924 is electrically connected to the first terminal of the transistor 1182 , the gate terminal of the transistor 1183 , the gate terminal of the transistor 1184 , and the second electrode of the capacitor 974 .

For the video signal, an analog current flowing from the source signal line 924 to the common electrode 975 through the transistor 1181 , the transistor 1182 , the transistor 1183 , and the display element 973 is supplied to the pixel 1180 . do. Then, a current such as a video signal is supplied to the transistor 1183 . Since the gate terminal of the transistor 1183, the gate terminal of the transistor 1184, and the second electrode of the capacitor 974 are connected to each other, the second electrode of the capacitor 974 has the gate terminal of the transistor 1183 at that time. potential is retained.

Next, the second period will be described. The gate signal line 925 goes to the L level, and the transistor 1181 and the transistor 1182 are turned off. The first terminal and the gate terminal of the transistor 1183 are not electrically connected through the transistor 1182 . Further, the source signal line 924 is not electrically connected to the first terminal of the transistor 1182 , the gate terminal of the transistor 1183 , the gate terminal of the transistor 1184 , and the second electrode of the capacitor 974 .

The capacitor 974 holds a potential corresponding to the video signal. That is, the potential of the gate terminal of the transistor 1183 is equal to the potential obtained in the first period. Accordingly, since the potential of the gate terminal of the transistor 1184 is also the same as the potential of the second electrode of the capacitor 974 , the transistor 1184 can supply a current corresponding to the video signal to the display element 973 .

Here, the functions of the transistors 1181 to 1184 will be described below.

The transistor 1181 connects the source signal line 924 to the first terminal of the transistor 1182, the gate terminal of the transistor 1183, the gate terminal of the transistor 1184, and the capacitor ( 974) has a function as a switch for selecting whether to connect or not to connect to the second electrode. In the first period, the transistor 1181 has a function of supplying a video signal to the pixel 1180 .

The transistor 1182 has a function as a switch that selects whether or not to connect the first terminal of the transistor 1183 and the gate terminal of the transistor 1183 according to the potential of the gate signal line 925 . In the first period, the transistor 1182 has a function of diode-connecting the transistor 1183 .

The transistor 1183 has a function of determining the potential of the first electrode of the display element 973 and the potential of the gate terminal of the transistor 1184 according to the video signal.

The transistor 1184 has a function as a current source for supplying a current to the display element 973 according to the potential of the second electrode of the capacitor 974 .

In this way, the pixel 1180 may be actively driven. In addition, if the other transistor on the same substrate as the pixel 1180 is an n-channel transistor, the manufacturing process can be simplified. Accordingly, it is possible to reduce the manufacturing cost and improve the product yield.

Further, the first electrode of the capacitor 974 may be connected anywhere as long as the first electrode of the capacitor 974 is maintained at a constant potential during the operation period of the pixel 1180 . For example, the first electrode of the capacitor 974 may be connected to the gate signal line 925 of the previous row.

As another example, as in the pixel 1190 of FIG. 119 , the first electrode of the capacitor 974 may be connected to the second terminal of the transistor 1184 . This is because, since the potential of the gate terminal of the transistor 1184 changes according to the change in the potential of the second terminal of the transistor 1184, a more accurate current is supplied to the display element. That is, if the size of the transistor 1183 is different from that of the transistor 1184 , the current supplied to the display element 973 also varies, so that the potential of the first electrode of the display element 973 in the first period is the first. It differs from his dislocation in the 2nd period. Accordingly, the potential of the gate terminal of the transistor 1184 fluctuates simultaneously with the capacitive coupling of the capacitor 974 . A so-called bootstrap operation is performed.

As described above, various pixels can be used in the display device of the present invention.

In addition, although various pixels are shown in this embodiment, the pixels usable in the display device of the present invention are not limited to these pixels.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the shift register circuit of the present invention connected to the pixel described in this embodiment supplies the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 4]

In this embodiment, the configuration of the display panel having the pixel configuration shown in the embodiment will be described with reference to FIGS. 100(A) and 100(B).

100(A) is a top view of the display panel, and FIG. 100(B) is a cross-sectional view taken along line A-A' of FIG. 100(A). This display panel includes a signal line control circuit 6701 indicated by a dotted line, a pixel portion 6702 , a first gate driver 6703 , and a second gate driver 6706 . In addition, this display panel includes a sealing substrate 6704 and a sealing material 6705 , and an inner side surrounded by the sealing material 6705 is a space 6707 .

Further, the wiring 6708 is a wiring for transmitting signals input to the first gate driver 6703, the second gate driver 6706, and the signal line control circuit 6701, and the FPC 6709 functioning as an external input terminal. It receives video signal, clock signal, start signal, etc. from (Flexible Print Circuit). An IC chip 6719 (a semiconductor chip including a memory circuit, a buffer circuit, etc.) is mounted on the connection portion between the FPC 6709 and the display panel by COG (Chip On Glass) or the like. In addition, although only FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The display device in this specification shall include not only the display panel main body but also the state in which the FPC or PWB is attached to the display panel main body, and also includes a display panel on which an IC chip or the like is mounted.

Next, the cross-sectional structure is demonstrated using FIG. 100(B). A pixel portion 6702 and a peripheral driver circuit (first gate driver 6703, second gate driver 6706, and signal line control circuit 6701) are formed on the substrate 6710, but here the signal line control circuit 6701 ) and a pixel portion 6702 are shown.

Further, the signal line control circuit 6701 is constituted by using a unipolar transistor such as an n-channel transistor 6720 or an n-channel transistor 6721 . Note that, by applying any of the pixel configurations of FIGS. 96 to 99, 118, and 119 to the pixel configuration, a pixel can be configured using a unipolar transistor. Accordingly, if the peripheral driving circuit is formed of an n-channel transistor, a unipolar display panel can be manufactured. Of course, the CMOS circuit may be formed using not only unipolar transistors but also p-channel transistors.

In addition, when the n-channel transistor 6720 and the n-channel transistor 6721 are p-channel transistors, a pixel can be configured using a unipolar transistor by applying the pixel configuration of FIG. 120 or FIG. 121 . Accordingly, if the peripheral driving circuit is formed of a p-channel transistor, a unipolar display panel can be created. Of course, the CMOS circuit may be formed using not only unipolar transistors but also n-channel transistors.

In addition, although the present embodiment shows a display panel in which the peripheral driver circuit is integrally formed on the same substrate as the pixel portion, it is not necessary to do so, and all or part of the peripheral driver circuit is formed on an IC chip or the like, and the IC The chip may be mounted with COG or the like. In that case, the driving circuit does not need to be unipolar, and a combination of an n-channel transistor and a p-channel transistor can be used.

Further, the pixel portion 6702 includes a transistor 6711 and a transistor 6712 . Further, a source electrode of the transistor 6712 is connected to a first electrode (a pixel electrode 6713 ). In addition, an insulating material 6714 is formed to cover the end of the pixel electrode 6713 . Here, a positive photosensitive acrylic resin film is used for the insulator 6714 .

In addition, in order to provide good coverage, a curved surface having a curvature is formed at the upper end or lower end of the insulator 6714 . For example, when positive photosensitive acrylic is used as the material of the insulator 6714, it is preferable that only the upper end of the insulator 6714 has a curved surface having a radius of curvature (0.2 µm to 3 µm). Further, as the insulating material 6714, a negative photosensitive acrylic that becomes insoluble in an etchant by light or a positive photosensitive acryl that becomes soluble in an etchant by light can be used.

On the pixel electrode 6713 , a layer 6716 containing an organic compound and a second electrode (counter electrode 6717 ) are formed. Here, as the material used for the pixel electrode 6713 functioning as the anode, it is preferable to use a material having a large work function. For example, in addition to a single-layer film such as an ITO (indium tin oxide) film, an indium zinc oxide (IZO) film, a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a titanium nitride film and aluminum are the main components. A lamination with a film, a three-layer structure of a titanium nitride film and a film containing aluminum as a main component, and a titanium nitride film, etc. can be used. Further, in the case of the laminated structure, the resistance as a wiring is also low, a good ohmic contact can be obtained, and it can further function as an anode.

In addition, the layer 6716 containing an organic compound is formed by the vapor deposition method using the vapor deposition mask, or the inkjet method. For a part of the layer 6716 containing the organic compound, a complex of a metal belonging to Group 4 of the periodic table of elements may be used, and a combination of a low molecular weight material or a high molecular weight material may be used. In addition, as a material used for a layer containing an organic compound, in many cases, an organic compound is usually used as a single layer or a layered layer, but in this embodiment, an inorganic compound is also included in a part of a film formed of an organic compound. do it by doing It is also possible to use a known triplet material.

In addition, as a material used for the counter electrode 6717 formed on the layer 6716 containing the organic compound, a material having a small work function (Al, Ag, Li, Ca, or an alloy thereof, for example, MgAg; MgIn, AlLi, calcium fluoride, or calcium nitride) may be used. In addition, when light generated from the layer 6716 containing the organic compound passes through the counter electrode 6717, as the counter electrode 6717 (cathode), a thin metal thin film and a transparent conductive film (ITO ( Indium Tin Oxide), Indium Zinc Oxide Alloy (In<sb>2</sb>O<sb>3</sb>-ZnO), zinc oxide (ZnO), etc.) is recommended.

Further, by attaching the sealing substrate 6704 to the substrate 6710 with the sealing material 6705 , the light emitting element 6718 is placed in the space 6707 surrounded by the substrate 6710 , the sealing substrate 6704 , and the sealing material 6705 . ) is the provided structure. In addition, it shall include the structure in which not only the inert gas (nitrogen, argon, etc.) but the sealing material 6705 is filled in the space 6707.

In addition, it is preferable to use an epoxy resin for the sealing material 6705. Moreover, it is preferable that the material of a sealing material is a material which does not permeate|transmit water|moisture content or oxygen as much as possible. In addition, as a material used for the encapsulation substrate 6704, in addition to a glass substrate or a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester or acrylic, etc. may be used. can

As described above, a display panel having the pixel configuration of the present invention can be obtained. In addition, the above configuration is only an example, and the configuration of the display panel of the present invention is not limited thereto.

100A and 100B, a signal line control circuit 6701, a pixel portion 6702, a first gate driver 6703, and a second gate driver 6706 are formed on the same substrate. By doing so, the cost of the display device can be reduced. Further, in this case, unipolar transistors are used for the signal line control circuit 6701 , the pixel portion 6702 , the first gate driver 6703 , and the second gate driver 6706 , thereby simplifying the manufacturing process. Therefore, further reduction in cost can be achieved.

Further, in the configuration of the display panel, as shown in Fig. 100A, the signal line control circuit 6701, the pixel portion 6702, the first gate driver 6703, and the second gate driver 6706 are formed on the same substrate. The configuration is not limited thereto, and the signal line control circuit 6801 shown in FIG. 101A corresponding to the signal line control circuit 6701 may be formed on an IC chip and mounted on a display panel by means of COG or the like. Further, in Fig. 101A, the substrate 6800, the pixel portion 6802, the first gate driver 6803, the second gate driver 6804, the FPC 6805, the IC chip 6806, and the IC chip 6807 are shown. ), the sealing substrate 6808, and the sealing material 6809 are the substrate 6710, the pixel portion 6702, the first gate driver 6703, the second gate driver 6706, and the FPC ( 6709), the IC chip 6719, the sealing substrate 6704, and the sealing material 6705, respectively.

That is, only the signal line control circuit required for high-speed operation is formed on the IC chip using CMOS or the like, thereby reducing power consumption. Further, by using a semiconductor chip formed of a silicon wafer or the like as the IC chip, higher speed operation and lower power consumption can be achieved.

Further, by forming the first gate driver 6803 and the second gate driver 6804 on the same substrate as the pixel portion 6802, cost reduction can be achieved. In addition, by using unipolar transistors for the first gate driver 6803 , the second gate driver 6804 , and the pixel portion 6802 , it is possible to further reduce the cost. As the configuration of the pixel included in the pixel portion 6802, the pixel shown in the third embodiment can be applied.

In this way, the cost of the high-definition display device can be reduced. In addition, by mounting an IC chip including a functional circuit (memory or buffer) in the connection portion between the FPC 6805 and the substrate 6800, the substrate area can be effectively used.

Further, the signal line control circuit 6811 of FIG. 101(B) corresponding to the signal line control circuit 6701, the first gate driver 6703, and the second gate driver 6706 shown in FIG. 100(A), the first The gate driver 6814 and the second gate driver 6813 may be formed on an IC chip and mounted on a display panel by COG or the like. In this case, it is possible to achieve low power consumption of the high-definition display device. Therefore, in order to obtain a display device with lower power consumption, it is preferable to use amorphous silicon for the semiconductor layer of the transistor used in the pixel portion. In addition, the board|substrate 6810, the pixel part 6812, the FPC 6815, the IC chip 6816, the IC chip 6817, the sealing board 6818, and the sealing material 6819 of FIG. 101(B) are shown in FIG. It corresponds to the board|substrate 6710 of 100(A), the pixel part 6702, the FPC 6709, the IC chip 6719, the sealing board|substrate 6704, and the sealing material 6705, respectively.

In addition, by using amorphous silicon for the semiconductor layer of the transistor of the pixel portion 6812, it is possible to further reduce the cost. Moreover, it becomes possible to manufacture a large-sized display panel.

In addition, it is not necessary to provide the second gate driver, the first gate driver, and the signal line control circuit in the row direction and the column direction of the pixel. For example, as shown in Fig. 102(A), the peripheral driving circuit 6901 formed on the IC chip includes the first gate driver 6814, the second gate driver 6813, and the signal line shown in Fig. 101(B). You may make it have the function of the control circuit 6811. Further, the substrate 6900, the pixel portion 6902, the FPC 6904, the IC chip 6905, the IC chip 6906, the sealing substrate 6907, and the sealing material 6908 in Fig. 102(A) are shown in Fig. 102A. It corresponds to the board|substrate 6710 of 100(A), the pixel part 6702, the FPC 6709, the IC chip 6719, the sealing board|substrate 6704, and the sealing material 6705, respectively.

Fig. 102(B) is a schematic diagram for explaining the wiring of the display device of Fig. 102(A). This display device includes a substrate 6910 , a peripheral driving circuit 6911 , a pixel portion 6912 , an FPC 6913 , and an FPC 6914 . An external signal and a power source potential are input from the FPC 6913 to the peripheral drive circuit 6911 . Then, the output from the peripheral driving circuit 6911 is input to the wiring in the row direction and the column direction connected to the pixels included in the pixel portion 6912 .

103(A) and 103(B) show examples of a light emitting device applicable to the light emitting device 6718. FIG. That is, the configuration of the light emitting device applicable to the pixels shown in the above embodiments will be described with reference to FIGS. 103(A) and 103(B).

The light emitting device of FIG. 103(A) has an anode 7002 on a substrate 7001, a hole injection layer 7003 formed of a hole injection material, a hole transport layer 7004 formed of a hole transport material, a light emitting layer 7005, and electron transport. This is an element structure in which an electron transport layer 7006 formed of a material, an electron injection layer 7007 formed of an electron injection material, and a cathode 7008 are laminated. Here, the light emitting layer 7005 may be formed of only one type of light emitting material, but may be formed of two or more types of materials. In addition, the structure of the device of the present invention is not limited to this structure.

In addition to the laminate structure in which each functional layer shown in Fig. 103(A) is laminated, a device formed using a polymer compound, a high-efficiency device using a triplet light emitting material that emits light when the light emitting layer returns from a triplet excited state, etc., Transformation is multifaceted. These modifications can also be applied to a white light-emitting device obtained by dividing the light-emitting area into two areas by controlling the recombination area of carriers by the hole-blocking layer.

In the manufacturing method of the device of the present invention shown in Fig. 103A, first, a hole injection material, a hole transport material, and a light emitting material are sequentially deposited on a substrate 7001 having an anode 7002 (ITO). Next, an electron transporting material and an electron injecting material are deposited, and finally a cathode 7008 is formed by vapor deposition.

Next, materials suitable for a hole injecting material, a hole transporting material, an electron transporting material, an electron injecting material, and a light emitting material will be described below.

As the hole injection material, a porphyrin-based compound, phthalocyanine (hereinafter referred to as "H<sb>2</sb>Organic compounds such as "Pc") and copper phthalocyanine (hereinafter referred to as "CuPc") are useful. In addition, a material having a smaller ionization potential than the hole transporting material used and having a hole transporting function is also useful. It can be used as a hole injection material.Some materials are chemically doped with a conductive polymer compound, for example, polyethylene dioxythiophene (hereinafter referred to as "PEDOT") doped with polystyrene sulfonic acid (hereinafter referred to as "PSS"). described), polyaniline, etc. In addition, insulating high molecular compounds are also effective in terms of planarization of the positive electrode, and polyimides (hereinafter referred to as "PI") are often used. In addition, inorganic compounds are also used, There are not only thin films of metals such as gold and platinum, but also ultra-thin films of aluminum oxide (hereinafter, referred to as "alumina").

The most widely used hole transport material is an aromatic amine compound (ie, a compound having a benzene ring-nitrogen bond). As a material widely used as a hole transport material, 4,4'-bis(diphenylamino)-biphenyl (hereinafter referred to as "TAD") and its derivative 4,4'-bis[N-(3-) Methylphenyl)-N-phenyl-amino]-biphenyl (hereinafter referred to as "TPD"), 4,4'-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (hereinafter referred to as "TPD") , "α-NPD"), and also 4,4',4''-tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred to as "TDATA"), and starburst aromatic amine compounds such as 4,4',4''-tris[N-(3-methylphenyl)-N-phenyl-amino]-triphenylamine (hereinafter referred to as "MTDATA"). have.

As the electron transport material, metal complexes are frequently used, and Alq, BAlq, tris(4-methyl-8-quinolinolato)aluminum (hereinafter referred to as "Almq"), bis(10-hydroxybenzo[h] -quinolinato) a metal complex having a quinoline skeleton or a benzoquinoline skeleton, such as beryllium (hereinafter, referred to as "Bebq"). In addition, bis[2-(2-hydroxyphenyl)-benzooxazolato]zinc (hereinafter "Zn(BOX)<sb>2</sb>"), bis[2-(2-hydroxyphenyl)-benzothiazolato]zinc (hereinafter "Zn(BTZ)<sb>2</sb>")), etc., also have a metal complex having an oxazole-based or thiazole-based ligand. In addition to the metal complex, 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3 ,4-oxadiazole (hereinafter referred to as "PBD"), oxadiazole derivatives such as OXD-7, TAZ, 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5 triazole derivatives such as -(4-biphenylyl)-2,3,4-triazole (hereinafter referred to as "p-EtTAZ"), vasophenanthroline (hereinafter referred to as "BPhen"); A phenanthroline derivative such as BCP has electron transport properties.

As the electron injection material, the electron transport material described above can be used. In addition, an ultra-thin film of an insulating material such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetyl acetonate (hereinafter referred to as "Li(acac)") and 8-quinolinolato-lithium (hereinafter referred to as "Liq") are also effective.

As the light emitting material, Alq, Almq, BeBq, BAlq, Zn (BOX)<sb>2</sb>, Zn(BTZ)<sb>2</sb> In addition to metal complexes, such as these, various fluorescent dyes are effective. As fluorescent dyes, blue 4,4'-bis(2,2-diphenyl-vinyl)-biphenyl and red-orange 4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminosti lil)-4H-pyran and the like. A triplet light emitting material is also possible, and a complex having platinum or iridium as a central metal is the main component. As a triplet light emitting material, tris(2-phenylpyridine)iridium, bis(2-(4'-tolyl)pyridinato-N,C<sp>2'</sp>) acetylacetonato iridium (hereinafter "acacIr (tpy)<sb>2</sb>), 2,3,7,8,12,13,17,18-octaethyl-21H,23H-porphyrin platinum and the like are known.

By using the materials having each function as described above in combination, it is possible to manufacture a light emitting device with high reliability.

Moreover, as the display element 973 shown in Example 3, the light emitting element in which the layer was formed in the reverse order as shown in FIG.103(B) as shown in FIG.103(A) can be used. That is, on the substrate 7011 , a cathode 7018 , an electron injection layer 7017 formed of an electron injection material, an electron transport layer 7016 formed of an electron transport material, a light emitting layer 7015 , and a hole transport layer 7014 formed of a hole transport material ), a hole injection layer 7013 formed of a hole injection material, and an anode 7012 are sequentially stacked.

In addition, at least one of the anode and the cathode of the light emitting element needs to be transparent in order to extract light emission. Then, a transistor and a light emitting element are formed on a substrate, and a top emission structure for extracting light emission from a surface opposite to the substrate, a bottom emission structure for extracting light emission from a surface on the substrate side, and a surface on the substrate side and a surface on the opposite side of the substrate There is a light emitting device having a double-sided emission structure that emits light from the light emitting device, and the pixel configuration of the present invention can be applied to a light emitting device having any emission structure.

A light emitting device having a top emission structure will be described with reference to FIG. 104(A).

A driving TFT 7101 is formed on a substrate 7100, a first electrode 7102 is formed in contact with the source electrode of the driving TFT 7101, and thereon, a layer 7103 containing an organic compound and a second electrode 7103 are formed. Two electrodes 7104 are formed.

In addition, the first electrode 7102 is an anode of the light emitting device, and the second electrode 7104 is a cathode of the light emitting device. That is, a region between the first electrode 7102 and the second electrode 7104 in which the layer 7103 containing the organic compound is sandwiched becomes a light emitting device.

Here, as the material used for the first electrode 7102 functioning as the anode, it is preferable to use a material having a large work function. For example, a single-layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a lamination of a film containing titanium nitride and aluminum as a main component, a titanium nitride film and a film containing aluminum as a main component, and a titanium nitride film A three-layer structure with a barrage can be used. Moreover, in the case of a laminated structure, resistance as a wiring is also low, a favorable ohmic contact can be obtained, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed.

In addition, as a material used for the second electrode 7104 functioning as a cathode, a material having a small work function (Al, Ag, Li, Ca, or an alloy thereof, for example, MgAg, MgIn, AlLi, calcium fluoride, Alternatively, it is preferable to use a lamination of a metal thin film formed of calcium nitride) and a transparent conductive film (made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using a thin metal thin film and a transparent conductive film having light-transmitting properties, a cathode capable of transmitting light can be formed.

In this way, as indicated by the arrow in Fig. 104(A), the light from the light emitting element can be extracted from the upper surface. That is, when applied to the display panel shown in FIGS. 100A and 100B, light is emitted toward the sealing substrate 6704 side. Therefore, when the light emitting device of the top-emission structure is used in a display device, a light-transmitting substrate is used as the encapsulation substrate 6704 .

In addition, when providing an optical film, what is necessary is just to provide an optical film to the sealing board|substrate 6704.

Further, for the first electrode 7102, a metal film formed of a material such as MgAg, MgIn, AlLi, which functions as a cathode and has a small work function can be used. A transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used for the second electrode 7104 . Therefore, according to this configuration, it is possible to increase the transmittance of the top surface injection.

Further, a light emitting device having a lower surface emission structure will be described with reference to FIG. 104(B). Since the light emitting device has the same structure as in FIG. 104(A) except for the light emission structure, the same reference numerals will be used.

Here, as the material used for the first electrode 7102 functioning as an anode, it is preferable to use a material having a large work function. For example, a transparent conductive film such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having light-transmitting properties, an anode capable of transmitting light can be formed.

In addition, as a material used for the second electrode 7104 functioning as a cathode, a material having a small work function (Al, Ag, Li, Ca, or an alloy thereof, for example, MgAg, MgIn, AlLi, calcium fluoride, or Ca<sb>3</sb>N<sb>2</sb>) may be used. By using a metal film that reflects light, a cathode through which light does not transmit can be formed.

In this way, as indicated by the arrow in Fig. 104(B), the light from the light emitting element can be extracted from the lower surface. That is, when applied to the display panel of FIGS. 100A and 100B , light is emitted toward the substrate 6710 . Accordingly, when a light emitting device having a bottom emission structure is used in a display device, the substrate 6710 is a light-transmitting substrate.

In addition, when providing an optical film, what is necessary is just to provide an optical film to the board|substrate 6710.

Further, a light emitting device having a double-sided emission structure will be described with reference to FIG. 104(C). Since the light emitting device has the same structure as in Fig. 104(A) except for the light emission structure, the same reference numerals are used for explanation.

Here, as the material used for the first electrode 7102 functioning as an anode, it is preferable to use a material having a large work function. For example, a transparent conductive film such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having light-transmitting properties, an anode capable of transmitting light can be formed.

In addition, as a material used for the second electrode 7104 serving as a cathode, a material having a small work function (Al, Ag, Li, Ca, or an alloy thereof, for example, MgAg, MgIn, AlLi, calcium fluoride, Or a metal thin film formed of calcium nitride), a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In<sb>2</sb>O<sb>3</sb>-ZnO), zinc oxide (ZnO), etc.) is preferably used. A cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having light-transmitting properties.

In this way, as indicated by the arrow in Fig. 104(C), the light from the light emitting element can be extracted from both sides. That is, when applied to the display panel of FIGS. 100A and 100B , light is emitted toward the substrate 6710 side and the encapsulation substrate 6704 side. Accordingly, when the light emitting element having the double-sided injection structure is used in a display device, a light-transmitting substrate is used for both the substrate 6710 and the encapsulation substrate 6704 .

In addition, when providing an optical film, what is necessary is just to provide an optical film on both of the board|substrate 6710 and the sealing board|substrate 6704.

Further, it is possible to apply the present invention to a display device that realizes full color display using a white light emitting element and a color filter.

105, a base film 7202 is formed on a substrate 7200, a driving TFT 7201 is formed thereon, and a first electrode 7203 in contact with the source electrode of the driving TFT 7201 is formed, and a layer 7204 containing an organic compound and a second electrode 7205 are formed thereon.

In addition, the first electrode 7203 is an anode of the light emitting device, and the second electrode 7205 is a cathode of the light emitting device. That is, a region between the first electrode 7203 and the second electrode 7205 in which the layer 7204 containing the organic compound is sandwiched becomes a light emitting device. In the configuration of FIG. 105, white light is emitted. Then, a red color filter 7206R, a green color filter 7206G, and a blue color filter 7206B are provided on the upper portion of the light emitting element, so that full color display can be performed. Also, a black matrix (BM) 7207 for separating these color filters is provided.

The configurations of the light emitting devices described above can be used in combination, and can be applied to the display device having the pixel configuration of the present invention. In addition, the configuration of the display panel and the light emitting device described above is only an example, and it goes without saying that the pixel configuration of the present invention may be applied to a display device having a different configuration.

Next, a partial cross-sectional view of the pixel portion of the display panel will be described.

First, in the case where a crystalline semiconductor film (polysilicon (p-Si:H) film) is used for the semiconductor layer of the transistor, Figs. 106(A) and 106(B), and Figs. 107(A) and 107(B) ) is used to explain.

Here, the semiconductor layer is obtained by, for example, forming an amorphous silicon (a-Si) film on a substrate by a known film forming method. Moreover, it is not limited to an amorphous silicon film, Any semiconductor film (including microcrystalline semiconductor film) which has an amorphous structure can be used. Further, a compound semiconductor film having an amorphous structure, such as an amorphous silicon germanium film, may be used.

Next, the amorphous silicon film is crystallized by a laser crystallization method, a thermal crystallization method using RTA or furnace annealing, a thermal crystallization method using a metal element that promotes crystallization, or the like. Of course, such crystallization methods may be combined and performed.

As a result of the above crystallization, a crystallized region is formed in a part of the amorphous semiconductor film.

Further, the crystalline semiconductor film with partially increased crystallinity is patterned into a desired shape to form an island-shaped semiconductor film from the crystallized region. This semiconductor film is used as a semiconductor layer of a transistor.

As shown in FIG. 106(A), a base film 26102 is formed on a substrate 26101, and a semiconductor layer is formed thereon. The semiconductor layer includes a channel forming region 26103 of the driving transistor 26118, an impurity region 26105 serving as a source region or a drain region, and a channel forming region 26106 serving as a lower electrode of the capacitor 26119, an LDD region ( 26107) and an impurity region 26108. In addition, channel doping may be applied to the channel forming region 26103 and the channel forming region 26106 .

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. Further, as the underlying film 26102, aluminum nitride (AlN), silicon oxide (SiO)<sb>2</sb>), silicon oxynitride (SiO<sb>x</sb>N<sb>y</sb>) and the like, or a laminate of these can be used.

A gate electrode 26110 and an upper electrode 26111 of a capacitor are formed on the semiconductor layer with a gate insulating layer 26109 interposed therebetween.

An interlayer insulating material 26112 is formed to cover the driving transistor 26118 and the capacitor 26119 , and a wiring 26113 is formed on the interlayer insulating material 26112 to contact the impurity region 26105 through a contact hole. A pixel electrode 26114 is formed in contact with the wiring 26113 , and a second interlayer insulator 26115 is formed to cover an end of the pixel electrode 26114 and the wiring 26113 . Here, the second interlayer insulating material 26115 is formed using a positive photosensitive acrylic resin film. Then, a layer 26116 containing an organic compound and a counter electrode 26117 are formed on the pixel electrode 26114 , and a layer 26116 containing an organic compound is formed between the pixel electrode 26114 and the counter electrode 26117 . A light emitting device 26120 is formed in the interposed region.

Also, as shown in FIG. 106(B) , a region 26202 in which the LDD region constituting a part of the lower electrode of the capacitor 26119 overlaps the upper electrode 26111 may be formed. In addition, common code|symbol is used for the part common to Fig.106(A), and the description is abbreviate|omitted.

Further, as shown in FIG. 107(A), the second upper electrode 26301 formed on the same layer as the wiring 26113 in contact with the impurity region 26105 of the driving transistor 26118 may be provided. In addition, common code|symbol is used for the part common to Fig.106(A), and the description is abbreviate|omitted. An interlayer insulator 26112 is sandwiched between the second upper electrode 26301 and the upper electrode 26111 to form a second capacitor. In addition, since the second upper electrode 26301 is in contact with the impurity region 26108, a first capacitor having a configuration in which a gate insulating film 26109 is sandwiched between the upper electrode 26111 and the channel forming region 26106; A second capacitor having a configuration in which an interlayer insulator 26112 is sandwiched between the upper electrode 26111 and the second upper electrode 26301 is connected in parallel to form a capacitor 26302 including the first capacitor and the second capacitor. are doing Since the capacitance of the capacitor 26302 is the sum of the capacitance of the first capacitor and the capacitance of the second capacitor, a capacitor having a large capacity can be formed with a small area. That is, if the capacitor having the pixel configuration of the present invention is used, the aperture ratio can be further improved.

Alternatively, the capacitor shown in Fig. 107(B) may be configured. A base film 27102 is formed on the substrate 27101, and a semiconductor layer is formed thereon. The semiconductor layer includes a channel forming region 27103 of the driving transistor 27118 and an impurity region 27105 serving as a source region or a drain region. In addition, channel doping may be performed in the channel formation region 27103 .

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. In addition, as the underlying film 27102, aluminum nitride (AlN), silicon oxide (SiO<sb>2</sb>), silicon oxynitride (SiO<sb>x</sb>N<sb>y</sb>) and the like, or a laminate of these can be used.

A gate electrode 27107 and a first electrode 27108 are formed on the semiconductor layer with a gate insulating film 27106 interposed therebetween.

A first interlayer insulating material 27109 is formed to cover the driving transistor 27118 and the first electrode 27108, and a wiring 27110 is formed on the first interlayer insulating material 27109 to contact the impurity region 27105 through a contact hole. is formed. In addition, the second electrode 27111 is formed on the same layer of the same material as the wiring 27110 .

In addition, a third interlayer insulating material 27112 is formed to cover the wiring 27110 and the second electrode 27111 , and the pixel electrode 27113 is in contact with the wiring 27110 through a contact hole on the second interlayer insulating material 27112 . is formed. In addition, the third electrode 27114 is formed on the same layer of the same material as the pixel electrode 27113 . Here, a capacitor 27119 is formed of the first electrode 27108 , the second electrode 27111 , and the third electrode 27114 .

A third interlayer insulating material 27115 is formed to cover the pixel electrode 27113 and the ends of the third electrode 27114 , and a layer containing an organic compound is formed on the third interlayer insulating material 27115 and the third electrode 27114 . 27116 and the counter electrode 27117 are formed, and a light emitting element 27120 is formed in a region where a layer 27116 containing an organic compound is sandwiched between the pixel electrode 27113 and the counter electrode 27117 .

As described above, examples of the configuration of the transistor using the crystalline semiconductor film for the semiconductor layer include the configurations shown in Figs. 106 (A) and 106 (B) and 107 (A) and 107 (B). . The transistors having the structures shown in Figs. 106 (A) and 106 (B) and 107 (A) and 107 (B) are examples of top-gate transistors. That is, the transistor may be a p-channel transistor or an n-channel transistor. In the case of an n-channel transistor, the LDD region may be formed to overlap the gate electrode, may not overlap the gate electrode, or a part of the LDD region may be formed to overlap the gate electrode. Further, the gate electrode may have a tapered shape, or an LDD region may be formed in a self-aligning manner under the tapered portion of the gate electrode. In addition, the number of gate electrodes is not limited to two, The multi-gate structure which has three or more gate electrodes may be sufficient, and one gate electrode may be sufficient.

By using a crystalline semiconductor film for the semiconductor layer (channel formation region, source region, drain region, etc.) of the transistor included in the pixel of the present invention, for example, the pixel portion ( It becomes easy to form the first gate driver 6703, the second gate driver 6706, and the signal line control circuit 6701 on the same substrate as the 6702.

In addition, as a configuration of a transistor using polysilicon (p-Si:H) as a semiconductor layer, each of FIGS. , a partial cross-section of a display panel using a transistor having a bottom gate structure in which a gate electrode is positioned under a semiconductor layer.

A base film 7502 is formed on the substrate 7501 . Further, a gate electrode 7503 is formed over the underlying film 7502 . Also, a first electrode 7504 is formed on the same layer as the gate electrode and made of the same material. As the material of the gate electrode 7503, phosphorus-doped polycrystalline silicon can be used. In addition to polycrystalline silicon, silicide, which is a compound of metal and silicon, may be used.

Then, a gate insulating film 7505 is formed so as to cover the gate electrode 7503 and the first electrode 7504 . As the gate insulating film 7505, a silicon oxide film, a silicon nitride film, or the like is used.

Further, a semiconductor layer is formed over the gate insulating film 7505 . The semiconductor layer includes a channel forming region 7506 , an LDD region 7507 , and an impurity region 7508 serving as a source region or drain region of the driving transistor 7522 , and a channel forming region serving as the second electrode of the capacitor 7523 . 7509 , an LDD region 7510 , and an impurity region 7511 . In addition, channel doping may be applied to the channel forming region 7506 and the channel forming region 7509 .

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. In addition, as the underlying film 7502, aluminum nitride (AlN), silicon oxide (SiO<sb>2</sb>), silicon oxynitride (SiO<sb>x</sb>N<sb>y</sb>) and the like, or a laminate of these can be used.

A first interlayer insulator 7512 is formed so as to cover the semiconductor layer, and a wiring 7513 is formed on the first interlayer insulator 7512 so as to be in contact with the impurity region 7508 through a contact hole. Further, a third electrode 7514 is formed on the same layer as the wiring 7513 and made of the same material. A capacitor 7523 is constituted by the first electrode 7504 , the second electrode and the third electrode 7514 .

In addition, an opening 7515 is formed in the first interlayer insulating material 7512 . A second interlayer insulating material 7516 is formed to cover the driving transistor 7522 , the capacitor 7523 , and the opening 7515 , and a pixel electrode 7517 is formed on the second interlayer insulating material 7516 through a contact hole. . Then, an insulating material 7518 is formed to cover the end of the pixel electrode 7517 . As the insulator 7518, for example, a positive photosensitive acrylic resin film can be used. Then, on the pixel electrode 7517 , a layer 7519 containing an organic compound and a counter electrode 7520 are formed, and a layer 7519 containing an organic compound between the pixel electrode 7517 and the counter electrode 7520 . A light emitting element 7521 is formed in this interposed region. In addition, an opening 7515 is positioned under the light emitting device 7521 . That is, when light emission from the light emitting element 7521 is taken out from the substrate side, since the opening 7515 is provided, the transmittance can be improved.

Further, the configuration shown in FIG. 108(B) may be adopted in which the fourth electrode 7524 is formed on the same layer as the pixel electrode 7517 in FIG. 108(A) and made of the same material. Then, the capacitor 7523 may be formed by the first electrode 7504 , the second electrode, the third electrode 7514 , and the fourth electrode 7524 .

Next, a case in which an amorphous silicon (a-Si:H) film is used for the semiconductor layer of the transistor will be described. 109(A) and 109(B) show a case of a top gate type transistor, and FIGS. 110(A) and 110(B) and 111(A) and 111(B) show a case of a bottom gate type transistor. indicates the case.

Fig. 109(A) shows a cross section of a transistor of a forward stagger structure using amorphous silicon as a semiconductor layer. A base film 7602 is formed on the substrate 7601 . Further, a pixel electrode 7603 is formed over the underlying film 7602 . Also, a first electrode 7604 is formed on the same layer as the pixel electrode 7603 and made of the same material.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. In addition, as the underlying film 7602, aluminum nitride (AlN), silicon oxide (SiO<sb>2</sb>), silicon oxynitride (SiO<sb>x</sb>N<sb>y</sb>) and the like, or a laminate of these can be used.

Further, a wiring 7605 and a wiring 7606 are formed on the underlying film 7602 , and the end of the pixel electrode 7603 is covered with the wiring 7605 . An n-type semiconductor layer 7607 and an n-type semiconductor layer 7608 each having an n-type conductivity are formed on the wiring 7605 and the wiring 7606 . Further, a semiconductor layer 7609 is formed on the underlying film 7602 between the wiring 7605 and the wiring 7606 . A part of the semiconductor layer 7609 extends even over the n-type semiconductor layer 7607 and the n-type semiconductor layer 7608 . Further, this semiconductor layer is formed of a non-crystalline semiconductor film such as an amorphous silicon (a-Si:H) film or a microcrystalline semiconductor (μ-Si:H) film. In addition, a gate insulating film 7610 is formed on the semiconductor layer 7609 . An insulating film 7611 made of the same material on the same layer as the gate insulating film 7610 is also formed on the first electrode 7604 . As the gate insulating film 7610, a silicon oxide film, a silicon nitride film, or the like is used.

Also, a gate electrode 7612 is formed on the gate insulating layer 7610 . Further, on the same layer as the gate electrode, a second electrode 7613 made of the same material is formed on the first electrode 7604 with an insulating film 7611 interposed therebetween. A capacitor 7619 in which an insulating film 7611 is sandwiched is formed between the first electrode 7604 and the second electrode 7613 . In addition, an interlayer insulator 7614 is formed to cover the end of the pixel electrode 7603 , the driving transistor 7618 , and the capacitor 7619 .

On the interlayer insulating material 7614 and the pixel electrode 7603 located in the opening of the interlayer insulating material 7614, a layer 7615 containing an organic compound and a counter electrode 7616 are formed. A light emitting element 7617 is formed in a region where a layer 7615 containing an organic compound is sandwiched between the pixel electrode 7603 and the counter electrode 7616 .

In addition, instead of the first electrode 7604 shown in FIG. 109(A), a first electrode 7620 as shown in FIG. 109(B) may be formed. The first electrode 7620 is formed on the same layer as the wiring 7605 and the wiring 7606 and made of the same material.

110(A) and 110(B) show partial cross-sections of a display panel including a bottom-gate transistor using amorphous silicon as a semiconductor layer.

A base film 7702 is formed on the substrate 7701 . Further, a gate electrode 7703 is formed over the underlying film 7702 . Also, a first electrode 7704 is formed on the same layer as the gate electrode and made of the same material. As a material of the gate electrode 7703, phosphorus-doped polycrystalline silicon can be used. In addition to polycrystalline silicon, silicide, which is a compound of metal and silicon, may be used.

Further, a gate insulating film 7705 is formed so as to cover the gate electrode 7703 and the first electrode 7704 . As the gate insulating film 7705, a silicon oxide film, a silicon nitride film, or the like is used.

Further, a semiconductor layer 7706 is formed over the gate insulating film 7705 . Further, a semiconductor layer 7707 is formed on the same layer as the semiconductor layer 7706 and made of the same material.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. In addition, as the underlying film 7602, aluminum nitride (AlN), silicon oxide (SiO<sb>2</sb>), silicon oxynitride (SiO<sb>x</sb>N<sb>y</sb>) and the like, or a laminate of these can be used.

N-type semiconductor layers 7708 and 7709 having n-type conductivity are formed on the semiconductor layer 7706 , and an n-type semiconductor layer 7710 is formed on the semiconductor layer 7707 .

Wirings 7711 and 7712 are formed on the n-type semiconductor layers 7708 and 7709, respectively, and on the n-type semiconductor layer 7710, a conductive layer ( 7713) is formed.

The second electrode is composed of a semiconductor layer 7707 , an n-type semiconductor layer 7710 , and a conductive layer 7713 . Also, a capacitor 7720 having a structure in which a gate insulating film 7705 is sandwiched between the second electrode and the first electrode 7704 is formed.

In addition, one end of the wiring 7711 is extended, and a pixel electrode 7714 is formed so as to be in contact with the upper portion of the extended wiring 7711 .

In addition, an insulating material 7715 is formed to cover the end of the pixel electrode 7714 , the driving transistor 7719 , and the capacitor 7720 .

A layer 7716 containing an organic compound and a counter electrode 7717 are formed on the pixel electrode 7714 and the insulator 7715 . A light emitting element 7718 is formed in a region where a layer 7716 containing an organic compound is sandwiched between the pixel electrode 7714 and the counter electrode 7717 .

The semiconductor layer 7707 and the n-type semiconductor layer 7710 that are part of the second electrode of the capacitor are not necessarily formed. That is, since the second electrode may be the conductive layer 7713 , the capacitor may have a structure in which a gate insulating layer is sandwiched between the first electrode 7704 and the conductive layer 7713 .

Further, in FIG. 110(A), the pixel electrode 7714 is formed before the wiring 7711 is formed, and as shown in FIG. 110(B), the second electrode 7721 composed of the pixel electrode 7714 and A capacitor 7720 having a structure in which a gate insulating layer 7705 is sandwiched between the first electrodes 7704 may be formed.

110(A) and 110(B) show a transistor having an inverse staggered channel-etch structure, however, a transistor having a channel protection structure may be used. A transistor having a channel protection structure will be described with reference to FIGS. 111(A) and 111(B).

The transistor of the channel protection structure shown in Fig. 111(A) has a channel etch shown in Fig. 110(A) in that an insulating material 7801 serving as an etching mask is provided over the region where the channel of the semiconductor layer 7706 is to be formed. The structure is different from that of the driving transistor 7719. The same code|symbol is used for other common parts other than that point.

Similarly, in the transistor of the channel protection structure shown in Fig. 111(B), the insulator 7802 serving as an etching mask is provided over the region where the channel of the semiconductor layer 7706 is to be formed, as shown in Fig. 110(B). It is different from the driving transistor 7719 of the channel etch structure shown in FIG. The same code|symbol is used for other common parts other than that point.

By using the amorphous semiconductor film as the semiconductor layer (channel formation region, source region, drain region, etc.) of the transistor included in the pixel of the present invention, the manufacturing cost can be reduced. For example, by using the pixel configuration shown in Embodiment 3, it is possible to apply an amorphous semiconductor film.

In addition, the structure of the transistor and the capacitor to which the pixel configuration of the present invention can be applied is not limited to the above-described configuration, and various transistors and capacitors may be used.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the shift register circuit of the present invention connected to the display panel shown in this embodiment supplies the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 5]

The display device of the present invention can be applied to various electronic devices. Specifically, it may be applied to a display unit of an electronic device. As such electronic devices, cameras such as video cameras and digital cameras, goggles-type displays, navigation systems, sound reproduction devices (car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones, a portable game machine or electronic book), an image reproducing apparatus equipped with a recording medium (specifically, an apparatus equipped with a display capable of reproducing a recording medium such as a DVD (Digital Versatile Disc) and displaying the image), etc. can

117(A) shows a display including a case 84101, a support 84102, a display unit 84103, and the like. A display device having the pixel configuration of the present invention can be used for the display portion 84103 . In addition, this display includes a display device for all information display, such as for personal computers, for receiving television broadcasts, and for displaying advertisements. A display using the display device having the pixel configuration of the present invention for the display unit 84103 can prevent display defects while suppressing power consumption. Moreover, it is also possible to achieve cost reduction.

In recent years, the request|requirement of the enlargement of a display is increasing. And with the enlargement of a display, an increase in price has become a problem. Therefore, it becomes a subject to reduce the manufacturing cost as much as possible and to provide a high-quality product at as low a price as possible.

For example, by applying the pixel configuration shown in Embodiment 3 to the pixel portion of the display panel, it is possible to provide a display panel configured using unipolar transistors. Accordingly, it is possible to reduce the number of steps and reduce the manufacturing cost.

Further, as shown in Fig. 100A, by forming the pixel portion and the peripheral driving circuit on the same substrate, a display panel can be formed using a circuit composed of a unipolar transistor.

In addition, by using an amorphous semiconductor (for example, amorphous silicon (a-Si:H)) for the semiconductor layer of the transistor of the circuit included in the pixel portion, the manufacturing process can be simplified and the cost can be further reduced. . In this case, as shown in Figs. 101(B) and 102(A), a driving circuit around the pixel portion may be formed on an IC chip and mounted on a display panel using COG or the like. In this way, by using the amorphous semiconductor, it becomes easy to enlarge the display.

117(B) shows a camera including a main body 84201, a display unit 84202, an image receiving unit 84203, operation keys 84204, an external connection port 84205, a shutter 84206, and the like.

BACKGROUND ART In recent years, production competition is intensifying along with higher performance of digital cameras and the like. Therefore, it is important to provide high-performance products at as low a price as possible. A digital camera using the display device having the pixel configuration of the present invention for the display portion 84202 can prevent display defects while suppressing power consumption. In addition, it is also possible to achieve cost reduction.

For example, by using the pixel configuration shown in the third embodiment for the pixel portion, the pixel portion can be configured with a unipolar transistor. Also, as shown in Fig. 101(A), a signal line control circuit with high operating speed is formed on the IC chip, and a gate driver with relatively low operating speed is formed with a circuit composed of unipolar transistors on the same substrate as the pixel portion. By doing so, high performance can be realized and cost reduction can be achieved. In addition, by using an amorphous semiconductor such as amorphous silicon for the pixel portion and the semiconductor layer of the transistor included in the gate driver formed on the same substrate as the pixel portion, the cost can be further reduced.

117(C) shows a computer including a main body 84301, a case 84302, a display unit 84303, a keyboard 84304, an external connection port 84305, a pointing device 84306, and the like. A computer using the display device having the pixel configuration of the present invention for the display unit 84303 can prevent display defects while suppressing power consumption. In addition, it is also possible to achieve cost reduction.

117(D) shows a mobile computer including a main body 84401, a display portion 84402, a switch 84403, operation keys 84404, an infrared port 84405, and the like. A mobile computer using the display device having the pixel configuration of the present invention for the display unit 84402 can prevent display defects while suppressing power consumption. In addition, it is also possible to achieve cost reduction.

117(E) shows a portable image reproducing apparatus (specifically, a DVD player) provided with a recording medium, which includes a main body 84501, a case 84502, a display unit A 84503, and a display unit B ( 84504), a recording medium reading unit 84505, operation keys 84506, a speaker unit 84507, and the like. The display unit A 84503 mainly displays image information, and the display unit B 84504 mainly displays character information. An image reproducing apparatus using the display device having the pixel configuration of the present invention for the display portion A 84503 and the display portion B 84504 can prevent display defects while suppressing power consumption. Moreover, it is also possible to achieve cost reduction.

117(F) shows a goggle-type display including a main body 84601, a display portion 84602, an earphone 84603, and a support portion 84604. In FIG. The goggle-type display using the display device having the pixel configuration of the present invention for the display portion 84602 can prevent display defects while suppressing power consumption. Moreover, it is also possible to achieve cost reduction.

Fig. 117(G) shows a portable game machine including a case 84701, a display unit 84702, a speaker unit 84703, operation keys 84704, a storage medium insertion unit 84705, and the like. A portable game machine in which the display device having the pixel configuration of the present invention is used for the display portion 84702 can prevent display defects while suppressing power consumption. Moreover, it is also possible to achieve cost reduction.

Fig. 117(H) shows a digital camera having a television receiving function, which digital camera has a main body 84801, a display unit 84802, operation keys 84803, a speaker 84804, a shutter 84805, and an image receiving unit 84806 ), an antenna 84807, and the like. A digital camera having a television reception function, in which the display device having the pixel configuration of the present invention is used for the display portion 84802, can prevent display defects while suppressing power consumption. Moreover, the aperture ratio of the pixel is high, and high-definition display is attained. In addition, it is also possible to achieve cost reduction.

For example, by using the pixel structures of FIGS. 96 to 99, 118, and 119 for the pixel portion, the aperture ratio of the pixel can be increased. Specifically, the aperture ratio may be increased by using the n-channel transistor as the driving transistor for driving the light emitting device. Accordingly, a digital camera having a television receiving function, having a high-definition display portion, can be provided.

A digital camera having a television receiving function is multifunctional, and while the frequency of use for watching television and the like increases, it is required to prolong the battery life per charge.

For example, as shown in Figs. 101(B) and 102(A), it is possible to reduce power consumption by forming a peripheral driving circuit on an IC chip and using CMOS or the like.

As described above, the present invention can be applied to various electronic devices.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the shift register circuit of the present invention connected to the electronic device described in this embodiment supplies the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 6]

In the present embodiment, a configuration example of a mobile phone having a display unit using the pixel configuration of the present invention will be described with reference to FIG.

The display panel 8301 is detachably assembled to the housing 8330 . The shape and size of the housing 8330 may be appropriately changed according to the size of the display panel 8301 . The housing 8330 to which the display panel 8301 is fixed is inserted into the printed circuit board 8331 and assembled as a module.

The display panel 8301 is connected to the printed circuit board 8331 through the FPC 8313 . On the printed circuit board 8331 , a signal processing circuit 8335 including a speaker 8332 , a microphone 8333 , a transmission/reception circuit 8334 , a CPU, a controller, and the like is provided. The module, the input unit 8336, the battery 8337, and the antenna 8340 are combined and housed in the case 8339. The pixel portion of the display panel 8301 is provided so as to be viewed from the opening window formed in the case 8339 .

In the display panel 8301, a pixel portion and a part of a peripheral driving circuit (a driving circuit having a low operating frequency among a plurality of driving circuits) are formed on the same substrate by using a transistor, and a part of the peripheral driving circuit (a plurality of driving circuits) is formed on the same substrate. A driving circuit having a medium operating frequency) may be formed on an IC chip, and the IC chip may be mounted on the display panel 8301 using COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed circuit board. With such a configuration, power consumption of the display device can be reduced, and the battery life per charge of the mobile phone can be prolonged. In addition, it is possible to reduce the cost of the mobile phone.

In addition, the pixel configuration shown in the above embodiments can be appropriately applied to the pixel portion.

For example, by applying the pixel configuration or the like shown in the third embodiment, the number of manufacturing steps can be reduced. That is, by configuring the pixel portion and the peripheral driving circuit formed on the same substrate as the pixel portion by unipolar transistors, cost reduction can be realized.

Further, in order to further reduce power consumption, as shown in Figs. 101 (B) and 102 (A), a pixel portion is formed on a substrate using transistors, and all peripheral driving circuits are formed on an IC chip, The IC chip may be mounted on a display panel by COG (Chip On Glass) or the like.

Further, the configuration shown in the present embodiment is an example of a mobile phone, and the pixel configuration of the present invention is not limited to the mobile phone having such a configuration, and can be applied to a mobile phone having various configurations.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the shift register circuit of the present invention included in the cellular phone described in this embodiment supplies the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.

[Example 7]

In this embodiment, a configuration example of an electronic device having a display unit including a display device using the pixel configuration of the present invention, particularly a television receiver including an EL module, will be described.

112 shows an EL module in which a display panel 7901 and a circuit board 7911 are combined. The display panel 7901 includes a pixel portion 7902 , a scan line driver circuit 7903 , and a signal line driver circuit 7904 . A control circuit 7912 , a signal dividing circuit 7913 , and the like are formed on the circuit board 7911 . The display panel 7901 and the circuit board 7911 are connected to each other by a connection wiring 7914 . As the connection wiring, an FPC or the like can be used.

In the display panel 7901, the pixel portion 7902 and a part of the peripheral driving circuit (a driving circuit having a low operating frequency among a plurality of driving circuits) are formed on the same substrate using transistors, and a part of the peripheral driving circuit (a plurality of driving circuits) is formed on the same substrate. A driving circuit having a high operating frequency among the driving circuits) may be formed on an IC chip, and the IC chip may be mounted on the display panel 7901 using COG (Chip On Glass) or the like. Alternatively, the IC chip may be mounted on the display panel 7901 using TAB (Tape Automated Bonding) or a printed circuit board.

Further, as the pixel portion, the pixel configuration shown in the above embodiments can be appropriately applied.

For example, by applying the pixel configuration or the like shown in the third embodiment, the number of manufacturing steps can be reduced. That is, by configuring the pixel portion and the peripheral driving circuit formed on the same substrate as the pixel portion by unipolar transistors, cost reduction can be realized.

Further, in order to further reduce power consumption, a pixel portion is formed using a transistor on a glass substrate, all peripheral driving circuits are formed on an IC chip, and the IC chip is mounted on a display panel by COG (Chip On Glass) or the like. It may be mounted.

In addition, by applying the pixel configurations shown in FIGS. 96 to 99, 118, and 119 of the above embodiments, since a pixel can be configured only with an n-channel transistor, an amorphous semiconductor (eg, amorphous silicon) can be applied to the semiconductor layer of the transistor. That is, it becomes possible to manufacture a large-sized display device in which it is difficult to form a uniform crystalline semiconductor film. In addition, by using the amorphous semiconductor film for the semiconductor layer of the transistor constituting the pixel, the number of manufacturing steps can be reduced and the manufacturing cost can also be reduced.

In addition, when the amorphous semiconductor film is applied to the semiconductor layer of the transistor constituting the pixel, the pixel portion is formed using the transistor on the substrate, all peripheral driving circuits are formed on the IC chip, and the IC chip is applied to the COG (Chip On Glass). ) is preferably mounted on the display panel. Fig. 101B shows an example of a configuration in which a pixel portion is formed on a substrate, and an IC chip having a peripheral driver circuit is mounted on the substrate by COG or the like.

An EL television receiver can be completed by this EL module. Fig. 113 is a block diagram showing the main configuration of an EL television receiver. The tuner 8001 receives a video signal and an audio signal. The video signal includes a video signal amplifier circuit 8002, a video signal processing circuit 8003 for converting a signal output from the video signal amplifier circuit 8002 into color signals corresponding to each color of red, green, and blue; It is processed by the control circuit 8012 which converts the image signal into the input specification of the driving circuit. The control circuit 8012 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 8013 may be provided on the signal line side to divide and supply the input digital signal into m signals.

Among the signals received by the tuner 8001 , an audio signal is sent to an audio signal amplifying circuit 8004 , and its output is supplied to a speaker 8007 via an audio signal processing circuit 8005 . The control circuit 8008 receives control data of the receiving station (reception frequency) and volume from the input unit 8009, and sends signals to the tuner 8001 and the audio signal processing circuit 8005.

114(A) shows a television receiver in which an EL module of a different form from that of FIG. 113 is assembled. In Fig. 114(A), a display screen 8102 is composed of an EL module. In addition, a speaker 8103 , an operation switch 8104 , and the like are appropriately provided in the housing 8101 .

Also, Fig. 114(B) shows a television receiver with a portable wireless display. The case 8112 has a built-in battery and a signal receiver, and the display unit 8113 and the speaker unit 8117 are driven by the battery. The battery may be repeatedly charged by the battery charger 8110 . Also, the battery charger 8110 may transmit/receive an image signal and may transmit the image signal to a signal receiver of the display. The case 8112 is controlled by an operation key 8116 . The device shown in Fig. 114(B) can also be called a video-audio two-way communication device because it is also possible to send a signal from the case 8112 to the battery charger 8110 by operating the operation key 8116 . In addition, this device sends a signal from the case 8112 to the battery charger 8110 by operating the operation key 8116, and causes other electronic devices to receive a signal that can be transmitted by the battery charger 8110. , it can also be said to be a general-purpose remote control device because communication control of other electronic devices is also possible. The present invention can be applied to the display unit 8113 .

115(A) shows a module in which a display panel 8201 and a printed wiring board 8202 are combined. The display panel 8201 includes a pixel portion 8203 in which a plurality of pixels are formed, a first gate driver 8204, a second gate driver 8205, and a signal line driver circuit 8206 for supplying a video signal to the selected pixel. are being prepared

The printed wiring board 8202 includes a controller 8207, a central processing unit (CPU) 8208, a memory 8209, a power supply circuit 8210, an audio processing circuit 8211, a transmission/reception circuit 8212, and the like. have. The printed wiring board 8202 is connected to the display panel 8201 via an FPC (Flexible Printed Circuit) 8213 . The printed wiring board 8202 may be configured such that a capacitor, a buffer circuit, or the like is provided to prevent noise from being applied to the power supply voltage or signal, or from slowing the rise of the signal. In addition, the controller 8207 , the voice processing circuit 8211 , the memory 8209 , the CPU 8208 , the power circuit 8210 , and the like may be mounted on the display panel 8201 using a chip on glass (COG) method. have. By using the COG method, the size of the printed wiring board 8202 can be reduced.

Various control signals are input and output through an interface unit (I/F unit) 8214 provided in the printed wiring board 8202 . In addition, an antenna port 8215 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 8202 .

Fig. 115(B) shows a block diagram of the module shown in Fig. 115(A). This module includes a VRAM 8216 , a DRAM 8217 , a flash memory 8218 , and the like as a memory 8209 . The VRAM 8216 stores data of images to be displayed on the panel, the DRAM 8217 stores image data or audio data, and the flash memory 8218 stores various programs.

The power supply circuit 8210 supplies power to operate the display panel 8201 , the controller 8207 , the CPU 8208 , the audio processing circuit 8211 , the memory 8209 , and the transmission/reception circuit 8212 . In addition, depending on the specifications of the panel, the power supply circuit 8210 may be provided with a current source.

The CPU 8208 has a control signal generating circuit 8220 , a decoder 8221 , a register 8222 , an arithmetic circuit 8223 , a RAM 8224 , an interface 8219 for the CPU 8208 , and the like. Various signals input to the CPU 8208 via the interface 8219 are once held in the register 8222 and then input to the arithmetic circuit 8223, the decoder 8221, and the like. The arithmetic circuit 8223 performs an arithmetic operation based on the input signal, and designates a place to send various commands. On the other hand, the signal input to the decoder 8221 is decoded and input to the control signal generating circuit 8220 . The control signal generating circuit 8220 generates a signal including various commands based on the input signal, and sends the signal to a location designated by the arithmetic circuit 8223, specifically, the memory 8209, the transmission/reception circuit 8212, the voice processing circuit 8211, the controller 8207, and the like.

The memory 8209, the transmission/reception circuit 8212, the voice processing circuit 8211, and the controller 8207 each operate according to the received command. Hereinafter, the operation will be briefly described.

A signal input from the input means 8225 is sent to the CPU 8208 mounted on the printed wiring board 8202 via the I/F unit 8214 . The control signal generating circuit 8220 converts the image data stored in the VRAM 8216 into a predetermined format according to a signal sent from an input unit 8225 such as a pointing device or a keyboard, and converts the converted data into the controller 8207 ) is sent to

The controller 8207 performs data processing of a signal including image data sent from the CPU 8208 in accordance with the specifications of the panel, and supplies the signal to the display panel 8201 . In addition, the controller 8207, based on the power supply voltage input from the power supply circuit 8210 and various signals input from the CPU 8208, the Hsync signal, the Vsync signal, the clock signal CLK, and the AC voltage (AC Cont) , generates a switching signal L/R, and supplies the signals to the display panel 8201 .

In the transmission/reception circuit 8212, signals transmitted and received as radio waves by the antenna 8228 are processed. Specifically, the transmission/reception circuit 8212 includes a high-frequency circuit such as an isolator, a band pass filter, a voltage controlled oscillator (VCO), a low pass filter (LPF), a coupler, and a balun. A signal including audio information among the signals transmitted and received by the transmission/reception circuit 8212 is sent to the audio processing circuit 8211 according to a command from the CPU 8208 .

A signal including audio information sent in accordance with an instruction from the CPU 8208 is demodulated into an audio signal in the audio processing circuit 8211 and sent to the speaker 8227 . In addition, the audio signal sent from the microphone 8226 is modulated by the audio processing circuit 8211, and is sent to the transmission/reception circuit 8212 according to an instruction from the CPU 8208.

The controller 8207 , the CPU 8208 , the power supply circuit 8210 , the audio processing circuit 8211 , and the memory 8209 may be mounted as a package according to the present embodiment.

Of course, the present invention is not limited to a television receiver, and can be applied to various uses, such as a monitor of a personal computer, an information display panel at a railway station or an airport, or an advertisement display panel at a street, especially as a display medium with a large area.

In addition, this embodiment can be practiced freely in combination with any description of other embodiments and examples in this specification. That is, in the non-selection period, the transistor is turned on at regular time intervals, so that the shift register circuit of the present invention included in the electronic device described in this embodiment supplies the power supply potential to the output terminal. Accordingly, a power supply potential is supplied to the output terminal of the shift register circuit through this transistor. Since this transistor is not always turned on in the non-selection period, the threshold voltage shift of this transistor can be suppressed. Further, the output terminal of the shift register circuit is supplied with a power supply potential at regular time intervals through this transistor. Accordingly, the shift register circuit can suppress the occurrence of noise at the output terminal.