Semiconductor device and method for manufacturing the same

Semiconductor device and manufacturing method thereof

<b>technical field</b>

The present invention relates to a semiconductor device having a full silicide gate electrode and a method for manufacturing the same, and in particular, a technology for enhancing the performance and reliability of MOS-type field effect transistors (MOSFET). is about

<b>background technology</b>

In the development of a state-of-the-art CMOS (complementary MOS) device requiring increasingly smaller transistors, a problem of deterioration in driving current due to depletion of a poly-Si electrode has been raised. Because of this problem, a technique for avoiding depletion of the electrode by applying metal gate electrodes to prevent deterioration of the driving current is being studied.

Materials contemplated for use for the metal gate electrodes include pure metals, metal nitrides and silicides, but in any case the threshold voltages of n-type MOSFETs (hereinafter "nMOS") and p-type MOSFETs (hereinafter "pMOS"). It is required that the values Vth can be set to appropriate levels.

For high-performance CMOS transistors, Vth is required to be set to about ±0.1 eV, whereas in order to satisfy this requirement, materials below the work function (4.0 eV) of n-type poly-Si (4.0 eV) for nMOS or pMOS are required. It is necessary to use a material with a work function (5.2 eV) or higher of p-type poly-Si for the gate electrode.

As a means of realizing these objects, a method of controlling the Vth of a transistor by separately using heterogeneous metals or alloys having different work functions for an nMOS gate electrode and a pMOS gate electrode (dual metal gate technology) is disclosed. suggest

For example, in non-patent document 1 (International electron devices meeting technical digest 2002, p. 359), SiO<sb>2</sb> It is described that the work functions of Ta and Ru formed in ? are 4.125 eV and 4.95 eV, respectively, and that work function modulation as much as 0.8 eV is possible between these two electrodes.

Meanwhile, a technology for full silicide electrodes in which poly-Si is completely silicided with Ni, Hf, W, etc. has recently attracted attention.

For example, in Patent Document 1 (US Patent Publication No. 2005/0070062), SiO as a gate insulating film<sb>2</sb> and a silicide electrode obtained by full silicidation of poly-Si implanted with impurities including P and B as a gate electrode (1) making the formation process more compatible with conventional CMOS processes, (2) SiO<sb>2</sb> It is disclosed that the threshold voltage can be controlled by adding impurities to poly-Si before silicidation of the phase.

The present disclosure proposes that the full silicide electrode is a promising metal gate. In particular, the threshold control made possible by adding impurities is that the impurities (B, Al, Ga, In and Tl in the case of pMOS or N, P, As, Sb and Bi in the case of nMOS) used in conventional semiconductor processes are removed. When applied, an effective work function of about 4.2 eV to 4.4 eV for nMOS or about 4.7 eV to 4.9 eV for pMOS was obtained. These threshold changes are caused by the so-called "snowflowing" effect upon silicidation, resulting in a silicide electrode/SiO<sb>2</sb> It arises from the separation of impurities added to the gate insulating film interface. Since the threshold control by the addition of impurities enables the differentiated fabrication of pMOS and nMOS, SiO2 as the gate insulating film<sb>2</sb> A promising method of controlling the threshold of a transistor using

Further, in the technique described in Patent Document 2 (Japanese Patent Laid-Open No. 2005-129551), for nMOS gate electrodes have a Ni content of 30% to 60% and contain n-type impurities, and for pMOS use obtained effective work functions of about 4.1 eV and 5.1 eV, respectively, when the gate electrodes had a Ni content of 40% to 70% and contained p-type impurities.

However, these techniques are accompanied by the following problems.

Dual metal gate technology for the differentiated fabrication of dissimilar metals or alloys with different work functions requires a process of removing the metal layer deposited on the pMOS gate insulating film or the nMOS gate insulating film by etching, which is the gate insulating film during etching. It deteriorates the quality and causes deterioration of performance characteristics and reliability of the device.

SiO<sb>2</sb> When a NiSi electrode (nickel monosilicide electrode) obtained by implanting impurities such as P and B into poly-Si and full silicidation of poly-Si having Ni as the gate electrode on the gate insulating film is used, as described above The effective work function achieved for nMOS is about 4.2 eV to 4.4 eV or the effective work function achieved for pMOS is about 4.7 eV to 4.9 eV, but the realization of high-performance transistors requires controlling the effective work function to achieve a low threshold. do it with

In Patent Document 2, for nMOS, the Ni content of the gate electrodes is 30% to 60% and includes n-type impurities, and for pMOS, the Ni content of the gate electrodes is 40% to 60% and p-type When impurities are included, effective work functions of about 4.1 eV and 5.1 eV are obtained, respectively. However, a Ni silicide electrode with effective work functions (4.0 eV for nMOS and 5.2 eV for pMOS) that enables the achievement of the required threshold for realizing high-performance nMOS and pMOS in this compositional region has not yet been found. .

When the Ni content of the gate electrode is 40% or more, the gate electrode and SiO<sb>2</sb> Since the adhesion between the gate insulating films is very poor, it is easy to peel off at the gate electrode/insulating film interface, often causing deterioration of device performance. In addition, when the Ni content of the gate electrode is 40% or more, it is known that compressive stress due to the electrode acts on the gate insulating film to cause a decrease in the reliability of the gate insulating film (International electron devices meeting technical digest 2005) , p.709). Because of these points, it is preferable that the Ni content of the Ni silicide electrode is less than 40%, but a Ni silicide electrode capable of realizing the threshold required for high-performance pMOS in this content region has not yet been found.

In manufacturing a CMOS device, it is preferable that both the nMOS silicide electrode and the pMOS silicide electrode are formed in one cycle of silicidation for the purpose of cost reduction through process simplification. In order to achieve this object, it is necessary that the Ni full silicide gate electrode of nMOS and the Ni full silicide electrode of pMOS have the same composition, but the silicides constituting the nMOS gate electrode and the pMOS gate electrode have the same composition, which is required for a high-performance CMOS device. A Ni silicide electrode with effective work functions (4.0 eV for nMOS and 5.2 eV for pMOS) that enables the realization of thresholds has not yet been found.

In addition, with the miniaturization of the device, it is required to suppress the imbalance of threshold values of the transistor.

<b>disclosure of the invention</b>

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device with enhanced performance and reliability of elements and a method for manufacturing the same.

According to the present invention, the following semiconductor devices and a manufacturing method thereof are provided.

(1) a silicon substrate; and

a field effect transistor including a gate insulating film on the silicon substrate, a gate electrode on the gate insulating film, and a source region and a drain region;

and the gate electrode includes a crystallized Ni silicide region containing an impurity element of a conductivity type opposite to that of a channel region of the field effect transistor at least in a portion in contact with the gate insulating film.

(2) The above item (1),

The silicide constituting the crystallized Ni silicide region is Ni<sb>x</sb>Si<sb>1</sb><sb>-x </sb>A semiconductor device having a composition expressed by (0.2x&lt;0.4).

(3) according to (1) or (2),

The silicide constituting the crystallized Ni silicide region is NiSi<sb>2</sb> A semiconductor device comprising a phase.

(4) according to any one of (1) to (3),

wherein the silicon substrate includes a region containing fluorine atoms in the case of a P-channel transistor and a region containing nitrogen atoms in the case of an N-channel transistor, at least in a portion in contact with the gate insulating film.

(5) silicon substrate;

a P-channel field effect transistor comprising a first gate insulating film on the silicon substrate, a first gate electrode on the first gate insulating film, and a first source region and a first drain region; and

an N-channel field effect transistor comprising a second gate insulating film on the silicon substrate, a second gate electrode on the second gate insulating film, and a second source region and a second drain region;

the first gate electrode includes a crystallized Ni silicide region containing p-type impurities, at least in a portion in contact with the first gate insulating film,

and the second gate electrode includes a crystallized Ni silicide region containing n-type impurities, at least in a portion in contact with the second gate insulating film.

(6) The item according to (5),

The silicides constituting the crystallized Ni silicide region of the first gate electrode and the second gate electrode are Ni<sb>x</sb>Si<sb>1</sb><sb>-x </sb>A semiconductor device having a composition expressed by (0.2x&lt;0.4).

(7) The item according to (5),

The silicides constituting the crystallized Ni silicide region of the first gate electrode and the second gate electrode are NiSi<sb>2</sb> A semiconductor device comprising a phase.

(8) according to any one of (5) to (7),

and the first gate electrode and the second gate electrode each include regions in contact with the first gate insulating film and the second gate insulating film including regions containing an impurity element in a higher concentration than the upper portion thereof.

(9) according to any one of (5) to (8),

The first gate electrode and the second gate electrode have 1×10 portions in contact with the first gate insulating layer and the second gate insulating layer, respectively.<sp>20</sp> cm<sp>-3</sp> A semiconductor device comprising regions having an impurity concentration equal to or greater than or equal to that of the semiconductor device.

(10) according to any one of (5) to (9),

and the first gate insulating film and the second gate insulating film are a silicon oxide film or a silicon oxynitride film.

(11) according to any one of (5) to (9),

wherein the first gate insulating film and the second gate insulating film include a silicon oxide film, a silicon oxynitride film, or a silicon nitride film in contact with the first gate electrode and the second gate electrode, respectively.

(12) according to any one of (5) to (11),

and the silicon substrate includes a region containing fluorine atoms at least in a portion in contact with the first gate insulating film.

(13) according to any one of (5) to (12),

and the silicon substrate includes a region containing a nitrogen atom at least in a portion in contact with the second gate insulating film.

(14) A method for manufacturing the semiconductor device according to (5), comprising:

providing a silicon substrate comprising an n-type active region and a p-type active region;

forming an insulating film for a first gate insulating film and a second gate insulating film on the silicon substrate;

forming a gate silicon film on the insulating film;

adding a p-type impurity to a gate silicon film in a region where the P-channel field effect transistor is formed;

adding an n-type impurity to a gate silicon film in a region where the N-channel field effect transistor is formed;

forming a gate pattern by processing the silicon film for the gate;

forming a first source region and a first drain region in the region where a P-channel field effect transistor is formed;

forming a second source region and a second drain region in the region where an N-channel field effect transistor is formed;

forming an interlayer insulating film to cover the gate pattern;

exposing the gate pattern by removing an upper portion of the interlayer insulating layer;

forming a nickel layer on the exposed gate pattern;

forming a first gate electrode and a second gate electrode by performing a heat treatment to silicide the gate pattern; and

and selectively removing excess nickel in the non-silicided portion of the nickel film.

(15) The item according to (14),

wherein the p-type impurity and the n-type impurity are added by ion implantation.

(16) according to (14) or (15),

and adding fluorine to the silicon substrate in a region where the P-channel field effect transistor is formed before forming the insulating film for the first gate insulating film and the second gate insulating film. .

(17) according to any one of (14) to (16),

and adding nitrogen to the silicon substrate in a region where the N-channel field effect transistor is formed before forming the insulating film for the first gate insulating film and the second gate insulating film. .

According to the present invention, it is possible to provide a transistor having high performance and reliability and a simple manufacturing method for manufacturing the same.

<b>Brief description of the drawing</b>

1 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present invention;

Fig. 2 is a diagram showing the relationship between the composition of crystallized Ni silicide and the film thickness ratio (Ni film thickness/Si film thickness) between polycrystalline silicon and Ni before silicidation;

3 is a diagram showing the effective work function of crystallized Ni silicide, Ni content, and the relationship to the effect of the addition of impurities;

4 is a diagram illustrating a threshold range of a transistor that may be realized with a work function of a silicide electrode fabricated in accordance with an exemplary embodiment of the present invention;

5 is a process cross-sectional view of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

6 is a process cross-sectional view of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

Fig. 7 is a view showing the measurement result of drain current-gate voltage characteristics of the MOSFET manufactured according to the present invention (Fig. 7(a) shows the measurement result for nMOS, and Fig. 7(b) shows the measurement result for pMOS) is shown);

Fig. 8 is a view showing the relationship between the composition of Ni silicide according to the prior art (Comparative Example) and the film thickness ratio between polycrystalline silicon and Ni before silicidation;

Fig. 9 is a diagram showing the relationship between the effective work function of Ni silicide and the Ni content according to the prior art (Comparative Example);

Fig. 10 is a diagram showing the non-uniformity of threshold values of transistors manufactured according to the present invention and the prior art (Comparative Example);

11 is a process cross-sectional view of a semiconductor device manufacturing method according to a second exemplary embodiment of the present invention;

12 is a process cross-sectional view of a semiconductor device manufacturing method according to a second exemplary embodiment of the present invention;

13 is a process cross-sectional view of a semiconductor device manufacturing method according to a second exemplary embodiment of the present invention;

14 is a schematic cross-sectional view showing a semiconductor device according to another exemplary embodiment of the present invention;

15 is a process cross-sectional view of a semiconductor device manufacturing method according to a third exemplary embodiment of the present invention;

16 is a schematic cross-sectional view showing a semiconductor device according to a third exemplary embodiment of the present invention;

Fig. 17 is a diagram showing a threshold range of a transistor manufactured according to a third exemplary embodiment (fluorine addition) of the present invention; and

Fig. 18 is a diagram showing a threshold range of a transistor manufactured according to a third exemplary embodiment (nitrogen addition) of the present invention;

<b>for the practice of the invention </b><b>best practice</b>

Hereinafter, the present invention will be described in detail with reference to exemplary embodiments of the present invention.

The present invention is based on the following newly discovered facts.

When a gate electrode made of Ni silicide with high crystallinity to which impurity elements are added is formed on the gate insulating film, the effective work function is changed by the addition of impurity elements according to the decrease in the Ni content of the silicide (when impurity elements are added) and the difference between the undoped case) is increased, and it is possible to achieve an effective work function suitable for threshold control than that based on the prior art. In particular, when crystallized Ni silicide having a Ni content of less than 40% and added with impurity elements is used for the gate electrode, pMOS and nMOS of lower threshold than those based on the prior art can be realized.

The above findings were derived from preliminary experiments using the following MOS capacitances.

First, SiO on a silicon substrate<sb>2</sb> A gate insulating film (thickness: 3 nm) was formed, and a polycrystalline silicon (poly-Si) film having a thickness of 80 nm was formed on the gate insulating film.

Next, impurity elements were ion-implanted into the poly-Si film. The added impurity elements are of a conductivity type opposite to the conductivity type of the channel region of the transistor (that is, the conductivity type opposite to the conductivity type of the silicon substrate active region in which the channel immediately below the gate insulating film is formed). For example, to realize nMOS, n-type impurities N, P, As, Sb, Bi, etc. may be ion-implanted into Si, and to realize pMOS, p-type impurities B to Si , Al, In, Ga, Tl, etc. can be ion-implanted.

After that, the poly-Si film (thickness: T<sb>Si</sb>) on the Ni film (thickness: T<sb>Ni</sb>) was formed, and the poly-Si film was fully silicidated by subsequent heat treatment.

Table 1 shows the thickness ratio between the poly-Si film and the Ni film before silicidation on one side and the type of crystalline phase of nickel silicide formed by silicidation on the other side.

As shown in Table 1, the crystal phase of nickel silicide is sequentially determined in proportion to the thickness of the Ni film formed on the poly-Si film, that is, the amount of Ni supplied to the poly-Si. For example, if it is desired to make a crystalline phase of Ni silicide near the gate electrode/gate insulating film interface, mainly NiSi phase, which affects the effective work function, the thickness of the poly-Si film (T<sb>Si</sb>) and the thickness of the Ni film (T<sb>Ni</sb>) the ratio between (T<sb>Ni</sb>/T<sb>Si</sb>) can be set in the range of 0.55 to 0.95, mainly Ni<sb>3</sb>If you wish to make a Si phase, T<sb>Ni</sb>/T<sb>Si</sb> can be set to 1.6 or higher. The crystal phase of Ni silicide near the gate electrode/gate insulating film interface is mainly composed of NiSi<sb>2</sb> T in the range of 0.28 to 0.54, if desired to make the trader silicide.<sb>Ni</sb>/T<sb>Si</sb> It is necessary to set the silicidation temperature to 600 °C or higher, more preferably 650 °C or higher. The composition ratio (Ni/(Ni+Si)) that determines the work function of Ni silicide is NiSi<sb>2</sb>, NiSi or Ni<sb>3</sb>Since it is determined in a virtual self-aligning manner by the formation of a crystalline phase such as Si, the margins allowed by the process conditions including Ni film thickness and silicidation temperature to obtain the same crystalline phase (ie, to obtain the same work function) are It is extensive and it is possible to suppress the imbalance due to the manufacturing process.

[Table 1]

<table><tgroup xmlns="http://www.oasis-open.org/tables/exchange/1.0" cols="5"><colspec colnum="1" align="center" colname="col1" colwidth="2245" /><colspec colnum="2" align="center" colname="col2" colwidth="2262" /><colspec colnum="3" align="center" colname="col3" colwidth="2267" /><colspec colnum="4" align="center" colname="col4" colwidth="2257" /><colspec colnum="5" align="center" colname="col5" colwidth="2267" /><tbody><row><entry align="center" namest="col1" nameend="col2" morerows="1"></entry><entry align="center" namest="col3" nameend="col5">Ni film thickness/Si film thickness ratio</entry></row><row><entry align="center" colname="col3">0.28-0.54</entry><entry align="center" colname="col4">0.55-0.95</entry><entry align="center" colname="col5">1.6 or higher</entry></row><row><entry align="center" colname="col1" morerows="4"> Annealing temperature</entry><entry align="center" colname="col2"> 650℃</entry><entry align="center" colname="col3">NiSi<sb>2</sb> (+NiSi)</entry><entry align="center" colname="col4"></entry><entry align="center" colname="col5"></entry></row><row><entry align="center" colname="col2"> 600℃</entry><entry align="center" colname="col3"> NiSi</entry><entry align="center" colname="col4"></entry><entry align="center" colname="col5"></entry></row><row><entry align="center" colname="col2"> 500℃</entry><entry align="center" colname="col3">NiSi</entry><entry align="center" colname="col4">NiSi</entry><entry align="center" colname="col5">Ni<sb>3</sb>Si (+NiSi)</entry></row><row><entry align="center" colname="col2"> 450℃</entry><entry align="center" colname="col3"></entry><entry align="center" colname="col4">NiSi</entry><entry align="center" colname="col5">Ni<sb>3</sb>Si (+NiSi)</entry></row><row><entry align="center" colname="col2"> 400℃</entry><entry align="center" colname="col3"></entry><entry align="center" colname="col4">NiSi</entry><entry align="center" colname="col5">Ni<sb>3</sb>Si (+NiSi)</entry></row></tbody></tgroup></table>

During this full silicidation, impurity elements are separated near the silicide electrode/insulating film interface by a "snowflowing" effect. At that time, the concentration of the separated impurity elements is 1×10 near the interface.<sp>20</sp> cm<sp>-3</sp> When dropped below, the effective work function hardly changed. Therefore, in order to change the effective work function, it is preferable to have an impurity isolation region containing a higher concentration of impurities than the upper region in the gate electrode portion near the gate electrode/gate insulating film interface, and the impurity concentration of the impurity isolation region is 1×10<sp>20</sp> cm<sp>-3</sp> It is preferable to be abnormal. On the other hand, from the viewpoint of reliability of the devices, the concentration of this impurity isolation region is 1 × 10<sp>23</sp> cm<sp>-3</sp> preferably no more than 5×10<sp>22</sp> cm<sp>-3</sp> It is more preferable that it is the following. Therefore, it is preferable that the gate electrode used in the present invention contains impurity elements in the above-mentioned concentration range in the portion in contact with the gate insulating film. In addition, it is preferable that the impurity region (impurity separation region) in the present concentration range in the gate electrode exists on the order of 5 nm or more from the gate electrode/insulating film interface in the thickness direction (vertical direction from the substrate surface).

The crystalline phase of Ni silicide of MOS capacitance prepared as described above was identified by XRD. As shown in Table 1, T<sb>Ni</sb>/T<sb>Si</sb> = 0.28 to 0.54, the Ni silicide formed is in fact NiSi<sb>2</sb> is made of However, in XRD, NiSi<sb>2</sb> has a weak peak intensity, and the peak of NiSi is observed. According to the depthwise direction analysis of the silicide electrode composition by XPS, the NiSi<sb>2</sb> A Ni content slightly higher than that in the Ni content is found, and therefore NiSi is mainly present in that portion. T<sb>Ni</sb>/T<sb>Si</sb> = 0.55 to 0.95, the Ni silicide formed substantially consists of NiSi. T<sb>Ni</sb>/T<sb>Si</sb> is greater than or equal to 1.6, the Ni silicide formed is effectively Ni<sb>3</sb>made of Si.

Fig. 2 shows the ratio of Ni content in the gate electrode and Ni film thickness before silicidation/poly-Si film thickness (Si film thickness) in the vicinity of the electrode/insulating film interface of the MOS capacitance prepared as described above (T<sb>Ni</sb>/T<sb>Si</sb>) represents the relationship between Ni content in the electrode was calculated|required from XPS measurement. The error bars in the electrode composition represent fluctuations in the multi-point XPS measurement.

From this figure, the Ni content in the electrode near the interface is T<sb>Ni</sb>/T<sb>Si</sb> It is understood that the ratio is determined in a step shape. For example, T<sb>Ni</sb>/T<sb>Si</sb> = 0.28 to 0.54, 0.55 to 0.95, and 1.6 or higher, the Ni content in the gate electrode near the interface was 33.3±7%, 50±5%, and 75±5%, respectively. Each of these compositions is NiSi<sb>2</sb> Ni content of (33.3%), Ni content of NiSi (50%), and Ni<sb>3</sb>It virtually corresponds to the Ni content of Si (75%). This is probably because the Ni content in the electrode near the interface by the crystal phase as shown in Table 1 is self-aligned crystal.

3 shows the MOS capacitances prepared as described above, when no impurity elements were added (undoped), when As was added, and when B was added (of As and B added in poly-Si). All doses are 5 × 10<sp>20</sp> cm<sp>-</sp><sp>3</sp> ) shows the relationship between the effective work function of crystallized Ni silicide and the composition of the silicide electrode near the interface. The error bars in the electrode composition represent the range of variation in the multi-point XPS measurements. The figure shows the main crystalline phase in its composition.

As shown in this figure, when no impurity elements are added, the effective work function of the crystallized Ni silicide hardly depends on the composition. Therefore, even if the Ni content varies by about ±5%, the fluctuation range of the threshold values can be suppressed.

Looking at the cases in which arbitrary impurities are added, the change in the effective work function (difference between the case in which the arbitrary impurity is added and the case in which it is undoped) increases as the Ni content is decreased (the Si content is increased). . In particular, the main crystalline phase is NiSi<sb>2</sb> and Ni content of 26 to 40 atomic%, the effective work function becomes 4.0 eV under As doping or 5.2 eV under B doping, and the effective work function required for high-performance CMOSFET devices (4.0 eV or less for nMOS) , 5.2 eV or higher for pMOS) can be realized.

The tendency that the change in the effective work function due to the addition of impurities increases with a decrease in the Ni content (increase in the Si content) in the Ni silicide was confirmed for all impurities having an effect of modulating the work function. In particular, crystallized NiSi<sb>2</sb> , the effective work function is 4.0 eV or less for n-type impurities (N, P, As, Sb, Bi, etc.) and 5.2 eV or more for p-type impurities (B, Al, In, Ga, Tl, etc.) , indicating that the effective work function requirements for high-performance CMOS devices (less than 4.0 eV for nMOS and 5.2 eV or more for pMOS) can be realized.

This dependence of the Ni content in the electrode on the change in the effective work function due to the addition of impurities is completely different from the tendency disclosed in Japanese Laid-Open Publication No. 2005-129551 (Patent Document 2). In particular, when any p-type impurity is added, the tendency of dependence of the Ni content in the electrode on the effective work function is reversed between the present exemplary embodiment and the case of Patent Document 2.

This is due to the following reasons. In the case of Patent Document 2, the change in the effective work function (difference between the case where an arbitrary impurity is added and the case where it is undoped) due to the addition of an impurity depends only on the type and amount of the impurity, but is almost dependent on the composition of the Ni silicide electrode. I never do that. Further, the effective work function of the undoped Ni silicide electrode rises (4.43 eV to 5.1 eV) with an increase in the Ni content (about 30 atomic % to 100 atomic %). In the case of the present exemplary embodiment, on the contrary, the effective work function of the undoped crystallized Ni silicide hardly depends on the Ni content, and the change in the effective work function results in a decrease in the Ni content ( increase in Si content). In this way, the present invention and the technique according to Patent Document 2 differ greatly in the dependence of the electrode composition on the change of the effective work function due to the addition of impurities. This difference is probably due to the difference in crystallinity resulting from the difference in the formation method as will be described later with reference to the comparative example.

As shown in Fig. 3, since the effective work function of the doped Ni silicide is affected by the Ni content, it is preferable to form a silicide in which the Ni content is determined in a self-aligning manner. That is, forming a silicide having a thermodynamically stable crystal phase as the main crystal phase, particularly NiSi<sb>2</sb> It is preferable to form a silicide having the crystal phase as the main crystal phase. As mentioned above, NiSi<sb>2</sb> Since the formation of the crystal phase determines the Ni content in a self-aligning manner, the margins allowed for the process conditions are wide, making it possible to suppress the fluctuation range of the Ni content due to the manufacturing process. Thus, doped crystallized NiSi<sb>2</sb> According to the present invention, which can also be applied to the gate electrode, since the electrode composition is determined in a self-matching manner at the time of full silicidation, it becomes possible to form a transistor that suppresses the threshold fluctuation range. In addition, since silicide having a Ni content of less than 40 atomic% can be formed, the junction between the silicide electrode and the gate insulating film is strengthened, and the compressive stress of the gate insulating film caused by the gate electrode is suppressed, so that a more reliable transistor is formed. It may be possible.

When the thickness of the oxide film is 1.8 nm, the threshold (Vth) range of the MOSFET predictable from the effective work function becomes as shown in Fig. 4 for the channel impurity concentration. According to the present invention using a crystallized Ni silicide electrode whose effective work function can be modulated to less than 4.0 eV for nMOS or more than 5.2 eV for pMOS by adding impurity elements, usually the channel concentration (10<sp>17</sp> to 10<sp>18</sp> cm<sp>-3</sp>) can realize a high-performance device with a low threshold of about 0.1 V, a level that cannot be achieved using a conventional impurity element-doped NiSi electrode.

According to the present invention, the crystallized Ni silicide constituting the gate electrode preferably has a Ni content of less than 40 atomic%. At a Ni content of less than 40 atomic%, the gate electrode is a silicon oxide film (SiO<sb>2</sb> film) and a gate insulating film such as a silicon oxynitride film (SiON film), and makes it possible to almost completely prevent the occurrence of stress due to the electrode to enhance the reliability of the MOSFET.

According to the present invention, from the viewpoint of suppressing gate depletion and reducing gate resistance, the Ni content of the crystallized Ni silicide constituting the gate electrode is preferably 5 atomic% or more, and 10 atomic% or more more preferred; In addition, from the viewpoint of threshold control, it is preferably 20 atomic % or more, more preferably 25 atomic % or more, and particularly preferably 30 atomic % or more. Considering the threshold control aspect in addition to the reliability enhancement described above, the Ni content is preferably 38 atomic% or less, more preferably 35% or less. In addition, the Ni content is expressed as a percentage with respect to the ratio (Ni/(Ni+Si)) of the amount of Ni to the total amount of Ni and Si in terms of the number of atoms. Therefore, from the viewpoint of suppressing gate depletion, reducing gate resistance, and improving reliability, Ni<sb>x</sb>Si<sb>1</sb><sb>-x</sb> Ni silicide represented by (0.1 x &lt; 0.4) is preferable, and considering the threshold control in addition to these points, Ni<sb>x</sb>Si<sb>1</sb><sb>-x</sb> (0.2 x &lt; 0.4) is more preferable. Also, in these formulas, x is preferably within a preferable range for the Ni content from the above-mentioned viewpoint.

The gate electrode according to the present invention has a region of crystallized silicide having a Ni content as mentioned above for the purpose of achieving a desired effective work function, and this region is in the thickness direction (direction perpendicular to the substrate plane) from the gate electrode/insulating film interface. ) is preferably extended to 5 nm or more, and more preferably 10 nm or more.

According to the present invention, since the doped crystallized Ni silicide electrode is applied to the gate electrode as mentioned above, when manufacturing CMOS devices, Ni silicide electrodes for nMOS and pMOS are performed in a single silicidation step as described below. can form. Accordingly, the number of steps can be reduced, and the process can be simplified to reduce costs.

As the gate insulating film of the present invention, a silicon oxide film (SiO<sb>2</sb> film) or a silicon oxynitride film (SiON film) can be used. Also, a high dielectric constant insulating film such as an HfSiON film may be used as the gate insulating film. In this case, the range of the threshold change due to the addition of impurities is SiO<sb>2</sb> and a silicon oxide film, silicon oxynitride film or silicon nitride film, which is smaller than the case of using a SiON gate insulating film, but is placed in contact with the gate electrode to increase the change in the effective work function, which makes it difficult to realize a low threshold in MOSFET will make it possible Between the high dielectric constant insulating film and the silicon substrate, a silicon oxide film or a silicon oxynitride film may be provided.

1 shows a schematic cross-sectional view of a CMOSFET structure using doped Ni silicide as a gate electrode. In this figure, reference numeral 1 denotes a silicon substrate; Reference numeral 2 denotes an element isolation region; Reference numeral 3 denotes a gate insulating film; Reference numeral 6 denotes an extended diffusion region; Reference numeral 7 denotes a gate sidewall; Reference numeral 8 denotes a source-drain diffusion region; Reference numeral 11 denotes an interlayer insulating film; Reference numeral 13 denotes an n-type full silicide gate electrode; Reference numeral 14 denotes a p-type full silicide gate electrode; Reference numerals 19 and 20 denote impurity separation regions. In such a CMOS structure, it is possible to achieve high-performance transistors with high levels of reliability and reproducibility that hitherto considered impractical, as well as the effect of avoiding gate electrode depletion.

In addition to the structure described above, in the silicon substrate of the pMOS region, providing fluorine atoms at least to the portion in contact with the gate insulating film increases the effective work function of the gate electrode by about 0.1 eV, thereby reducing the threshold of pMOS by about 0.1 V can do it In addition, if nitrogen atoms are provided in at least a portion of the silicon substrate in the nMOS region in contact with the gate insulating film, the effective work function of the gate electrode can be decreased by about 0.1 eV, and the threshold value of the nMOS can be lowered by about 0.1 V.

According to the present invention, the work function of the gate electrode of pMOS and the work function of the gate electrode of nMOS can be controlled by the composition of the silicide constituting the gate electrode and impurities contained in the silicide, as mentioned above. Therefore, the silicide of the pMOS region and the silicide of the nMOS region may contain different impurities while forming crystallized silicides of the same composition as the gate material of the pMOS region and the nMOS region. Therefore, in the manufacturing process according to the present invention, after formation of the gate material on the gate insulating film, the step of removing the gate material does not need to be performed, so that a gate electrode having a work function difference between pMOS and nMOS can be formed. For this reason, the surface of the gate insulating film is not exposed to a wet etching liquid or an organic solvent, and therefore the quality of the gate insulating film is not adversely affected. As a result, a CMOS device with high reliability can be manufactured. In addition, since the addition of impurities to the gate material can be accurately performed by an already established technique such as ion implantation, the fluctuation range of the threshold can be suppressed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

<b>Exemplary first embodiment</b>

5(a) to 5(h) and 6(i) to 6(j) are cross-sectional views showing a MOSFET manufacturing process according to the first exemplary embodiment of the present invention.

First, the device isolation region 2 was formed by applying a shallow trench isolation (STI) technique to the surface region of the silicon substrate 1 . Thereafter, a gate insulating film 3 made of SiON was formed on the element-isolated silicon substrate surface.

Next, as shown in Fig. 5(a), a poly-Si film 4 having a thickness of 80 nm was formed on the gate insulating film 3, and ion implantation was performed in combination with a normal PR process using a resist. Thus, different impurity elements were ion-implanted into the nMOS region and the pMOS region for this poly-Si film. As was implanted in the nMOS region and B was implanted in the pMOS region. The implantation energy and dose were 5 KeV and 5×10 for As, respectively.<sp>15</sp> cm<sp>-</sp><sp>2</sp> and for B, 2 KeV and 6×10, respectively.<sp>15</sp> cm<sp>-</sp><sp>2</sp> It was.

Thereafter, a silicon oxide film 5 having a thickness of 150 nm was laminated as shown in Fig. 5(b).

Next, as shown in Fig. 5(c), a gate electrode pattern is formed by processing the laminated poly-Si film 4 and the silicon oxide film 5 using a lithography technique and a reactive ion etching (RIE) technique. did. Thereafter, an extended diffusion region 6 was formed in a self-aligning manner by performing ion implantation using the gate electrode pattern as a mask. This step was performed for each of the nMOS region and the pMOS region.

Next, a silicon nitride film and a silicon oxide film were sequentially formed, followed by etching back to form a gate sidewall 7 as shown in Fig. 5(d).

Next, one of the nMOS region and the pMOS region was masked and ion implantation was again performed in the other region to form the source-drain diffusion region 8 . This step was performed on each of the nMOS region and the pMOS region. The source-drain diffusion region is activated by subsequent thermal treatment.

Next, as shown in Fig. 5(e), a metal film 9 having a thickness of 20 nm was formed over the entirety by sputtering, and in the silicide technique using the gate electrode pattern, the gate sidewall and the device isolation region as a mask. Thus, a silicide layer 10 having a thickness of about 40 nm was formed alone in the source-drain diffusion region (FIG. 5(f)). As the present silicide layer 10, a Ni monosilicide (NiSi) layer capable of minimizing contact resistance was formed. Instead of such Ni silicide, Co silicide or Ti silicide may be used.

Next, as shown in Fig. 5(g), an interlayer insulating film 11 made of a silicon oxide film was formed by a chemical vapor deposition (CVD) method.

This interlayer insulating film 11 was planarized by a chemical mechanical polishing (CMP) technique, and then the interlayer insulating film was etched again as shown in Fig. 5(h) to expose the poly-Si film 4 of the gate electrode pattern. .

Next, as shown in Fig. 6(i), a Ni film 12 for silicidating the poly-Si film 4 of the gate electrode pattern portion was formed. In this step, the thickness of the Ni film is determined at the portion in contact with the gate insulating film when poly-Si and Ni sufficiently react to form silicide.<sb>2</sb> set to form In this exemplary embodiment, a 25 nm Ni film was formed at room temperature by DC magnetron sputtering.

After that, poly-Si and Ni are sufficiently reacted with each other by heat treatment at 650° C. for 2 minutes to crystallize NiSi<sb>2</sb> Gate electrodes 13 and 14 made of In this silicidation, the dopant (As) in the silicide electrode of the nMOS region was separated in the vicinity of the electrode/insulating film interface as shown in Fig. 6(j) to form a thin impurity isolation region 19. Further, the dopant (B) in the silicide electrode of the pMOS region was separated in the vicinity of the electrode/insulating film interface as shown in Fig. 6(j) to form a thin impurity isolation region 20. As shown in FIG.

Finally, the excess Ni film that was not silicided in the heat treatment step was removed by wet etching using an aqueous solution of sulfuric acid-hydrogen peroxide. Thereafter, contact plugs and upper layer wirings (not shown) were formed by conventional methods.

These steps were followed to form a CMOS structure having full silicide electrodes that separate impurity elements causing a difference between the nMOS region and the pMOS region in the vicinity of the electrode/insulation film interface, as shown in Fig. 6(j). In the MOSFET fabricated in this way, the effective work function of the silicide electrode was 4.0 eV for nMOS and 5.2 eV for pMOS.

7(a) shows a gate electrode (NiSi) with an effective work function adjusted to 4.0 eV.<sb>2</sb> electrode) and the dependence of the gate voltage on the drain current of the nMOS. The channel concentration is 5×10<sp>17</sp> cm<sp>-</sp><sp>3</sp> and Vth expected from the rms work function of 4.0 eV shown in FIG. 4 is 0.1 V. According to Fig. 7(a), NiSi<sb>2</sb> The Vth of the nMOS with electrodes is 0.1 V as expected from the effective work function. In addition, the electron mobility of this transistor is determined by the poly-Si for the gate electrode and the SiO for the gate insulating film.<sb>2</sb> It was confirmed that it can have a value comparable to the electron mobility of a transistor using

In Fig. 7(b), the effective work function is adjusted to 5.2 eV for the gate electrode (NiSi<sb>2</sb> electrode) and the dependence of the gate voltage on the drain current of the pMOS. The channel concentration is 5×10<sp>17</sp> cm<sp>-</sp><sp>3</sp> and Vth expected from the effective work function of 5.2 eV shown in FIG. 4 is -0.1 V. According to Fig. 7(b), NiSi<sb>2</sb> The Vth of the pMOS with electrodes is -0.1 V as expected from the effective work function. In addition, the electron mobility of this transistor is determined by the poly-Si for the gate electrode and the SiO for the gate insulating film.<sb>2</sb> It was confirmed that it can have a value comparable to the electron mobility of a transistor using

Additionally, in the case of adding p-type dopant impurities (Al, In, Ga, Tl) other than B to the Ni full silicide electrode for pMOS, and n-type dopant impurities other than As to the Ni full silicide electrode for nMOS A similar effect was achieved even when (N, P, Sb, Bi) was added.

In addition, crystallized NiSi<sb>2</sb> When the electrode is used as the gate electrode, SiO<sb>2</sb> Alternatively, since it adheres tightly to the gate insulating film made of SiON (silicon oxynitride film) and stress due to the gate electrode hardly occurs, a highly reliable MOSFET can be provided.

When a CMOS device is manufactured, according to the present invention, the manufacturing cost can be saved by simplifying the process by forming Ni full silicide electrodes for nMOS and pMOS in a single silicide step.

As disclosed so far, a crystallized Ni full silicide electrode (NiSi<sb>2</sb> electrode) and SiON gate insulating film to achieve excellent transistor performance characteristics.

<b>comparative example</b>

The silicidation layer was formed according to the method disclosed in Japanese Patent Laid-Open No. 2005-129551 (Patent Document 2) as follows: forming a poly-Si film through a thermal oxidation film on a silicon substrate; forming a Ni film on the poly-Si film; Heat treatment was performed at 400° C. for 1 minute to cause the silicidation reaction to occur. According to this process, Ni films of different thicknesses were formed on poly-Si films having a predetermined thickness, and heat treatment was performed on the Ni films to form silicidated layers having different Ni contents. In the silicidation layers, in the vicinity of the interface with the insulating film, their impurity concentration is 10<sp>21</sp> cm<sp>-3</sp> It was more than that.

Measurement of the XRD spectrum of the silicided layer formed revealed, in particular the nickel film thickness (T<sb>Ni</sb>)/poly-Si film thickness (T<sb>Si</sb>) was less than 0.55, there was no peak accompanying crystallization or the peak intensity was very weak; That is, it was confirmed that the formed silicidation layer was non-crystallized but had very low crystallinity.

Fig. 8 shows the Ni content (composition near the interface between the silicide layer and the insulating film) of the silicided layer (silicide electrode) of the MOS capacitance and the ratio of the Ni film thickness/poly-Si film thickness before silicidation (T<sb>Ni</sb>/T<sb>Si</sb>) represents the relationship between This Ni content was computed from XPS measurement. The error bars in the Ni content in the figure represent variations in the multi-point XPS measurements. From this figure, the Ni content in the silicided layer is T<sb>Ni</sb>/T<sb>Si</sb> It is understood to be continuously changing according to the ratio.

Fig. 9 shows the effective work function of the silicided layer in the undoped case with the As addition and B addition cases. In this figure, in the case of undoping, it is understood that the effective work function of the silicidation layer increases as the Ni content increases. Thus, for example, fluctuations in the Ni content by about ±5% will cause threshold fluctuations by as much as 0.1 to 0.2V. This trend is entirely different from the case of crystallized Ni full silicides formed according to embodiments of the present invention as described above. The difference in effective work function change due to this electrode composition is probably the difference in crystallinity resulting from the difference in the formation method. Although silicidation was achieved by heat treatment at 400 DEG C for 1 minute according to the method disclosed in Patent Document 2, the obtained silicided layer was found to be non-crystallized but very low in crystallinity as mentioned above. On the other hand, the silicidation condition according to the embodiment of the present invention is T<sb>Ni</sb>/T<sb>Si</sb> is 0.55 or more, at 400 ° C for 5 minutes, T<sb>Ni</sb>/T<sb>Si</sb> When is less than 0.55, since it was at 650 °C for 2 minutes, a Ni silicide electrode with excellent crystallinity was formed, and especially T<sb>Ni</sb>/T<sb>Si</sb> When is less than 0.55, a highly crystalline Ni silicide electrode is formed.

In addition, FIG. 9 shows effective work functions of the silicided layer doped with impurities (As and B), manufactured by the method described in Patent Document 2 . In this figure, it is understood that the effective work function increases as the Ni content of the silicided layer of the parent increases as well as in the case of doping. Therefore, no significant increase is found in the change of the work function (difference between the case in which an arbitrary impurity is added and the case in which it is undoped) according to the Ni content. This trend is quite different from the case of crystallized Ni full silicide electrodes formed according to the present invention. Therefore, in the crystallized Ni full silicide electrode according to the present invention, the change in the effective work function increases with the decrease in the Ni content (increase in the Si content). The difference in the electrode-composition dependence of the effective work function change due to the addition of these impurities is probably the crystallinity difference resulting from the formation method as in the undoped case described above.

In addition, the effective work function of the doped silicidation layer prepared by the method described in Patent Document 2 is shown to be about 4.1 eV when the Ni content is 30 to 60 atomic%, and contains n-type impurities, and the Ni content This is 40 atomic% to 70 atomic%, and an effective work function of about 5.1 eV when containing p-type impurities was obtained, but an effective work function (4.0 for nMOS) capable of realizing the required threshold for high performance nMOS and pMOS. A Ni silicide electrode with eV, 5.2 eV for pMOS) was not obtained. Further, especially when the Ni content is 40 atomic% or more, Ni and SiO<sb>2</sb> Since the adhesive force between the gate insulating layers is very weak, coming-off from the silicide layer/insulation layer interface occurred frequently. Further, when the Ni content is 40 atomic% or more, the compressive stress on the gate insulating film due to the silicide layer acts on the insulating film, causing a decrease in the reliability of the gate insulating film.

In addition, since the doped silicidation layer formed by the method described in Patent Document 2 is not Ni silicide of stoichiometric composition as described in Patent Document 2 itself, heat treatment after formation requires a content distribution in the layer It is observed that the effective work function fluctuates significantly. Fig. 10 shows variations in threshold values of transistors using doped crystalline NiSi formed according to the present invention as gate electrodes, and also a doped Ni silicided layer (Ni) formed by the method described in Patent Document 2, like the gate electrodes. content of NiSi<sb>2</sb> The variation of threshold values of transistors using the same as 33.3%) is shown. In the case of an embodiment of the present invention, the absolute amount of fluctuation was 4 mV. In the case according to Patent Document 2, the absolute amount of the fluctuation was 150 mV.

<b>Exemplary second embodiment</b>

11(a) to 11(h), FIG. 12(i) to 12(k), and FIGS. 13(1) to 13(n) show MOSFET fabrication according to the second exemplary embodiment of the present invention. Cross-sectional views showing the process.

In this exemplary embodiment, the steps include: forming a silicide layer in the source-drain diffusion region after silicidation for forming a gate electrode; and forming a silicon nitride film to enhance electron mobility by distorting the channel of the MOSFET.

Steps up to source-drain diffusion region formation (FIGS. 11(a) to 11(d)) are similar to their corresponding steps (FIGS. 6(a) to 6(d)) in the first exemplary embodiment Therefore, descriptions thereof are omitted, and descriptions are made from the next step (FIG. 11(e)). Incidentally, in this exemplary embodiment, Sb was added to the poly-Si film of the nMOS region, and In was added to the poly-Si film of the pMOS region.

As shown in Fig. 11(e), a silicon nitride film 15 was formed on the whole by the CVD method. This nitride film serves to protect the substrate and the like when the interlayer insulating film 11 is removed by wet processing.

Next, as shown in Fig. 11(f), an interlayer insulating film 11 made of a silicon oxide film was formed by the CVD method.

This interlayer insulating film 11 was planarized by the CMP technique, and then the interlayer insulating film was etched back to expose the poly-Si film 4 of the gate electrode pattern as shown in Fig. 11(g).

Next, as shown in Fig. 11(h), a Ni film 12 for silicidating the poly-Si film 4 of the gate electrode pattern was formed. The thickness of the Ni film in this step is determined by the composition of the portion in contact with the gate insulating film when poly-Si and Ni sufficiently react with each other to form silicide.<sb>2</sb> is set to be In this exemplary embodiment, a 25 nm Ni film was formed at room temperature by DC magnetron sputtering.

After that, poly-Si and Ni were sufficiently reacted with each other by heat treatment at 650° C. for 2 minutes to crystallize NiSi<sb>2</sb> Electrodes 13 and 14 were formed. In this silicidation, the dopant (Sb) in the silicide electrode of the nMOS region was separated in the vicinity of the electrode/insulating film interface as shown in Fig. 12(i) to form a thin impurity isolation region 19. Further, the dopant (In) in the silicide electrode of the pMOS region was separated in the vicinity of the electrode/insulating film interface as shown in Fig. 12(i) to form a thin impurity isolation region 20. As shown in FIG.

Thereafter, the excess Ni film that did not undergo a silicidation reaction in the heat treatment step was removed by wet etching.

Next, as shown in Fig. 12(j), the interlayer insulating film 11 was removed with an aqueous hydrofluoric acid solution, and then the silicon nitride film 15 was removed with phosphoric acid.

Next, a metal film having a thickness of 20 nm is formed over the entire top by sputtering, and a silicide layer having a thickness of about 40 nm only in the source-drain diffusion region by a silicide technique using the gate electrode, the gate sidewall and the device isolation region as a mask. (10) was formed (Fig. 12(k)). As the silicide layer 10, a Ni monosilicide (NiSi) layer capable of minimizing contact resistance was formed. Instead of such Ni silicide, Co silicide or Ti silicide may be used.

Next, as shown in FIG. 13(l), a silicon nitride layer 16 was formed in order to enhance electron mobility by applying a tensile stress to the n-type channel on the entire top by a CVD method.

Next, as shown in Fig. 13(m), ion implantation in combination with a normal PR process using a resist is performed to perform ion implantation into the silicon nitride film 16 on the pMOS region, thereby stressing the silicon nitride film 16. was alleviated.

Next, as shown in Fig. 13(n), an interlayer insulating film 17, which is a silicon oxide film, was formed by the CVD method.

Finally, a contact plug and an upper layer wiring (not shown) were formed by conventional methods, whereby the full silicide gate electrodes 13 and 14) was obtained. In the MOSFET manufactured in this way, the effective work function of the full silicide electrode 13 was 4.0 eV for nMOS and 5.2 eV for pMOS.

Also in the exemplary embodiment, the same as in the present exemplary first embodiment, as expected from the effective work function, Vth is 0.1 V for nMOS and -0.1 V for pMOS. In addition, the electron mobility of this transistor is determined by poly-Si for the gate electrode and SiO for the gate insulating film.<sb>2</sb> It was confirmed that it can have a value comparable to the electron mobility of a transistor using

Incidentally, p-type impurities (B, Al, Ga, Tl) other than In are added to the Ni full silicide electrode for pMOS, and n-type impurities other than Sb (N, P, Even when As, Bi) was added, similar effects were achieved.

As described so far, crystallized Ni full silicide electrode (NiSi<sb>2</sb> electrode) and SiON gate insulating film to achieve excellent transistor performance characteristics.

<b>Exemplary third embodiment</b>

15A to 15E are cross-sectional views illustrating a MOSFET manufacturing process according to a third exemplary embodiment of the present invention. In the present exemplary embodiments, for the purpose of realizing a low threshold, ion implantation of fluorine into the silicon substrate of the pMOS region where the p-channel is formed and nitrogen ion implantation into the silicon substrate of the nMOS region where the n-channel is formed is included. do.

First, as shown in Fig. 15(a), an element isolation region 2 was formed by applying the STI technique in the surface region of the silicon substrate 1 .

Thereafter, as shown in Fig. 15(b), an nMOS region 101 and a pMOS region 102 were formed in the isolated silicon substrate surface by using a conventional lithography step and ion implantation. The impurity concentration in the substrate forming the channel is about 5×10<sp>17</sp> and 10<sp>18</sp> cm<sp>-3</sp> to suppress device degradation due to the short-channel effect of micro MOSFETs.

Next, sacrificial oxide films 103 and 104 having a thickness of about 16 nm and 3 nm, respectively, were formed on the surfaces of the nMOS region 101 and the pMOS region 102, as shown in Fig. 15(c).

Then, using a conventional lithography step and ion implantation with one of the regions being masked, fluorine, and the pMOS region 102 from the top of the sacrificial oxide films 103 and 104 into the nMOS region 101 of the silicon substrate Nitrogen was injected into The implantation energy and dose are, for example, 15 KeV and 1×10 for both fluorine and nitrogen, respectively.<sp>15</sp> cm<sp>-2</sp> it was The amounts of nitrogen 105 and fluorine 106 just below the sacrificial oxide films 103 and 104 were evaluated by the SIMS method, and both were about 1×10<sp>20</sp> cm<sp>-</sp><sp>3</sp> was confirmed to be

Next, heat treatment was performed at 900 DEG C for about 10 seconds, and then the sacrificial oxide films 103 and 104 were removed with a hydrofluoric acid solution.

Then, as shown in Fig. 15(d), SiO with a thickness of 1.8 nm<sb>2</sb> A gate insulating film 3 was formed.

After the formation of the gate insulating film 3, a process similar to that of the MOSFET manufacturing process related to the first exemplary embodiment was performed to form the CMOS shown in FIG. This CMOS has different dopant elements between pMOS and nMOS in the vicinity of the gate electrode/insulating film interface (n-type impurity 19 such as As for nMOS region and p-type impurity 20 such as B for pMOS region) NiSi with these separated impurity isolation regions<sb>2</sb> It has full silicide gate electrodes 13 and 14, and also has fluorine 105 in the p-channel region and nitrogen 106 in the n-channel region. SiO in fabricated MOSFETs<sb>2</sb> The amounts of nitrogen 105 and fluorine 106 in the silicon substrate immediately under the gate insulating film 3 were evaluated by the SIMS method, and each was approximately 1×10<sp>19</sp> cm<sp>-3</sp> and 1×10<sp>17</sp> cm<sp>-</sp><sp>3</sp> was confirmed to be

Fig. 17 shows the threshold value of pMOS in the MOSFET manufactured as described above when the amount of fluorine in the silicon substrate is changed after formation of the MOSFET by changing the implantation amount of fluorine. The absolute value of the threshold decreases with an increase in the amount of fluorine and is approximately 1×10<sp>17</sp> cm<sp>-</sp><sp>3</sp> It reaches about 0.1 V at the amount of phosphorus fluoride. As shown from Fig. 17, from the viewpoint of actually changing the threshold, the amount of fluorine in the channel immediately below the gate insulating film is 1 x 10<sp>16</sp> cm<sp>-3</sp> It is preferable that it is more than 5x10<sp>16</sp> cm<sp>-3</sp> More preferably. On the other hand, the amount of fluoride is 2 × 10<sp>17</sp> cm<sp>-3</sp> , the junction leakage in the source-drain region tends to increase due to the formation of crystal defects due to ion implantation. In addition, the amount of fluoride is 5 × 10<sp>17</sp> cm<sp>-3</sp> If it exceeds, accelerated oxidation tends to be promoted, making it difficult to control a gate insulating film having a thickness of 2 nm or less required for formation of a micro CMOS device. Therefore, from the viewpoint of suppressing the crystal defect formation due to accelerated oxidation and ion implantation, the amount of fluorine in the channel just below the gate insulating film is 5 × 10<sp>17</sp> cm<sp>-3</sp> It is preferably less than or equal to 2 × 10<sp>17</sp> cm<sp>-3</sp> It is more preferable that it is the following.

Fig. 18 shows the threshold of nMOS in the MOSFET manufactured as described above when the amount of nitrogen in the silicon substrate is changed after formation of the MOSFET by changing the implantation amount of nitrogen. The threshold decreases with an increase in the amount of nitrogen, approximately 1 × 10<sp>19</sp> cm<sp>-</sp><sp>3</sp> It reaches about 0.1 V at the amount of phosphorus nitrogen. As shown from Fig. 18, from the viewpoint of actually changing the threshold, the amount of nitrogen in the channel immediately below the gate insulating film is 1 x 10<sp>18</sp> cm<sp>-3</sp> It is preferable that it is more than 5x10<sp>18</sp> cm<sp>-3</sp> More preferably. On the other hand, if the amount of nitrogen is very large, especially 1×10<sp>20</sp> cm<sp>-3</sp> , the reliability of the gate insulating film tends to deteriorate. Therefore, from the viewpoint of suppressing deterioration of the reliability of the gate insulating film, the amount of nitrogen in the channel immediately below the gate insulating film is 1 x 10<sp>20</sp> cm<sp>-3</sp> It is preferably not more than 5 × 10<sp>19</sp> cm<sp>-3</sp> It is more preferable that it is the following.

As shown with reference to this exemplary embodiment, NiSi substantially doped with impurities.<sb>2</sb> CMOS device having a threshold much lower than that of the first exemplary embodiment by bonding a gate electrode made of crystallized Ni full silicide having a composition and a silicon substrate having a region containing fluorine or nitrogen in the vicinity of the gate insulating film/silicon substrate interface can be obtained.

Although exemplary embodiments of the present invention have been described so far, the present invention is not limited to these exemplary embodiments, and can be implemented by appropriately selecting materials and structures without departing from the spirit of the present invention.

For example, when it is desired to reduce the gate leakage current, a so-called high dielectric constant insulating film such as HfSiON can be used as the gate insulating film. In this case, the threshold change will be smaller than in the case of using a silicon oxide film or a silicon oxynitride film. However, as shown in Fig. 14, by disposing a silicon oxide film, a silicon oxynitride film or a silicon nitride film as the cap film 22 interposed between the gate electrode and the high dielectric constant insulating film 21, the effective work function is reduced, resulting in a lower threshold can be achieved. A silicon oxide film or a silicon oxynitride film may be provided between the high dielectric constant insulating film and the substrate.

Incidentally, in this detailed description, the "effective work function" of the gate electrode is generally calculated from the flat band by CV measurement, and not only the work function of the gate electrode itself, but also the fixed charge in the insulating film, on the interface. The formed dipole is affected by Fermi level pinning. It is distinct from the intrinsic "work function" of the material constituting the gate electrode. In addition, the term "high dielectric constant insulating film" refers to silicon dioxide (SiO2) which is conventionally used as a gate insulating film.<sb>2</sb>) is used to distinguish it from an insulating film made of , and means having a dielectric constant greater than that of silicon dioxide, but the specific value thereof is not limited by this term.