Method for testing memory cell of semiconductor memory device, especially including a memory cell array, mux, and repair fuse box

The present invention relates to a memory cell test method capable of performing a parallel bit test after repairing a defective cell using a repair cell inserted into another block when a defect occurs in a specific block memory cell. To this end, in the memory cell test method of a semiconductor memory device having a spare cell for repairing a defective cell of an arbitrary memory block of a memory cell array according to the present invention, the spare cell is a defective cell of a specific block or of another memory block. repairing defective cells; performing a parallel bit test by accessing data through different input/output lines (I/O) for each block of the memory cell array after repairing the defective memory cell with a spare cell; and repairing the defective memory cell with a spare cell; The method further comprises the step of detecting whether the spare cell is defective by performing a test on the spare cell before performing the test.