Vertical power semiconductor device and method of making the same

Power semiconductor devices having laterally extending base shielding regions that inhibit base reach through and methods of forming same

The present invention relates to a semiconductor switching device, and more particularly, to a switching device for power switching and power amplification applications and a manufacturing method thereof.

In general, power MOSFETs (MOSFETs) have been developed for applications requiring power switching and power amplification. Commercially available devices for power switching applications are typically DMOSFETs (DMOSFETs) and UMOSFETs (UMOSFETs). One main purpose in these devices is to achieve low specific on-resistance to reduce power dissipation. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon application of an appropriate gate bias. For example, turn-on in an N-type enhancement MOSFET is a conductive N-type inversion layer channel (also referred to as "channel region") in a P-type base region in response to application of a positive gate bias. occurs when it is formed. The inversion layer channel electrically connects the N-type source and drain regions to allow majority carrier conduction between the source and drain.

The gate electrode of the power MOSFET is isolated from the base region by an intervening insulating film, typically a silicon oxide film. Because the gate is isolated from the base region, little gate current is required to keep the MOSFET conductive or switch it from on-state to off-state and vice versa. The gate current is kept small during switching because the gate forms a capacitor with the base region of the MOSFET. Thus, only charge and discharge currents ("displacement current") are required during switching. Because of the high input impedance associated with the insulated gate electrode, a minimum current is required for the gate electrode and the gate driving circuit can be easily realized. Moreover, since current conduction in the MOSFET occurs only by the transport of majority carriers across the inversion layer channel, there is no delay associated with storage and recombination of surplus minority carriers. Therefore, the switching speed of the power MOSFET can be made more than 10 times faster than the switching speed of the bipolar transistor. Unlike bipolar transistors, power MOSFETs can be designed to simultaneously withstand high current densities and high voltage applications for relatively long periods of time, without a detrimental breakdown mechanism known as "second breakdown". Power MOSFETs can also be easily paralleled, as the forward voltage drop of the power MOSFETs increases with increasing temperature, thereby promoting uniform current distribution between paralleled devices.

DMOSFET and UMOSFET are described more faithfully in BJBaliga's "Power Semiconductor Devices" [PWS Publishing Co. (ISBN-0-534-94098-6) (1995)] textbook, which is incorporated herein by reference. Chapter 7 of this textbook describes power MOSFETs on pages 335-425. Additionally, examples of silicon power MOSFETs including accumulation, inversion, and extended trench FETs with trench gate electrodes extending into the N+ drain region are described in the paper "Comparison of Ultralow Specific On- Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Convention UMOSFETs" are described in IEEE Transactions on Electron Devices, Vol. 41, No. 5, May (1994). As described by Syau et al., 100-250 μΩcm for devices capable of withstanding 25V max.² The range of intrinsic on-resistance was verified experimentally. However, the performance of these devices is limited by the fact that the forward blocking voltage must be sustained across the gate oxide at the bottom of the trench. U.S. Patent No. 4,680,853 to Lidow et al. discloses a general power MOSFET that uses a heavily doped N+ region 130 between adjacent P-base regions to reduce on-state resistance. For example, Fig. 22 by Lidow et al. discloses a high conductivity region 130 with a constant lateral density, but with a slope starting from a high concentration on the chip surface below the gate oxide and extending to a low concentration within the chip body.

Fig. 1(d) from the aforementioned paper by Syau et al. discloses a typical UMOSFET structure. In the blocking mode of operation, this UMOSFET carries most of the forward blocking voltage across the N-type drift layer. To achieve high maximum blocking voltage capability, the N-type drift layer must be doped to a relatively low level, but in general, a low doping level increases the on-state series resistance. Based on these two competing design requirements: high blocking voltage and low on-state resistance, a basic figure of merit for the power device is derived, which is the intrinsic on-resistance (R)._{on, sp}) and the maximum blocking voltage (BV). As described on page 373 of the above textbook of BJBaliga, the ideal specific on-resistance of the N-type silicon drift region is given by the following equation.

R_{on, sp}= 5.93×10^-9(BV)^2.5 (1)

Therefore, for a device with 60V blocking capability, the ideal specific on-resistance is 170 μΩcm²am. However, there is an additional resistive contribution from the channel, so the reported specific on-resistance for UMOSFETs is usually much higher. For example, 730 μΩ cm²A UMOSFET with intrinsic on-resistance of pp.247-251, (1989)]. However, in this device, a uniform drift region doping concentration lower than the outlier was required to compensate for the high concentration of field lines near the bottom corner of the trench when blocking high forward voltages. U.S. Patent Nos. 5,637,989 and 5,742,076, which are incorporated herein by reference, and U.S. Patent Application Serial No. 08/906,916, filed on August 6, 1997, also disclose popular power semiconductor devices with vertical current carrying capability.

In particular, U.S. Patent No. 5,637,898 to Baliga discloses a preferred silicon field effect transistor commonly referred to as a graded-doped (GD) UMOSFET. As shown in FIG. 3 of the '898 patent, the unit cell 100 of the integrated power semiconductor device field effect transistor has a width "W of 1 μm._c", a first conductivity type (eg N+) substrate drain layer 114 heavily doped, a drift layer 112 of a first conductivity type having a linear gradient doping concentration, a second conductivity type (eg, N+) For example, a relatively thin base layer 116 of P-type) and a source layer 118 of a first conductivity type (ie, N+) doped with high concentration are provided. The drift layer 112 is 100 μm thick and 1×10¹⁸㎝^-3Higher doping concentrations (e.g. 1×10¹⁹㎝^-3) can be formed by epitaxially growing an N-type in-situ doped single crystal silicon layer having a thickness of 4 μm on the N-type drain layer 114 having the . Drift layer 112 also has a linear gradient doping concentration, with a maximum concentration of 3 x 10 at the N+/N junction with drain layer 114 .¹⁷㎝^-3and the minimum concentration is 1×10 starting from 3 μm (ie, 1 μm in depth) from the N+/N junction and leading to a uniform level up to the top surface.¹⁶㎝^-3am. The base layer 116 introduces a P-type dopant such as boron (B) into the drift layer 112 with an energy of 100 keV and 1×10¹⁴㎝^-2It can be formed by injecting at a dose level of The P-type dopant may then be diffused into the drift layer 112 to a depth of 0.5 μm. N-type dopants such as arsenic (As) also have an energy of 50 keV and 1×10¹⁵㎝^-2can be injected at a dose level of N-type and P-type dopants may be simultaneously diffused to a depth of 0.5 μm and 1.0 μm, respectively, to form a composite semiconductor substrate including drain, drift, base, and source layers.

Next, a stripe-shaped trench having a pair of facing sidewalls 120a and a bottom 120b extending in a third direction (not shown) is formed in the substrate. 1 μm width W_cIn the unit cell 100 having_tIt is preferable to form it to have ". An insulated gate electrode comprising a gate insulating region 124 and an electrically conductive gate 126 (eg, polysilicon) is formed in the trench. A portion of the gate insulating region 124 that extends close to the trench bottom 120b and the drift layer 112 has a thickness "T of about 2000 Angstroms.₁" to suppress the generation of high electric fields at the bottom of the trench and provide a nearly uniform potential gradient along the trench sidewalls 120a. A portion of the gate insulating region 124 that extends opposite the base layer 116 and the source layer 118 has a thickness "T of about 500 Å.₂", the threshold voltage of the device can be maintained at about 2-3V. Simulating the unit cell 100 at a gate bias of 15V, the maximum blocking voltage capability is 60V and the intrinsic on-resistance (R)_{on, sp}) is 40 μΩ cm²It can be confirmed that a race-type silicon field effect transistor is obtained. This is 170 μΩcm for a 60V power UMOSFET.²4 times less than the ideal intrinsic on-resistance of Despite these excellent characteristics, the transistor shown in FIG. 3 of the '898 patent has a total gate-to-drain capacitance (C_GDIf ) is too large, it may suffer from a relatively low high-frequency figure of merit (HFOM). Improper edge termination of the MOSFET can also prevent the maximum blocking voltage from being achieved. Another UMOSFET having a sloped drift region and a trench-type source electrode is also disclosed in U.S. Patent No. 5,998,833 to Baliga, which is incorporated herein by reference.

Power MOSFETs can also be used in power amplification applications (eg audio or rf). In these applications, the linearity of the transfer characteristics (e.g., I_d- V_g) becomes very important. The commercially available devices used in these power amplification applications are typically LDMOS (LDMOS) and gallium arsenide MESFETs (MesFET). However, as described below, power MOSFETs including LDMOS transistors can have non-linear characteristics that can lead to signal distortion. The physics of current saturation in power MOSFETs is described in SMSze's textbook "Physics of Semiconductor Devices" [section 8.2.2, pages 438-451 (1981)]. As described in this textbook, MOSFETs typically operate in one of two modes. At low drain voltages (relative to the gate voltage), the MOSFET_dand V_gIt operates in a linear mode in which there is an almost linear relationship. At this time, transconductance (g)_m) is V_galso is irrelevant

g_m=(Z/L)u_nsC_oxV_d (2)

where Z and L are the width and length of the channel, respectively, u_nsis the channel mobility, C_oxis the intrinsic capacitance of the gate oxide, and V_dis the drain voltage. However, once the drain voltage is increased, the gate voltage (V_g), the MOSFET operates in saturation mode as a result of channel pinch-off. When this occurs, the expression for transconductance can be

g_m=(Z/L)u_nsC_ox(V_g-V_th) (3)

where V_gis the gate voltage, V_this the threshold voltage of the MOSFET. Therefore, as described by Equation (3), as the gate bias increases during the saturation operation, the transconductance also increases. This makes the relationship between drain current (output side) and gate voltage (input side) non-linear. This is because the drain current increases in proportion to the square of the gate voltage. This nonlinearity can lead to signal distortion in the power amplifier. Moreover, although the voltage drop along the channel remains below the gate voltage, the 1×10⁴When it becomes large enough to produce a longitudinal electric field greater than V/cm, the electrons in the channel move with reduced differential mobility due to carrier velocity saturation.

Therefore, despite attempts to develop power MOSFETs for power switching and power amplification applications, the need for the development of power MOSFETs with improved electrical characteristics, including high voltage and highly linear transfer characteristics when withstood high voltage, continues to be a necessity. It continues.

The vertical power device according to an embodiment of the present invention enhances forward on-state and reverse breakdown voltage characteristics by using a retrograde doped transition region. A heavily doped shielding region extending adjacent the transition region is also provided, contributing to the depletion of the transition region during forward on-state conduction and reverse blocking modes of operation.

A vertical power device (eg, MOSFET) according to a first embodiment of the present invention extends into first and second trenches, between the first and second trenches, into a mesa defined by the first and second trenches. and a semiconductor substrate having a drift region of a first conductivity type (eg, N-type) therein. The drift region is preferably non-uniformly doped to have a retrograded doping profile with respect to the upper surface of the substrate on which the first and second trenches are formed. In particular, the substrate may include a heavily doped drain region of the first conductivity type and a drift region extending between the drain region and the upper surface. The doping profile in the drift region may decrease monotonically from a non-rectifying junction with the drain region to the upper surface of the substrate and the upper region of the drift region may be at a relatively low level (eg, 1×10 ).¹⁶cm^-3) can be uniformly doped. First and second insulating electrodes may also be formed in the first and second trenches. The first and second insulating electrodes may constitute a trench-type source electrode of a three-terminal device.

First and second base regions of a second conductivity type (eg P-type) are also formed in the mesa. This base region preferably extends adjacent to the sidewalls of the first and second trenches respectively. First and second source regions of the first conductivity type heavily doped are also formed in the first and second base regions, respectively. An insulated gate electrode extending over the mesa is formed. The insulated gate electrode is patterned such that the top surface defines an interface between the insulated gate electrode and the first and second base regions. By applying a gate bias of sufficient magnitude to the insulated gate electrode, an inversion layer channel is formed in the first and second base regions during forward on-state conduction.

A first conductivity type transition region is also formed in the mesa. This transition region extends between the first and second base regions and extends to the interface with the insulated gate electrode. The transition region forms a non-rectifying junction with the drift region and has a doping profile of the first conductivity type that is retrograded perpendicular to the upper surface. The doping profile has a highest doping concentration at a first depth to the upper surface, the first depth extending from about 0.2 to 0.5 microns relative to the upper surface. Preferably, between the first depth and the upper surface, the doping profile decreases monotonically toward the upper surface. The slope of this monotonically decreasing profile is preferably 3×10²¹cm^-4bigger than "buried" at the first depth. Establishment of the peak may be achieved by performing a single implantation step at a predetermined dose and energy level, or performing multiple implantation steps at different energy levels from a predetermined dose. Preferably, the highest concentration of the dopant of the first conductivity type in the transition region is at least two times greater than the concentration of the dopant in the transition region in the upper surface. More preferably, the peak concentration of the dopant of the first conductivity type in the transition region is at least 10 times greater than the concentration of the dopant in the transition region in the top surface.

According to a preferred aspect of the power device according to the first embodiment, the maximum concentration of the dopant of the first conductivity type in the transition region (concentration at the first depth) multiplied by the width of the transition region at the first depth. this 1×10¹²cm^-2 to 7×10¹²cm^-2 within the range, more preferably about 3.5×10¹²cm^-2 to about 6.5×10¹²cm^-2 is within range Depending on the unit cell design in the integrated multi-cell device, the maximum concentration of the dopant of the first conductivity type in the transition region multiplied by the width of the non-rectifying junction between the transition region and the drift region is 1×10¹²cm^-2 to 7×10¹²cm^-2 may be within range. The product of the maximum concentration of the dopant of the first conductivity type in the transition region, the width of the transition region at the first depth, and the width of the mesa is 2×10¹⁵cm^-1It can be set to a smaller level. To achieve sufficient charge coupling within the drift region mesa, the product of the drift region mesa width and the amount of charge of the first conductivity type in the portion of the drift region mesa extending below the transition region is 2×10⁹cm^-1 to 2×10¹⁰cm^-1 is within range

According to another aspect of the first embodiment, forward on-state and reverse blocking characteristics may be improved by including a heavily doped second conductivity-type shielding region extending into the mesa on opposite sides of the transition region. In particular, the first shielding region of the second conductivity type extends between the first base region and the drift region and is doped with a higher concentration than the first base region. Similarly, a second shielding region of a second conductivity type extends between the second base region and the drift region and is doped with a higher concentration than the second base region. To be depleted during forward on-state and reverse blocking modes of operation, the first and second shield regions each form a PN rectifying junction with the transition region. The maximum concentration of the dopant of the first conductivity type in the transition region multiplied by the width between the first and second shielding regions is 1×10¹²cm^-2 to 7×10¹²cm^-2 By coming within range, high breakdown voltage capability can also be achieved.

An integrated vertical power device according to a second embodiment of the present invention comprises an active unit cell that provides a forward on-state current and an equivalent maximum reverse blocking voltage while removing heat generated from the active cell during forward on-state conduction. It is preferable to include a supporting dummy cell. According to the second embodiment, each integrated unit cell may include one active cell and one or more dummy unit cells. In addition to the first and second trenches, a third trench may be formed in the semiconductor substrate. The first and second trenches define an active mesa in which an active unit cell is formed, and the second and third trenches define a dummy mesa in which a dummy unit cell is formed therebetween. Preferably, a dummy base region of the second conductivity type is formed in the dummy mesa together with the dummy shielding region. The dummy base and the shielding region may extend past the dummy mesa to be electrically connected to the first and second source electrodes in the active unit cell. When one or more dummy unit cells are formed, a uniform reverse blocking voltage characteristic is achieved by making the width of the mesa in which the active unit cell is formed is the same as the width of each dummy mesa formed in each of the dummy unit cells. can do. Instead, and in place of the third dummy base region, a field plate insulating layer may be formed on the upper surface of the dummy mesa, and a third insulating electrode may be formed in the third trench. The source electrode may extend on the field plate insulating layer and electrically connected to the first, second, and third insulating electrodes in the trench. In the case where the field plate insulating layer is formed on the dummy mesa instead of using the dummy base region, the gap between the first and second trenches is the gap between the second and third trenches to support the maximum blocking voltage. does not necessarily have to be the same as

Additional embodiments of the present invention also include a method of manufacturing a vertical power device. The method preferably comprises implanting a transition region dopant of a first conductivity type at a first dose and at a first energy level into a surface of the semiconductor substrate having a drift region of a first conductivity type therein extending adjacent the surface of the substrate. includes Then, an insulating gate electrode is formed on the surface. Preferably, the insulating gate electrode is patterned to extend opposite the implanted transition region dopant. A shield region dopant of a second conductivity type is implanted into the surface at a second dose and at a second energy level. This ion implantation step is preferably performed in a self-aligned manner with respect to the gate electrode by using the gate electrode as an ion implantation mask. Using the gate electrode as an ion implantation mask, a base region dopant of a second conductivity type is also implanted into the surface at a third dose and a third energy level. Accordingly, the base and the shielding region dopant are self-aligned with respect to each other.

A thermal treatment step is then performed to diffuse the implanted transition, shield and base region dopants into the substrate, such that a transition region, first and second shield regions on opposite sides of the transition region, and the transition region define first and second base regions on opposite sides of The transition region extends into the drift region and has a doping profile of the first conductivity type retrograded relative to the surface. This retrograde profile is achieved by establishing the highest dopant concentration buried well below the surface. The first and second shielding regions each form a PN rectifying junction with the transition region, and the first and second base regions also form a PN rectifying junction with the transition region, respectively. Doses and implant energies related to the base and occlusion dopants are selected such that the occlusion region is more heavily doped with respect to the base region and extends deeper into the substrate.

According to a preferred aspect of this embodiment, the first dose and energy level and the duration of the diffusion step are the transition region measured between the first and second shielding regions and the highest concentration of a dopant of a first conductivity type in the transition region. The product of the width is 1×10¹²cm^-2 to 7×10¹²cm^-2 It is large enough to be within range. When the depths of highest concentration are measured for the surface, the first and second energy levels are such that the depth of the highest concentration of the dopant of the second conductivity type in the transition region is 10 of the depth of the highest concentration of the dopant of the first conductivity type in the transition region. It can be set to a level that comes within %.

Before the step of implanting the shielding region dopant, a step of forming trenches in the semiconductor substrate and lining the trenches with a trench insulating layer may be followed. Conductive regions are also formed on the trench insulating layer. Such trench-related steps may be performed before the step of implanting the transition region dopant. In such a case, the transition region dopant is preferably implanted into the conductive region in the trenches and into a mesa defined between the trenches. According to another preferred aspect of this embodiment, a step may also be performed to improve the shape of the source contact to increase the maximum on-state current density in the power device. In particular, after the source, base, and shielding regions are exposed by etching back the trench insulating layer, a source contact in ohmic contact with the conductive region and a source contact in ohmic contact with the source, base, and shielding regions on the sidewalls of each trench are formed. forming the source contact on the trench sidewall.

A vertical power MOSFET according to another embodiment of the present invention includes a semiconductor substrate having a drift region of a first conductivity type therein and an insulated gate electrode extending on a first surface of the semiconductor substrate. A first base shielding region of a second conductivity type is provided extending within the semiconductor substrate. The first base shielding region has a first lateral length with respect to the first end of the insulating gate electrode. A first base region of a second conductivity type is also provided in the substrate. The first base region extends between the first base shielding region and the first surface. The first base region has a second side length smaller than the first side length with respect to the first end of the insulating gate electrode. The power device also includes a first source region of a first conductivity type forming a PN junction with the first base region in the first base region. A transition region of a first conductivity type is provided extending between the drift region and a portion of the first surface extending opposite the insulated gate electrode. The transition region forms a rectifying junction with the first base region and the first base shield region. The upper portion of the transition region has a doping profile of the first conductivity type vertically retrograded therein. The transition region may have a highest concentration of a dopant of the first conductivity type at a first depth with respect to the first surface.

A second base region and a second base shielding region may also be provided in the substrate. In particular, the first and second base regions are self-aligned to opposite first and second ends of the insulated gate electrode, respectively, with opposite sides of the top of the transition region extending adjacent to the first surface and PN junctions can be formed. The first and second base shield regions are more heavily doped than the first and second base regions and extend laterally towards each other into the semiconductor substrate, thereby reducing the amount of the transition region at a second depth relative to the first surface. Limit the neck of the upper area to a minimum width. Preferably, the second depth is greater than about 0.25 microns. The product of the maximum concentration of the dopant of the first conductivity type in the transition region and the width of the transition region at the first depth is about 1×10¹²cm^-2 to about 7×10¹²cm^-2 preferably within the range, more preferably about 3.5 x 10¹²cm^-2 to about 6.5×10¹²cm^-2 is within range

A method of manufacturing such a vertical MOSFET includes forming a drift region of a first conductivity type within a semiconductor substrate and a transition region of a first conductivity type extending between the drift region and a first surface of the semiconductor substrate. An insulating gate electrode is formed on the first surface. After forming the gate electrode, using the gate electrode as an ion implantation mask, a base shielding region dopant of the second conductivity type is implanted into the upper region of the transition region at a high dose and high energy level. The highest concentration of the implanted base shield region dopant may be sufficiently spaced from the first surface to form a buried base shield region having the properties disclosed herein. The semiconductor substrate is annealed to partially diffuse the base shield region dopant vertically into the transition region and horizontally partially under the gate electrode. This annealing step defines first and second intermediate shielding regions. A base region dopant of a second conductivity type is implanted into the first and second intermediate shield regions at a low dose and low energy level. During this implantation step, the gate electrode is used again as an implantation mask to form a self-aligned shape. Annealing the semiconductor substrate to vertically diffuse the base region dopant into the substrate and horizontally diffuse it along the first surface under the gate electrode to define first and second base regions. During this annealing step, the base shield region dopant also diffuses sufficiently vertically and horizontally all the way into the substrate. First and second limiting the neck of the upper region of the transition region to a minimum width at a depth corresponding to the depth corresponding to the initial highest concentration of the implanted base shield region dopant because of the early ion implantation and multiple annealing steps A shielding area is achieved. Next, first and second source regions are respectively formed in the first and second base regions.

1 is a cross-sectional view of a vertical power device according to a first embodiment of the present invention.

2 is a cross-sectional view of a vertical power device according to a second embodiment of the present invention.

3 is a cross-sectional view of a vertical power device according to a third embodiment of the present invention.

4 is a cross-sectional view of a vertical power device according to a fourth embodiment of the present invention.

5 is a cross-sectional view of a vertical power device according to a fifth embodiment of the present invention.

6 is a cross-sectional view of a vertical power device according to a sixth embodiment of the present invention.

7 is a cross-sectional view of a vertical power device according to a seventh embodiment of the present invention.

FIG. 8a graphically illustrates a preferred vertical retrograde doping profile across the transition region of the embodiment of FIG. 1 obtained by performing multiple transition region dopant implants at different energies; FIG.

8B graphically illustrates a preferred vertical doping profile across the source, base and shield regions of the embodiment of FIG. 1 .

9A-9K are cross-sectional views of an intermediate stage structure illustrating a preferred method of manufacturing the vertical power device of FIG. 5;

10 is a cross-sectional view of a vertical power device according to another embodiment of the present invention.

11 is a cross-sectional view of a vertical power device including a dummy gate electrode electrically connected to a source electrode according to another embodiment of the present invention.

12 is a cross-sectional view of a conventional double-spreading power MOSFET.

13 is a cross-sectional view of a vertical power device unit cell according to another embodiment of the present invention.

14A-14G are cross-sectional views of an intermediate stage structure illustrating a method of manufacturing the device of FIG. 13 ;

Hereinafter, the present invention will be more fully described with reference to the accompanying drawings showing preferred embodiments of the present invention. However, the present invention may be embodied in many different forms, and the scope of the present invention should not be construed as being limited by the examples shown below. Rather, the embodiments of the present invention are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. Furthermore, the various layers and regions in the drawings are schematically drawn. As will be appreciated by those skilled in the art, when a layer is described as being "on" a semiconductor substrate or other layer, the layer may be in direct contact with the semiconductor substrate or other layer. Alternatively, a third layer may be interposed therebetween. Furthermore, the terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types, such as N or P-type, each embodiment described and illustrated herein being its complement. Examples are also included. Like reference numerals refer to like elements throughout the specification.

Referring now to FIG. 1 , the integrated vertical power device 10 according to the first embodiment of the present invention includes a plurality of active vertical power device unit cells arranged side by side in a semiconductor substrate. As shown, the power device 10 has a heavily doped first conductivity type (represented by N+) drain region 100 , and a first conductivity type drift region forming a non-rectifying junction with the drain region 100 . (102). The drain electrode 136 is also formed in ohmic contact with the drain region 100 . The drain region 100 may have a thickness between about 10 microns and about 500 microns. The drift region 102 is preferably non-uniformly doped. In particular, the drift region 102 preferably has a monotonically decreasing gradient doping profile along a direction extending from the non-rectifying junction to the first surface 102a of the drift region 102 . This inclined doping profile is preferably about 1×10¹⁷to 2.5×10¹⁷㎝^-3It can be a linear gradient doping profile decreasing from a maximum drift region dopant concentration with a range between to a minimum dopant concentration. Accordingly, the drain region 100 is approximately 1×10¹⁹㎝^-3 If it is doped to a higher level, the non-rectifying junction will become an abrupt non-rectifying junction. The upper area within the drift area 102 is approximately 1×10¹⁶㎝^-3 The level may be uniformly doped, and the uniformly doped upper region in the drift region 102 may have a thickness in the range of about 0.5 to about 1.0 μm.

Several trenches 104 may be formed in the drift region 102 . If trenches are to be formed, the trenches 104 are preferably formed side by side as parallel strip-shaped trenches within the drift region 102 . However, other trench shapes may also be used (eg, arcuate, tortuous, polygonal including rings and hexagons, etc.). As described herein, regions will be defined as distinct regions if they are seen as distinct regions on a cross-section. As shown, each pair of trenches preferably defines a drift region mesa 102b therebetween. An electrically insulating film 106 is also formed on the sidewalls and bottom of the trench 104 . These "trench" The insulating film 106 may have a thickness of about 3000 Angstroms, but the thickness may vary depending, among other things, on the grade of the power device 10 . The electrically insulating film 106 may be a silicon oxide film or other common dielectric material. Each trench 104 is preferably filled with a conductive region 110 electrically insulated from the drift region 102 by a respective electrically insulating film 106 . The conductive region 110 may constitute a trench-type electrode electrically connected to each other by the source electrode 138 . This source contact/electrode 138 may extend on the first surface 102a of the drift region 102 , as shown.

Each of the uniformly doped upper regions in the drift region mesa 102b constitutes the transition region 130 of the first conductivity type. The transition region 130 forms a non-rectifying junction with each of the drift regions 102 and, depending on the thickness, a non-rectifying junction with a uniformly doped upper region of the drift region 102 or a gradient doped portion of the drift region 102 . can form. For example, the uniformly doped upper region in the drift region 102 may have a thickness of about 1.0 μm with respect to the first surface 102a and the transition region 130 about the first surface 102a. It may have a thickness of 0.7 μm. Furthermore, according to a preferred aspect of the present invention, each transition region 130 has a doping profile of the first conductivity type that is retrograded perpendicular to the first surface 102a. In particular, the peak concentration of the dopant of the first conductivity type at the first depth of the transition region is at least two times greater than the concentration at the first surface 102a of the doping profile of the retrograded first conductivity type. More preferably, the peak concentration of the dopant of the first conductivity type in the transition region is at least 10 times greater than the concentration at the first surface of the doping profile of the first conductivity type. According to another preferred aspect, the slope of at least a portion of the retrograde first conductivity type doping profile is 3×10²¹cm^-4bigger than The doping profile in the transition region 130 also includes a high-doping profile that extends in a descending direction from the highest concentration to the non-rectifying junction between the transition region 130 and the drift region 102 . A desirable doping profile can be achieved by performing a single implantation step or performing several implantation steps at a relatively high dose and energy level. For example, as shown in FIG. 8A , the relatively broad peak of the transition region doping profile uses a dopant with an intrinsic diffusion length of about 1.0 microns and reduces the first, second and third implant depths to about 0.15, 0.3 and This can be achieved by performing three implantation steps at each energy (same or similar dose level) to form at 0.45 microns.

As shown, a gate electrode 118 is formed on the first surface 102a. This gate electrode 118 may be strip-shaped and may extend parallel to the trench-type electrode 110 . As shown, the gate electrode 118 preferably constitutes an insulated gate electrode (eg, a MOS gate electrode). With the regions 130 , 133 , 126 , and 128 in each drift region mesa 102b rotated 90 degrees with respect to the sidewall of the trench 104 , the gate electrode 118 is positioned in the longitudinal direction of the trench-type electrode 110 . It may extend in a vertical longitudinal direction. The vertical power element 10 also includes a high concentration second conductivity type (denoted P+) shielding region 128 formed at spaced apart locations within the drift region mesa 102b. This shielding region 128 is preferably self-aligned to the gate electrode 118 . Each shield region 128 preferably forms a PN rectifying junction with each of the sides of the transition region 130 , the drift region mesa 102b (or the tail of the transition region 130 ). According to a preferred aspect of the present invention, the peak concentration of the dopant of the second conductivity type in each shield region 128 is approximately the same depth (from the first surface 102a) as the peak concentration of the dopant of the first conductivity type in each transition region 130 . depth) is formed. A second conductivity type (denoted P) base region 126 is also formed in each drift region mesa 102b. Each base region 126 is preferably self-aligned to the gate electrode 118 . A heavily doped first conductivity type (indicated by N+) source region 133 is also formed in each base region 126 as shown. The spacing between each edge of the source region 133 and the transition region 130 at the first surface 102a defines the channel length of the power device 10 . The source region 133 is in ohmic contact with the source electrode 138 . Edge termination is provided by extending the source electrode 138 onto the peripheral drift region extension 102c and electrically insulating the source electrode 138 from the peripheral drift region extension 102c using a field plate isolation region 125 . You may.

A combination of (i) a pair of spaced apart shielding regions 128 in each drift region mesa 102b and (ii) a desired transition region extending between the shielding regions 128 and having a vertical retrograde doping profile is: The breakdown voltage characteristic of each active unit cell of the multi-cell power device 10 may be enhanced. In particular, the shielding region 128 sufficiently suppresses the P-base reach-through effect when the power element 10 blocks the reverse voltage and passes the shielding region 128 instead of the base region 126 . It can operate to "shield" each base region 126 by inducing a reverse current. This P-base reach-through suppression allows for a reduction in the channel length of the device 10 . In addition, the preferred retrograde doping profile in the transition region 130 allows full depletion of the transition region 130 when the power device 10 blocks the maximum reverse voltage and the drift region mesa 102b supports the reverse voltage. do.

Complete depletion of transition region 130 may also occur during forward on-state conduction. In particular, complete depletion during forward operation preferably occurs before the voltage in the channel (the portion adjacent to the edge of the transition region 130) equals the gate voltage on the insulated gate electrode 118. As used herein, a transition region being "fully depleted" means that the transition region is at least sufficient to provide a JFET-style pinch-off of an extended forward current path vertically across the transition region 130 . It should be interpreted to mean that the area is sufficiently depleted. In order to obtain sufficient depletion, a relatively highly doped shield region 128 of a second conductivity type (eg P+) is provided near the transition region 130 and on opposite sides of the transition region 130 . As the voltage in the channel increases during forward on-state conduction, transition region 130 becomes increasingly depleted within which a JFET-style pinch-off occurs. This JFET-style pinch-off in transition region 130 is the drain-side voltage (V) of the channel._CD) is equal to the gate voltage (e.g. V_CDV_gs) can be designed to occur. For example, the MOSFET is 0.1V_CD 0.5V and V_gs = 4.0V, the transition region can be designed to be completely depleted. The preferred use of transition region 130 is that the channel of the field effect transistor within power device 10 operates in a linear mode of operation during forward on-state conduction, while the drain region of the transistor operates in a rate saturation mode of operation. can make it Other power devices exhibiting similar modes of operation are described in U.S. Patent Application Serial No. 09/602,414, filed June 23, 2000 and assigned to the present assignee, "MOSFET Devices Having Linear Transfer Characteristics When Operating in Velocity Saturation Mode and Methods of Forming. and Operating Same", the disclosures of which are incorporated herein by reference.

For the device of Figure 1, simulations were performed for a unit cell with a trench depth of 4.7 microns, a trench width of 1.1 microns, and a mesa width of 1.9 microns. A sidewall oxide thickness of 3000 Å was used. The drift region had a thickness of 6 microns and the uniformly doped upper region within the drift region had a thickness of 0.5 microns. The concentration of the dopant of the first conductivity type in the uniformly doped upper region in the transition region is 1×10¹⁶㎝^-3and the drain area is 5×10¹⁹㎝^-3had a phosphorus (P) doping concentration of The gate oxide thickness was set to 250 Å and a total gate length (length across the mesa) of 0.9 microns was used. The width (width to sidewall) of the shield, base and source regions were 0.65, 0.65, and 0.45 microns, respectively, and the channel length was 0.2 microns. The thickness of the transition region (thickness at the depth of the highest concentration in the transition region) was set to 0.6 microns. The depths of the source, base, shielding and transition regions, and their highest concentrations, can be obtained from the following Table 1 and Figures 8a and 8b, where the peak N_dwith peak N_ais the highest concentration of donor and acceptor.

<tables id="1"><table id="1" cols="5"><row><entry he="309" wi="1724" rb="1" re="1" cb="1" ce="1" al="c">area</entry><entry he="309" wi="2093" rb="1" re="1" cb="2" ce="2" al="c">Ion implantation energy (KeV)</entry><entry he="309" wi="1909" rb="1" re="1" cb="3" ce="3" al="c">Ion implantation dose (cm)^-2)</entry><entry he="309" wi="1390" rb="1" re="1" cb="4" ce="4" al="c">dopant</entry><entry he="309" wi="2757" rb="1" re="1" cb="5" ce="5" al="c">peak N_{d, a}cm^-3</entry><row><entry he="173" wi="1724" rb="2" re="2" cb="1" ce="1" al="c">N+ source</entry><entry he="173" wi="2093" rb="2" re="2" cb="2" ce="2" al="c">40-50</entry><entry he="173" wi="1909" rb="2" re="2" cb="3" ce="3" al="c">1-5×10¹⁵</entry><entry he="173" wi="1390" rb="2" re="2" cb="4" ce="4" al="c">P, As</entry><entry he="173" wi="2757" rb="2" re="2" cb="5" ce="5" al="c">1×10²⁰</entry><row><entry he="358" wi="1724" rb="3" re="3" cb="1" ce="1" al="c">P-base</entry><entry he="358" wi="2093" rb="3" re="3" cb="2" ce="2" al="c">40-50</entry><entry he="358" wi="1909" rb="3" re="3" cb="3" ce="3" al="c">1-5×10¹³</entry><entry he="358" wi="1390" rb="3" re="3" cb="4" ce="4" al="c">B</entry><entry he="358" wi="2757" rb="3" re="3" cb="5" ce="5" al="c">2×10¹⁸(Surface) 4×10¹⁷(Channel Max) </entry><row><entry he="173" wi="1724" rb="4" re="4" cb="1" ce="1" al="c">P+ shielding</entry><entry he="173" wi="2093" rb="4" re="4" cb="2" ce="2" al="c">100</entry><entry he="173" wi="1909" rb="4" re="4" cb="3" ce="3" al="c">1-5×10¹⁴</entry><entry he="173" wi="1390" rb="4" re="4" cb="4" ce="4" al="c">B</entry><entry he="173" wi="2757" rb="4" re="4" cb="5" ce="5" al="c">5×10¹⁸</entry><row><entry he="177" wi="1724" rb="5" re="5" cb="1" ce="1" al="c">-transition</entry><entry he="177" wi="2093" rb="5" re="5" cb="2" ce="2" al="c">200</entry><entry he="177" wi="1909" rb="5" re="5" cb="3" ce="3" al="c">1-10×10¹²</entry><entry he="177" wi="1390" rb="5" re="5" cb="4" ce="4" al="c">P</entry><entry he="177" wi="2757" rb="5" re="5" cb="5" ce="5" al="c">1.3×10¹⁷</entry></row></row></row></row></row></table></tables>

Based on the characteristics described above, the peak dopant concentration in the transition region (Peak_TR) and the width of the transition region (W_TR), and the simulated breakdown voltages of Tables 2 and 3 to be described later were obtained. For performing device simulations, Avant!^TM Medici supplied by^TM Simulation software was used.

<tables id="2"><table id="2" cols="4"><row><entry he="207" wi="1739" rb="1" re="1" cb="1" ce="1" al="c">W_TR(㎛)</entry><entry he="207" wi="2407" rb="1" re="1" cb="2" ce="2" al="c">(Peak_TR) (cm^-3)</entry><entry he="207" wi="2613" rb="1" re="1" cb="3" ce="3" al="c">BV(volts)</entry><entry he="207" wi="2857" rb="1" re="1" cb="4" ce="4" al="c">Q (#/cm²)</entry><row><entry he="173" wi="1739" rb="2" re="2" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="2" re="2" cb="2" ce="2" al="c">0.4×10¹⁷</entry><entry he="173" wi="2613" rb="2" re="2" cb="3" ce="3" al="c">80</entry><entry he="173" wi="2857" rb="2" re="2" cb="4" ce="4" al="c">0.2×10¹³</entry><row><entry he="173" wi="1739" rb="3" re="3" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="3" re="3" cb="2" ce="2" al="c">0.7×10¹⁷</entry><entry he="173" wi="2613" rb="3" re="3" cb="3" ce="3" al="c">80</entry><entry he="173" wi="2857" rb="3" re="3" cb="4" ce="4" al="c">0.35×10¹³</entry><row><entry he="173" wi="1739" rb="4" re="4" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="4" re="4" cb="2" ce="2" al="c">1.2×10¹⁷</entry><entry he="173" wi="2613" rb="4" re="4" cb="3" ce="3" al="c">79</entry><entry he="173" wi="2857" rb="4" re="4" cb="4" ce="4" al="c">0.6×10¹³</entry><row><entry he="173" wi="1739" rb="5" re="5" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="5" re="5" cb="2" ce="2" al="c">1.3×10¹⁷</entry><entry he="173" wi="2613" rb="5" re="5" cb="3" ce="3" al="c">78</entry><entry he="173" wi="2857" rb="5" re="5" cb="4" ce="4" al="c">0.65×10¹³</entry><row><entry he="173" wi="1739" rb="6" re="6" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="6" re="6" cb="2" ce="2" al="c">1.4×10¹⁷</entry><entry he="173" wi="2613" rb="6" re="6" cb="3" ce="3" al="c">62</entry><entry he="173" wi="2857" rb="6" re="6" cb="4" ce="4" al="c">0.7×10¹³</entry><row><entry he="173" wi="1739" rb="7" re="7" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="7" re="7" cb="2" ce="2" al="c">1.6×10¹⁷</entry><entry he="173" wi="2613" rb="7" re="7" cb="3" ce="3" al="c">35</entry><entry he="173" wi="2857" rb="7" re="7" cb="4" ce="4" al="c">0.8×10¹³</entry><row><entry he="173" wi="1739" rb="8" re="8" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2407" rb="8" re="8" cb="2" ce="2" al="c">1.9×10¹⁷</entry><entry he="173" wi="2613" rb="8" re="8" cb="3" ce="3" al="c">20</entry><entry he="173" wi="2857" rb="8" re="8" cb="4" ce="4" al="c">0.95×10¹³</entry><row><entry he="177" wi="1739" rb="9" re="9" cb="1" ce="1" al="c">0.5</entry><entry he="177" wi="2407" rb="9" re="9" cb="2" ce="2" al="c">2.5×10¹⁷</entry><entry he="177" wi="2613" rb="9" re="9" cb="3" ce="3" al="c">9</entry><entry he="177" wi="2857" rb="9" re="9" cb="4" ce="4" al="c">1.25×10¹³</entry></row></row></row></row></row></row></row></row></row></table></tables>

<tables id="3"><table id="3" cols="4"><row><entry he="207" wi="1903" rb="1" re="1" cb="1" ce="1" al="c">W_TR(㎛)</entry><entry he="207" wi="2477" rb="1" re="1" cb="2" ce="2" al="c">(Peak_TR) (cm^-3)</entry><entry he="207" wi="2420" rb="1" re="1" cb="3" ce="3" al="c">BV(volts)</entry><entry he="207" wi="2795" rb="1" re="1" cb="4" ce="4" al="c">Q (#/cm²)</entry><row><entry he="173" wi="1903" rb="2" re="2" cb="1" ce="1" al="c">0.3</entry><entry he="173" wi="2477" rb="2" re="2" cb="2" ce="2" al="c">1.4×10¹⁷</entry><entry he="173" wi="2420" rb="2" re="2" cb="3" ce="3" al="c">80</entry><entry he="173" wi="2795" rb="2" re="2" cb="4" ce="4" al="c">0.42×10¹³</entry><row><entry he="173" wi="1903" rb="3" re="3" cb="1" ce="1" al="c">0.4</entry><entry he="173" wi="2477" rb="3" re="3" cb="2" ce="2" al="c">1.4×10¹⁷</entry><entry he="173" wi="2420" rb="3" re="3" cb="3" ce="3" al="c">80</entry><entry he="173" wi="2795" rb="3" re="3" cb="4" ce="4" al="c">0.56×10¹³</entry><row><entry he="173" wi="1903" rb="4" re="4" cb="1" ce="1" al="c">0.5</entry><entry he="173" wi="2477" rb="4" re="4" cb="2" ce="2" al="c">1.4×10¹⁷</entry><entry he="173" wi="2420" rb="4" re="4" cb="3" ce="3" al="c">62</entry><entry he="173" wi="2795" rb="4" re="4" cb="4" ce="4" al="c">0.7×10¹³</entry><row><entry he="173" wi="1903" rb="5" re="5" cb="1" ce="1" al="c">0.6</entry><entry he="173" wi="2477" rb="5" re="5" cb="2" ce="2" al="c">1.4×10¹⁷</entry><entry he="173" wi="2420" rb="5" re="5" cb="3" ce="3" al="c">37</entry><entry he="173" wi="2795" rb="5" re="5" cb="4" ce="4" al="c">0.84×10¹³</entry><row><entry he="177" wi="1903" rb="6" re="6" cb="1" ce="1" al="c">0.7</entry><entry he="177" wi="2477" rb="6" re="6" cb="2" ce="2" al="c">1.4×10¹⁷</entry><entry he="177" wi="2420" rb="6" re="6" cb="3" ce="3" al="c">24</entry><entry he="177" wi="2795" rb="6" re="6" cb="4" ce="4" al="c">0.98×10¹³</entry></row></row></row></row></row></row></table></tables>

As determined by the inventor and shown in the simulation results in Tables 2 and 3, the maximum concentration (concentration at the first depth) of the dopant of the first conductivity type in the transition region multiplied by the width of the transition region at the first depth This preferred range, i.e. about 1×10¹²cm^-2 to about 7×10¹²cm^-2 within the range, more preferably about 3.5×10¹²cm^-2 to about 6.5×10¹²cm^-2 By bringing it within the range, it is possible to provide a power device with a high breakdown voltage. A narrower range, which is more desirable here, can result in devices with high breakdown voltages and excellent on-state resistance characteristics. Depending on the unit cell design in the integrated multi-cell device, the product of the maximum concentration of the dopant of the first conductivity type in the transition region multiplied by the width of the non-rectifying junction between the transition region and the drift region is approximately 1×10¹²cm^-2 to about 7×10¹²cm^-2 may be within range. The product of the maximum concentration of the dopant of the first conductivity type in the transition region, the width of the transition region at the first depth, and the width of the mesa is approximately 2×10¹⁵cm^-1It may be set to a smaller level. To achieve sufficient charge coupling within the drift region mesa, the product of the drift region mesa width and the amount of charge of the first conductivity type in the portion of the drift region mesa extending below the transition region is approximately 2×10⁹cm^-1 to about 2×10¹⁰cm^-1 It is preferable to be within the range.

2 to 7 , a power device according to a further embodiment of the present invention includes the multi-cell power device 20 of FIG. 2 . This device 20 is similar to the device 10 of FIG. 1, except that a non-parallel diode is provided by a Schottky rectifying contact extending between the source electrode 138 and the drift region extension 102c. The power device 30 of FIG. 3 is similar to the power device 20 of FIG. 2 , but a plurality of dummy unit cells are formed in the dummy drift region mesa 102d. A dummy shield region (indicated by P+) and a dummy base region (indicated by P) may also be formed in the dummy drift region mesa 102d. As shown, the dummy base region is in electrical contact with the source electrode 138 . The dummy base area and the dummy shielding area may be formed simultaneously with the base and the shielding area in the active unit cell. Depending on the thermal rating of the multi-cell power device, one or more dummy unit cells may be provided to facilitate heat dissipation from each active unit cell.

The power device 40 of FIG. 4 is similar to the power device 30 of FIG. 3 , but a dummy drift region mesa 102d (which may not contribute to forward on-state conduction but preferably supports an equivalent reverse breakdown voltage). ) is capacitively coupled to the source electrode 138 through the field plate insulating layer 125 . In contrast to the width of the dummy drift region mesa 102d of Fig. 3, which should be equal to the width of the drift region mesa 102b of the active unit cell, the width of the dummy drift region mesa 102d of Fig. 4 need not be equal. . The power device 50 of FIG. 5 is similar to the device 20 of FIG. 2 , except that the electrical insulating film 106 on the sidewall of the trench is recessed so that the source electrode 138 and the source, base, and shielding region inside the active unit cell are separated. Enables direct sidewall contact. Establishing such direct sidewall contact reduces the active region of device 50 by reducing or preferably eliminating the condition that the source region must be periodically interrupted in a third direction (not shown) to provide direct contact to the base region. can increase

The power device 60 of FIG. 6 shows a relatively wide active drift region mesa 102b with a centrally located base region 126a and a shield region 128a. The transition region 130a may have the same characteristics as described above for the transition region 130 inside the power devices 10 to 50 of FIGS. 1 to 5 . The power device 70 of FIG. 7 is similar to the device 60 of FIG. 6 , but in FIG. 6 , a centrally located base region 126a and a shielding region 128a are isolated by a centrally located trench 104 . . The power device 10' of FIG. 10 is similar to the power device 10 of FIG. 1, except that the insulated gate electrode 118 on each active mesa 102b is replaced by a pair of short insulated gate electrodes 118a, 118b. have. For a mesa with a width of 2.6 microns, the gate electrodes 118a and 118b may have a length of, for example, 0.3 microns. Using a pair of short gate electrodes instead of one continuous gate electrode extending opposite the full width of transition region 130 results in the gate-to-drain capacitance (C) of device 10'._gd) can be reduced and the high-frequency power gain can be increased. The source electrode 138 also extends into the gap between the gate electrodes 118a and 118b, as shown in FIG. The portion of the source electrode 138 that extends into the gap between the gate electrodes 118a and 118b may have a length of about 0.2 microns. The insulator extending directly between the source electrode 138 and the transition region 130 may be a gate oxide layer and may have a thickness between about 100 Å and about 1000 Å. The sidewall insulator extending between the sidewalls of the gate electrodes 118a and 118b and the source electrode 138 may also have a thickness between about 1000 angstroms and about 5000 angstroms, although other sidewall insulator thicknesses may be used. According to another aspect of this embodiment, the portion of the source electrode 138 extending into the gap between the gate electrodes 118a and 118b is a conductive layer (eg, polysilicon) used to form the gate electrodes 118a and 118b. ) can be formed by patterning. In particular, the third "dummy" The gate electrode 118c may be patterned to extend opposite the transition region 130 . An example of a vertical power device 10" using a dummy gate electrode 118c is shown in FIG. Device 10" of Figure 11 is otherwise similar to device 10' of Figure 10. The electrical contact between the third dummy gate electrode 118c and the source electrode 138 may be formed using a general back-end process technique.

A preferred method of fabricating the vertical power device of FIG. 5 with a 65V product grade will be described. As shown in FIG. 9A , the method includes epitaxially growing a drift region 202 of a first conductivity type (denoted as N) on a heavily doped silicon substrate 200 (eg, an N+ substrate). includes This heavily doped substrate 200 is about 1×10¹⁹cm^-3It may have a greater first conductivity type doping concentration and an initial thickness T of about 500 microns._Scan have The epitaxially growing step is preferably performed while simultaneously doping the drift region 202 with a dopant of the first conductivity type in an inclined manner. Achieving the 65V product grade requires a vertical power device with a true 75V blocking voltage. To achieve this blocking voltage, a trench with a depth of about 4.5 to 5 microns is generally required. To support a trench of this depth, a thickness T of about 6 microns is required._dA gradient doped drift region 202 with Preferably, the drift region 202 having a thickness of about 6 microns includes a uniformly doped region on its upper surface. This uniformly doped region can have a thickness in the range of about 0.5 to 1.0 microns and about 1×10 microns.¹⁶㎝^-3can be doped to a uniform level of The obliquely doped portion of the drift region 202 may have a thickness of 5.0 to 5.5 microns and a 1×10 micron depth of 0.5 to 1.0 microns.¹⁶㎝^-3from a level of at least about 5×10 eg 6.0 microns deep¹⁶㎝^-3It can be doped obliquely to a high concentration level of . The drift region 202 may form an abrupt non-rectifying junction with the substrate 200 .

A general selective etching technique using a first etching mask (not shown) is performed to define several parallel band-shaped trenches 204 in the drift region 202 . Trench 204 having other shapes may also be used. For example, pairs of trenches 204 that are adjacent to each other may represent opposite sidewalls of each ring-shaped trench. Trench 204 is, for example, 5 microns deep D_tcan have Adjacent trenches 204 may define a drift region mesa 202b between them, the width W of each mesa 202b._mis controlled by the spacing between adjacent trenches 204 . Next, as shown in FIG. 9B , a thin thermal oxide film 206 is grown on the sidewalls and bottom of the trench 204 and the upper surface 202a of each mesa 202b. For example, the thin oxide film 206 is wet O₂ It can be grown for 30 minutes at a temperature of 900°C in an atmosphere. This thermal growth step may result in an oxide film 206 that is about 700 Angstroms thick. This thin oxide film 206 is used to improve the interface between the trench 204 sidewalls and the regions subsequently formed inside the trench 204 by removing etch-related defects. The thermal budget associated with this thermal oxide film growth step must be insufficient to significantly change the gradient doping profile in the drift region 202 . However, the doping concentration at the surface 202a of each mesa 202b increases as a result of dopant segregation. A thick conformal oxide film 208 is deposited at a low temperature to form electrically insulated spacers on the sidewalls and bottom of the trench 204 . For a 65V product grade, the total oxide film thickness (thermal oxide film plus deposited oxide film thickness) may be 3000 Angstroms.

Referring now to FIG. 9C , the polysilicon layer 210 may be conformally deposited using a low-temperature CVD process. The thickness of this film should be sufficient to fill the trench 204 . The polysilicon film 210 may be doped in-situ (eg, with phosphorus) to achieve a low sheet resistance of 10 Ω/square. As shown in FIG. 9D , the deposited polysilicon layer 210 is etched back using a conventional etching technique. The duration of this etch step is long enough so that the polysilicon region 210a in the trench 204 is flush with the upper surface 202a of the mesa 202b. This etch-back step may be performed without an etch mask. Referring now to FIG. 9E , a second mask (not shown) capable of selectively removing the oxide film on the mesa 202b but preserving the oxide film in the field oxide region (not shown) that may be located around the drift region 202 . ) to perform the etching step. This second mask may include a photoresist film patterned to define an etch window within the boundaries of an external trench (not shown) surrounding an integrated power device containing the illustrated plurality of power devices as unit cells.

As shown in FIG. 9F, a thin pad oxide film 212 is grown as a blocking oxide film over the exposed upper surface of the mesa 202b. The thin pad oxide layer 212 may have a thickness of about 250 Å. This thin pad oxide film 212 is wet O₂ It can be grown for 10 minutes at a temperature of 900°C in an atmosphere. Next, a first conductivity type transition region dopant 214 is implanted using blanket ion implantation. In particular, the transition region with a retrograded doping profile for the upper surface 202a was subjected to phosphorus (P) dopants at an energy level of 200 keV and 5×10¹²cm^-2Phosphorus can be formed by implantation at a desired dose level. These 200 keV energy levels and 5×10¹²cm^-2Phosphorus dose levels range from about 0.25 to 0.3 microns with a peak implantation depth (N_PID) and about 1.3×10¹⁷cm^-3This can result in an N-type transition region with a phosphorus peak dopant concentration.

Referring to FIG. 9G , after removing the pad oxide layer 212 , a gate oxide layer 216 having a thickness of about 500 Å is formed instead. This gate oxide film 216 is wet O₂ It can be formed by performing a thermal growth step for 20 minutes at a temperature of 900° C. in an atmosphere. A plurality of gate electrodes 218 are defined by depositing a blanket polysilicon film 218 and then patterning using a photoresist mask layer 220 (third mask). A series of self-aligned ion implantation processes are performed. In particular, the shielding region dopant 222 (eg boron) has an energy level of 100 keV and 1×10¹⁴cm^-2A heavily doped second conductivity type self-aligned shielding region may be formed by implanting into the transition region at a phosphorus dose level. After heat treatment, these energy and dose levels will ultimately be about 5×10 at a depth of about 0.3 microns, given an intrinsic diffusion length of about 0.1 microns.¹⁸cm^-3This can result in a shielded region with a phosphorus peak boron concentration. The shielding region 222 is preferably implanted using the gate electrode 218 and the mask layer 220 as an ion implantation mask. Base region dopant 224 (e.g. boron) with an energy level of 50 keV and 3×10¹³cm^-2The second conductivity type self-aligned base region may be formed by implanting into the shielding region at a phosphorous dose level. The peak concentration positions of the shield region dopant 222 and the base region dopant 224 within the mesa 202b are indicated by the letters "+". The peak concentration of the shielding region dopant is 3×10 at a depth of 0.25 to 0.3 microns.¹⁸cm^-3may be the same as This depth preferably coincides with the peak depth of the transition region dopant.

Referring to FIG. 9H , after removing the mask layer 220 , a drive-in step is performed at a temperature of about 1000° C. for about 60 minutes to form a self-aligned base region 226 (indicated by P), self-aligned. A shielding region 228 (indicated by P+) and a transition region 230 (indicated by N) are defined. This drive-in step causing the lateral and downward diffusion of the implanted base, shield and transition region dopants can form the highest thermal cycle within the methods disclosed herein. If the uniform concentration profile and the sloped concentration profile in the drift region are significantly altered during this step, the initial drift region doping profile can be adjusted because of the thermal cycle involved in the drive-in phase. As shown in FIG. 9H, the ion implantation energy and the time and temperature of the drive-in step are dependent on the depth of the PN junction between the P+ shield region 228 and the drift region 202 is the transition region 230 and the drift region 202. ) can be chosen to be approximately equal to the depth of the non-commutating junction between However, other depths may also be used. The depth of the PN junction may be equal to 0.7 microns.

Referring to FIG. 9I , the first conductivity type source region dopant 232 is implanted into the base region 226 using the gate electrode 218 as an ion implantation mask. The source region dopant 232 has an energy level of 40 keV and 2×10¹⁴cm^-2It can be injected at the phosphorus dose level. As shown in FIG. 9J, the N+ source region 233 is defined by driving-in the ion-implanted source region dopant (indicated by the letters "-") at a temperature of 900 DEG C for about 10 minutes. This ion implantation step is performed using the gate electrode 218 and a fourth photoresist mask (not shown) as an ion implantation mask. A fourth photoresist mask may be patterned to define a shot location relative to the P-base region in a third direction relative to the cross-section shown. A plurality of insulated gate electrodes 234 are defined by performing conventional insulator deposition, sidewall spacer formation, and patterning steps. These steps may be performed to define the source region, the P-base region, the polysilicon in the trench and contact windows for the gate electrode. The insulating regions 206/208 lining the trench top sidewalls may also be selectively etched back to expose the sidewalls of the source, base, and shield regions. This etch-back step eliminates the need to define a short to the P-base region using a fourth photoresist mask and thus results in an increase in the forward on-state conduction area for a given horizontal unit cell dimension. As shown in FIG. 9K , a source contact 238 and a gate contact (not shown) may be formed by performing a normal front surface metal deposition and patterning step. As shown, a source contact 238 extends along the upper sidewall of the trench 204, making contact with the exposed portions of the source, base, and shield regions. A drain contact 236 is defined to perform a backside metal step by thinly grinding the backside of the substrate 200 .

A vertical power device according to another embodiment of the present invention provides an improvement over a conventional double diffusion power MOSFET. As shown in FIG. 12 , a unit cell of a conventional double diffusion MOSFET 300 includes a semiconductor substrate 302 having a drift region 304 therein. The upper region 304a of the drift region 304, extending adjacent the upper surface of the substrate 302, can be more heavily doped and has a downwardly sloping vertical doping profile, as shown on the right side of FIG. can have As will be appreciated by those skilled in the art, the upper region 304a of the drift region 304 is referred to as a JFET neck region. The illustrated doping profile shows the dopant concentration of the first conductivity type in the substrate 302 taken along 12A-12A'. The upper region 304a of this drift region 304 is formed by implanting an N-type dopant at a relatively low energy level into the upper surface of the substrate 302 and then annealing the substrate 302 so that the implanted dopant has a peak concentration at the surface. It can be formed by diffusing downward from the The peak concentration is preferably at the surface because the lateral distance between the pair of P-type base regions 314 is smallest at the surface of the substrate 302, which typically results in strong JFET activity. The drift region 304 may be formed by epitaxially growing an in-situ doped semiconductor layer on the heavily doped drain region 306 (eg, an N+ wafer). The drain electrode 308 is formed in ohmic contact with the drain region 306 of the lower surface of the substrate 302 .

MOSFET 300 also includes an insulated gate electrode 318 spaced apart from the top surface of substrate 302 by gate oxide 320 . The insulating gate electrode 318 is also isolated from the adjacent source electrode 310 by the insulating capping layer 322 . The pair of P-type base regions 314 may be formed as band-shaped regions extending in a third direction (not shown) and parallel to the gate electrode 318 . A heavily doped base contact region 312 (denoted as P+) is also formed. As shown, this contact region 312 extends beyond the base region 314 towards the drift region 304 . The base region 314 may be formed by implanting a base region dopant into the substrate 302 using the gate electrode 318 as an ion implantation mask. A thermal treatment step is then performed to at least partially drive-in the implanted base region dopant. After this annealing step, the source region dopant may be implanted into the substrate 302 using the gate electrode 318 again as an ion implantation mask. A short annealing step is performed to drive-in the implanted base region and source region dopants simultaneously. Following this second annealing step, a masking layer is deposited on the substrate 302 and then patterned to have openings therein. Then, a high-concentration dopant of the base contact region is implanted at a relatively high energy level into the center of each base region 314 through the opening. A third anneal is performed to diffuse the base contact region dopant laterally and perpendicular to the substrate 302 . The use of P+ base contact regions 312 may suppress parasitic bipolar transistor operation by reducing the effective base resistance under each source region 316, thereby improving stable-operation-region and ruggedness. U.S. Patent No. 5,879,967 to Kim "Methods of Forming Power Semiconductor Devices Having Latch-UP Inhibiting Additional Power Devices (e.g., MOSFETs, IGBTs) using a buried P-type layer self-aligned to the gate electrode Regions". As with the device of Figure 12, the buried P-type layer in the device disclosed in the '967 patent does not extend laterally beyond the P-base region.

Referring to FIG. 13 , a MOSFET device 400 according to an additional embodiment of the present invention expands laterally and is heavily doped, and when the MOSFET device 400 blocks the reverse voltage, the P-base rich-through effect is sufficiently achieved. and a base shield region 412 , operative to suppress and shield or protect each base region 414 by causing a reverse current to pass through the base shield region 412 instead of the base region 414 . As described in more detail below with reference to FIGS. 14A-14G , this P-base reach-through suppression allows for reduced channel length of device 400 . In particular, the MOSFET device 400 of FIG. 13 is a semiconductor substrate having a drift region 404 of the first conductivity type therein overlying an underlying drain region 406 (indicated by N+) and forming a non-rectifying junction. (402). As shown in FIG. 14A , the drift region 404 may be formed by epitaxially growing a uniformly or non-uniformly doped epitaxial layer on an underlying heavily doped substrate. A first conductivity type transition region 424 is also formed adjacent the top surface 402a of the substrate 402 . The transition region 424 may be formed simultaneously with the step of epitaxially growing the drift region 404 . Instead, the transition region 424 implants a dopant of the first conductivity type at a relatively high energy level into the upper surface 402a of the substrate 402 , which after an appropriate annealing step has It can be formed in such a way that a retrograde doping profile having the highest concentration at depth 1 is obtained. This retrograde doping profile similar to the profile shown in Figure 8a is shown on the right side of Figures 13 and 14a. Before the step of implanting the transition region dopant, a step of forming a masking layer having an opening defining an active region of the substrate 402 may be performed. Instead, a field oxide separation region (not shown) may be formed in an inactive region of the upper surface of the substrate 402 , and the transition region dopant may be implanted using the field oxide separation region as an ion implantation mask.

The MOSFET of FIG. 13 also includes an insulated gate electrode 418 on top surface 402a. Gate electrode 418 is spaced apart from upper surface 402a by gate oxide 420 . The insulating gate electrode 418 is also isolated from the adjacent source electrode 410 by the insulating capping layer 422 . The gate electrode may be patterned into a strip-shaped or serpentine shape, annular (eg, ring or hexagonal) or other similar shape. A second conductivity type (denoted p-type) base region 414 is formed in the substrate 402 and this base region 414 is preferably self-aligned to each end of the insulated gate electrode 418 . This base region 414 extends opposite the insulated gate electrode and supports the inversion layer channel during forward on-state conduction. A source region 416 of a first conductivity type is provided in the base region 416 and may be wide enough to extend into the more heavily doped base shield region 412 . A source region 416 extends laterally below each end of the gate electrode 418 . The lateral distance between the end of each source region 416 and the opposite edge of the transition region 424 defines the channel length of the MOSFET.

Base shield region 412 extends below base region 414 and is transversely wider than base region 414 . As shown in FIG. 13 , the base region 414 is more heavily doped than the base region 414 of the base shield region 412 and the top region of the transition region 424 extending adjacent the top surface 402a A PN junction is formed with each of the opposite sides. The opposing sides of the upper region of the transition region 424 extend laterally towards each other and at a second depth relative to the first surface limit the neck above the transition region 424 to a minimum. This second depth preferably corresponds to the depth at which the dopant concentration in the base shield region 412 is highest. The second depth is preferably approximately equal to the first depth (ie, the depth in the retrograde doping profile of the transition region 424 ). In addition, the combination of the vertical doping profile in the base shield region 412 and the desired retrograde doping profile in the transition region 424 results in complete depletion of the transition region 424 when the power device 400 blocks the maximum reverse voltage. promote Each of the illustrated base, source and base occlusion regions may be, for example, separate band-shaped regions, or may be portions of base, source and base occlusion regions having annular, polygonal or other shapes. These regions are nevertheless seen as distinct regions in cross-section.

The base shielding region 412 may be formed by implanting a base shielding region dopant 412a into the upper surface 402a using the gate electrode 418 as an ion implantation mask. As shown in FIG. 14B , the gate electrode 418 may be formed as a high-conductivity film on the lower gate oxide insulating film 420 . Next, a masking layer is deposited on the high-conductivity film, and then the masking layer is patterned in the shape of a gate electrode to be formed to form a mask 421 . A portion of the high-conductivity film not covered by the mask 421 is etched out by performing an optional etching step. The gate oxide insulating layer 420 may be used as an etch stop layer. Referring to FIG. 14C , about 2×10 using the gate electrode 418 as an ion implantation mask.¹⁴cm^-2 The base shield region dopant 412a is implanted into the substrate 402 at a dose level and an energy level between about 100 keV and about 150 keV. This energy level is high enough to form a peak dopant concentration about 0.3 to 0.5 microns deep below the top surface 402a. An annealing step is then performed to drive-in the implanted base shield region dopant 412a to define the intermediate shield region 412 . Following this annealing step, a base region dopant 414a of the second conductivity type is implanted at a relatively low level into the upper surface 402a of the substrate 402, as shown in FIG. 14D. The annealing step is performed again to drive in the implanted base region dopant vertically and horizontally under the gate electrode 418 and further drive in the already implanted and annealed base shield region dopant 412a. Here, the side length of the base region 414 with respect to the opposite end of the gate electrode 418 is shorter than the side length of the base shielding region 412 . The base occlusion region 414 acts to confine the transition region 424 to a minimum width at a level corresponding to the depth into which the base occlusion region dopant 412a is implanted.

Referring now to FIG. 14E , a source ion implantation mask (not shown) is formed on the substrate 402 . The source ion implantation mask may include an opening exposing the upper surface of the gate electrode 418 and the periphery of the base region 414 . A source region dopant 416a is implanted into the substrate 402 to drive-in to a short annealing step. As shown in FIG. 14F , an electrically insulating film is deposited on the gate electrode 418 and then patterned to define an insulating capping film 422 . As shown in FIG. 14G , a conventional metal step is performed to define a source electrode 410 on the upper surface 402a and a drain electrode 408 on the back surface of the substrate 402 .

A two-dimensional computational simulation was performed for the vertical MOSFET of FIG. 13 . For the unit cell, a gate width of 1.2 microns (in cross-section) and a gate oxide thickness of 40 nm (400 Å) were used. The drift region doping concentration is 1.75×10¹⁶㎝^-3, and the thickness was 2 microns. The depth of the base shielding area was also set at 0.75 microns and the cell pitch was set at 3 microns. The P-base channel length was also set to 0.17 microns. Based on these figures, the breakdown voltage was simulated to be 40 volts, and 0.17 mΩ·cm²low intrinsic on-state resistance (R_sp) was obtained. Intrinsic gate charge Q_t (Vg = 4.5V) is 2.57×10^-7C/cm²and the intrinsic Miller gate charge is 1.1 × 10^-7C/cm²appeared as The figure of merit (FOM) corresponding to these results is 23 × 10⁹(i.e. (R_sp ×Q_t)^-1 = 23×10⁹) was. In contrast, the vertical MOSFET of FIG. 12 was simulated to have a gate width of 2 microns and a gate oxide thickness of 40 nm (400 Å). Drift region doping concentration is 1.5×10¹⁶㎝^-3, and the thickness was 2 microns. The depth of the contact area was set to 1 micron and the cell pitch was set to 4 microns. The P-base channel length was also set to 0.5 microns. Based on these figures, the breakdown voltage was simulated to be 40 volts, and 0.30 mΩ·cm²low intrinsic on-state resistance (R_sp) was obtained. Intrinsic gate charge Q_t (Vg = 4.5V) is 2.8×10^-7C/cm²and the intrinsic Miller gate charge is 1.5 × 10^-7C/cm²appeared as The figure of merit (FOM) corresponding to these results is 12 × 10⁹(i.e. (R_sp ×Q_t)^-1 = 12×10⁹) was.

In the drawings and examples, typical examples of preferred embodiments of the present invention are disclosed, and although specific terms are used, these terms have a general meaning and are used only in a descriptive sense, and the patents described below It is not used for the purpose of limiting the technical spirit of the present invention and the object of the present invention disclosed in the claims.

The power semiconductor device according to the present invention can be used for power switching and power amplification applications because it withstands a high voltage and has improved electrical properties including a fairly linear transfer characteristic when withstand a high voltage.