Enhanced deposition control in fabricating devices in a semiconductor wafer

ENHANCED DEPOSITION CONTROL IN FABRICATING DEVICES IN A SEMICONDUCTOR WAFER in semiconductor wafer fabrication

1A-1C illustrate partial cross-sections of a semiconductor wafer during formation of a silicon nitride layer using enhanced deposition control followed by application of a dielectric layer;

2A-2C show portions of FIG. 1C along with the formation of local interconnects extending through a dielectric layer and a silicon nitride layer;

3 is a diagram illustrating an on-drive current versus an off-current characteristic of an n-channel metal oxide semiconductor field effect transistor;

4 is a diagram illustrating an on-drive current versus an off-current characteristic of a p-channel metal oxide semiconductor field effect transistor;

5 is a diagram showing the on-drive current change according to different stresses in the applied silicon nitride layer.

Fig. 6 is a diagram showing a change in [(transconductance) x (gate length Lg)] according to different gate lengths.

7A-7C illustrate partial cross-sections of a semiconductor wafer during the formation of a silicon nitride layer using enhanced deposition control followed by application of a dielectric layer;

8 is a diagram illustrating a change in gate capacitance according to different gate voltages for an n-channel metal oxide semiconductor field effect transistor in the absence of a silicon nitride layer.

9 is a view showing a partial cross-section of a semiconductor wafer according to Comparative Example 1;

10A to 10C are partial cross-sections of a semiconductor wafer according to Comparative Example 2;

11 is a diagram illustrating an on-drive current versus an off-current characteristic of an n-channel metal oxide semiconductor field effect transistor according to Comparative Example 1;

12 is a diagram illustrating a change in gate capacitance according to different gate voltages for an n-channel metal oxide semiconductor field effect transistor according to Comparative Example 2;

<Explanation of symbols for main parts of the drawing>

1: Silicon substrate

2: Field oxide region

3: gate oxide layer

4: polysilicon layer

5: silicide layer

6: Gate

7: Oxide Spacer

8a: source area

8b: drain region

9: Silicon nitride layer

10: dielectric layer

<background-art><p>BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for controlling enhanced deposition in manufacturing devices in semiconductor wafers.</p><p>A continuing trend in semiconductor technology is to fabricate integrated circuits with more and/or faster semiconductor devices. In accordance with the pursuit of such ultra-high integration, continuous deterioration of device and circuit characteristics is occurring. In this trend, semiconductor device fabrication steps include depositing a silicon nitride layer over a semiconductor wafer to protect the underlying structure.</p><p>Various techniques for depositing silicon nitride layers are known. One of these techniques is disclosed in U.S. Patent No. 6,060,393, in which an oxynitride layer is deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process as an etch stop layer for local wiring. used Another technique is disclosed in US Pat. No. 5,997,757, in which a silicon nitride layer is deposited using a Low-Pressure Chemical Vapor Deposition (LPCVD) process for 1 hour.</p></background-art><tech><p>It is one object of the present invention to provide a method for controlling the enhanced deposition of conventional silicon nitride layers over time and/or improving the electron mobility within the underlying structure.</p></tech>

<p>In accordance with the present invention, there is provided a method comprising the steps of: forming at least one device in a substrate of a semiconductor wafer;⁴ A method for controlling enhanced deposition is provided which includes depositing a silicon nitride layer over a wafer in a reactor under pressure on the order of Pa.</p><p>Objects, features and advantages other than the foregoing objects, features and advantages will become apparent from the following more specific description of embodiments of the invention illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Some emphasis is placed on the accompanying drawings to explain the principles of the present invention and do not reflect actual scale ratios.</p><p>The following process steps and structures do not represent a complete process flow for fabricating integrated circuits in semiconductor wafers. The present invention can be practiced with integrated circuit manufacturing techniques used in the art, and only processes commonly performed to the extent necessary for an understanding of the present invention are included. BRIEF DESCRIPTION OF THE DRAWINGS The drawings showing partial cross-sections of the device during manufacture are not drawn to scale but are shown to illustrate the features of the present invention.</p><p>[Example]</p><p>In accordance with one embodiment of the present invention, an enhanced deposition process used to fabricate a bilayer dielectric in a manner that enhances the performance of an underlying device or devices is provided. This double-layer dielectric comprises a silicon nitride layer 9 and a dielectric layer 10 overlying it (see Fig. 1c). For example, this double layer dielectric includes a thick dielectric layer 10 over a thin silicon nitride layer 9 . According to embodiments of the present invention, the deposition pressure is monitored and controlled upon deposition of the silicon nitride layer 9, at least about 10⁴maintained at about Pa.</p><p>1A shows a partial cross-section of a semiconductor wafer prior to forming a double-layer dielectric comprising a silicon nitride layer 9 . As shown, this part comprises a silicon substrate 1 on which one or more elements are formed. A field oxide region 2 used to isolate devices is formed in the substrate 1 . This part also includes a gate 6 which is part of a metal oxide semiconductor field effect transistor (MOSFET) having a source region 8a and a drain region 8b formed in the substrate 1 . As shown, a gate 6 is formed on the gate oxide layer 3, below which a channel is formed between the source and drain regions 8a and 8b. The gate oxide layer 3 is formed on the substrate 1 . In one embodiment, the gate oxide layer 3 is 2 nm thick silicon oxynitride (SiO2)._XN_Y) is the membrane of The gate 6 comprises a layer 4 of polycrystalline silicon (hereinafter referred to as polysilicon). In this embodiment, the polysilicon layer 4 is on the order of 150 nm thick, and the gate 6 also optionally includes a conductive silicide layer 5 formed on the polysilicon layer 4 . Also, in this embodiment, the gate 6 has a gate length Lg of 0.1 mu m. The gate length Lg is the dimension of the gate 6 measured in the direction in which the source and drain regions 8a and 8b are separated from each other across the channel. For example, silicon dioxide (SiO₂Oxide spacers 7 of ) are formed on the wall or vertical side of the gate 6 .</p><p>The material of the polysilicon layer 4 and the silicide layer 5 is demonstrated. For an n-channel MOSFET (NMOSFET), the polysilicon layer 4 is doped with dopants of an n-type conductor such as phosphorus and arsenic. For a p-channel MOSFET (PMOSFET), the polysilicon layer 4 is doped with a p-type dopant, such as boron. The doping ions are activated by rapid thermal annealing at 1000° C. for 10 seconds. The material of the silicide layer 5 is cobalt silicide (CoSi).₂) and nickel silicide (NiSi₂) is included. A silicide layer 5 is also formed on the source and drain regions 8a and 8b. That is, the upper surface of the gate 6 and the surfaces of the source and drain regions 8a and 8b are formed of the silicide layer 5 .</p><p>1B shows one embodiment of a cross-section of a portion of a semiconductor wafer upon deposition of a silicon nitride layer 9 . Silicon nitride layer 9 is silicon nitride (Si_XN_Y), including dielectric materials or materials. In this embodiment, a silicon nitride layer 9 is deposited within the reactor chamber and is schematically indicated by a broken line and reference numeral 40 . A silicon nitride layer 9 is deposited over the entire surface of the semiconductor wafer by an LPCVD process. The thickness of the silicon nitride layer 9 is about 50 nm. In the deposition process in the reactor chamber 40, silane (SiH₄) and ammonia (NH₃) is applied into the chamber 40 . nitrogen molecule (N₂) is used as the carrier gas. nitrogen molecule (N₂), other inert gases such as helium (He), argon (Ar), etc. may be used as the carrier gas. Ammonia (NH₃) is the flow rate of silane (SiH₄) is maintained to be greater than the flow rate. Ammonia (NH₃) flow rate versus silane (SiH₄) the ratio of flow rates does not significantly exceed 100 and it is appropriate to vary approximately from this value by about +30% or about -20%. In one embodiment, silane (SiH₄) The flow rate is suitable in the range of 30 sccm to 50 sccm. Ammonia (NH₃) The flow rate is suitable in the range of 2000sccm to 4000sccm. nitrogen molecule (N₂) The flow rate is suitable in the range of 2000 sccm to 7000 sccm. According to this embodiment, a silicon nitride deposition layer 9 over the gate 6 and spacers 7 provides conformal step coverage. The pressure in the reactor chamber 40 is about 4 x 10⁴Step coverage is improved when held at Pa. According to embodiments of the present invention, the pressure in the reactor chamber 40 is about 1 x 10⁴Pa to 6 x 10⁴Pa is suitable. Under these pressure conditions, the deposition rate exceeds 50 nm/min, so that a 50 nm-thick silicon nitride layer 9 is deposited within 1 minute. Within the reactor chamber 40, the temperature is in the range of 600°C to 800°C.</p><p>Conventional LPCVD processes have tended to maintain deposition pressures in the range of 30 Pa to 50 Pa ("VLSI TECHNOLOGY" 2nd Edition by SM Sze, published by McGraw-Hill Book Company, 1998). This pressure is 1 x 10 according to embodiments of the present invention.⁴Pa to 6 x 10⁴It is much smaller than the pressure range of Pa. The pressure range of embodiments of the present invention is 10 of the deposition pressure used by conventional LPCVD processes.² to 10³it's a boat</p><p>Referring to FIG. 1C , after deposition of the silicon nitride layer 9 , a dielectric layer 10 is deposited over the silicon nitride layer 9 . Dielectric layer 10 may be formed of any suitable dielectric material or materials (borophosphosilicate glass (BPSG), or hydrogen silsesquioxane, methyl silsesquioxane, methyl ray methylated hydrogen silsesquioxane, or fluorinated silsesquioxane). Dielectric layer 10 may be formed to any suitable thickness using, for example, any suitable technique depending upon the material or materials used above. In this embodiment, the dielectric layer 10 of the BPSG is formed to a thickness of approximately 500 nm via deposition using a plasma enhanced chemical vapor deposition (PECVD) process followed by planarization using a chemical mechanical polishing (CMP) process. BPSG layer 10 is silicon dioxide (SiO)₂), about 4 wt % boron, and 4 wt % phosphorus. The temperature during this PECVD process is about 400° C., which is lower than the temperature in the range of 600° C. to 800° C. for LPCVD for silicon nitride layer 9 deposition. This temperature difference between the two deposition processes effectively maintains the tensile stress created in the silicon nitride layer 9 . Due to the high temperature for the deposition of the silicon nitride layer 9 and the low temperature for the deposition of the dielectric layer 10 , the tensile stress of the silicon nitride layer 9 is maintained. It will be appreciated that the dielectric layer 10 functions to maintain the tensile stress created in the silicon nitride layer 9 .</p><p>The tensile stress maintained in the silicon nitride layer 9 affects the underlying structure. Before further explaining the tensile stress in the silicon nitride layer 9, a local wiring forming process using the silicon nitride layer 9 as an etch stop layer will be described with reference to Figs. 2A, 2B and 2C.</p><p>In Figure 2a, dielectric layer 10 was planarized using a CMP process. A patterned resist mask 11 formed with etching openings 12 is coated on top of the dielectric layer 10 . The dielectric layer 10 exposed by the patterned resist mask 11 is dry etched in a reactive ion etching (RIE) etcher. Select portions of the dielectric layer 10 are removed from below the etch opening 12 . In the RIE Etcher, octafluorobutene (C₄F₈), argon (Ar) and oxygen (O₂) containing feed gas is used. The etching process is stopped at the silicon nitride layer 9 .</p><p>In Figure 2b, the selected portion of the silicon nitride layer 9 is freon (CHF).₃) is dry etched from below the etch opening 12 in the same RIE etcher using a fresh feed gas containing A contact hole 12a is formed through the dielectric layer 10 and the silicon nitride layer 9 . The underlying silicide layer 5 of cobalt silicide is not damaged during the etching process, thus protecting the underlying structure including the source and drain regions 8a and 8b. In this etching, selectivity, that is, the ratio between [etch rate of silicon nitride layer 9] and [etch rate of cobalt silicide layer 5] exceeds 50.</p><p>In FIG. 2C , one or more conductive materials comprising tungsten (W) are deposited to form contact plugs 13 in etched contact holes 12a created through dielectric layer 10 and silicon nitride layer 9 . . The contact plug 13 is electrically connected to the metal region 14 formed on the dielectric layer 10 . In this embodiment, a contact hole 12a is created and a contact plug 13 is deposited to electrically connect with the source and drain regions 8a and 8b, respectively. In another embodiment of the present invention, a contact hole is created through the dielectric layer 10 and the silicon nitride layer 9 to expose the silicide layer 5 of the gate 6, in which a contact plug is deposited to the gate. (6) is electrically connected.</p><p>In order to evaluate the performance of the NMOSFET manufactured according to the above embodiment of the present invention (see Figs. 1a - 1c and 2a - 2c), two comparative examples, namely the first and second comparative examples, are presented. Referring to Fig. 9, a first comparative example will be described. A second comparative example will be described later with reference to FIGS. 10A - 10C.</p><p>Referring to Fig. 9, a first comparative example is described.</p><p>9 shows a partial cross-section of a semiconductor wafer having a silicon nitride layer 107 and a dielectric layer 108 prepared for a local wiring process. This part includes a silicon substrate 101 . This portion also includes a gate 105 that is part of an NMOSFET having a source region and a drain region (not shown) formed in a substrate 101 . The gate 105 includes a polysilicon layer 103 formed on a gate oxide layer 102 formed on a substrate 101 . The gate 105 also includes a conductive silicide 104 formed on top of the polysilicon layer 103 . Oxide spacers 106 are added to the walls or vertical surfaces of the gate 105 .</p><p>Silane (SiH₄), nitric oxide (N₂O) and nitrogen (N₂), a silicon nitride layer 107 is deposited on the wafer to a thickness of about 50 nm at approximately 480° C. in a plasma enhanced chemical vapor deposition (PECVD) system. The dielectric layer 108 is a conformal layer of tetraethlorthosilicate (TEOS). The exposed top surface of the dielectric layer 108 is planarized using a CMP process.</p><p>Although not shown, a patterned resist mask having etch openings is formed on the top surface of the dielectric layer 108 . A local interconnect is formed using damascene technology, and the materials of the dielectric layer 108 and silicon nitride layer 107 are removed from below the etch opening using a plasma etch process. A glue layer 110 and a plug 111 are deposited in the etch opening 109 created through the dielectric layer 108 and the silicon nitride layer 107 to make electrical connection with the underlying structure.</p><p>A second comparative example is described with reference to Figs. 10A to 10C.</p><p>10A shows a partial cross-section of a semiconductor wafer having a silicon nitride layer 207 and a dielectric layer 208 prepared for a local wiring process. This part includes a silicon substrate 201 . This portion also includes a gate 203 that is part of a MOS, each having source/drain regions 206 formed in a substrate 201 . The source/drain region 206 has an LDD structure. The gate 203 includes a tungsten polysilicide layer formed on a gate oxide layer 202 formed on a substrate 201 . Gate 203 also includes an offset oxide 204 formed on top of tungsten polysilicide. Oxide spacers 205 are added to the walls or vertical surfaces of gate 203 . The offset oxide 204 of each gate 203 is silicon dioxide (SiO2).₂) is a membrane made of Oxide spacer 205 is silicon dioxide (SiO)₂) is made of</p><p>Ammonia (NH3) and silane (SiH4) or dichlorosilane (SiH)₂Cl₂), a silicon nitride layer 207 is deposited over the wafer to a thickness of about 50 nm at a temperature ranging from 750° C. to 800° C. by a low pressure chemical vapor deposition (LPCVD) process. nitrogen molecule (N₂) is used as the carrier gas. The pressure ranges from 10 Pa to 100 Pa. The time required to deposit silicon nitride to a thickness of 50 nm using the LPCVD process is about 1 hour. The dielectric layer 208 is silicon dioxide (SiO2).₂) is a conformal layer. The exposed top surface of the dielectric layer 208 is planarized using a CMP process.</p><p>In FIG. 10B , a patterned resist mask having etch openings 210 is formed on top of dielectric layer 208 . The material of the dielectric layer 208 is removed from below the etch opening 210 using a plasma etch process. During this etching process, the silicon nitride layer 207 protects the underlying structure.</p><p>In FIG. 10C , the material of the silicon nitride layer 207 is removed from below the etch opening 210 using a plasma etching process. A plug 211 is deposited in the etch opening 210a created through the dielectric layer 208 and the silicon nitride layer 207 to electrically connect to the underlying structure.</p><p>Variations in performance of NMOSFETs having silicon nitride layers made of different deposition techniques are evaluated for Comparative Example 1, Comparative Example 2, and Examples of the present invention.</p><p>First, the performance of the NMOSFET having the silicon nitride layer 107 according to the first comparative example is evaluated. As described above, a silicon nitride layer 107 is deposited over the NMOSFET at a temperature of about 480[deg.] C. using a PECVD process. 11 shows the on-drive current (I) in the NMOSFET according to Comparative Example 1 as well as the NMOSFET not covered by the silicon nitride layer._On) versus off current (I_off) is summarized by showing In FIG. 11, black circles indicate experimental data for the NMOSFET according to Comparative Example 1, and white circles indicate experimental data for NMOSFETs not covered with silicon nitride. These experimental data are obtained by measuring the on-drive current and the off-current. The on current was measured under the conditions (gate voltage Vg = 0V, drain voltage Vd = 1.5V, and source voltage Vs = 0V). 11 shows experimental data for different gate lengths (Lg). Ten different gate lengths were selected. Some of these were chosen to investigate the on-current fluctuations for a gate length (Lg) range of 0.08 µm to 0.2 µm, while others showed on-current fluctuations with other gate lengths (Lg) outside of 0.2 µm and exceeding this range. was chosen to investigate. In FIG. 11 , the experimental data indicated by white circles clearly shows the tendency of the on current to increase as the gate length Lg decreases. As long as the gate length Lg is not less than a specific value, the same on-current increase trend appears from the experimental data indicated by black circles. However, when the gate length Lg becomes less than or equal to this specific value, another increasing tendency of the on current appears. It was confirmed that this specific value was 0.3 mu m. Over a gate length Lg of 0.3 μm or less, having the same gate length, the NMOSFET according to Comparative Example 1 has an on current lower than that of the NMOSFET without the silicon nitride layer. This means that the NMOSFET according to Comparative Example 1 exhibits inferior performance over a gate length smaller than 0.3 mu m. The inventors of the present application have noticed that such inferior performance arises from a decrease in electron mobility due to compressive stress generated in the deposited silicon nitride layer during the PECVD process according to Comparative Example 1.</p><p>Second, also the performance of the NMOSFET having the silicon nitride layer 207 according to the second comparative example and the performance of the NMOSFET having the silicon nitride layer 9 according to the embodiment of the present invention are evaluated. As described above in the second comparative example of FIG. 10A, a silicon nitride layer 207 was deposited over the NMOSFET to a thickness of about 50 nm at a pressure ranging from 10 Pa to 100 Pa and a temperature ranging from about 750° C. to 800° C. using an LPCVD process. adhered As described above in the embodiment of the present invention, 1×10 using a PECVD process⁴Pa to 6×10⁴A silicon nitride layer 9 is deposited over the NMOSFET at a pressure in the range of Pa and a temperature in the range of about 600°C to 800°C. Similar to FIG. 11, FIG. 3 shows the on-drive current (I) in the NMOSFET of the second comparative example and the NMOSFET according to the embodiment of the present invention._On) versus off current (I_off) to summarize the effect. In FIG. 3 , black squares indicate experimental data for the NMOSFET according to Comparative Example 2, and white squares indicate experimental data for the NMOSFET according to the embodiment of the present invention. 3 and 11, black circles represent the same experimental data for the NMOSFET according to the first comparative example. The experimental data shown in FIGS. 3 and 11 are obtained by measuring the on drive current and the off current in the same manner. In FIG. 3, experimental data indicated by white squares is the on-current (I) of an NMOSFET according to embodiments of the present invention, having the same gate length._On) is the on-current (I) of the NMOSFETs according to the first and second comparative examples._On) is greater than This means that the NMOSFET according to the embodiment of the present invention shows good performance over almost all gate lengths selected for obtaining experimental data. The inventors of the present application note that such good performance according to the embodiment of the present invention arises from the improvement of electron mobility due to the tensile stress generated in the deposited silicon nitride layer in the high-pressure LPCVD process according to the embodiment of the present invention. did.</p><p>It is clearly stated in the preceding description that electron mobility within an NMOSFET depends on the stress generated within the overlapping silicon nitride layer. The stress-dependent mobility of electrons is further explained with reference to FIGS. 5 and 6 . Before giving this explanation, consider a PMOSFET in which holes carry charge. As is well known, the mobility of holes is lower than that of electrons. Also, hole mobility is much less dependent on the stress generated in the overlapping silicon nitride layer than the mobility of electrons. 4 shows off current I_offon-drive current I for_On, which is common to three different PMOSFETs, one of which is the first comparative example, the other is the second comparative example, and the other is an embodiment of the present invention. Thus, there is no or little difference in the on-current for the different PMOSFETs.</p><p>NMOSFET on-drive current I_On depends on the stress generated in the overlapping silicon nitride layers. 5 shows the on-current I_On The relationship between the stress generated in the silicon nitride layer overlapping with The white square is the off current I_off is 5 nA/μm (= 5 x 10^-9A/μm), the on-current I measured under the same conditions as in FIG. 3_Onrepresents the experimental data. Fig. 5 shows an increase trend of the on-current as the tensile stress in the overlapping silicon nitride layer increases. A significant increase in on-current indicates that the tensile stress is approximately 1000 MPa (= 10¹⁰dyn/cm2).</p><p>The increase in the on current in the NMOSFET depends on the gate length Lg. In Fig. 6, the solid line shows the change of [(transconductance) x (gate length Lg)] with different gate length Lg, for an NMOSFET according to an embodiment of the present invention. The thick dashed line shows the change of [(transconductance) x (gate length Lg)] with different gate length Lg for the NMOSFET according to the first comparative example. The normal broken line shows the change of [(transconductance) x (gate length Lg)] with different gate lengths Lg, for the NMOSFET according to the second comparative example.</p><p>6 shows that [(transconductance) x (gate length Lg)] according to an embodiment of the present invention is larger than that of Comparative Example 1 when the gate length Lg is less than a threshold value of 0.6 μm having the same gate length. , which is larger than [(transconductance) x (gate length Lg)] of the second comparative example. This means that the NMOSFET according to the embodiment of the present invention exhibits the best operation when the gate length Lg is less than the threshold value of 0.6 mu m.</p><p>6 also shows that [(transconductance) x (gate length Lg)] according to the embodiment of the present invention is higher than that of Comparative Example 1 when the gate length Lg is greater than a threshold value of 0.6 μm having the same gate length. It is also shown that less is less than [(transconductance) x (gate length Lg)] of the second comparative example.</p><p>The inventors believe that the above-described inversion relationship when passing the threshold of 0.6 mu m is due to the extent to which the stress applied to the edge of the channel affects the electron mobility in the NMOSFET. In accordance with an embodiment of the present invention, a silicon nitride film deposited over the wafer coats the gate top and sides of an NMOSFET having source/drain regions separated by channels under the gate. The deposited silicon nitride layer has a tensile stress, which produces a horizontal force component applied to the edge of the channel to generate a tensile stress and a normal force component to cause the gate opposite the channel to develop a compressive stress. The compressive stress in the channel becomes dominant when the gate length is long. The tensile stress in the channel becomes dominant when the gate length is less than 0.6 μm. The inventor believes that the electron mobility increases as the tensile stress in the channel becomes dominant. When the compressive stress in the channel becomes significant, the electron mobility is limited.</p><p>7A-7C, another embodiment of the present invention is described. This embodiment is substantially the same as the first embodiment shown in Figs. 1a to 1c with respect to the deposition of the silicon nitride layer 27 (see Fig. 7b). The silicon nitride layers 27 (Fig. 7B) and 9 (Fig. 1B) have the same deposition and construction methods, and the silicon nitride layer 27 acts as an etch stop layer in the same manner as the silicon nitride layer 9. .</p><p>7A shows a cross-section of a portion of a semiconductor wafer prior to forming a double-layer dielectric comprising a silicon nitride layer 27 . This part includes a silicon substrate 21 on which one or more elements are formed. This portion also includes a gate 23 , each of which is a portion of a MOS having a source/drain region 26 formed in a substrate 21 . The source/drain region 26 has an LDD structure. The gate 23 comprises a doped tungsten polysilicide layer and is formed on the gate oxide layer 22 formed on the substrate 21 . Gate 23 also includes a cap oxide 24 formed on top of tungsten polysilicide. Oxide spacers 25 are added to the vertical sides or walls of gate 23 .</p><p>7B shows an exemplary cross-section of an enhanced portion of a semiconductor during deposition of a silicon nitride layer 27 . The silicon nitride layer 27 is a thin film silicon nitride approximately 50 nm thick. Silicon nitride layer 27 is ammonia (NH₃) and silane (SiH₄), deposited in the reactor chamber 40 at a temperature ranging from 600° C. to 800° C. by an LPCVD process. nitrogen molecule (N₂) is used as a carrier gas. pressure is 1 x 10⁴Pa to 6 x 10⁴range of Pa. The time required to deposit silicon nitride to a thickness of 50 nm is approximately 1 minute or less.</p><p>Referring to Figure 7c, after depositing the conformal dielectric layer 28 to a thickness of 500 nm, the exposed top surface of the dielectric layer is planarized by a CMP process. The temperature during deposition is approximately 500°C. Although not shown, a patterned resist mask having etching openings is formed on the upper surface of the dielectric layer 28 . The material of the dielectric layer 28 is removed from underneath the etch openings using a dry etch process. In the dry etching process, octafluorobutane (C₄F₈), argon (Ar) and oxygen (O₂) containing feed gas is used. During this etching process, the silicon nitride layer 27 protects the underlying structure. The selectivity, that is, the ratio of (etch rate of dielectric layer 28) to (etch rate of silicon nitride layer 27) is approximately 30. The material of the silicon nitride layer 27 is nitrogen trifluoride (NF).₃) and carbon monoxide (CO) are removed from the bottom of the etching opening in a dry etching process using a feed gas. A contact hole 29 is formed through the dielectric layer 28 and the silicon nitride layer 27 . Although not shown, a plug is deposited in the contact hole to make electrical contact with the underlying structure.</p><p>The silicon nitride layer 9 or 27 deposited according to an embodiment of the present invention is porous and has a sufficiently large number of pores for hydrogen to pass into the underlying structure during hydrogen annealing. The silicon nitride layer 207 (see Figs. 10A to 10C), deposited using the conventional LPCVD process described in accordance with the second comparative example, is agglomerated, resulting in small porosity.</p><p>In a conventional LPCVD process, the doped polysilicon layer of each gate 203 is exposed at a temperature of approximately 750° C. for at least 1 hour until a silicon nitride layer 207 is deposited to a thickness of 50 nm. Due to this long-time exposure to high temperature, the doped impurity portion in the polysilicon layer is deactivated, causing a significant decrease in the concentration of the activated impurity. Reducing the concentration of activated impurities creates a depletion layer in the polysilicon layer of gate 203 . In the deposition process according to the embodiment of the present invention, the exposure time of the polysilicon layer of the gate 6 (see FIG. 1A ) or 23 (see FIG. 7A ) is very short, less than 1 minute. The reduction in the concentration of the activated impurities and thus the generation of the depletion layer in the polysilicon layer is completely or at least suppressed to a satisfactory low level.</p><p>The presence of the depletion layer in the gate affects the operation of NMOSFETs and PMOSFETs formed in semiconductor wafers. 12 shows the change of the gate capacitance Cg with different gate voltages Vg and summarizes the effect thereof. An NMOSFET is considered to have a gate with dimensions of 100 mu m x 100 mu m formed on a 2 nm thick oxynitride layer formed on a silicon substrate. A first test sample was prepared according to the second comparative example with reference to FIGS. 10A to 10C. A second test sample was made without the silicon nitride layer. 8 shows, for a second test sample, the change in gate capacitance Cg with different gate voltages Vg. In FIG. 12 , the dashed line shows the change of the gate capacitance Cg with different gate voltages Vg for the first test sample, and the solid line shows the change of the gate capacitance Cg shown in FIG. 8 . From Fig. 12, it can be seen that there is a significant deviation in the gate capacitance Cg when the gate voltage exceeds 0.5V. This variation is due to the presence of a depletion layer in the gate of the first test sample. A third test sample was prepared using a silicon nitride layer deposition process in accordance with an embodiment of the present invention. 8 shows the change in gate capacitance Cg with different gate voltages Vg for the third test sample. The solid line in FIG. 8 is similar to the solid line in FIG. 12 in that there is no depletion layer in the gate of the third test sample prepared according to an embodiment of the present invention. Therefore, when the gate voltage exceeds 0.5V, there is no undesirable deviation.</p><p>In an embodiment of the present invention, silane (SiH₄) and ammonia (NH₃) is applied to the reactor chamber 40 which deposits the silicon nitride layer 9 . In another embodiment of the present invention, fluorosilane (SiH_XF_4-X) is silane (SiH₄), where x = 0, 1, 2, 3 or 4. In this example, fluorosilane (SiH_XF_4-X) and ammonia (NH₃) is applied into the chamber 40 by the flow. nitrogen molecule (N₂) is used as a carrier gas. nitrogen molecule (N₂), other inert gases such as helium (He) and argon (Ar) may be used as the carrier gas.</p><p>In another embodiment of the present invention, disilane (Si₂H₆) is silane (SiH₄) is used instead. In this case, the deposition temperature should be kept below 600°C. In another embodiment of the present invention, dichlorosilane (SiH₂Cl₂) is silane (SiH₄) is used instead.</p><p>In an embodiment according to the invention, a suitable pressure in the reactor chamber 40 is 1 x 10⁴Pa to 6 x 10⁴range of Pa. Pressures in this range are generally adequate. If a deposition pressure higher than this range is used, the thickness variation of the silicon nitride layer increases, and particles are frequently generated. When the deposition pressure is lower than this range, the deposition rate decreases.</p><p>While the present invention has been specifically described in connection with exemplary embodiments, many alternatives, modifications and variations will become apparent to those skilled in the art by reference to the foregoing description. Accordingly, the appended claims are intended to cover all alternatives, modifications and variations within the scope and spirit of the present invention.</p>

<p>The present invention provides an enhanced deposition control method for the deposition of a conventional silicon nitride layer over time, thereby improving electron mobility in the underlying structure.</p>