Trench semiconductor device having gate oxide layer with multiple thickness and processes of fabricating the same

A trench semiconductor device having a gate oxide layer having a plurality of thicknesses, and a process for manufacturing the same

FIELD OF THE INVENTION The present invention relates to a semiconductor device having a gate electrode inserted in a trench, in particular a structure and method for protecting the device from damage to the gate oxide layer when the device is placed in a high voltage differential during an off state. is about In particular, the present invention relates to a trench MOS field effect transistor.

There is a type of semiconductor device in which a gate electrode is formed in a trench extending from the surface of a semiconductor chip. One example is a trench-gated MOS field effect transistor (MOSFET), and another example is an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), and an accumulation mode field effect transistor (ACCUFET). have. All of these devices share the general properties of a trench structure where, for some reason, the base of the trench can be exposed to a high electric field, or the base of the trench can form a parasitic capacitor comprising a gate electrode and semiconductor material surrounding the trench.

1-10 show the cross-sectional views and characteristics of known trench gated devices. 1 shows a trench gated MOSFET having a top metal layer 102 and a gate 102 formed in the trench 106 and separated from the epitaxial silicon layer 108 by a gate oxide layer 110 ( 100) is shown. MOSFET 100 also includes an N+ source region 112 and a P-body 114 . A drain of the MOSFET 100 includes an N-epi layer 108 and an N+ substrate 116 . Deep P+ region 118 is described in US Patent No. 5,072,266 made under the P-body 114 as proposed for Bulucea et al. The PN junction between the deep P+ region 118 and the N-epi layer 108 forms a voltage-clamping diode 117 in which avalanche breakdown typically occurs. P+ body contact region 119 forms a contact between metal layer 102 and P-body 114 . A gate, typically formed of polysilicon, overlies the gate 104 and is protected from the metal layer 102 by an oxide layer 120 that is patterned into the trench itself, typically not corresponding to a contact mask. .

As shown, the gate oxide layer 110 is composed of a uniform thin oxide layer along three sides of the polysilicon gate 104 . That is, the portions of the gate oxide layer 110 at the sidewall of the trench and the curved and linear portions of the gate oxide layer 110 at the bottom of the trench (related to some pressure in the oxide layer occurring at the bottom of the trench) and excluding etch-related changes) usually have a uniform thickness within the range of, for example, 150 angstroms-1,200 angstroms.

There are several common types of these MOSFETs. For example, FIG. 2 shows a MOSFET 130 that is generally similar to MOSFET 100 but does not include a deep P+ region 118 . The gate of MOSFET 130 protrudes slightly through P-body 132 because the depth of P-body 132 and the depth of trench 134 are determined in two unrelated processes. Therefore, in a vertical device, there is no guarantee that the polysilicon gate will net overlap with the drain region. It has been found that this deformation not only affects the operation of the device, but can also affect its reliability. Also in Figure 2, there is no additional diode formed by the deep P+ region 118 to clamp the voltage, so breakdown can occur whenever the voltage rises to the point where the device becomes avalanche.

The MOSFET 140 shown in FIG. 3 is a modified example of the MOSFET 100 and the MOSFET 130, wherein the MOSFET cell 142 does not have a deep P+ region, but a diode cell 144 having a deep P+ region. ) is distributed at predetermined intervals throughout the array, which acts as a voltage clamp in the MOSFET cell and limits the force of the electric field. In MOSFET 140, the gate oxide layer is of uniform thickness.

4A-4G illustrate various aspects of breakdown. 4A shows a contour line of electric field strength at breakdown of a trench gated device 150 having a relatively thick gate oxide layer. Device 150 is effectively a gated diode and is the most trench gated structural element of the vertical axis power supply MOSFET. As pointed out, the strongest electric field for collision ionization during avalanche breakdown lies at the junction just below the P+ body region. In contrast, device 160 shown in FIG. 4B is a relatively thin gate oxide layer. While some ionization continues to occur just below the P+ region, the region of the highest electric field is located right near the corner of the trench. The field plate that induces the breakdown action causes the electric field strength to increase.

4C and 4D show the ionization contours of devices 150 and 160 respectively as devices 150 and 160 enter avalanche breakdown. Then, as shown in Fig. 4C, whether it is a thick gate oxide layer or a thin oxide layer, eventually as shown in Fig. 4D, "deep" It is in avalanche, i.e., then the device causes a lot of current to be charged in the avalanche region, and breakdown begins to occur at the corner of the trench. Even in the case of a thick oxide layer (Figure 4C), where the peak electric field is not at the corner of the trench (Figure 4A), ionization eventually occurs at the trench corner as the drain voltage increases. However, there are many contour lines in Fig. 4D, which shows that the ionization rate is higher where the gate oxide layer is thin.

Figure 4E shows, as shown on the right side, that if a diode clamp containing a deep P+ region is sandwiched, the diode will break at low voltage and no avalanche breakdown will occur at the trench corner. If the resistance of the current path through the diode is low enough, the diode will clamp the maximum voltage of the device. As a result, the voltage will not rise close to the trench corner to the point where avalanche breakdown occurs.

Figure 4F shows the gate oxide thickness (X) for the 20V and 30V devices._0X) is a graph showing the breakdown voltage (BV) as a function of In a 30 volt device, the doping concentration of the epitaxial (epi) layer is less doped. A 30V device would ideally have an avalanche breakdown of about 38 volts. At a device of 20 volts, the epi will be more heavily doped, and the device will ideally have an avalanche breakdown at about 26 or 27 volts. When the gate oxide is thinned from 1,000 Angstroms to several hundred Angstroms, essentially the breakdown voltage is relatively constant or may actually even increase somewhat, as the shape of the gate's field plate actually starts to help the electric field weaken. However, at thicknesses less than a few hundred Angstroms, yield degradation begins to occur.

The region identified as field-plate induced breakdown is outside the point at which the breakdown voltage starts to drop (below 30V for 30V devices epi and below 20V for 20V devices). In this region, yielding occurs near the trench. For a reliable device, it is necessary to add a diode clamp with a lower breakdown than the breakdown in the field plate induction region, as a result of which the diode is destroyed first. As shown in Fig. 4F, if there is a diode having a breakdown voltage, the breakdown phenomenon never occurs in the 30V device near the gate, and therefore the diode has a breakdown voltage too high to protect the 20V device. To protect the 20V device, the breakdown voltage of the diode clamp will have to be below the curve for the 20V device.

4G is a schematic diagram of the devices shown in FIGS. 4A-4D with the gated diode placed in parallel with the MOSFET and the diode voltage clamp shown in parallel with both the MOSFET and the gated diode. The arrangement is designed so that the diode clamp breaks first. A gated diode never "avalanches" before the diode is clamped. As the gate oxide layer gets thinner and thinner, this becomes more and more difficult.

5A and 5B show ionization contours in a device 170 with sharp trench corners and a device 172 with rounded trench corners. Figure 5B shows that if rounding the trench corners reduces the amount of ionization and eventually leads to a sufficiently deep yield of the device, then yielding will continue to occur at the trench corner, and the device is at risk.

6A-6C show contours, equipotential lines and electric field lines of electric field strength in MOSFET 180, respectively. The gate of MOSFET 180 is coupled to the source and body, grounded, and the drain is V_{to D} is biased. From Figure 6B, the drain voltage V_DIt is clearly shown that is separated and is placed across the region. In the left side of Figure 6B, the equipotential lines are squeezed closer to each other, especially around the trench corners, where they are squeezed more tightly. As shown in Figure 6C, this creates electric field lines perpendicular to the equipotential lines. You can understand why high electric fields occur in trench corners and why rounded corners don't solve this problem. There is a fundamental measurement problem in that there is a lower surface area, a so-called electric field terminating over the gated electrode, and thus the electric field lines are clustered at the corners.

6D shows the positive voltage V_GThe MOSFET 180 is shown when power is turned on by applying to the gate. Current flows down the trench sidewalls, which also spreads along the bottom of the trench and enters the region below the mesa at an angle from the trench side. However, in the above process, the current flows through the region with the high electric field as shown by the electric field contour in Fig. 6A. When a high current passes through a region with a high electric field (and when the device is saturated), the carriers of the current collide with atoms in the epi layer and knock off additional carriers by the transfer of momentum. . This, in turn, accelerates, creating additional collisions, creating new electron-hole pairs that further ionize the atoms.

6E shows the ionization contour at MOSFET 180 when in the powered-on state. The ionization contour shown in FIG. 6E differs from that shown in FIG. 4C, for example when device 150 is in a de-energized state. The difference is that the ionization contour approaches the top of all paths around the trench face, even in the upward direction close to the P-body. This has many effects that damage the device. One effect is to create electron-hole pairs around the gate oxide layer that can be very easily accelerated by the high electric field in that region. The electron-hole pairs can actually be trapped in the gate oxide, which can damage the gate oxide layer.

Moreover, this phenomenon is caused by the fact that the region around the side of the trench is doped more heavily than it actually is, so many electron-hole pairs are created, which starts to control the effective doping concentration of the epitaxial layer, so the voltage that can be provided on the device. creates a higher limit on the amount of This is the positive drain voltage (V_D) occurs because electrons move into the substrate in the newly created electron-hole pair, and the holes move into the P-body. The net effect is to control the local charge distribution to keep the charge neutral, since electrons and holes only move at a constant rate. In particular, the perimeter of a reverse biased junction is a known region, such as a depletion region or space charge region, where (in the absence of shock ionization) free charge carriers are absent. A fixed charge lying within the depletion region, i.e. a positive ion on the N-type side of the junction and a negative ion on the P-type side of the junction, crosses the junction and becomes "built-in" create an electric field In the presence of impact ionization, holes drifting across the N-type region increase the fixed positive charge, thereby increasing the electric field and also enhancing the impact ionization process. These excess holes create an epitaxial region, which in this embodiment is an N-type material, and are more heavily doped as they are increased in a fixed magnetic field. The net effect is increased in the electric field where the yield is reduced. This effect is shown in the current-voltage characteristic of Figure 6F, where the drain current (I_D) increases significantly at a constant drain voltage. The drain voltage at which it is generated is equal to the respective gate voltage shown. This problem gets worse as the gate oxide gets thinner.

Another problem with trench devices is related to capacitance. 7A is a schematic diagram of a MOSFET 190 having a gate driven by a current source 192 and a resistive load 194 . A voltage source 196 connected to the source and drain is a voltage (V)_DD) from drain to drain voltage (V_D) to occur. As shown in Figures 7B-7D, time t₁The current source 192 starts supplying a constant current to the gate, V in Figure 7C._GThe voltage on the gate, denoted by , begins to rise proportional to the source. However, this does not immediately reach the threshold, since MOSFET 190 has not yet turned on, so the drain voltage (V_D) does not start to fall. t₂V in_GAs soon as n reaches the threshold, MOSFET 192 saturates and turns on, carrying current. V_Dstarts to drop, electrocapacitance coupling occurs between the drain and gate of MOSFET 192, and the gate voltage (V_G) is stopped. V_Gremains parallel until MOSFET 192 is in a linear region. Then, MOSFET 192 becomes like an on-resistance in a voltage divider, with a small voltage across MOSFET 192 and most of the voltage across resistor 194 (V)._DD) will have

At this point, the electric capacitance coupling effect between the gate and drain is satisfied and V_Gcontinues with a high voltage. The plateau is due to gate-drain overlap capacitance similar to the Miller effect, but this is not a small signal effect. This has a large signaling effect. At this time, the drain current (I_D) also rises continuously, but the progress of the ascent is slow as shown in Fig. 7D.

7E shows the gate (Q_GV as a function of charge on )_Gshows a diagram of where Q_Gis I at time t_GSame as ship, I_Gis a constant. gate voltage (V_G) rises to a certain degree, thereafter remains constant, and then rises again. If there is no feedback capacitance between drain and gate, the voltage will rise linearly, instead the straight line will be stopped by a plateau.

In Figure 7E, the point (V_G1, Q_G1) corresponds to a constant capacitance because C is equal to ΔQ/ΔV. dot (Q_G2 and V_G1), since it gains more charge, it indicates that there is more capacitance at this point. The capacitance in the device is a relatively constant low value (C), as shown in Fig. 7F._ISS), starting at a relatively constant high effective value (C_G(eff)) rises. Because of this effect, the device has an effective capacitance that is higher than a desired capacitance during the switching transition. As a result, the amount of energy lost when turning on the device is large.

As shown in Figure 7G, the input capacitance is the gate-source capacitance (C_GS) and gate-body capacitance (C_GB), any of which has a gate-drain capacitance (C_GD) does not have an amplification effect. Gate-drain capacitance (C_GD) is shown around the trench base and sidewalls in FIG. 7 . In Fig. 7H, a schematic diagram corresponding thereto is shown. although C_GDgo C_GSand C_GBEven if it has the same dimension as , it will be electrically larger (eg, 5 to 10 times or more) because it is amplified during the switching process.

As mentioned above, the rounded lower perimeter helps to limit damage to the gate oxide layer, although not a perfect solution to the problem. 8A-8C show a process for forming a trench having rounded corners. In Figure 8A, small reactive ions 202 etch silicon through holes in mask 200 at the surface. The ions 200 are accelerated by the electric field downward to etch the trenches having essentially straight sidewalls. When the trench reaches a certain depth, the electric field is relieved as shown in Figure 8B. Alternatively, the chemical properties may be changed. At the end of the process, as shown in Figure 8C, the electric field is modified so that the etch ions move in all other directions. Not only is the trench widened, but the bottom is rounded. The process then includes an anisotropic etch that is converted to an isotropic etch. The anisotropy is also affected by polymer formation as a by-product of the etching action on the sidewalls of the trench. If the chemistry removes the polymer as soon as it is formed, the etching can act in a more isotropic manner. If the polymer remains on the sidewalls, only the bottom of the trench is continuously etched.

9A-9D illustrate the steps of creating a mask 210 over the walls of the trench (FIG. 9A), etching the trench 212 (FIG. 9B), forming an oxide layer 214 (FIG. 9C), poly A method is shown that includes filling the trench with a layer of silicon 216 (FIG. 9D), wherein the oxide layer can be removed and regrown to remove the defect (called sacrificial oxidation).

10A-10F show the formation of a trench MOSFET. show a general process for . The process begins with an N-epitaxial layer 220 grown on an N+ substrate 222 . For example, using the process of Figures 9A-9C, a trench 224 filled with polysilicon is formed in the N-epitaxial layer 220 (Figure 10B). The surface may or may not be flat depending on how the surface oxide is made in the process. The P-body 226 is then introduced, which may be introduced prior to the formation of the trench 224 (FIG. 10C). Although both process flows are manufacturable, it is preferred that the trench is formed first because the etch process can affect the doping concentration in the P-body. The surface is then masked and an N+ source region 228 is implanted (FIG. 10D). Optionally, a thin P+ region 230 is implanted into an ohmic contact between the P-body and a later deposited metal layer. A P+ region 230 can be inserted through a hole in the oxide layer 232 that is deposited over the region and then etched to form a contact mask (FIG. 10E). A contact mask may or may not be used to designate the P+ region 232 . Finally, a metal layer 234 is deposited over the surface to contact the N+ source region 228 and the P+ region 230 (FIG. 10F).

In accordance with the present invention, a trench gated semiconductor device is formed having a dielectric layer that separates the gate electrode from the semiconductor material surrounding the trench where the thickness of the dielectric layer is greater than at the base region of the trench. This structure helps to reduce the strength of the electric field close to the bottom of the trench, especially at corners or rounds where the base of the trench transitions to the sidewalls of the trench, reducing the capacitance.

Several processes are used to build this structure. One process includes the following steps: A trench is etched in the semiconductor material. Directional deposition of the dielectric is performed such that the dielectric is preferentially deposited over a horizontal surface, such as the base of the trench. This is done by creating an electric field in a deposition chamber (eg, a chemical vapor deposition or sputtering chamber) to accelerate ions of a charged dielectric towards the semiconductor material. The trench is filled with a conductive material that will create a gate electrode. Subsequent to the directional deposition, any dielectric deposited on the sidewalls of the trench may be removed, and a conventional dielectric layer may be grown on the sidewalls of the trench. In many processes, the dielectric material is silicon dioxide and the conductive material is polysilicon.

In one process, the conductive material is etched back to a level approximately coplanar with the surface of the semiconductor material, and a dielectric is deposited over the top surface of the dielectric material. In the other, after the conductive material is etched back into the trench, the conductive material (eg polysilicon) is oxidized to form an oxide layer. The conductive material may be oxidized to a thickness that the oxide itself is sufficient to insulate the gate electrode, or another conductive material, such as glass, may be deposited over the oxidized conductive material.

As another variation example, a conductive material that creates a gate electrode is deposited in two stages.

Alternatively, a masking material, such as a photoresist, is deposited after preferential deposition of the dielectric material. Masking material is removed at all locations except the trench base, and the trench is etched or dipped to remove dielectric material from the trench sidewalls. A dielectric layer is then formed over the trench sidewalls.

Alternatively, following the directional deposition of the dielectric, a material, such as polysilicon, that can be oxidized to form the dielectric is deposited and etched back until only a portion of the material remains on top of the dielectric at the bottom of the trench. The material is then oxidized to form a thicker dielectric layer at the bottom of the trench.

Another group of alternatives avoid directional deposition of dielectric material. Instead, a material such as polysilicon, which can be oxidized to form a dielectric, is deposited and etched back until only a portion remains at the bottom of the trench.

A process in accordance with the present invention may include self-aligning the trench with a contact point to the upper surface of the mesa between the trenches. "hard" of materials such as silicon nitride. The layer is used as a trench mask. The hard mask remains in place until a dielectric layer is formed over the gate electrode, rather by oxidizing the polysilicon gate. The hardmask is then removed, exposing all of the top surface of the mesa and allowing the metal layer and contacts to be used there.

The process of the present invention may include using spacers in the sidewalls proximate the upper corners of the trenches to prevent shorting between the gate electrode and the semiconductor mesa. After the trench mask is deposited, holes are made in the trench mask to locate the trench, and a "hard" A layer of material is isotropically deposited on the opening of the trench mask. "hard" Material is deposited over the exposed edges of the trench mask. An etch is then performed, followed by exposing the surface of the semiconductor material in the central region of the hole, leaving a series of deposited dielectric at the edges of the trench mask to form sidewall spacers. Then the trench is etched. The dielectric sidewall spacers provide additional insulation between the semiconductor material and the gate electrode formed later in the mesa.

Another group of processes provides a "keyhole" shaped trench, in which a thick dielectric layer extends some distance upwards from the trench sidewalls. After the trench is etched, a relatively thick oxide lining is either grown or deposited on the bottom and sidewalls of the trench. The trenches are filled with polysilicon, and the polysilicon is etched back, leaving only a portion at the bottom of the trenches over the oxide lining. The exposed oxide lining is removed from the sidewalls of the trench. The polysilicon is then partially oxidized by heating to form an oxide layer at the exposed surface, during the same heating process an oxide layer is formed over the sidewalls of the trench. The trench is then oxide etched, which removes the oxide layer formed from polysilicon as well as certain oxide from the sidewalls of the trench. The trench is backfilled with polysilicon to yield a keyhole shaped gate electrode.

In one variation of the above process for forming a keyhole-shaped gate electrode, after an oxide lining is formed at the base and sidewalls of the trench, a significant amount of a masking material, such as a photoresist, is deposited over the oxide lining at the base of the trench. An oxide etch is performed on the oxide lining removed from the trench sidewalls, and masking material is removed at the bottom of the trench. A relatively thin gate oxide layer is grown on the sidewalls of the trench, and the trench is filled with a conductive material, such as polysilicon, to create the gate electrode.

1 is a cross-sectional view of a prior art trench power MOSFET with a deep P+ diode acting as a voltage clamp;

2 is a cross-sectional view of a prior art trench power MOSFET having a planar body-drain junction;

3 is a cross-sectional view of a prior art trench power MOSFET having a voltage clamp distributed among a MOSFET cell having a planar body-drain junction;

4A is a cross-sectional view showing electric field contours in a MOSFET with a thick gate oxide layer;

Fig. 4B is a cross-sectional view showing electric field contours in a MOSFET with a thin gate oxide layer;

4C is a cross-sectional view showing the ionization contours in a MOSFET with a thick gate oxide layer at the beginning of avalanche breakdown;

4D is a cross-sectional view showing the ionization contours in a MOSFET with a thin gate oxide layer at the beginning of avalanche breakdown;

Fig. 4E is a cross-sectional view showing ionization contours in a device with a deep P+ region used as a voltage clamp;

4F is a graph showing the breakdown voltage as a function of gate oxide thickness in MOSFETs fabricated from epitaxial layers with different doping concentrations;

4G is a schematic diagram of a trench power MOSFET with antiparallel diode clamp;

5A is a cross-sectional view showing ionization contours in a trench power MOSFET with rectangular trench corners;

5B is a cross-sectional view showing ionization contours in a trench power MOSFET with rounded trench corners;

6A is a cross-sectional view showing electric field contours in a trench power MOSFET with a planar body-drain junction;

6B is a cross-sectional view showing the equipotential lines in a trench power MOSFET with a planar body-drain junction;

6C is a cross-sectional view showing electric field lines in a trench power MOSFET with a planar body-drain junction;

6D is a cross-sectional view showing the current flow lines in a trench power MOSFET with a planar body-drain junction;

6E is a cross-sectional view showing the ionization contours in a trench power MOSFET when powered on;

6F is a graph showing a family of I-V curves for a power MOSFET at different gate voltages, and how the sustaining voltage is reduced by collision ionization;

7A is a schematic diagram of a gate-charged circuit for a power MOSFET;

7B is a graph showing the application of a stepwise function of a gated drive circuit to a power MOSFET;

7C is a graph showing how the gate voltage and drain voltage change under the conditions of FIG. 7B;

Fig. 7D is a graph showing how the current in the drain changes under the conditions of Fig. 7B;

7E is a graph showing how the gate voltage varies as a function of charge;

7F is a graph showing how the effective input capacitance changes when the power MOSFET is turned on;

7G is a cross-sectional view showing the components of gate capacitance in a trench power MOSFET;

Fig. 7H is an equivalent circuit diagram of a trench MOSFET showing the capacitance between the electrodes;

8A-8C are cross-sectional views showing how a gate trench with rounded corners is formed;

9A-9D are cross-sectional views illustrating the process of etching the gate trench and filling the trench with polysilicon;

10A-10F are cross-sectional views illustrating the process of manufacturing a typical trench power MOSFET;

11A is a cross-sectional view of a trench MOSFET with a thick oxide layer at the bottom of the trench;

11B is a cross-sectional view showing the MOSFET of FIG. 11A with a thick oxide layer made on the semiconductor top surface;

11C is a cross-sectional view of the power MOSFET of FIG. 11A with an oxide layer overlaid on the oxide layer aligned with the walls of the trench;

12 is a schematic flow diagram illustrating the sequence of a number of processes in accordance with the present invention;

13A-13N show a process sequence for making a trench power MOSFET having a thick oxide layer at the bottom of the trench, using directional deposition of the oxide layer, and etching polysilicon to an equivalent extent on top of the semiconductor material;

14A-14F are a continuation of an exchange process in which polysilicon is etched to a lower degree than the surface of the semiconductor material and then oxidized;

15A-15E illustrate an alternative process sequence in which polysilicon is deposited in two stages;

16A-16E illustrate an alternative process in which a small amount of photoresist is used to mask the thick oxide underlying the trench;

17A-17F illustrate a process in which polysilicon is etched to near the base of the trench and then oxidized;

18A-18F illustrate an alternative process in which polysilicon is oxidized;

19A-19L are diagrams of a process for making a trench power MOSFET having an oxide layer for the gate electrode that is self-aligned with the trench wall;

20A-20F is a continuation of the process of making trench gates on the active array portion of the power MOSFET as well as on the gate bus;

21A-21E show the problems that can arise from cutting the thin oxide layer under the nitride;

22A-22C show additional examples of the above problem;

23A-23G illustrate other problems that may arise in the manufacture of power MOSFETs according to the present invention;

24A-24F illustrate the problems that may arise from cutting the hard mask while removing the top oxide layer in a self-aligned device;

25A-25H show the manufacturing process of a power MOSFET with a thick base oxide layer and a nitride-faced spacer;

26A-26B illustrate problems that may arise during the formation of a gate oxide layer in a thick base oxide device;

27A-27D illustrate a method of avoiding the problem shown in FIGS. 267A and 26B;

28-33 illustrate various types of trench power MOSFETs that may be made in accordance with the present invention;

34 is a diagram of a process sequence for making a trench power MOSFET using a common contact mask and making a thick base oxide layer;

35A-35L are cross-sectional views illustrating the process of FIG. 34;

36-39 are cross-sectional views illustrating a trench power MOSFET having a "keyhole" shaped gate electrode;

40A-40L show the sequence of the process for making a MOSFET having a "keyhole" shaped gate electrode;

41A-41F illustrate an alternative process sequence for making a MOSFET having a "keyhole" shaped gate electrode;

Figures 42A-42C show the intensity in a conventional power MOSFET, the power MOSFET with a thick base gate oxide, and the power MOSFET with a keyhole-shaped gate electrode, respectively.

The problem related to the interaction between the gate and drain of a MOSFET can be partially solved by reducing the coupling capacitance between them. In accordance with the present invention, this is done by thickening the gate oxide layer at the bottom of the trench. 11-27 show various structures and sequences for forming a thick gate oxide over the trench base.

11A shows an epitaxial (epi) layer 242 grown over a substrate 240 . A trench 250 is formed in the epi layer 242 . Gate oxide layer 244 aligns the walls of trench 250 , and a thick portion 246 of gate oxide layer 244 is located at the bottom of trench 250 . Trench 250 is filled with polysilicon 248 . Note that there is no oxide layer over the polysilicon 248 . The arrangement of FIG. 11A may be an intermediate structure. An oxide layer may be formed on top of polysilicon 248 at a later stage of the process. Polysilicon 248 is generally doped with a heavy doping concentration. It is also formed as a generally planar top surface, that is, a silicon epi surface by various methods. One way to level the surface is to deposit a polysilicon layer to a greater thickness, and then etch back it. Another method to form a flat surface is to deposit polysilicon to a thickness greater than the amount required to fill the trench, and then a chemical mechanically erodes the surface flat. A flat surface is preferred in order to reduce the height of the steps that may be formed later in the manufacturing process.

11B shows a structure with an oxide layer 252 over a polysilicon layer 248. Since the side edges of the oxide layer 252 do not correspond to the trench 250 walls, the oxide layer 252 is best formed by a masking and etching step. The oxide layer 252 may be deposited (chemical vapor deposition), grown thermally, or a combination of these steps. 11C is a reference document in its entirety as application No. No. 09/296,959 shows the top oxide layer 254 grown as said in 09/296,959, the cross-section of the oxide layer 254 is generally aligned with the walls of the trench 250, and the oxide layer 254 is below the trench 250. expands Accordingly, a polysilicon layer is implanted in trench 250 . 11B and 11C both have a thick gate oxide region 246 at the bottom of the trench.

Figure 12 is a schematic flow diagram of various processes that may be used to fabricate a gate trench in accordance with the present invention. Details of the flow of these processes are shown in Figures 13-20. Figure 12 shows in the form of a block diagram in the form of a trench formed using a photoresist mask or hardmask sequence followed by planarized directional oxide deposition by selective etching, dipback or selective oxidation. Selective oxidation can be used without directional deposition. Finally, the trench is filled with polysilicon using a one- or two-step process.

More specifically, starting from the left side of FIG. 12 , there are two options for forming the trench. In one option shown in Figures 13-18, the trench is formed using a mask that is later removed, and the mask is not useful as a reference for steps in another process. Another option is to use "hard" to form a trench. to use a mask. Application No. No. referenced above. 09/296,959, used as a reference later in the process. This option is generally described in FIGS. 19 and 20 . After the trench is formed, a sacrificial oxide layer is typically grown on the walls of the trench and then removed. An oxide lining can then be formed in the walls of the trench. This step deposits a trench with a uniform oxide layer on its walls, with or without a hardmask on the top surface of the silicon.

What else is called directed dielectric deposition continues, which involves depositing more oxide at the bottom of the trench than at the sidewalls of the trench. Then you have three choices. As shown in FIG. 16, a selective etchback may be performed to remove oxide from the sidewalls of the trench while leaving a thick oxide at the bottom of the trench. 13-15, a "deepback" may be performed to remove the oxide layer from the sidewalls of the trench. Finally, as shown in Figures 17A and 18, a selective oxidation can be performed, in which a polysilicon layer is formed at the bottom of the trench and then oxidized at the bottom of the trench to form additional oxides. Selective oxidation of the polysilicon layer may be performed in lieu of or in addition to directional dielectric deposition.

At this stage of the process, a trench is fabricated with an underlying thick oxide layer. There may or may not be a "hard" mask on the semiconductor top surface. Next, a thin oxide layer is grown in the walls of the trench and the trench is filled with polysilicon. The polysilicon can be deposited as a single layer, or it can be deposited as two layers with an etch back between depositions. Depositing polysilicon in a two-step process involves the "mesa" between the trenches. It may be useful to implant a dopant into the furnace, making a less doped polysilicon layer useful over the surface of the wafer to create diodes, resistors, and other polysilicon devices.

Finally a glass layer is deposited, and a contact gap is formed in the glass layer.

13A-13N show a process using the oxide "deepback" method. The process begins with an epi layer 262 formed over a substrate 260 . A mask layer 264 is formed on the upper surface of the epi layer 262 with a gap in which a trench is formed. The mask layer 264 may be photoresist or other material, and may be formed on top of the oxide layer 262 . As shown in Figure 13A, trench 268 is formed using a common process.

13B, a sacrificial oxide layer 270 is formed on the surface of the trench. As shown in Figure 13C, the sacrificial oxide 270 is removed. The sacrificial oxide 270 may have a thickness of 100 angstroms to 1000 angstroms, and is generally about 300 angstroms thick. It can be produced by heating the structure at 800° C.-1100° C. for 10 minutes to 5 hours while oxidizing the environment. The surroundings may be oxygen or oxygen and hydrogen. If the environment is a compound of oxygen and hydrogen, this reaction produces water vapor, which is "humid" because this will affect the density and growth rate of the oxide. Oxidation should be considered.

Optionally, an oxide lining 272 is created in the walls of the trenches 268 . Lining 272 may have a thickness on the order of 100 Angstroms-600 Angstroms. The lining 272 prevents the deposited oxide from contacting the silicon directly, and it will have a potential to a charged state, particularly the interface between the silicon and the deposited oxide. Adding a clean oxide layer to the walls of the trench provides reduced electrification.

As shown in FIG. 13E , an electric field is applied over the surface of epi layer 262 , and ions in the dielectric are formed by the electric field and directed in the direction of trench 268 . Rather, a plasma-enhanced chemical vapor deposition chamber is used for this process. The electric field accelerates the dielectric ions downward, so that they preferentially deposit on the horizontal surface including the base of the trench 268 . Chemical vapor deposition of oxides involves a gaseous chemical reaction of oxygen with silane, dichlorosilane, or silicon tetrachloride. The source of oxygen is usually nitrous oxide, and silane is usually a silicon source. Plasma-enhanced chemical vapor deposition machines are available from companies such as Novellus Systems and Applied Materials.

Another way to achieve directional deposition is to sputter an oxide film from an anodized target towards the wafer. Since sputtering is a momentum transfer process, deposition occurs in a straight line.

The result of this process is shown in FIG. 13F , where an oxide layer 270 is formed inside and outside the trench 268 . It should be noted that the oxide layer 270 is thicker at the base of the trench 268 than at the sidewalls of the trench 268 . It is thicker on the flat surface of the epi layer 262 . A process other than chemical vapor deposition, such as sputtering, may be used to make the oxide layer 270 .

Layer 270 is formed of a non-oxide material such as phosphorus doped glass or boron phosphide silicon glass. It is also composed of polymers or other materials with low dielectric constant (K) such as polyimide. Air bubbles may be coupled to the layer 270 to reduce the dielectric constant.

In FIG. 13G the oxide layer 270 may be etched back or deep backed to remove portions of the sidewalls of the trench 268 . A bottom portion 274 of the oxide layer 270 remains at the bottom of the trench 268 . 13H, the structure is heated to form a thin oxide layer 2760 on the sidewalls of the trench 268. A polysilicon layer 278 is then deposited to fill the trench 268, which overflow over the upper surface, which is shown in Fig. 13I.

As shown in FIG. 13J , polysilicon layer 278 is etched back until it is approximately coplanar with the surface of epi layer 262 . Next, a portion of the oxide layer 270 at the surface of the epi layer 262 is removed, taking care not to etch too much of the oxide layer 276 at the sidewalls of the trench. The result of this step is shown in Figure 13K. Avoiding removal of oxide layer 276 is best accomplished by having polysilicon layer 278 protruding slightly above oxide layer 276 . In FIG. 13L , the entire top surface of the structure, including the top surface of polysilicon layer 278 , is oxidized to form oxide layer 280 .

As shown in FIG. 13M , a glass layer 282 is overlaid on the surface of the oxide layer 280 , and then the glass layer 282 and the oxide layer 280 are formed to form contact openings in the epi layer 262 . It is patterned and etched into the structure shown in Fig. 13N.

14A-14F show an alternative process flow starting with the structure shown in FIG. 13I. Fig. 14A corresponds to Fig. 14I. As shown in FIG. 14B, polysilicon layer 278 is etched back, and then the top surface of the remainder of polysilicon layer 278 is oxidized to form oxide layer 290, as shown in FIG. 14C. . A glass layer 292 is then deposited over the entire surface of the structure, as shown in Figure 14D. A mask layer 294 is formed on the upper surface of the glass layer 292, and the layers 270 and 292 are etched to form contact openings as shown in FIG. 14F. The mask layer 294 is then removed.

Figures 15A-15F illustrate another alternative process of starting over with the structure shown in Figure 13I. Fig. 15A corresponds to Fig. 13I. Polysilicon layer 278 is etched back to the level inside the trench, as shown in Figure 15B. Next, a second polysilicon layer 300 is deposited over the entire structure, as shown in FIG. 15C. The polysilicon layer 300 is then etched back, and care is taken to ensure that no portion of the oxide layer 276 is exposed at the upper corner of the trench. The resulting structure is shown in Fig. 15D. Next, the oxide layer 270 is removed as shown in FIG. 15E, and an oxide layer 302 is formed overlying the entire surface of the structure. A glass layer 304 is then deposited over the oxide layer 302, creating the structure shown in FIG. 15F.

Figures 16A-16E show an alternative process starting with the structure shown in Figure 13F. Fig. 16A corresponds to Fig. 13F. A layer of photoresist is then formed over the structure, developed, and cleaned in a manner sufficient to wash away the layer of photoresist from the top of the structure, but leave it at the bottom of the trench 268 . This has the advantage that it is difficult to remove the photoresist at the base of the trench 268 . The resulting structure with the remainder of the photoresist layer 310 at the base of the trench 268 is shown in FIG. 16B. An oxide etch is then performed while removing portions 270 of the oxide layer from the sidewalls of the trenches 268 . A thorough rinsing is then performed to remove the photoresist 310, creating the structure shown in FIG. 16C. The structure is then oxidized to form a thin oxide layer 312 on the sidewalls of the trench, which is then filled with a polysilicon layer 314 as shown in Figures 16D and 16E. A two-step polysilicon deposition can be performed as shown in Figs. 15A-15C.

17A-17F show a sequence of another alternative process starting with the structure shown in FIG. 13F. Fig. 17A corresponds to Fig. 13F. 17B, a sacrificial polysilicon layer 320 is deposited. Polysilicon layer 320 is etched back until only a small portion 322 remains at the base of trench 268 . The portion 322 of the polysilicon layer 320 is then oxidized. At low temperatures, polysilicon oxidizes faster than single-crystal silicon, so a low-temperature oxidation process is used (eg 700-950°C). As a result, oxide forms more rapidly in portion 322 than at the sidewalls of trench 268 . The resulting structure is shown in FIG. 17B with an oxide layer 324 at the base of the trench 268 . A portion of oxide layer 270 is removed from the sidewalls of trench 268 as shown in FIG. 17E, and a thin gate oxide layer 326 is formed on the sidewalls of trench 268 as shown in FIG. 17F.

18A-18F show a sequence of another alternative process starting with a structure such as that shown in FIG. 13B. Figure 18A corresponds to Figure 13D, where an oxide lining 272 is formed. Instead of using a directional dielectric deposition as shown in FIG. 13E, a sacrificial polysilicon layer 330 is deposited as shown in FIG. 18B. Polysilicon layer 330 is etched back until only a small portion 332 remains at the bottom of trench 268, as shown in FIG. 18C. The structure is subjected to low temperature oxidation as detailed above, converting the polysilicon portion 332 into an oxide layer 334 as shown in FIG. 18D. Oxide lining 272 is then removed from the sidewalls and top surfaces of the structure as shown in FIG. 18E , and gate oxide 336 grows in the sidewalls of trench 268 . The resulting structure is shown in Fig. 18F.

19A-19I illustrate a process comprising elements of the super self-aligned process described in Application No. 09/296,959 referenced above. The structure is formed in an epi layer 342 grown over a substrate 340 . A thin oxide layer 346 is formed on the surface of the epi layer 342, which is covered by a layer 344 of a hard masking material, such as silicon nitride. Openings are etched in nitride layer 344 and oxide layer 346, as shown in FIG. 19A.

As shown in Figure 19B, trench 348 is etched in epi layer 342 using a common process. A sacrificial oxide layer is formed in the walls of trench 348 (not shown) and removed. As shown in FIG. 19C , an oxide lining 350 is formed in the walls of the trench 348 . As shown in FIG. 19D , a directional deposition of the kind depicted above in connection with FIG. 13E is performed while forming an oxide layer 352 . Oxide layer 352 includes thick portion 284 at the base of trench 348 . 19E and 19F , the oxide layer 352 and a portion of the oxide lining 350 are removed from the sidewalls of the trench 348 . This is done, for example, by dipping the structure in HF acid 170 . A gate oxide layer 356 is then formed, and the trench is filled with a polysilicon layer 358 . These steps are shown in Figures 19G and 19H.

As shown in FIG. 19I , the polysilicon layer 358 is then etched back to an extent above the surface of the thin oxide layer 346 . In FIG. 19J thick oxide layer 352 is removed from above nitride layer 344 along with polysilicon layer 358 protecting thin oxide layer 356 at the edge of trench 348 . As shown in Figure 19K, the structure is annealed to oxidize a portion of the polysilicon layer 358 to form a thick oxide layer 360 in the upper region of the trench. Finally, the nitride layer 344 is removed as shown in FIG. 19L.

20A-20F show a two-state polysilicon process with two trenches, one in the active array and one part of the gate bus. The process begins at the point shown in Figure 19H with a polysilicon layer 388 filling trenches 374A and 374B. A thick oxide layer 384 is formed at the base of trenches 374A and 374B. A silicon nitride layer 374 is superimposed on the surface of the epi layer 372 . The nitride layer 374 is covered by an oxide layer 382 .

Polysilicon layer 388 is etched back as shown in Fig. 20B, and oxide layer 382 is removed. A second polysilicon layer 390 is deposited over the polysilicon layer 388 , and a "hard" layer 392 formed, for example, of nitride or polyimide, is deposited on top of the second polysilicon layer 390 . do. The resulting structure is shown in Fig. 20C.

As shown in Figure 20D, polysilicon layer 390 and hard layer 392 are etched from the active array region (trench 374A) leaving these layers in the region of the gate bus (trench 374B). The structure is heated to oxidize the polysilicon layer 388 in trench 374A creating a thick oxide layer 394 in the upper regions of the trench. At the same time, an oxide layer 396 is formed over the exposed edges of the second polysilicon layer 390 . This structure is shown in Fig. 20E.

Finally, the exposed portions of hard layers 374 and 392 are removed resulting in the arrangement shown in Figure 20F.

21A-21E and 22A-22C illustrate two problems that should be avoided. 21A shows a thin oxide layer 404 and a nitride layer 402 over the top surface of the epi layer and the sacrificial oxide layer 400 along the walls of the trench. As shown in FIG. 21B , in the process of removing the sacrificial oxide layer 400 , a portion of the thin oxide layer 404 is removed under the nitride layer 402 . A solution to this problem is to minimize the overetch time or use as thin an oxide layer 404 as possible on the order of 15-90 Angstroms.

When the gate oxide layer 406 is formed following the formation of the thick oxide layer 408 at the base of the trench, the gate oxide layer 406 may not sufficiently cover the upper corners of the trench as shown in Figure 21C. have. 21D and 21E show the arrangement after the polysilicon layer 412 has been deposited and etched back from the active array region of the device and the thin layer separating the polysilicon layer 412 and the epi layer 412 at the upper corners of the trench. The oxide layer is shown.

22A-22C illustrate another potential problem area. 22A shows the device at the same stage shown in FIG. 19D with a thick oxide layer 352 deposited directionally at the bottom of the trench and forming a thick portion 354 . 22B , in the process of removing oxide from the sidewalls of the trench, a portion of the thin oxide layer 346 is removed from underneath the nitride layer 344 . Then, when the gate oxide layer 356 is grown, the portion of the oxide layer at the upper corner of the trench is very thin, and between the gate and the epi layer this can lead to an oxide starvation and short circuit. This problem is illustrated in Figure 22C. Again the solution is to use plasma etching which minimizes overetching of all oxides or alternatively chemically etches isotropically.

23A illustrates a problem that may arise when polysilicon fills the holes formed under the nitride layer, as shown in FIG. 21E. Portion 420A of polysilicon layer 420 extends out of the trench, forms a short to the later deposited metal layer, and contacts the epi layer. During oxidation, the oxide 422 does not explode the nitride and consume the silicon. Removal of the nitride exposes the gate to shorting of the source metal. 23B shows a variant in which portion 420B is separated from the main polysilicon layer 420 by an oxide. 23C shows the case where a polysilicon layer 420 is formed protruding above the spike 420C, creating the possibility of a short between the gate polysilicon layer 420 and a later deposited metal layer. The polysilicon filling under the nitride again leaves a possible gate-to-source short after oxidation.

23D shows the characteristics of gates I-V of the shorted device. Low resistance means "hard" It is called a paragraph. 23E shows "soft" or diode type short circuit. Unlike hard shorts caused by direct metal contact to the top of the polysilicon gate, diode type shorts can occur within the gate bus region as shown in Fig. 23F. In this failed configuration the N+ region or plume is doped with the P body whenever polysilicon contacts the silicon mesa, making a parasitic diode and MOSFET as schematically shown in Figure 23G.

Figures 24A-24F illustrate the mechanism of a process that causes a diode short as an overetched initial polysilicon layer or a erroneously generated warped trench. In Figure 24A the active cell and gate bus regions are filled with a first layer of N+ doped polysilicon and then etched back to create the structure as shown in Figure 24B. If the etchback of the polysilicon is not uniform, one side of the trench oxide can be exposed as shown in Figure 24C, which is then infiltrated and etched during dipping to remove the oxide on top. In Figure 24D, a second polysilicon layer is deposited and patterned by a mask, leaving the active cell on the left and the gate bus on the right. Although the active cell on the left oxidizes and heals itself after the top oxidation shown in Figure 24E, the polysilicon contacting the silicon in the gate bus region will dope the N+ plume, resulting in a diode type gate short in Figure 24F. Uniform etchback of polysilicon and uniformly shaped trenches avoid this problem.

25A-25H illustrate a process for avoiding these problems by the use of nitride sidewall spacers. The process begins with an epi layer 502 growing on a substrate 500 . A thin oxide layer 504 is grown on the top surface of epi layer 502 and nitride layer 506 (or other "hard" layer) and a second oxide layer 508 is successively over oxide layer 504 . is formed As a result, layers 504, 506, and 508 form oxide-nitride-oxide (ONO) sandwiches well known in the field. The resulting structure is shown in Figure 25A.

As shown in Figure 25B, the opening is etched in the ONP sandwich. A layer of nitride 510 is then deposited on top of the structure, resulting in the arrangement shown in Figure 25C. The nitride layer 510 is anisotropically etched. The anisotropic etch leaves sidewall spacers 512 at the exposed edges of the oxide layer 504 and the nitride layer 506 because the thickness of the vertical plane of the nitride layer 510 is so thick that it approximates the edge of the ONO sandwich. This structure following the removal of the oxide layer 508 is shown in Figure 25D.

As shown in Figure 25E, trench 514 is etched and a typical sacrificial gate layer (not shown) is formed and removed. 25F shows the structure after the directional deposition of an oxide layer 516, which leaves a thick oxide portion 518 at the bottom of the trench 514. This is done after formation of the gate oxide layer 520 . The trench is then filled with a polysilicon layer 522 , which is etched back, taking care not to penetrate the underlying oxide layer 520 . The approximate contact of the silicon with the top region shear polysilicon will be oxidized much later in the process. Also, various oxides will grow under the caps of the nitride sidewalls, such as "bird's beak". This structure is shown in Fig. 25G. The oxide layer 516 is then removed, resulting in the embodiment shown in Figure 25H.

As shown in Figures 26A and 26B, the growth of gate oxide at the sidewalls of the trench can lead to "kinks" at the sidewalls of the trench, as shown by kink 530 in Figure 26B. As shown in Figure 26A, the problem is that the oxide grows uniformly on the exposed sidewalls 532 of the trench. However, due to the geometry of the structure where the thick oxide 534 starts at the bottom of the trench, oxidation does not proceed in a linear fashion. This results in a reduced thickness of the oxide layer in the kink 530 .

A solution to this problem is shown in Figures 27A-27D. 27A shows the structure after thermal growth of oxide lining 540 and directional deposition of oxide layer 54 as depicted above. Lining 540 and layer 542 are removed from the sidewalls of the trench shown in FIG. 27B. The structure is then immersed in HF acid (170). Since the oxide deposited by deposition etches faster than the thermally grown oxide, the structure is shown as FIG. 27C followed by dipping with the top surface of the lining 540 slightly above the top surface of the oxide layer 542. When the gate oxide layer is thermally grown on the sidewalls of the trench, the resulting oxide is of relatively uniform thickness. There is no "kink" on the wall of the trench. 27D shows the arrangement after gate oxide 544 has grown on the sidewalls of the trench. The dotted line represents the original position of the silicon prior to oxidation.

28-33 illustrate various devices that can be fabricated using the principles of the present invention.

28 shows a power MOSFET with a flat bottom P-body region and a recessed N layer at the interface between the epi layer and the substrate. Figure 28 shows a device for coupling a thick trench bottom oxide with contacts extending across the mesa between the trenches, although a contact mask and a non-planar top oxide layer may be useful. FIG. 29 shows a MOSFET similar to that shown in FIG. 28 except that each MOSFET cell contains a deep P+ region as described in US Patent Application No. 5,072,266 to Bulucea et al. The embodiment of Figure 30 has a flat bottom P-body region in the MOSFET, as well as a diode cell containing a deep P+ region used in a voltage clamp MOSFET cell. An arrangement of this kind is shown in Application No. 08/846,688, which is hereby incorporated by reference.

In the device shown in Figure 31, there is no contact between the P-body region and the metal layer over it in each MOSFET cell. Instead, the body contacts in three dimensions, as described in US Pat. No. 5,887,538 to Williams et al., which is incorporated herein by reference. Note that one of the MOSFET cells has a deep P+ region to limit the strength of the electric field at the bottom of the trench. Again, a planarized top oxide layer using self-aligned contacts is preferred but not required.

In the embodiment of Figure 32, the trench extends into the N-buried layer so that only the thick oxide region overlaps the heavily doped buried layer.

The embodiment of Figure 33 is a cumulative mode MOSFET (ACCUFET) as recognized in US Pat. No. 5,856,692 to Williams et al., which is incorporated herein by reference.

34 is a conceptual diagram illustrating a process flow for a trench MOSFET using a conventional contact mask and incorporating a thick trench base oxide. The steps of the process generally include formation of drain and body regions, etching of trenches and formation of gates, implantation of body and source regions, and deposition of contact gaps and metal layers. Boxes with short chamfered corners in FIG. 34 represent preferred steps. Therefore, implantation of deeper body regions or implantation by implantation and diffusion is consistent with this process.

This process is shown in Figures 35A-35L. A trench 552 is formed in the Nepi layer 550 using the oxide layer 554 as a mask. An oxide lining 556 is formed over the walls of the trench 552 (FIG. 35B), and directional oxide deposition is performed as described above, forming an oxide layer 558 having a thick portion 560 at the bottom of the trench (Fig. 35B). 35C). The sidewalls of the trench 552 are then etched 35D and a gate oxide layer is generally thermally grown in the walls of the trench 552 (FIG. 35E).

A polysilicon layer 564 is then deposited to fill trench 552 (FIG. 35F). Polysilicon layer 564 is etched into the trench (FIG. 35G). An oxide layer 566 is deposited on top of the structure and extends down into a trench to the top surface of the polysilicon layer 564 . The oxide layer 566 is then etched back (FIG. 35I), and a P-type impurity, such as boron, is implanted to form a P body region 568 . The upper surface is masked (not shown), and an N-type impurity, such as arsenic or phosphorus, is implanted to form an N+ source region 570 . Another oxide layer 572 is deposited on the top surface and patterned, resulting in the structure shown in FIG. 35L. The contact may be filled by a top metal or alternatively first filled with a planar metal such as tungsten or a barrier metal such as Ti/TiN.

Figures 36-39 illustrate several embodiments in which polysilicon gates appear in the form of "keyholes" in cross-section. The thicker gate oxide extends not only along the bottom of the trench towards the junction between the P body region and the Nepi layer, but also along the sidewalls of the trench. The thickened gate oxide along the sidewalls of the trench helps to weaken the electric field at that junction.

Fig. 36 shows a MOSFET having a P-body region having a flat base and a diode cell coupled at periodic intervals among the MOSFET cells. In a more preferred form of this MOSFET, a keyhole-shaped gate is used. Figure 37 shows an embodiment in which the P-body does not extend to the surface, but instead is contacted in three dimensions. A thin P+ region is shown in the mesa deeper than the N+ source region. 38 shows an embodiment when the trench extends into the N buried layer formed at the interface between the epi layer and the substrate. Fig. 39 shows the three-dimensional contact of the P bodies and the extension of the trench into the N buried layer.

A sequence of processes for forming a device having a keyhole-shaped trench is shown in FIGS. 40A-40L. The process begins with an epi layer 602 growing on a substrate 600 . An oxide layer 604 is formed on the upper surface of the epi layer 602 as shown in FIG. 40A. The oxide layer 604 is patterned and trenches 606 are etched as shown in FIG. 40B. A sacrificial oxide layer (not shown) is formed over the walls of the trench and removed. An oxide lining 608 is then grown over the walls of the trench 606 (as shown in Figure 40C).

40D and 40E, a polysilicon layer 610 is deposited to fill trench 606, which is then etched back to leave a portion 612 at the bottom of the trench. An oxide lining 608 is then etched from the walls of the trench 606 as shown in FIG. 40F. An anisotropic silicon etch is performed, pushing the top surface of the polysilicon portion down below the top surface of the oxide lining 608 as shown in FIG. 40G. A thermal oxidation process is then applied to form an oxide layer 616 over the walls of the trench 606 and an oxide layer 618 at the top surface of the polysilicon portion 612 . The results are shown in FIG. 40H. The oxide layer 618 is then etched away, a portion of the oxide layer 616 is removed in the process, and the structure shown in Fig. 40I is created.

A second polysilicon layer 619 is deposited over the entire structure as shown in FIG. 40J. Polysilicon layer 619 is etched back as shown in FIG. 40K. The upper surface of the polysilicon layer 619 is oxidized as shown in FIG. 40L.

A variant of this process is shown in Figures 41A-41F. After an oxide lining 608 is formed over the walls of the trench as shown in FIG. 40C, a layer of photoresist is applied, developed, and cleaned to leave a portion 630 at the bottom of the trench 606. An oxide lining 608 is etched from the walls of the trench 606 as shown in FIG. 41B, and a portion 630 of the photoresist layer is removed from the bottom of the trench. This results in the structure shown in Figure 41C.

A gate oxide layer 632 grows thermally in the walls of the trench 606, which is filled with a polysilicon layer 634, as shown in Figures 41D and 41E. The polysilicon layer 634 is etched back to the extent of the top surface of the epi layer 602 . Polysilicon layer 634 is thermally oxidized to make the device shown in FIG. 41F.

42A-42C show a comparison of the strength of an electric field along a trench sidewall in a prior art trench device with that in an implementation of the present invention. Fig. 41A shows that in a prior art device the electric field has two sharp apexes that occur at the base of the body-drain junction and the gate electrode, respectively. 42B shows a device with a thick oxide layer at the bottom of the trench. As mentioned, the electric field continues to have a sharp peak at the body-drain junction, but the peak at the base of the gate electrode is somewhat lower than that of the prior art. Finally, Figure 42C shows a device with a keyhole-shaped gate electrode. In this case, the electric field continues to peak at the body-drain junction, and the sharp apex at the base of the gate electrode is removed.

While many embodiments have been described in accordance with the present invention, it will be understood that these embodiments are for illustrative purposes only and do not limit the broad scope or broad principles of the invention.