Method for forming an interlayer insulating film and semiconductor device
Abstract
The present invention relates to a method for forming an interlayer insulating film. This method comprises the steps of forming an underlying insulating film on the formation, TEOS (tetraethoxy silane) and O3using a gas source containing O in a first concentration lower than the concentration required to oxidize3Porous SiO on the underlying insulating film by chemical vapor deposition containing2forming a film. The present invention also relates to another method of forming an interlayer insulating film. This method comprises the steps of forming a base insulating film on the formation, performing Cl (chlorine) plasma treatment on the base insulating film, TEOS (tetraethoxy silane) and O3Porous SiO on the underlying insulating film by chemical vapor deposition using a gas source containing2forming a film.

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17 claims: 9 independent, 8 dependent
- 1TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 제1 농도로 O 3 을 가스원에 함유하는 화학 기상 증착법으로 형성물(object to be formed) 상에 다공성 SiO 2 막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 2형성물 상에 하지 절연막을 형성하는 단계와, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 제1 농도로 O 3 을 가스원에 함유하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO 2 막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 3제1항 또는 제2항에 있어서, 상기 다공성막의 형성 후에, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 제2 농도로 O 3 을 가스원에 함유하는 화학 기상 증착법에 의해 SiO 2 막이 상기 다공성막 상에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 4제3항에 있어서, 상기 다공성 SiO 2 막 상의 상기 SiO 2 막의 형성 후에, 상기 SiO 2 막의 표면이 CMP법으로 연마되어 평탄화되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 5제4항에 있어서, 상기 SiO 2 막의 표면이 CMP법으로 연마되어 평탄화된 후에, 피복 절연막이 상기 표면에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 6형성물에 Cl(염소) 플라즈마 처리를 수행하는 단계와, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 형성물 상에 다공성 SiO 2 막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 7형성물 상에 하지 절연막을 형성하는 단계와, 상기 하지 절연막에 Cl(염소) 플라즈마 처리를 수행하는 단계와, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO 2 막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 8제6항 또는 제7항에 있어서, 상기 다공성 SiO 2 막의 형성 후에, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하는 화학 기상 증착법으로 다공성 SiO 2 막 상에 제1 절연막을 형성하는 단계와, 상기 제1 절연막의 표면을 평탄화하기 위해 상기 표면을 에칭하는 단계 를 더 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 9제8항에 있어서, 상기 제1 절연막의 상기 표면을 평탄화한 후에, 피복 절연막이 상기 제1 절연막 상에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 10TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 농도로 O 3 을 가스원에 함유하는 화학 기상 증착법으로 형성물 상에 다공성 SiO 2 막을 형성하는 단계와, 다마신 트렌치(trench)가 상기 형성물에 도달하도록 상기 다공성 SiO 2 막에 다마신 트렌치를 형성하는 단계와, 상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와, 금속막을 상기 다마신 트렌치에 매립하는 단계와, 상기 금속막 상에 배리어 금속막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 11형성물 상에 하지 절연막을 형성하는 단계와, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하고, TEOS를 산화하는 데에 필요한 농도보다 낮은 농도로 O 3 을 가스원에 함유하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO 2 막을 형성하는 단계와, 다마신 트렌치가 상기 형성물에 도달하도록 상기 하지 절연막과 상기 다공성 SiO 2 막에 다마신 트랜치를 형성하는 단계와, 상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와, 금속막을 상기 다마신 트렌치에 매립하는 단계와, 상기 금속막 상에 배리어 금속막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 12형성물에 Cl(염소) 플라즈마 처리를 수행하는 단계와, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 형성물 상에 다공성 SiO 2 막을 형성하는 단계와, 다마신 트렌치가 상기 형성물에 도달하도록 상기 다공성 SiO 2 막에 다마신 트랜치를 형성하는 단계와, 상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와, 금속막을 상기 다마신 트렌치에 매립하는 단계와, 상기 금속막 상에 배리어 금속막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 13형성물 상에 하지 절연막을 형성하는 단계와, 상기 하지 절연막에 Cl(염소) 플라즈마 처리를 수행하는 단계와, TEOS(테트라에톡시 실란)와 O 3 을 함유하는 가스원을 사용하는 화학 기상 증착법으로 상기 하지 절연막 상에 다공성 SiO 2 막을 형성하는 단계와, 상기 형성물에 도달하도록 다마신 트렌치를 상기 하지 절연막과 상기 다공성 SiO 2 막에 형성하는 단계와, 상기 다마신 트렌치의 측부에 측벽 절연막을 형성하는 단계와, 금속막을 상기 다마신 트렌치에 매립하는 단계와, 상기 금속막 상에 배리어 금속막을 형성하는 단계 를 포함하는 것을 특징으로 하는 층간 절연막 형성 방법.
- 14제10항 내지 제13항중 어느 한항에 있어서, 상기 다마신 트렌치의 형성 후에 상기 다공성 SiO 2 막과 상기 다마신 트렌치의 측부 및 저부 상에 제2 절연막을 형성함으로써 상기 측벽 절연막이 형성되고, 상기 다마신 트렌치의 측부에 형성된 제2절연막의 부분을 남기도록 상기 제2 절연막에 이방성 에칭을 수행하여, 상기 다마신 트렌치의 저부에서 상기 형성물의 표면을 노출시키는 것을 특징으로 하는 층간 절연막 형성 방법.
- 15제10항 내지 제13항중 어느 한항에 있어서, 상기 배리어 금속막의 형성 후에, 피복 절연막이 상기 다공성 SiO 2 막 및 상기 배리어 금속막 상에 형성되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 16제1항, 제2항, 제6항, 제7항, 제10항 내지 제13항중 어느 한항에 있어서, 상기 다공성 SiO 2 막의 형성 후에, H(수소) 플라즈마 처리가 다공성 SiO 2 막에 수행되는 것을 특징으로 하는 층간 절연막 형성 방법.
- 17제1항 내지 제15항중 어느 한항의 방법에 의해 형성된 층간 절연막을 갖는 것을 특징으로 하는 반도체 장치.
Independent claims17
8 paragraphs, as filed
Interlayer insulating film formation method and semiconductor device
1A to 1G are cross-sectional views each showing a method of forming an interlayer insulating film according to a first embodiment of the present invention.
2A to 2L are cross-sectional views each showing a method of forming an interlayer insulating film according to a second embodiment of the present invention.
3A to 3I are cross-sectional views each showing a method of forming an interlayer insulating film according to a third embodiment of the present invention.
4A to 4N are cross-sectional views each showing a method of forming an interlayer insulating film according to a fourth embodiment of the present invention.
<background-art><p>The present invention relates to a method of forming an interlayer insulating film, and more particularly, to a method of forming an interlayer insulating film having a low dielectric constant required for a high-density semiconductor device. The development of high integration in semiconductor devices in recent years has resulted in narrowing of the wiring spacing. As the capacitance between the wirings increases due to the narrowing of the spacing between the wirings, there is a demand for the formation of an interlayer insulating film having a low dielectric constant. </p><p>In recent years, with advances in high integration of LSI devices, wirings have been miniaturized and multi-layered. Also, the capacitance between wirings increased. This increase in capacitance caused a significant decrease in operating speed. Accordingly, there was a strong demand for improvement in this regard. As one of the means of improvement, a method of reducing the capacitance between wirings has been studied. This method is currently used as an interlayer insulating film for SiO<sub>2</sub>An interlayer insulating film having a lower dielectric constant is used. </p><p>Examples of the low dielectric constant interlayer insulating film currently under study include (1) SiOF film and (2) low dielectric constant organic insulating film. These will be described in detail. </p><p>(1)SiOF film</p><p>The SiOF film uses a gas source containing F to form SiO<sub>2</sub>It is formed by substituting a part of the Si-O bond of the Si-F bond. This SiOF film has a relative dielectric constant that monotonically decreases as the concentration of F in the film increases. </p><p>In forming such a SiOF film, several methods have been reported (see page 82 of the February 1996 issue of the monthly "Semiconductor World"). Among these methods, the most promising is SiH<sub>4</sub>, O<sub>2</sub> and SiF<sub>4</sub>This is a method of forming an SiOF film by a high-density plasma enhanced CVD method (HDCVD method) using as a gas source. The relative permittivity of the SiOF film formed by this method is in the range of 3.1 to 4.0 (varies with the concentration of F in the film). This value is based on SiO, which has been conventionally used as an interlayer insulator.<sub>2</sub>is lower than the relative permittivity of 4.0. </p><p>(2) low dielectric constant organic insulating film</p><p>As an insulating material (less than 3.0) having a dielectric constant lower than that of the SiOF film, a low dielectric constant organic insulating film is attracting attention. Table 1 shows some examples of reported low dielectric constant organic insulating films and their respective dielectric constants and thermal decomposition temperatures. </p><p><tables id="1"><img file="KR20000076868A_D0001.tif" /></tables></p><p>However, the SiOF film is disadvantageous in that an increase in the concentration of F in the film leads to a decrease in moisture absorption resistance. The decrease in hygroscopic resistance poses a serious problem because it affects the transistor characteristics and adhesion of the upper barrier metal layer. </p><p>The low dielectric constant organic insulating film has a silicon wafer or SiO<sub>2</sub>It is prone to peeling due to poor contact with the membrane. Moreover, since the thermal decomposition temperature is 400 degreeC, the organic insulating film is disadvantageous in that heat resistance is low. Deterioration of heat resistance causes problems in wafer annealing at high temperatures. </p></background-art><tech><p>SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for forming a low dielectric constant interlayer insulating film having good moisture absorption resistance and heat resistance. Another object of the present invention is to provide a semiconductor device using the above method. </p></tech>
<p>According to the method of the present invention for forming an interlayer insulating film, firstly, porous SiO<sub>2</sub>A film is formed on the object to be formed. This porous SiO<sub>2</sub>The membrane is TEOS (tetraethoxy silane) and O<sub>3</sub>A gas source containing O<sub>3</sub>The concentration of is lower than the concentration required to oxidize TEOS. Therefore, many voids are formed in the film. In other words, in this way, SiO<sub>2</sub>, the membrane is provided with porosity. </p><p>Therefore, porous SiO<sub>2</sub>The membrane is a normal SiO with no porosity.<sub>2</sub>The dielectric constant is lower than that of the membrane. </p><p>Also SiO<sub>2</sub>The membrane is porous SiO<sub>2</sub>formed on the film. O<sub>3</sub>TEOS and O such that the concentration of TEOS is sufficient to oxidize TEOS.<sub>3</sub>SiO by chemical vapor deposition using a gas source containing<sub>2</sub>A film is formed. Therefore, the SiO formed in this way<sub>2</sub>The film is a high-density SiO containing no CH and OH groups.<sub>2</sub>become a barrier </p><p> Therefore, porous SiO<sub>2</sub>SiO formed on the film<sub>2</sub>Since the membrane is dense, porous SiO<sub>2</sub>The penetration of moisture into the film can be prevented, so that an interlayer insulating film having good moisture resistance can be formed. </p><p>Also, these SiO<sub>2</sub>Since the film is mainly made of Si and O, it is expected to exhibit good heat resistance compared to the organic insulating film of the prior art. </p><p>Second, according to the method of the present invention for forming an interlayer insulating film, Cl (chlorine) plasma treatment is performed on the formation. As a result, Cl (chlorine) atoms remain on a part of the surface of the formation. Then porous SiO<sub>2</sub>Membrane is a gas source for TEOS and O<sub>3</sub>It is formed on the formation by a chemical vapor deposition method comprising a. At this time, a part of the surface where Cl (chlorine) atoms remain is SiO<sub>2</sub>The growth of the film is prevented. As a result, many voids in SiO<sub>2</sub>formed on the membrane. In other words, SiO formed in this way<sub>2</sub>The membrane is provided with porosity. </p><p>Therefore, SiO<sub>2</sub>The membrane is a normal SiO with no porosity.<sub>2</sub>The dielectric constant is lower than that of the membrane. </p><p>Also, these SiO<sub>2</sub>Since the film is mainly made of Si and O, it is expected to exhibit good heat resistance compared to the organic insulating film of the prior art. </p><p>Third, according to the method of the present invention for forming an interlayer insulating film, the porous SiO formed on the formation<sub>2</sub>A first insulating film is formed on the film, and the formed product is subjected to Cl (chlorine) plasma treatment. After the first insulating film is etched and planarized, a covering insulating film is formed. </p><p>In other words, the porous SiO<sub>2</sub>It can prevent moisture from penetrating into the membrane. Accordingly, an interlayer insulating film having a flat surface and good moisture absorption and heat resistance can be formed. </p><p>In addition, the porous SiO<sub>2</sub>The film formation method may be applied to a damascene process. According to the damascene process, a Cu (copper) wiring layer having low thermal resistance can be formed. The Cu (copper) wiring layer was formed on the porous SiO<sub>2</sub>By bonding to the film, it is possible to provide a semiconductor device having a small parasitic capacitance of the wiring and a high data processing speed. </p><p>Fourth, according to the method of the present invention for forming an interlayer insulating film, the porous SiO<sub>2</sub>After formation of the film, H (hydrogen) plasma treatment is performed. Therefore, in the Si-O bond on the surface of the void, the dangling bond of Si is replaced by the Si-H bond. </p><p>Therefore, penetration of moisture from the surface of the void is prevented, and an interlayer insulating film having good moisture absorption resistance can be formed. </p><p>(Example)</p><p>Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. </p><p>(Example 1)</p><p>1A to 1G are cross-sectional views each showing a first embodiment of the present invention. </p><p>As shown in FIG. 1A , a BPSG (borophosphosilicate glass) film 102 is formed on a silicon substrate 101 . Next, an aluminum film is formed on the BPSG film 102, and an aluminum wiring layer 103 is formed by patterning the aluminum film. The silicon substrate 101 , the BPSG film 102 , and the aluminum wiring layer 103 formed in this way constitute the formation 104 . </p><p>Next, as shown in Fig. 1b, SiO<sub>2</sub>A film 105 (underlying insulating film) is formed on the formation 104 . SiO<sub>2</sub>Film 105 is SiH<sub>4</sub>and N<sub>2</sub>O is formed by a plasma enhanced CVD method (plasma enhanced chemical vapor deposition method) in which O is used as a gas source, and this SiO<sub>2</sub>The film thickness of the film 105 is 100 nm. </p><p>As shown in Figure 1c, porous SiO<sub>2</sub>The film 106 is SiO<sub>2</sub>It is formed on the film 105 (underlying insulating film). This porous SiO<sub>2</sub>The film 106 is formed by a plasma-enhanced CVD method (plasma-enhanced chemical vapor deposition), and the gas source of the CVD method contains a low concentration of O<sub>3</sub>(O<sub>3</sub> of low concentration) and<sub></sub>O<sub>2</sub>is included. where low concentrations of O<sub>3</sub>is a lower concentration of O than needed to oxidize TEOS.<sub>3</sub>means Specifically, the flow rate of TEOS is 25 sccm and O<sub>2</sub>If the flow rate of is 7.5 slm, 1~2% O<sub>3</sub>this O<sub>2</sub>is included in </p><p>Also flow rate 1-3 slm N<sub>2</sub>(nitrogen) is contained in the gas source. SiO<sub>2</sub>The temperature of the silicon substrate 101 is maintained at 400 DEG C during the formation of the film 106 . </p><p>In general, TEOS and O<sub>3</sub>In the case of the atmospheric CVD method using as a gas source, the formed SiO<sub>2</sub>The following facts were found about the membrane. That is, O from the gas source<sub>3</sub>As the concentration of SiO increases, the oxidation of TEOS becomes fluid.<sub>2</sub>It goes faster on the wafer on which the film is to be formed. Conversely, O<sub>3</sub>If the concentration of TEOS decreases, the oxidation of TEOS is insufficient. So O<sub>3</sub>When the concentration of SiO is low, many CH or OH groups will be formed on the wafer.<sub>2</sub>remains on the membrane. In particular, the underlying film is SiO<sub>2</sub>If it is a film, a low concentration of O<sub>3</sub>SiO with a rough surface by using TEOS and<sub>2</sub>Abnormal growth of the membrane occurs. </p><p>SiO<sub>2</sub>Porous SiO by exploiting the abnormal growth of the film<sub>2</sub>A film 106 is formed, and many voids are formed in the film. </p><p>Next, as shown in Fig. 1d, H (hydrogen) plasma treatment was performed on porous SiO<sub>2</sub>is performed on the membrane 106 . </p><p>This H plasma treatment is 600 sccm H<sub>2</sub>is performed by supplying RF power to the chamber (not shown), and applying RF power to the upper and lower electrodes (not shown) facing each other in the chamber. RF power is applied to the upper electrode at a frequency of 13.56 MHz and a power of 50 W. Meanwhile, the RF power applied to the lower electrode has a frequency of 400 kHz and a power of 400 W. During the H plasma treatment, the pressure in the chamber is 0.1 to 0.2 Torr, and the temperature of the silicon substrate 101 is maintained at 400°C. In addition, the H plasma treatment time is 60 seconds. </p><p>H plasma treatment replaces Si-H bonds for Si-H bonds in Si-O bonds at the surface of the voids. Therefore, the hygroscopicity resistance of the film is improved by making it difficult for the OH group and water to bond to the Si suspension. </p><p>As shown in Figure 1e, SiO<sub>2</sub>The membrane 107 is porous SiO<sub>2</sub>It is formed on the film 106 . SiO<sub>2</sub>A film 107 is formed by atmospheric CVD, and O<sub>2</sub>, O<sub>3</sub> and a gas source containing TEOS is used. At this time, the flow rate of TEOS is 25 sccm, O<sub>2</sub>The flow rate is 7.5 slm. Also O<sub>2</sub>is the flow ratio, O<sub>3</sub>5-6% of , which is sufficient to oxidize TEOS. Therefore, as described above, SiO<sub>2</sub>The film 107 has fluidity. Thus, the SiO formed underneath<sub>2</sub>Even if unevenness is formed on the surface of the film 106, SiO<sub>2</sub>The film 107 is formed to have an almost smooth surface shape, and self-planarization is performed. </p><p>In addition, N of flow ratio 1-3<sub>2</sub>(nitrogen) is contained in the gas source. The temperature of the silicon substrate 101 is SiO<sub>2</sub>It is maintained at 400° C. during the formation of the film 107 . </p><p>Therefore, as shown in Fig. 1f, SiO<sub>2</sub>Porous SiO formed on the film 107 and the convex portion 103a of the aluminum wiring layer<sub>2</sub>The film 106 is polished and planarized by a CMP method (chemical mechanical polishing method). After performing the polishing, SiO formed in the convex portion 103a of the aluminum wiring film<sub>2</sub>A film 105 (underlying insulating film) and SiO<sub>2</sub>Porous SiO formed in the recesses of the membrane 105<sub>2</sub>A film 106 is exposed to the surface. </p><p>Next, as shown in Fig. 1g, SiO<sub>2</sub>SiO in which a film 108 (coating insulating film) is formed on the convex portion 103a of the aluminum wiring layer<sub>2</sub>A film 105 (underlying insulating film) and SiO<sub>2</sub>Porous SiO formed in the recesses of the membrane 105<sub>2</sub>It is formed on the film 106 . This SiO<sub>2</sub>The film 108 is performed by a plasma enhanced CVD method. The gas source used at this time is SiH<sub>4</sub>and N<sub>2</sub>O and SiO<sub>2</sub>The film thickness of the film 108 is 100 nm. </p><p>SiO<sub>2</sub>Film 105 (underlying insulating film), SiO<sub>2</sub>Film 106, SiO<sub>2</sub>The above process of forming the film 108 (coating insulating film) allows the formation 104 to be formed of an interlayer insulating material of low dielectric constant, good heat resistance and moisture absorption resistance. i.e. SiO<sub>2</sub>The film 106 is porous and has a dielectric constant of 2.0-3.0. This value is typical for SiO<sub>2</sub>less than 4.0 of the membrane. In addition, conventional SiO<sub>2</sub>Membrane 108 is porous SiO<sub>2</sub>Since it is formed on the film 106, the moisture<sub>2</sub>Penetration into the membrane 106 can be prevented. </p><p>Also SiO<sub>2</sub>The H plasma treatment for the film 106 was SiO<sub>2</sub>It is possible to improve the moisture absorption resistance of the membrane 106 . </p><p> Also SiO<sub>2</sub>Since the films 105, 106, and 108 are mainly made of Si and O, they have good heat resistance compared to conventional organic insulating films. </p><p>(Second embodiment)</p><p>2A to 2L are cross-sectional views each showing a second embodiment. </p><p>The second embodiment is a case where the first embodiment is applied to the damascene process. </p><p>First, as shown in FIG. 2A , a BPSG (borophosphosilicate glass) film 202 is formed on a silicon substrate 201 . After the aluminum layer is formed on the BPSG film 202, an aluminum wiring layer 203 is formed by patterning the aluminum layer. Next, the silicon substrate 201, the BPSG film 202, and the aluminum wiring layer 203 constitute the formation 204. </p><p>Then, as shown in Fig. 2b, SiO with a thickness of 100 nm<sub>2</sub>A film 205 (underlying insulating film) is formed on the aluminum wiring layer 203 . This SiO<sub>2</sub>Film 205 is SiH<sub>4</sub>and N<sub>2</sub>It is formed by a plasma enhanced CVD method (plasma enhanced chemical vapor deposition method) in which O is used as a gas source. </p><p>Next, as shown in Fig. 2c, SiO with a thickness of 500 nm<sub>2</sub>The film 206 is SiO<sub>2</sub>It is formed on the film 205 (underlying insulating film). This SiO<sub>2</sub>Membrane 206 is a gas source O<sub>2</sub>and low concentrations of O<sub>3</sub> and an atmospheric CVD method (atmospheric chemical vapor deposition method) containing TEOS (tetraethoxy silane). </p><p>where low concentrations of O<sub>3</sub>is a lower concentration of O than needed to oxidize TEOS.<sub>3</sub>means Specifically, the flow rate of TEOS is 25 sccm and O<sub>2</sub>If the flow rate of is 7.5 slm, 1~2% O<sub>3</sub>this O<sub>2</sub>is included in </p><p>As described in Example 1, low concentrations of O<sub>3</sub>As is used, SiO<sub>2</sub>The membrane 206 is provided with porosity. Therefore, many voids in SiO<sub>2</sub>formed on the film 206 . </p><p>Also flow rate 1-3 slm N<sub>2</sub>Please keep in mind that (nitrogen) is contained in the gas source. SiO<sub>2</sub>The temperature of the silicon substrate 201 is maintained at 400 DEG C during the formation of the film 206 . </p><p>Next, as shown in Fig. 2d, H (hydrogen) plasma treatment was performed on porous SiO<sub>2</sub>is performed on the membrane 106 . The process conditions for the H (hydrogen) plasma treatment are the same as those described in the first embodiment. ie 600 sccm H<sub>2</sub>is performed by supplying RF power to the chamber (not shown), and applying RF power to the upper and lower electrodes (not shown) facing each other in the chamber. And RF power is applied to the upper electrode at a frequency of 13.56 MHz and power of 50 W. Meanwhile, the RF power applied to the lower electrode has a frequency of 400 kHz and a power of 400 W. Also, while the H plasma treatment is in progress, the pressure in the chamber is 0.1 to 0.2 Torr, and the temperature of the silicon substrate 201 is maintained at 400°C. In addition, the H plasma treatment time is 60 seconds. </p><p>H plasma treatment replaces Si-H bonds for Si-H bonds in Si-O bonds at the surface of the voids. Therefore, the hygroscopicity resistance of the film is improved by making it difficult for the OH group and water to bond to the Si suspension. </p><p>Then, as shown in Figure 2e, SiO<sub>2</sub>Patterning is performed on the films 205 and 206 so that damascene trenches 207 are SiO<sub>2</sub>The aluminum wiring layer 203 formed under the film 206 is reached. </p><p>As shown in Figure 2f, SiO<sub>2</sub>The film 208 (second insulating film) is SiO<sub>2</sub>It is formed over the membrane 206 and on the sides and bottom of the damascene trench 207 . This SiO<sub>2</sub>The film 208 is formed by a plasma enhanced CVD method, and SiH<sub>4</sub>and N<sub>2</sub>O is used as the gas source. SiO formed on the side of the damascene trench 207<sub>2</sub>Copper SiO, later buried in the damascene trench 207 by the film 208<sub>2</sub>Diffusion to the inside of the film 206 can be prevented. </p><p>As shown in Fig. 2g, the anisotropic etching is<sub>2</sub>It is performed on the film 208 (the second insulating film). Etching the SiO formed at the bottom of the damascene trench 207<sub>2</sub>Remove the film 208, but the SiO formed on the side of the damascene trench 207<sub>2</sub>The film 208 is not removed by this etching. Residual SiO<sub>2</sub>The film 208 constitutes a sidewall insulating film on the side of the damascene trench 207 . </p><p>As shown in Fig. 2H, the Cu (copper) plated film 209 is formed in the damascene trench 207 and the SiO<sub>2</sub>formed on the film 206 . The Cu plating film 209 formed in the damascene trench 207 is used as the Cu wiring. </p><p>Next, as shown in Fig. 2i, SiO<sub>2</sub>The Cu plating film 209 formed on the film 206 is removed by polishing by a CMP method (chemical mechanical polishing method). Accordingly, the Cu plating film remains only in the damascene trench 207 . </p><p>Then, as shown in FIG. 2J , a barrier metal TiN film 210 is formed on the damascene trench 207 . Accordingly, Cu in the damascene trench 207 is later formed on SiO2 in the damascene trench 207 .<sub>2</sub>diffusion into the membrane can be prevented. </p><p>As shown in Fig. 2K, patterning is performed to leave the TiN film 210a formed on the damascene trench 207, and the TiN film 210 formed in the other portion is etched and removed. </p><p>Then, as shown in Fig. 2l, SiO<sub>2</sub>The film 211 (coating insulating film) is SiO<sub>2</sub>It is formed on the film 206 and the TiN film 210a. This SiO<sub>2</sub>Film 211 is SiH<sub>4</sub>and N<sub>2</sub>It is formed by a plasma enhanced CVD method in which O is used as a gas source. </p><p>The process allows the formation 204 to be formed of a low dielectric constant, heat and moisture resistant interlayer insulator. i.e. SiO<sub>2</sub>The film 206 is porous and has a dielectric constant of 2.0-3.0. This value is typical for SiO<sub>2</sub>less than 4.0 of the membrane. In addition, conventional SiO<sub>2</sub>The film 211 (coating insulating film) is porous SiO<sub>2</sub>Since it is formed on the film 206, the moisture<sub>2</sub>penetration into the membrane 206 may be prevented. </p><p>Also SiO<sub>2</sub>The H plasma treatment for the film 206 is SiO<sub>2</sub>The moisture absorption resistance of the film 206 may be improved. </p><p> Also SiO<sub>2</sub>Since the films 206 and 211 are mainly made of Si and O, they have better heat resistance than the conventional organic insulating films. </p><p>(Example 3)</p><p>3A to 3I are cross-sectional views each showing a third embodiment. </p><p>First, as shown in FIG. 3A , a BPSG (borophosphosilicate glass) film 302 is formed on a silicon substrate 301 . After the aluminum layer is formed on the BPSG film 302, an aluminum wiring layer 303 is formed by patterning the aluminum layer. A silicon substrate 301 , a BPSG film 302 , and an aluminum wiring layer 303 constitute a formation 304 . </p><p>Then, as shown in Fig. 3b, SiO<sub>2</sub>A film 305 (underlying insulating film) is formed on the formation 304 . This SiO<sub>2</sub>Film 305 is SiH<sub>4</sub>and N<sub>2</sub>It is formed by plasma-enhanced CVD method (plasma-enhanced chemical vapor deposition) in which O is used as a gas source, and SiO<sub>2</sub>The film thickness of the film 305 is 100 nm. </p><p>Then, as shown in Fig. 3c, Cl (chlorine) plasma treatment was performed on SiO<sub>2</sub>It is performed on the film 305 (underlying insulating film). </p><p>This Cl plasma treatment produced 600 sccm of Cl<sub>2</sub>is performed by supplying RF power to the chamber (not shown), and applying RF power to the upper and lower electrodes (not shown) facing each other in the chamber. RF power is applied to the upper electrode at a frequency of 13.56 MHz and a power of 100 W. Meanwhile, the RF power applied to the lower electrode has a frequency of 400 kHz and a power of 400 W. While the Cl plasma treatment is in progress, the pressure in the chamber is 0.2 Torr, and the temperature of the silicon substrate 301 is maintained at 400°C. </p><p>500 nm thick SiO<sub>2</sub>The film 306 is SiO subjected to Cl (chlorine) plasma treatment.<sub>2</sub>It is formed on the film 305 (underlying insulating film). This SiO<sub>2</sub>Membrane 306 is a gas source O<sub>2</sub>, O<sub>3 </sub>and an atmospheric CVD method (atmospheric chemical vapor deposition method) containing TEOS (tetraethoxy silane). The flow rate of TEOS is 25 sccm and O<sub>2</sub>If the flow rate of is 7.5 slm, 4~6% O<sub>3</sub>this O<sub>2</sub>is included in Also flow rate 1-3 slm N<sub>2</sub>(nitrogen) is contained in the gas source. Also SiO<sub>2</sub>The temperature of the silicon substrate 301 is maintained at 400 DEG C while the film 306 is formed. </p><p>At this time, a part of the surface where Cl (chlorine) atoms remain is SiO<sub>2</sub>The growth of the film 306 is prevented. Therefore, many voids in SiO<sub>2</sub>formed on the film 306 . Accordingly, SiO<sub>2</sub>Many voids are formed in the membrane 306 to provide porosity. </p><p>Then, as shown in Figure 3e, porous SiO<sub>2</sub>The film 306 is subjected to H (hydrogen) plasma treatment. </p><p>The process conditions of the H plasma treatment are the same as in the first and second embodiments. ie 600 sccm H<sub>2</sub>is performed by supplying RF power to the chamber (not shown), and applying RF power to the upper and lower electrodes (not shown) facing each other in the chamber. RF power is applied to the upper electrode at a frequency of 13.56 MHz and a power of 50 W. Meanwhile, the RF power applied to the lower electrode has a frequency of 400 kHz and a power of 400 W. Also, while the H plasma treatment is in progress, the pressure in the chamber is 0.1 to 0.2 Torr, and the temperature of the silicon substrate 101 is maintained at 400°C. In addition, the H plasma treatment time is 60 seconds. </p><p>H plasma treatment replaces Si-H bonds for Si-H bonds in Si-O bonds at the surface of the voids. Therefore, the hygroscopicity resistance of the film is improved by making it difficult for the OH group and water to bond to the Si suspension. </p><p>Then, as shown in Fig. 3f, SiO<sub>2</sub>The membrane 307 is porous SiO<sub>2</sub>It is formed on the film 306 . This SiO<sub>2</sub>The film 307 is formed by a plasma enhanced CVD method. </p><p>Next, as shown in Fig. 3g, SiO with a thickness of 200 nm<sub>2</sub>The film 308 (first insulating film) is SiO<sub>2</sub>It is formed on the film 307 . This SiO<sub>2</sub>The film 308 is formed by atmospheric CVD, and O<sub>2</sub>, O<sub>3</sub> and a gas source containing TEOS is used. At this time, the O of the gas source<sub>3</sub>Since the concentration of SiO is higher than usual, the fluidity is<sub>2</sub>A film 308 is provided. As a result, SiO formed underneath<sub>2</sub>Even if unevenness is formed on the surface of the film 307, SiO<sub>2</sub>The film 308 is formed to have an almost smooth surface shape, and self-planarization is performed. </p><p>In this case, preformed SiO<sub>2</sub>SiO with fluidity by the film 307<sub>2</sub>Film 308 is SiO<sub>2</sub>Penetration into the voids of the membrane 306 can be prevented. </p><p>Then, as shown in Fig. 3h, in order to planarize the surface, SiO<sub>2</sub>Film 307 and SiO<sub>2</sub>Etching is performed on the film 308 (first insulating film). This etch is SiO<sub>2</sub>This should be done so that the film 308 is not completely removed. </p><p>Next, as shown in Fig. 3i, SiO<sub>2</sub>SiO on which the film 309 (coating insulating film) remains<sub>2</sub>Film 307 and SiO<sub>2</sub>It is formed in the film 308 (first insulating film), that is, the portion of the film remaining not removed by etching. This SiO<sub>2</sub>The film 309 is formed by the plasma enhanced CVD method, and the film thickness is 100 nm. </p><p>SiO<sub>2</sub>Film 305 (underlying insulating film), SiO<sub>2</sub>Films 306 and 307, SiO<sub>2</sub>Film 308 (first insulating film) and SiO<sub>2</sub>The above process of forming the film 309 (coating insulating film) allows the formation 304 to be formed of an interlayer insulating material of low dielectric constant, good heat resistance and moisture absorption resistance. i.e. SiO<sub>2</sub>The film 306 is porous and has a dielectric constant of 2.0-3.0. This value is typical for SiO<sub>2</sub>less than 4.0 of the membrane. </p><p>Also SiO<sub>2</sub>The H plasma treatment for the film 306 is SiO<sub>2</sub>The moisture absorption resistance of the membrane 306 may be improved. </p><p>In addition, conventional SiO<sub>2</sub>Membrane 307, 308, 309 is porous SiO<sub>2</sub>Since it is formed on the film 306, the moisture<sub>2</sub>Penetration into the membrane 306 can be prevented. </p><p>Also SiO<sub>2</sub>Since the films 305, 306, 307, 308, and 309 are mainly made of Si and O, they have better heat resistance than the conventional organic insulating films. </p><p>(Example 4)</p><p>The fourth embodiment is a case in which the third embodiment is applied to the damascene process. </p><p>4A to 4N are cross-sectional views each showing a fourth embodiment. </p><p>First, as shown in FIG. 4A , a BPSG (borophosphosilicate glass) film 402 is formed on a silicon substrate 401 . After the aluminum layer is formed on the BPSG film 402, an aluminum wiring layer 403 is formed by patterning the aluminum layer. A silicon substrate 401 , a BPSG film 402 , and an aluminum wiring layer 403 constitute a formation 404 . </p><p>Then, as shown in Fig. 4b, SiO with a thickness of 100 nm<sub>2</sub>A film 405 (underlying insulating film) is formed on the aluminum wiring layer 403 . This SiO<sub>2</sub>Film 405 is SiH<sub>4</sub>and N<sub>2</sub>It is formed by a plasma enhanced CVD method (plasma enhanced chemical vapor deposition method) in which O is used as a gas source, and then Cl (chlorine) plasma treatment is performed on SiO as shown in Fig. 4C.<sub>2</sub>It is performed on the film 405 (underlying insulating film). </p><p>This Cl plasma treatment produced 600 sccm of Cl<sub>2</sub>is performed by supplying RF power to the chamber (not shown), and applying RF power to the upper and lower electrodes (not shown) facing each other in the chamber. RF power is applied to the upper electrode at a frequency of 13.56 MHz and a power of 100 W. Meanwhile, the RF power applied to the lower electrode has a frequency of 400 kHz and a power of 400 W. While the Cl plasma treatment is in progress, the pressure in the chamber is 0.2 Torr, and the temperature of the silicon substrate 401 is maintained at 400°C. </p><p>500 nm thick SiO<sub>2</sub>SiO film 406 subjected to Cl (chlorine) plasma treatment<sub>2</sub>It is formed on the film 405 (underlying insulating film). This SiO<sub>2</sub>Membrane 406 is a gas source O<sub>2</sub>, O<sub>3</sub>and an atmospheric CVD method (atmospheric chemical vapor deposition method) containing TEOS (tetraethoxy silane). The flow rate of TEOS is 25 sccm and O<sub>2</sub>If the flow rate of is 7.5 slm, 4~6% O<sub>3</sub>this O<sub>2</sub>is included in Also flow rate 1-3 slm N<sub>2</sub>(nitrogen) is contained in the gas source. Also SiO<sub>2</sub>The temperature of the silicon substrate 401 is maintained at 400 DEG C while the film 406 is formed. </p><p>At this time, SiO in which Cl (chlorine) atoms remain<sub>2</sub>Part of the surface of the film 405 has SiO<sub>2</sub>The growth of the film 406 is prevented. As a result, many voids in SiO<sub>2</sub>It is formed in the membrane 406 to provide porosity. </p><p>Then, as shown in Figure 4e, porous SiO<sub>2</sub>The film 406 is subjected to H (hydrogen) plasma treatment. </p><p>The process conditions of the H plasma treatment are the same as those of the first and third embodiments. ie 600 sccm H<sub>2</sub>is performed by supplying RF power to the chamber (not shown), and applying RF power to the upper and lower electrodes (not shown) facing each other in the chamber. RF power is applied to the upper electrode at a frequency of 13.56 MHz and a power of 50 W. Meanwhile, the RF power applied to the lower electrode has a frequency of 400 kHz and a power of 400 W. Also, while the H plasma treatment is in progress, the pressure in the chamber is 0.1 to 0.2 Torr, and the temperature of the silicon substrate 101 is maintained at 400°C. In addition, the H plasma treatment time is 60 seconds. </p><p>H plasma treatment replaces Si-H bonds for Si-H bonds in Si-O bonds at the surface of the voids. Therefore, the hygroscopicity resistance of the film is improved by making it difficult for the OH group and water to bond to the Si suspension. </p><p>Then, as shown in Fig. 4f, SiO<sub>2</sub>The membrane 407 is porous SiO<sub>2</sub>It is formed on the film 406 . This SiO<sub>2</sub>The film 407 is formed by a plasma enhanced CVD method, and SiH<sub>4</sub>and N<sub>2</sub>O is used as the gas source. This SiO<sub>2</sub>SiO by film 407<sub>2</sub>Cu of the Cu plating film formed later on the film 407 is porous SiO<sub>2</sub>It is possible to prevent diffusion into the film 406 . </p><p>Then, as shown in Fig. 4g, the patterning<sub>2</sub>Film 405 (underlying insulating film), SiO<sub>2</sub>Films 406 and 407 are performed to form damascene trenches 408 . This damascene trench 408 is SiO<sub>2</sub>The aluminum wiring layer 403 formed under the film 405 is reached. </p><p>Next, as shown in Fig. 4h, SiO<sub>2</sub>The film 409 (second insulating film) is SiO<sub>2</sub>The film 407 and the bottom of the damascene trench 408 are formed. This SiO<sub>2</sub>The film 409 is formed by a plasma enhanced CVD method. SiO formed on the side of the damascene trench 408<sub>2</sub>With the film 409, the Cu later buried in the damascene trench 408 is porous SiO.<sub>2</sub>It is possible to prevent diffusion into the film 406 . </p><p>Next, as shown in Fig. 4i, anisotropic etching is performed on SiO<sub>2</sub>A film 409 (second insulating film) is applied. As a result, SiO2 except for the portion of the side of the damascene trench 408 .<sub>2</sub>The film 409 is removed and a contact hole reaching the aluminum wiring layer 403 is formed in the bottom of the damascene trench 408 . and SiO remaining on the side of the damascene trench 408 .<sub>2</sub>The film 409 constitutes a sidewall insulating film. SiO<sub>2</sub>The film 407 is not removed by etching, and the porous SiO<sub>2</sub>It remains on the film 406 . </p><p>Subsequently, as shown in FIG. 4J, the Cu plating film 410 is formed with the damascene trench 408 and the SiO<sub>2</sub>formed on the film 407 . The Cu plating film 410 formed in the damascene trench 408 is used as the Cu wiring layer. </p><p>Next, as shown in Fig. 4k, SiO<sub>2</sub>The Cu plating film 410 formed on the film 407 is polished and removed by the CMP method. As a result, the Cu plating film 410 remains only in the damascene trench 408 . </p><p>Then, as shown in FIG. 4L, a barrier metal TiN film 411 is formed on the damascene trench 408. As shown in FIG. As a result, the Cu in the damascene trench 408 is later formed on the SiO2 on the damascene trench 408 .<sub>2</sub>It can prevent diffusion into the membrane. </p><p>As shown in Fig. 4M, patterning is performed to leave the TiN film 411a formed on the damascene trench 408, and the TiN film 411 formed in the other portion is etched away. </p><p>Then, as shown in Fig. 4n, SiO<sub>2</sub>The film 412 (coating insulating film) is SiO<sub>2</sub>It is formed on the film 407 and the TiN film 411a. This SiO<sub>2</sub>Film 412 is SiH<sub>4</sub>and N<sub>2</sub>It is formed by a plasma enhanced CVD method in which O is used as a gas source. The process allows the formation 404 to be formed of a low dielectric constant, heat and moisture resistant interlayer insulator. i.e. SiO<sub>2</sub>The film 406 is porous and has a dielectric constant of 2.0-3.0. This value is typical for SiO<sub>2</sub>less than 4.0 of the membrane. </p><p>Also SiO<sub>2</sub>The H plasma treatment for the film 406 is SiO<sub>2</sub>The moisture absorption resistance of the membrane 406 may be improved. </p><p>In addition, conventional SiO<sub>2</sub>Film 407 and SiO<sub>2</sub>The film 412 (coating insulating film) is porous SiO<sub>2</sub>Since it is formed on the film 406, SiO<sub>2</sub>It is possible to prevent moisture from penetrating into the membrane 406 . </p><p>Also SiO<sub>2</sub>Since the films 406, 407, and 412 are mainly made of Si and O, they have better heat resistance than the conventional organic insulating films. </p>
<p>As described above, according to the present invention, it is possible to form a low dielectric constant interlayer insulating film having good moisture absorption resistance and heat resistance.</p>
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Every citation, both ways
| Document | Relation | Office | Cited during |
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| US7972941B2 | Cited by | United States of America | Applicant |
13 members in 6 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 9972245 | Japan | – | |
| 7224599 | Japan | A | |
| 2000009419 | Japan | A |
Members13
| Document | Office | Kind | |
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| EP1037276A1 | European Patent Office (EPO) | A1 | |
| JP2000332011A | Japan | A | |
| KR20000076868AThis record | Republic of Korea | A | |
| EP1213759A1 | European Patent Office (EPO) | A1 | |
| KR20020072259A | Republic of Korea | A | |
| US6524972B1 | United States of America | B1 | |
| KR100390322B1 | Republic of Korea | B1 | |
| TW552639B | Taiwan Province of China | B | |
| EP1037276B1 | European Patent Office (EPO) | B1 | |
| DE60005875D1 | Germany | D1 | |
| KR100430114B1 | Republic of Korea | B1 | |
| DE60005875T2 | Germany | T2 | |
| JP3827056B2 | Japan | B2 |
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Numbers
- Publication
- 2000-0076868
- Application
- 100013124
Titles4
- Korean
- 층간 절연막 형성 방법 및 반도체 장치
- English
- Interlayer insulating film forming method and semiconductor device
- Unlabeled
- 층간 절연막 형성 방법 및 반도체 장치{METHOD FOR FORMING AN INTERLAYER INSULATING FILM, AND SEMICONDUCTOR DEVICE}
- Unlabeled
- Interlayer insulating film formation method and semiconductor device
Classification
- CPC, 22
- C23C16/04
- H10W20/037
- C23C16/402
- Y10S438/96
- H10P14/6922
- H10P14/665
- H10P14/6682
- H10P14/6686
- H10P14/69215
- H10P14/6506
- H10P14/6334
- H10P14/6514
- H10P14/6548
- H10P14/6336
- H10W20/071
- H10W20/096
- H10W20/092
- H10W20/076
- H10W20/075
- H10W20/077
- H10W20/072
- H10W20/46
- IPC, 5
- H10P14 24
- C23C16 04
- C23C16 40
- H01L23 522
- H10P14 692