Packet deconstruction/reconstruction and link-control

PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL

BACKGROUND This specification relates generally to packet processing in electronic devices, systems, and methods, and more specifically to packet teardown/reconfiguration and link-control.

Memory devices are typically provided as internal, semiconductor, integrated circuits and/or externally removable devices in computers, personal digital assistants (PDAs), digital cameras, and cell phones, among a variety of other electronic devices. Random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and flash memory, among others There are many different types of memories, including

A system may include a host, host system memory, and a number of peripheral devices such as memory devices. The host may have one or more multiple processors, a host controller, a host controller memory located on the host controller, and control circuitry including multiple internal memory devices. The host may communicate with the peripheral devices to receive data from the devices to the host system or to transmit data from the host system to the peripheral devices in the peripheral devices. Commands controlling the reception and/or transmission of data may be issued by the host system.

Data may be communicated, eg, transmitted and/or received, using a flow of packets between the host and one or more peripheral devices. Such packets may be generated by a transport layer protocol, eg, a communication/transport layer protocol understood by both the host and one or more peripheral devices. The generation of such transport layer packets may be independent of how the packets are communicated. When a host and a specific peripheral device are directly connected, data flow packets generated by the transport layer protocol can be directly transferred between the host and a specific peripheral device. However, when more than one peripheral device is connected to a common physical connection, the link-control layer may be used to provide flow control for simultaneous data transfer between the host and peripheral devices.

1 is a block diagram of a computing system in accordance with one or more embodiments herein; 2 is a block diagram of a computing system in accordance with one or more embodiments herein. 3A is a block diagram of an architecture for a layered interface in accordance with one or more embodiments herein; 3B is a block diagram of multiple packets in a layered architecture in accordance with one or more embodiments herein.

This specification includes methods, apparatus, and systems for packet processing. One embodiment of a method for packet processing comprises decomposing a transport layer packet into a plurality of link-control layer packets each having an associated sequence number, and multiple link-controlling via a common physical connection for a plurality of peripheral devices. It includes forwarding layer packets and limiting a number of significant link-control layer devices in forwarding.

DETAILED DESCRIPTION In the following detailed description of the specification, reference is made to the accompanying drawings, which form a part hereof, in which by way of example is shown how one or more embodiments of the disclosure may be practiced. While these embodiments have been described in sufficient detail to enable any person skilled in the art to practice the embodiments herein, it is understood that other embodiments may be utilized and that process, electrical, and/or mechanical changes may be made without departing from the scope of the specification. you have to understand The identifier "N", particularly used with reference to reference numerals in the drawings, indicates that a number of the specific features indicated may be included in one or more embodiments of the present disclosure. Identifiers may refer to the same or different numbers of specific features.

A number indicated in the drawings is a number or numbers in front correspond to a reference number, and numbers after that indicate a component or component in the drawing. Similar components or components between different figures may be identified using like numbers. For example, 110 may be referred to as "10" in FIG. 1 , and similar components may be referred to as 210 in FIG. 2 . As will be appreciated, components shown in the various embodiments herein may be added, exchanged, and/or removed to provide numerous additional embodiments of the disclosure. Also, as can be understood, the relative scales and proportions of components provided in the drawings are intended to illustrate the embodiments of the present specification and should not be construed in a limiting sense.

1 is a block diagram of a system 100 in accordance with one or more embodiments herein. 1 , a host 110 is shown. In one or more embodiments, the host may be a computing device, such as a personal computer, among other computing device types. One example of host 110 includes, among other examples, laptop computers, personal computers, mobile phones, digital cameras, digital recording and playback devices, PDAs, memory card readers, and interface hubs.

The host 110 of FIG. 1 includes a host control circuit 102, among other host components not shown. Host control circuitry 102 may include one or more processors, host controllers, and/or host memory. In one or more embodiments, host control circuit 102 passes information between multiple peripheral devices 120 - 1 , 120 - 2 , ..., 120 -N and another device, such as host 110 . can be used to Those skilled in the art will understand that "processor" means one or more processors, such as a parallel processing system, multiple coprocessors, and the like.

Host 110 may include a transport layer, eg, a communication/transport layer, link-control layer, and/or physical layer that may be associated with host control circuitry. The host control circuit 102 may be coupled to the peripheral devices 120-1, 120-2, ..., 120-N. In some embodiments, host control circuitry 102 may manage transport, link, and physical layer activity without processor intervention and also manage instruction re-execution without processor intervention. Those skilled in the art will appreciate that the transport layer may be analogous to the transaction layer as tolerated by various standards.

In one or more embodiments, the host control circuitry 102 may be coupled to a standardized interface. For example, the host control circuit 102 may be coupled to an interface operated according to the Universal Flash Storage (UFS) standard, among other interfaces. In general, the host control circuit 102 controls, addresses, and data between the peripheral devices 120-1, 120-2, ..., 120-N, the host 110, and/or other devices. and other signals.

In one or more embodiments, the peripheral devices 120 - 1 , 120 - 2 , ... , 120-N provide information from the host 110 to the peripheral devices 120 - 1 , 120 - 2 , ..., 120-N. Peripheral device control circuitry 104-1, 104-2, ..., 104-N, which may be used to facilitate operations such as read, write, and/or erase commands to memory devices, among other operations communicated. may include. One or more peripheral devices may comprise and/or include an RF transceiver 108 connected to control circuitry, eg, control circuitry 104-N. Although only peripheral device 120 -N having an RF transceiver 108 is shown in FIG. 1 , embodiments do not limit the number of peripheral devices that may include such a transceiver. The RF transceiver 108 may transmit and/or receive data to and/or from a wireless device (not shown). For example, the RF transceiver 108 may receive a transport layer packet from a wireless device.

The peripheral devices 120 - 1 , 120 - 2 , ..., 120 -N may share a common physical connection 105 with the host 110 . The common physical connection 105 may include upstream and/or downstream connections between the host 110 and the peripheral devices 120-1, 120-2, ..., 120-N. For example, the peripheral devices 120 - 1 , 120 - 2 , ..., 120 -N may be coupled to the host 110 in a chain structure, for example, tied together. In some embodiments, one or more peripheral devices, eg, peripheral device 120 -N, may be removed from the chain. In one or more embodiments, the peripheral device control circuits 104-1, 104-2, ..., 104-N include the host 110 and the peripheral devices 120-1, 120-2, ..., 120-N. A transformation layer can be provided in between. Therefore, the peripheral device control circuitry can selectively couple the peripheral device's I/O connector (not shown in Figure 1) to receive the appropriate signal at the appropriate I/O connection at the right time. Similarly, the communication protocol between the host 110 and the peripheral devices 120-1, 120-2, , 120-N is accessed by the peripheral devices 120-1, 120-2, , 120-N. may be different from what is required. Thereafter, the peripheral device control circuits 104-1, 104-2, ..., 104-N convert the command sequence received from the host 110 into an appropriate command sequence, so that the peripheral devices 120-1, 120-2 , ..., 120-N) to achieve a given access. Each transformation may further include a change in signal voltage levels as well as a command sequence.

As used herein, in one or more embodiments, chained peripherals (eg, 120-1, 120-2, ..., 120-N) connect to a common physical connection, such as a shared interface port of a host. Peripheral devices communicatively coupled to a host (eg, host 110 ) via (eg, via the same interface port of host control circuitry 102 ) may be represented. A specific host interface port may include a data input port and a data output port. Accordingly, data may be transferred between the host 110 and the chained peripheral devices 120-1, 120-2, ..., 120-N via the same single interface port of the host 110. The use of specific ports on the host or peripheral devices is described in more detail with respect to FIG. 2 .

The embodiments of Figure 1 may include additional circuitry not shown so as not to obscure the embodiments herein. For example, in one or more embodiments in which peripheral devices 120-1, 120-2, ..., 120-N are memory devices, the memory devices have an address provided to the I/O connectors via I/O circuitry. It may include an address circuit that latches the signals. Address signals may be received and decoded by a row decoder and a column decoder to access memory devices. Those skilled in the art will understand that the number of address input connectors depends on the density and architecture of the memory devices. Further, in one or more embodiments, the host and/or peripheral device may include one or more cache lines for storing data and/or arranging incoming data prior to processing, for example, among other operations.

2 is a block diagram of a system 200 in accordance with one or more embodiments herein. System 200 includes a chain of peripheral devices, eg, memory devices, in accordance with one or more embodiments herein. Although memory devices are used as examples, other types of peripheral devices or combinations of peripheral devices are also within the scope of this disclosure. Examples of other peripheral devices include, but are not limited to, printers, scanners, cameras, wireless communication peripherals such as Bluetooth or WiFi devices, external hard drives, solid state drives, flash drives, etc. not limited Examples of memory devices are flash memory, DRAM, SRAM, one or more NAND devices or a Managed NAND (Managed NAND) implementation, such as a NAND controller and one or more NAND devices, or other peripherals that store data. .

In FIG. 2 , the host 210 is shown having a data output port 212 , a data input port 214 , and a buffer 206 . Host 210 is similar to host 110 shown in FIG. 1 and may include control circuitry such as control circuitry 102 shown in FIG. 1 . Combining peripheral devices to a single data output port 212 and a single data input port 214 may reduce the number of pins not included on the host 210 . Such embodiments can help reduce device cost and help simplify fabrication. In one or more embodiments, single data ports, such as single data output port 212 or single data input port 214, may each include multiple data lanes. The term single data port is used to denote a single serial connection to the host for multiple peripherals versus a parallel connection to each peripheral on the host.<b>.</b>

As detailed herein, the host 210 may be configured to break up a transport layer packet into a plurality of link-control layer packets and forward a plurality of link-control layer packets via the data output port 212 . have. The host may monitor for multiple acknowledgments corresponding to multiple link-control layer packets received via data input port 214 . Multiple grants may be used by the host to restrict the number of link-control layer packets forwarded via data output port 214 as described herein. Host 210 may reconstruct a transport layer packet from a number of link-control layer packets received via data input port 214 .

The first peripheral device 220-1 is shown together with the second peripheral device 220-2 and the N-th peripheral device 220-N coupled in a chain configuration. As shown in Fig. 2, the chained peripheral device configuration can perform point-to-point signaling. Using the configuration shown, the chain of peripherals can be arbitrarily long without the use of complex addressing circuitry as described herein. The peripheral devices 220-1, 220-2, ..., 220-N shown in FIG. 2 are similar to the peripheral devices 120-1, 120-2, ..., 120-N shown in FIG. It may include a control circuit such as the control circuits 104-1, 104-2, ..., 104-N shown in FIG. Each of the peripheral devices 220-1, 220-2, ..., 220-N may be associated with one or more device identifiers (DIDs) and/or logical unit numbers (LUNs). For example, a particular peripheral could have one DID and more than one LUN.

The peripheral devices 220-1, 220-2, ..., 220-N are connected to the upstream side 222-1, 222-2,..., 222-N and the downstream side 224-1, 224-2,... , 224-N). Peripheral devices include upstream data input ports 226-1, 226-2, ..., 226-N, downstream data output ports 228-1, 228-2, ..., 228-N, and downstream data input ports. It may include ports 230-1, 230-2, ..., 230-N, and upstream data output ports 232-1, 232-2, ..., 232-N. Each data port for a particular peripheral may be coupled to control circuitry for that particular peripheral. In operation, data or device commands such as address assignment, data request, etc. may pass along arrows 234-1, 234-2, ..., 234-N from an upstream data input port to a downstream data output port through a given device. can Data/commands are upstriped from data input ports 226-1, 226-2, ..., 226-N along arrows 238-1, 238-2, ..., 238-N within a given peripheral device. Data output ports (232-1, 232-2, ..., 232-N) can pass through internally. Data/commands are routed through a given peripheral on a return path to the downstream data input ports 230-1, 230-2 as shown by arrows 236-1, 236-2, ..., 236-N. ,, 230-N) to the upstrip data output ports 232-1, 232-2,, 232-N. Peripheral devices 220-1, 220-2, ..., 220-N may include buffers 206-1, 206-2, ..., 206-N coupled to control circuitry of individual peripheral devices. A buffer for each individual peripheral device may be coupled to one or more upstream and downstream data input and output ports. Although three peripheral devices are shown in system 200, the present disclosure is not so limited. Using the illustrated configuration, more or less peripheral devices may be included.

As described, the peripheral devices 220-1, 220-2, ..., 220-N deconstruct a transport layer packet into a plurality of link-control layer packets to decompose the plurality of link-control layer packets into one or more upstreams. to communicate, eg, forward, via data output ports 232-1, 232-2, ..., 232-N and downstream data output ports 228-1, 228-2, ..., 228-N; can be configured. The peripheral devices 220-1, 220-2, ..., 220-N are connected via the upstream data output ports 232-1, 232-2, ..., 232-N to, for example, the host 210. Interrupt link-control layer packets can be delivered. A peripheral device may pass through a number of link-control layer packets from an input port, either upstream or downstream, to an output port, as described. Peripheral devices 220-1, 220-2, ..., 220-N include one or more upstream data input ports 226-1, 226-2, ..., 226-N and downstream data input ports 230-1, 226-N. A transport layer packet may be reconstructed from a plurality of link-control layer packets received via 230-2, ..., 230-N).

Control circuitry for a specific peripheral device, eg, peripheral device 220-N, inputs specific data when link-control layer packets are associated with a destination address, eg, DID or LUN, for peripheral device 220-N. and reconstruct a transport layer packet from link-control layer packets received via the port. When the received link-control layer packets are associated with a destination address for a different peripheral device, for example, an address associated with the peripheral device 220-2, the receiving peripheral device 220-N is directed in the upstream or downstream direction. may pass through multiple link-control layer packets, eg, via an appropriate output port, towards a destination address associated with multiple link-control layer packets. In one or more embodiments, the link-control layer may not be used for route packets.

The host 210 is connected to a common physical connection part between the host 210 and the plurality of peripheral devices 220-1, 220-2, ..., 220-N, for example, on the common physical connection part 105 of FIG. 1 . It may be configured to maintain packet flow control. Accordingly, the peripheral devices 220-1, 220-2, ..., 220-N may be configured to forward the interrupt link-control layer packet to the host 210, for example, to the host 210 in the upstring direction. can The interrupt link-control layer packet may serve to notify the host 210 that the peripheral devices 220-1, 220-2, ..., 220-N are ready to transmit data via a common physical connection. For example, peripheral devices 220-1, 220-2, ..., 220-N are receiving data, eg, one or more interrupt-link-control layer packets, via RF transceiver 108. Interrupt Link-Control Layer Packet may indicate. The Interrupt Link-Control Layer Packet may contain the context of data transferred via a common physical connection.

In one or more embodiments, the peripheral devices 220-1, 220-2, ..., 220-N send the interrupt link-control layer packet to the host 210 after a delay from a command previously received from the host 210. It can be configured to pass to The Interrupt Link-Control Layer Packet may contain a command indication. Peripherals 220-1, 220-2, ..., 220-N may be configured to forward interrupt link-control layer packets when data associated with the command is ready to be delivered via a common physical connection.

1 and 2 may include hard wired devices or may include sockets for assembly or expandability. One or more embodiments include multiple expansion sockets, with sockets downstream of the final peripheral still available in chain. In such a configuration, after the last peripheral device, eg, peripheral device 220-N, is removed and an additional peripheral device is placed in the chain, the last peripheral device can be reinserted at the end of the newly extended chain. In some embodiments, additional peripherals can be added to the end of the chain for expansion purposes without removing and reinstalling the dedicated last peripheral from the chain.

3A is a block diagram of a layered architecture for an interface in accordance with one or more embodiments herein. For example, such a layered architecture may include host control circuitry in accordance with one or more embodiments herein, eg, host control circuit 102 of FIG. 1 and/or device control circuitry, eg, device control circuitry ( 104-1, 104-2, ..., 104-N).

The layered architecture may include a transport layer 356 , a link-control layer 354 , and a physical layer 352 , among other layers. A data flow packet between the host and one or more devices may be generated by the transport layer using, for example, a protocol between the host and the devices. Such a protocol may be separate from the method of transporting the data flow of packets, eg wired, wireless, and the like. When the device is attached directly to the host, the data flow packets generated by the transport layer 356 may be passed directly between the host and the device.

When one or more devices are attached to a host via a common physical connection, a link-control layer is used to improve the utilization of data flow connections between the host and devices and to provide flow control for simultaneous data transfer between the host and multiple devices. (354) may be installed. A link-control layer 354 may be implemented to monitor and/or coordinate data transfer between the host and one or more devices. As described, the link-control layer 354 may disassemble and reconstruct the data packets generated by the transport layer 356 between the host and devices to exercise finer control of packet size and flow control.

3B is a block diagram of multiple packets in a layered architecture in accordance with one or more embodiments herein. In one or more embodiments, the data flow from the host to the target device, or the data flow from the device to the host, may be broken into link-control layer packets and also into the original data flow, e.g., transport layer packets. can be reconstructed.

As shown in FIG. 3B , a transport layer packet 372 includes one or more headers 374 , payloads 376 , and cyclic redundancy check (CRC) values, checksums, or error correction codes (ECCs). ) may include an error detection element 378-T such as a parity value. In one or more embodiments, the error detection element 378 - T may be part of the payload 376 . The header 374 may contain a context, eg, the destination address of the transport layer packet 372 . For example, header 374 may contain information associated with command type, target device ID (DID), logical unit number (LUN), status, and/or other contexts. The payload 376 of the transport layer packet 372 may include data and/or instructions.

The transport layer packet 372 may be broken down into multiple link-control layer packets, for example, link-control layer packets 380-1, 380-2, ..., 380-N. Transport layer packet 372 may, for example, be disassembled according to a priority and/or order associated with transport layer packet 372 with respect to a number of other transport layer packets. In some embodiments, the transport layer packet 372 may be transmitted over a common physical connection over a common physical connection, e.g., from a host to a peripheral device, from a peripheral device to a host, or from a first peripheral device to a second peripheral device. Link-control layer packets 380-1, 380-2, ..., 380-N may be deconstructed. In one or more embodiments, before the transport layer packet is broken up into link-control layer packets 380-1, 380-2, ..., 380-N, as described, the entire transport layer packet 372 is It may be loaded into a buffer, for example, the host buffer 106 shown in FIG. 1 or the peripheral device buffers 106-1, 106-2, ..., 106-N. Alternatively, as transport layer packets enter the link-control layer 354 from the transport layer 356, the transport layer packets may be disassembled.

Each link-control layer packet, e.g., link-control layer packet 380-1, contains, for example, fewer bits than a transport layer packet, such as transport layer packet 372, from which the link-control layer packet is dismantled. It may be smaller, such as inclusive. Transport layer depacking in accordance with one or more embodiments of the present application provides for more efficient delivery of, for example, data over a common physical connection.

In one or more embodiments, a link-control layer packet, such as each link-control layer packet, has a sequence number such as sequence number "1" 382-1 in link-control layer packet 380-1 appended thereto. . In some embodiments, each link-control layer packet dismantled from the transport layer packet has a sequence number inserted in an order corresponding to the sequential portion of the transport layer packet representing the link-control layer packet, for example from 1 to N . As shown in FIG. 3B , the last link-control layer packet 380-N may include sequence number "N" 382-N. Sequence numbers can help maintain link-control layer packet order and can help reconstruct the original transport layer packet.

A sequence number may be appended to link-control layer packets in an x-bit field of a header of link-control layer packets, such as a field capable of storing an x number of bits. Since the total number of usable sequence numbers may be limited by a limit on the size of the field to which the sequence numbers are appended, the sequence numbers may be recycled. i.e. 2^x As after link-control layer packets have sequence numbers assigned to specific data flows, 2^x After the sequence numbers have been used, the sequence numbers may be recycled, for example for reuse. For example, if sequence numbers are limited to a set containing 1,2,3 and 4, then after all four sequence numbers are used once, the numbers are assigned to sequence number 1 in both the first and fifth link-control layer packets. It can be reused as it can be assigned. Link-control layer packets may be delivered out of sequence for an appended sequence number.

In one or more embodiments, the number of outstanding link-control layer packets carried over a common physical connection to multiple peripheral devices may be limited. Limiting the number of outstanding link-control layer packets comprises:<img file="KR101417543B1_D0001.tif" />limiting the number of outstanding packets to below the link-control layer packet. That is, for example, a control circuit such as the host control circuit 102 of FIG. 1 may verify that link-control layer packets worth more than half of the total number of sequence numbers are recognized before forwarding further link-control layer packets. can For example, if 16 sequence numbers are available, the control circuit may be configured to limit the outstanding number of link-control layer packets to 8.

Unprocessed packets may include packets that have received an acknowledgment, such as a retransmission request that is negated, for example, and/or packets that are not acknowledged. Accordingly, in one or more embodiments, limiting the number of outstanding link-control layer packets may include using a bit in the x-bit field as the retransmission request bit. A specific link-control layer packet may be forwarded again if the sending device does not receive an acknowledgment for the specific link-control layer packet, or if the sending device receives a denial of acknowledgment. Such embodiments help prevent packet errors because a particular sequence number is recycled before a particular link-control layer packet associated with a particular sequence number that has been successfully received.

In accordance with one or more embodiments of the present invention, the link-control layer provides full data in transport layer packet 372 such as header 374, payload 376, and error detection element 378-T as data payload. can deal with That is, the entire transport layer packet 372 is more suitable for the link-control layer packets 380-1, 380-2, ..., 380-N, regardless of the distinction between the header 374 and the payload 376 . Can be cut into small pieces. For example, link-control layer packet 380-1 includes a portion of header 374 of transport layer packet 372, includes full header 374, or pays at least a portion of header 374. It may include a portion of rod 376 .

Although a transport layer packet is broken up into a number of link-control layer packets, each link-control layer packet has a direction and/or end of data transmission such as upstream or downstream, for example a data direction that is a target such as a DID or LUN. , and may hold and/or represent a packet sequence number, eg, a packet sequence number 380-1. That is, each link-control layer packet may have the same direction and/or end of data transmission in the link-control layer as the transport layer packet had in the transport layer. For example, the direction and/or end of the data transmission may be maintained and/or represented within the header of the link-control layer packet as assigned by the control circuitry of the device transmitting the data.

One or more embodiments include decomposing the transport layer packet 372 into a plurality of link-control layer packets 380-1, 380-2, ..., 380-N. The number of -1, 380-2, ..., 380-N) has the same payload (384-1, ..., 384-N) size as the cache line size of the receiving device. Such embodiments may provide for valid data acceptance and reconstruction of transport layer packets 372 . That is, the receiving device's cache line may be filled and emptied with each received link-control layer packet payload 384-1, ..., 384-N, thereby causing partial loading of the cache line or of the cache line. Inefficiencies associated with fragmentation of individual packets for multiple loads can be avoided. Examples of sizes for a cache line in accordance with this disclosure include, but are not limited to, 32 bytes or 64 bytes. After reconstruction, the receiving device may store the transport layer packet 372 payload 376 as one sector of data, as the case may be. An example of a size for one sector of data may be 512 bytes, although embodiments are not limited thereto.

Each link-control layer packet 380-1, 380-2, ..., 380-N includes a respective error detection element 378-L1, ..., 378-LN. The error detection element, e.g. CRC 378-L1, for a link-control layer packet, such as packet 380-1, is the CRC 378-T associated with the transport layer packet 372 from which the link-control layer packet is dismantled. ) can be generated for link-control layer packets separately from error detection elements such as . 3B, for link-control layer packet 380-1, sequence number 382-1, while payload 384-1 contains data from original transport layer packet 372, ) and the error detection element 378-L1 are generated by the link-control layer. Sequence number 382-1 and error detection element 378-L1 for a particular link-control layer packet 380-1 may be used by link-control for re-delivery, flow control, and the like. As described above, the payload 384 - 1 of a particular link-control layer packet 38 - 1 may include one or more headers 374 , payload 376 , and/or of a corresponding transport layer packet 372 . data from the error detection element 378-T.

The transport layer packet 372 may include, for example, a plurality of link-control layer packets 380 according to a sequence number associated with each of the link-control layer packets 380-1, 380-2, ..., 380-N. -1, 380-2, ..., 380-N). The device receiving the number of link-control layer packets 380-1, 380-2, ..., 380-N may be configured to accept each number of link-control layer packets. Alternatively, the device receiving the number of link-control layer packets 380-1, 380-2, ..., 380-N may be configured to accept the transport layer packet 372 once reconfigured.

In one or more embodiments, the device or host processes the received link-control layer packets in sequential order according to a sequence number associated with each packet, which is sequence number 382-1 associated with link-control layer packet 380-1. can be loaded into the buffer. Once the entire transport layer packet is reconstructed, data may be forwarded in a direction according to address information associated with the reconstructed packet, for example as stored in the header 374 of the reconstructed packet.

In one or more embodiments, the payload 384-1 of the first link-control layer packet 380-1 disassembled from the transport layer packet 372 may store the header 374 of the transport layer packet 372. have. The header 374 may include a context indicating destination information for the transport layer packet 372 . The context, such as destination information, may be derived from a header of the transport layer packet 372 received in association with the first link-control layer packet 380-1. The context of the receiving device prior to sending link-control layer packets, such as the first link-control layer packet 380-1 and/or the subsequent link-control layer packets 380-2, ..., 380-N. It can be loaded into a buffer.

The link-control layer of the device receiving the first link-control layer packet 380-1 disassembled from the transport layer packet 372 may transmit the first link-control layer packet 380-1 to its destination. . Subsequent link-control layer packets 380 - 2 , ... , 380 -N may be transmitted without reconstructing the transport layer packet 372 . In such an embodiment, subsequent link-control layer packets 380-2, ..., 380-N may be transmitted to the destination in the order received by the receiving device. Subsequent link-control layer packets 380-2, ..., 380-N may be transmitted according to the context in the buffer. In some cases, the step of transmitting the subsequent link-control layer packets 380-2, ..., 380-N according to the received order may include, for example, a sequence number associated with the link-control layer packet 380-N ( 382-N), sending subsequent link-control layer packets 380-2, ..., 380-N out of order with respect to the sequence number associated with each link-control layer packet. The destination device, in which the receiving device is the device that transmits the link-control layer packets 380-1, 380-2, ..., 380-N, may reconstruct the transport layer packet 372.

In accordance with one or more embodiments, the receiving device may reconstruct and transmit the transport layer packet 372 in a direction described in the context of the transport layer packet 372, for example, to the destination device. For example, the host generally receives for a transport layer packet 372 reconstructed from a plurality of link-control layer packets 380-1, 380-2, ..., 380-N received from a peripheral device. may be, but the transport layer packet 372 may have a more specific direction, described, for example, in the context associated with it within the transport layer packet header 374 . The more specific directional address may be a memory address associated with the host, among other specific directional addresses. Also, a peripheral device, such as, for example, peripheral device 220 - 2 in FIG. 2 , would be a receiving device capable of sending the reconstructed transport layer packet 372 in the direction described in the context of transport layer packet 372 . , where the direction is another peripheral device, such as peripheral device 220-1 shown in FIG. In some cases, the receiving device may be the destination device.

<u>conclusion</u>

This specification includes methods, apparatuses, and systems for packet processing. One method embodiment for packet processing comprises decomposing a transport layer packet into a plurality of link-control layer packets, each of the link-control layer packets having an associated sequence number, the plurality of link- forwarding control layer packets via a common physical connection to a plurality of peripheral devices, and also limiting a number of outstanding link-control layer packets in the forwarding.

When an element is referred to as being "on" of, "connected to" or "coupled with" another element, the other element or All cases involving other components are included. On the other hand, an element is referred to as being "directly on" of another element, "directly connected to" another element, or "directly coupled with" another element. This indicates a case in which other components or layers are not interposed in the middle. The term "and/or" as used includes any one and all combinations of one or more associated list items.

The term "and/or" as used includes any one and all combinations of one or more associated list items. The term "or" as used means logically inclusive, unless otherwise stated. That is, "A or B" may include (only A), (only B), or (both A and B). In other words, "A or B" may mean "A and/or B" or "one or more of A and B".

In this specification, terms such as first, second, etc. are used to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish the components from each other. Therefore, the first component may be referred to as the second component without departing from the spirit of the present specification.

Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This specification is intended to cover applications or variations of the various embodiments. It is to be understood that the foregoing description has been made in an exemplary manner and not in a limiting manner. Combinations of the above embodiments, and other embodiments not described in detail herein, will be apparent to those skilled in the art upon review of the above description. The scope of various embodiments of the present invention includes other applications in which the structures and methods are used. Therefore, the scope of various embodiments of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which these claims are entitled.

In the above detailed description, various features are grouped together in a single embodiment to streamline the present application. No method herein is to be interpreted as reflecting an intention that the disclosed embodiments herein employ more features than are expressly recited in each claim. Rather, as the following claims indicate, inventive subject matter lies in less than all features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.