Signal comparison circuit and power conversion device

SIGNAL COMPARISON CIRCUIT AND POWER CONVERSION DEVICE

The present invention includes a signal comparison circuit for generating a target signal from an analog quantity and a digital quantity, an output voltage detection circuit and a current control circuit, wherein the output voltage value detected by the output voltage detection circuit and the target output voltage value are A power conversion device equipped with a signal comparator circuit capable of high-precision on-off control of the current flowing from the DC power supply to the reactor by the current control circuit based on the deviation and digitizing the control arithmetic circuit. will be.

Conventionally, a current injection type power conversion device 9 (DC/DC converter) as shown in Fig. 19 is known.

The power conversion device 9 includes a control circuit 91 , a driving circuit 92 , and a converter circuit. The converter circuit consists of a power supply Ei, a transistor switch Tr, and a resistor R for current detection.<sb>s</sb>and a reactor L, a flywheel diode FD, and an output capacitor C.

The control circuit 91, the output voltage e<sb>o</sb>With resistance R the current flowing through the reactor L<sb>s</sb>voltage drop of e<sb>s</sb>detected as, e<sb>o</sb>go e<sb>o</sb><sp>*</sp>to be close to (so that the deviation is zero), the voltage drop e<sb>s</sb>With reference to the value of the input current i by turning the transistor switch Tr on and off<sb>It's</sb>is controlling

In this power conversion device 9, as shown in Fig. 19, e<sb>o</sb>with e<sb>o</sb><sp>*</sp>A certain gain K for the deviation from<sb>P</sb>multiplied by the bias e<sb>c</sb>on the compensation signal S<sb>h</sb>peak voltage e by adding<sb>P</sb>write

peak voltage e<sb>P</sb>w, voltage V<sb>s</sb>(voltage drop e<sb>s</sb>A given gain to A<sb>cc</sb>) is compared by a comparator, and the result of the comparison is<sb>s</sb>(Sample cycle T<sb>s</sb>) to the FF circuit that operates as Thereby, the peak voltage e<sb>P</sb>Control signal S whose duty is the time until reaching<sb>c</sb>is created The drive circuit 92 sends this control signal S<sb>c</sb>Based on this, the on/off control of the transistor switch Tr is performed.

By the way, the response precision (control precision) of the power conversion circuit 9 of FIG. 19 is, as shown in FIG. 20, the control signal S<sb>c</sb>depends on the resolution of At present, since the frequency of a practical oscillator used in the power conversion circuit 9 is only 100 MHz, the response accuracy of the power conversion circuit 9 also does not exceed this range.

(The problem the invention is trying to solve)

An object of the present invention is to provide a signal comparison circuit and a power conversion device capable of on-off control of a current flowing from a power source to a reactor with high precision and capable of digitizing a control arithmetic circuit.

(Means to solve the task)

The signal comparison circuit of the present invention is based on (1) or (2).

(1) A signal comparison circuit for generating a target signal from an analog quantity and a digital quantity, comprising:

a first integration circuit for inputting a reference signal and outputting a first integral value;

a second integration circuit for inputting an analog amount and outputting a second integral value;

an operation signal generating circuit for converting the digital amount into a time amount to shift an operation start timing of the first integrating circuit with respect to an operation start timing of the second integrating circuit;

A target signal generating circuit that compares the time until the first integral value and the second integral value each reach a threshold value and generates the target signal

A signal comparison circuit comprising a.

(2) The signal comparison circuit according to (1), wherein the analog amount is a second analog amount, and the digital amount is generated from the first analog amount.

The power conversion device of this invention makes (3)-(6) a summary.

(3) an output voltage detection circuit and a current control circuit, and based on a deviation between an output voltage value which is a first analog amount detected by the output voltage detection circuit and a target output voltage value, by the current control circuit, A power conversion device equipped with a signal comparison circuit for on/off control of a current flowing from a DC power supply, which is a second analog amount, to a reactor, the power conversion device comprising:

The output voltage detection circuit comprises:

The timing of the rise of the reference clock signal with a higher resolution than the frequency of the reference clock signal by the time according to the digital value, which is a digital quantity equivalent to the deviation between the output voltage value and the target output voltage value a manipulation variable signal generating circuit as an manipulation signal generating circuit that generates a time-varyed manipulation variable signal;

The current control circuit,

a first integrating circuit for current control as a first integrating circuit for inputting a voltage determined by a peak value of a current flowing through the reactor as a reference signal at a rising timing of the manipulated variable signal and outputting a first integrated value for current control;

A second integration for current control as a second integration circuit for repeatedly inputting a voltage corresponding to a current flowing through the reactor once or plural times at a timing synchronized with the rise of the reference clock signal and outputting a second integrated value for current control circuit and

Comparing the time until the first integral value for current control reaches a first predetermined value and the time until the second integral value for current control reaches a second predetermined value, the first integral value for current control The time until this first predetermined value is reached is,

When the second integral value for current control is equal to or less than (less than) the time until the second predetermined value is reached, or

Current control as the target signal for turning off the current flowing from the DC power supply to the reactor when the second integral value for current control is equal to or greater than the time until reaching the second predetermined value or equal or greater A current control signal generating circuit as the target signal generating circuit for generating a signal

A power conversion device comprising a.

(4) the output voltage detection circuit,

a first integration circuit for voltage detection that inputs the output voltage value at a timing of a predetermined clock and outputs a first integral value for voltage detection;

a second integration circuit for voltage detection that inputs the target output voltage value at the timing of the predetermined clock and outputs a second integral value for voltage detection;

The difference between the time until the first integral value for voltage detection reaches a first predetermined value and the time until the second integral value for voltage detection reaches a second predetermined value is calculated as the voltage deviation detection clock an output deviation detection circuit for counting by the number of pulses of

A control arithmetic circuit for inputting the digital deviation value and generating a digital value for controlling the current control circuit based on the digital deviation value

provide more,

The manipulated variable signal generating circuit is configured to input the digital value and a reference clock signal as a time reference for an operation in the current control circuit, and change the timing of the reference clock signal by time according to the digital value. to create

The power conversion device according to (3), characterized in that.

(5) the manipulated variable signal generating circuit,

a decoder for inputting digital values for controlling the current control circuit and outputting a multi-bit signal;

A delay circuit for inputting the plurality of bit signals and the reference clock signal (which serves as a time reference for operation in the current control circuit)

The power conversion device according to (3) or (4), characterized in that it consists of.

(6) the manipulated variable signal generating circuit,

a DA converter for inputting a digital value for controlling the current control circuit and outputting an analog threshold voltage;

an integrating circuit for inputting the reference clock signal (which serves as a time reference for operation in the current control circuit) and outputting an integral voltage thereof;

A comparator for outputting a comparison value between the integral voltage and the analog threshold voltage

The power conversion device according to (3) or (4), characterized in that it consists of.

(Effects of the Invention)

In the power conversion device of the present invention, since the voltage detection circuit is digitized, it is possible to generate various manipulated variable signals. At the same time, in the present invention, by configuring one of the two integration circuits used in the current control system to shift the integration start time to a temporally high resolution by the amount equivalent to the deviation (minute equivalent to the deviation), high-precision control can be realized. can be

Since the power conversion device of the present invention can suppress peak current with high precision, the input (E<sb>It's</sb>) can be used very suitably when it is unstable.

1 is an explanatory diagram of a signal comparison circuit of the present invention;

Fig. 2 is a simplified block diagram of a power conversion device showing one embodiment of the present invention;

3 is a detailed block diagram of a power conversion device showing an embodiment of the present invention;

4A and 4B are diagrams showing an embodiment in which high precision and high speed are achieved;

5(a), (b), and (c) are diagrams showing another embodiment in which high precision and high speed are achieved;

Fig. 6 is a timing diagram showing the operation of the first integrating circuit for voltage detection and the second integrating circuit for voltage detection of Fig. 2;

7 shows the difference ΔN of the above-described coefficient values per cycle of the first clock.<sb>R</sb>A drawing showing the state (state) detected multiple times,

Fig. 8 is an explanatory diagram in a case where a plurality of pulses are shifted by 1/N with respect to the period of the reference pulse, and the actual driving period is made N times the period of the reference pulse;

Fig. 9 is a timing diagram showing the operation of the manipulated variable signal generating circuit of Fig. 2;

Fig. 10 is a diagram showing an example of a manipulation variable signal generating circuit in the power conversion device of Fig. 2;

Fig. 11 (a) is a diagram showing an example of a circuit embodying the manipulated variable signal generating circuit of Fig. 10; Fig. 11 (b) is a timing diagram of this circuit;

Fig. 12(a) is a diagram showing another example of the manipulated variable signal generating circuit, Fig. 12(b) is a timing diagram of this circuit;

Fig. 13 is a diagram showing an example of a current control signal generating circuit in the power conversion device of Fig. 2;

Fig. 14 is a timing diagram showing the operation of the current control signal generating circuit of Fig. 13;

15 is a timing diagram for concisely explaining the operation of the power conversion device of FIG. 2;

Fig. 16 (a) is a diagram showing the configuration of a plurality of manipulation variable signal generating circuits to increase detection accuracy and speeding up the operation, and Fig. 16 (b) is a diagram showing a specific configuration of the manipulated variable signal generating circuit. ,

17(a), (b), and (c) are diagrams showing a design modification example of the above-described power conversion device;

18 (a) and (b) are explanatory views of an approximate technique of the present invention;

19 is a diagram showing a conventional power conversion circuit;

Fig. 20 is an explanatory diagram of the operation of the power conversion circuit of Fig. 19;

Fig. 1A is a block diagram showing one embodiment of a signal comparison circuit of the present invention. In Fig. 1A, the signal comparison circuit 8 includes an analog amount/digital amount conversion circuit 81, an operation signal generating circuit 82, a first integrating circuit 83, and a second integrating circuit ( 84) and a target signal output circuit (85).

The analog amount/digital amount conversion circuit 81 generates a digital amount D (digital signal) from the first analog amount A1 (analog signal). The analog amount/digital amount conversion circuit 81 can be configured to perform arithmetic processing such as digital filter processing on the digital amount D.

The operation signal generating circuit 82 converts the digital amount into a time amount to shift the operation start timing of the first integrating circuit with respect to the operation start timing of the second integrating circuit.

The first integrating circuit 83 inputs the reference signal R, and the integral value S<sb>1</sb>to output The second integrating circuit 84 inputs the second analog amount A2, and the integral value S<sb>2</sb>to output The target signal output circuit 85 compares the time until the first integrator 83 and the second integrator 84 each reach a threshold, and the target signal S<sb>tgt</sb>create

In the analog amount/digital amount conversion circuit 81, the operation signal generation circuit 82, the first integrator circuit 83, and the second integrator circuit 84, the reference clock clk is multi-phased to substantially ( Practically), it can be configured to operate at a clock that is an integer multiple of the clock clk. That is, from the reference clock clk, N clocks clk of the same frequency are made, and T<sb>P</sb>/N, 2T<sb>P</sb>/N, , (N-1)T<sb>P</sb>It can be configured to perform a high-speed operation by performing delay processing of /N delay and adopting a signal obtained by combining these signals as a new clock.

In Fig. 1(b), the reference signal R (threshold value TH<sb>R</sb>), integral value S<sb>1</sb>, high-speed clock clk<sb>R</sb>, the second analog quantity A2 (threshold<sb>A2</sb>), integral value S<sb>2</sb>, high-speed clock clk<sb>A2</sb>shows

In Fig. 1(b), the integral value S<sb>1</sb>, S<sb>2</sb>The value of the clock clk<sb>R</sb>, clk<sb>A2</sb>is replaced by the number of , and a difference between the respective integral values of the first and second integrating circuits 83 and 84 is expressed as a difference between these numbers. Also, clock clk<sb>R</sb>, clk<sb>A2</sb>is the same in FIG.

2 and 3 are explanatory views showing the power conversion device of the present invention. The power conversion device 1 includes an output voltage detection circuit 2 , a current control circuit 3 , and a DC/DC conversion circuit 4 . The current control circuit 3 has the output voltage e detected by the output voltage detection circuit 2<sb>o</sb>and target output voltage e<sb>o</sb><sp>*</sp>Based on the deviation from<sb>It's</sb>Current i flowing from to reactor L<sb>It's</sb>) is turned on and off.

As shown in Fig. 3, the DC/DC conversion circuit 4 is a DC power supply E<sb>It's</sb>with, transistor switch Tr, and current sensing resistor R<sb>s</sb>and a reactor L, a flywheel diode FD, and an output capacitor C. power E<sb>It's</sb>The current (power) supplied from the current detection resistor R<sb>s</sb>It is supplied to the load R through the and reactor L. The flywheel diode FD is turned on when the transistor switch Tr is turned off, and supplies the energy stored in the reactor L to the load R. The output capacitor C is a smoothing capacitor.

As shown in Fig. 2, the output voltage detection circuit 2 includes a first integrator circuit 21 for voltage detection, a second integrator circuit 22 for voltage detection, an output deviation detection circuit 23, and control An arithmetic circuit 24 and an operation amount signal generating circuit 25 are provided.

As referenced in the timing diagram of FIG. 6 , the first integrating circuit 21 for voltage detection is output voltage e<sb>o</sb>1st clock S<sb>s</sb>input at the timing of , and the first integral value S for voltage detection<sb>eo</sb>to output The second integrating circuit 22 for voltage detection is configured to generate a target output voltage e<sb>o</sb><sp>*</sp>1st clock S<sb>s</sb>input at the timing of , and the second integral value S for voltage detection<sb>eo</sb><sp>*</sp>to output The first integrating circuit 21 for voltage detection and the second integrating circuit for voltage detection can be configured by a capacitor and a resistor.

In the first integrating circuit 21 for voltage detection and the second integrating circuit 22 for voltage detection, the first clock S<sb>s</sb>As shown in (a) and (b) of Fig. 4, the reference clock P, T<sb>P</sb>/N(T<sb>P</sb>is the period of P, and N is an integer ("4" in Fig. 4(a)) by shifting to speed up the shift.

Further, as shown in Fig. 5(a), using the first integrating circuits 211 and 212 for voltage detection of N (here, N=2), their operation timing is set to T by the delay x.<sb>P</sb>By shifting by /N, it is possible to increase the accuracy of voltage detection and speed up the operation. Moreover, as shown in FIG.5(b), using the 2nd integration circuits 221 and 222 for voltage detection of N (here, N=2), these operation timings are set to T by the delay x.<sb>P</sb>By shifting by /N, it is possible to increase the accuracy of voltage detection and speed up the operation. Further, as shown in Fig. 5(c), N (here, N=2) sets of first integrating circuits 211 and 212 for voltage detection and second integrating circuits 221 and 222 for voltage detection are used. So, the timing of their operation is T by the delay x.<sb>P</sb>By shifting by /N, it is possible to increase the accuracy of voltage detection and speed up the operation.

The output deviation detection circuit 23 includes a comparator 231 , a counter 232 , and a subtractor 233 . The comparator 231 is a first integral value S for voltage detection.<sb>eo</sb>is the first predetermined value V<sb>thv1</sb>The time until reaching , and the second integral value S for voltage detection<sb>eo</sb><sp>*</sp>This second predetermined value V<sb>thv2</sb>Compare the time until reaching . In the present embodiment, the first predetermined value V<sb>thv1</sb> and a second predetermined value V<sb>thv2</sb>to the same threshold S<sb>thv</sb>is doing with The counter 232 is, as shown in FIG. 6 , the first integral value S for voltage detection.<sb>eo</sb>is the threshold S<sb>thv</sb>time until reaching N<sb>eo</sb>and the second integral value S for voltage detection<sb>eo</sb><sp>*</sp>This threshold S<sb>thv</sb>time until reaching N<sb>eo</sb><sp>*</sp>is the clock S for voltage deviation detection.<sb>smp1</sb>is counted by the number of pulses of

The subtractor 233 calculates the difference ΔN between the coefficient values.<sb>R</sb>is the clock S for voltage deviation detection.<sb>smp1</sb>Count by the number of pulses of , and the count value ΔN<sb>R</sb>, the output voltage value e<sb>o</sb>and the target output voltage value e<sb>o</sb><sp>*</sp>It is output as a digital deviation value indicating the deviation from .

The control arithmetic circuit 24 is a digital deviation value ΔN<sb>R</sb>, and this value ΔN<sb>R</sb>Based on the digital numerical value N for controlling the current control circuit 3<sb>RM</sb>occurs

In addition, in Fig. 6, the first clock S<sb>s</sb>1 cycle of T<sb>e</sb>Clock S for voltage deviation detection once per (one cycle of on/off of transistor switch Tr)<sb>smp1</sb>is one circuit (digital numerical value N for controlling the current control circuit 3)<sb>RM</sb>is detected once), as shown in Fig. 7, the first clock S<sb>s</sb>1 cycle of T<sb>e</sb>per, digital number N<sb>RM</sb>may be detected multiple times. In Fig. 7, the first clock S<sb>s</sb>1 cycle of T<sb>e</sb>Per, the difference ΔN of the above-mentioned coefficient values<sb>R</sb>multiple times (here, 4 times, the measured value is ΔN<sb>R1</sb>, ΔN<sb>R2</sb>, ΔN<sb>R3</sb>, ΔN<sb>R4</sb>indicated by ) the detected state is shown.

Further, as shown in Fig. 8, a plurality of pulses P<sb>1</sb>, P<sb>2</sb>, P<sb>3</sb>is the reference pulse P<sb>0</sb>By shifting by 1/N (in this example, by 1/4) with respect to the period of<sb>P</sb>It can be set to N times the period of (in this example, 4 times).

The manipulated variable signal generating circuit 25 has an output voltage e<sb>o</sb>and target output voltage e<sb>o</sb><sp>*</sp>The reference clock signal (reference signal S<sb>smp2</sb>) to generate a manipulated variable signal whose timing is changed with a resolution higher than the frequency of the reference clock. That is, the manipulated variable signal generating circuit 25 is a digital numerical value N<sb>RM</sb>and a signal serving as a time reference for the operation in the current control circuit 3 (reference signal S<sb>smp2</sb>), and, as shown in Fig. 9, a digital numerical value N<sb>RM</sb>signal S by time according to<sb>smp2</sb>The manipulated variable signal S that time-varyed the rise of<sb>smp3</sb>create For example, S<sb>smp2</sb>The frequency of is 25 MHz, and the resolution of the time change Δt can be 25 GHz.

As shown in FIG. 10 , the manipulated variable signal generating circuit 25 is a digital numerical value N for controlling the current control circuit 3 .<sb>RM</sb>Enter the multi-bit signal S<sb>RM</sb>A decoder 251 that outputs a, and a multi-bit signal S<sb>RM</sb>and reference signal S<sb>smp2</sb>It can be configured as a delay circuit 252 for inputting .

Fig. 11(a) shows a circuit embodied in the manipulated variable signal generating circuit 25 of Fig. 10, and Fig. 11(b) shows a timing diagram of this circuit. 11A is a delay circuit using a plurality of buffers, and the signal S<sb>0</sb>A signal S with a delay time depending on the number of buffers it passes through<sb>1</sb>, S<sb>2</sb>, can create For example, the digital number N<sb>RM</sb>If this Q bit, clock S<sb>smp2</sb>delayed 2<sp>Q</sp>Prepare some kind of delay signal. digital number N<sb>RM</sb>is the signal S by the decoder 251<sb>RM</sb>is converted to this S<sb>RM</sb>By selecting a buffer corresponding to , an arbitrary delay can be created. The number of buffers can be set to about 1000, and by this, the clock S<sb>smp2</sb>When is 25 MHz, the manipulated variable signal S with a resolution accuracy of 1000 times (25 GHz)<sb>smp3</sb>can create

Another configuration example of the manipulated variable signal generating circuit 25 is shown in Fig. 12A. The manipulated variable signal generating circuit 25 of FIG. 12A includes a DA converter 255 that inputs a digital value for controlling the current control circuit 3 and outputs an analog threshold voltage, and a reference signal S<sb>smp2</sb>input and the integral voltage S<sb>L</sb>It is composed of an integration circuit 256 for outputting , and a comparator 257 for outputting a comparison value between the integral voltage and the analog threshold voltage. digital number N<sb>RM</sb>By D/A conversion, the threshold V<sb>th</sb>to set reference signal S<sb>smp2</sb>is input, integration is started by the integration circuit 256 . The output S of the integrating circuit<sb>L</sb>Since the time until this threshold is reached is determined by the threshold, the digital number N<sb>RM</sb>delay can be created. Fig. 12B shows a timing diagram of this circuit.

Moreover, when a high-frequency signal of about 25 GHz can be used (for example, when it can be acquired from an external circuit), the manipulated variable signal generating circuit 25 can also be constituted by a counter.

The output of the output voltage detection circuit 2 described above is supplied to the current control circuit 3 as shown in FIG. 2 .

The current control circuit 3 includes a first integrating circuit 31 for current control, a second integrating circuit 32 for current control, and a current control signal generating circuit 33 .

The first integrating circuit 31 for current control has a predetermined set value e<sb>c</sb>, the manipulated variable signal S<sb>smp3</sb>input at the rising timing of , and the first integral value S for current control<sb>ep</sb>to output

The second integrating circuit 32 for current control is a voltage e corresponding to the current flowing through the reactor L.<sb>s</sb>A given gain to<sb>cc</sb>voltage V multiplied by<sb>s</sb>, reference clock (reference signal) S<sb>smp4</sb>Timing synchronized with the rise of<sb>smp2</sb>timing of ), and the second integral value S for current control<sb>Vs</sb>to output

The current control signal generating circuit 33 is, for example, a clock with a resolution level of the time change Δt, and the first integral value S for current control.<sb>ep</sb>Second integral value S for eddy current control<sb>Vs</sb>It is also possible to compare by sampling, but in the present embodiment, the first integral value S for current control<sb>ep</sb>Second integral value S for eddy current control<sb>Vs</sb>are compared analogously.

The current control signal generating circuit 33 can be composed of, for example, a comparison circuit 331 and an off signal generating circuit 332 as shown in FIG. 13 . Fig. 14 shows a timing diagram showing the operation of the current control signal generating circuit 33. In Fig. 14, the current control signal generation circuit 33 is operated. The comparison circuit 331 includes comparators 3311 and 3312 and an AND gate 3313 . The comparator 3311 is a first integral value S for current control.<sb>ep</sb>and a first predetermined value V<sb>th3</sb>by comparing the result of S<sb>ep_edg</sb>and the comparator 3312 is the second integral value S for current control.<sb>Vs</sb>and the second predetermined value V<sb>th4</sb>and compare the result of S<sb>Vs</sb><sb>_</sb><sb>edg</sb>output as In Fig. 14, the predetermined value V<sb>th3</sb>and V<sb>th4</sb>is the same threshold V<sb>thc</sb>is made of

The off signal generating circuit 332 is constituted by two FF circuits 3321 and 3322 in FIG. 13 . The FF circuit 3321 is a first integral value S for current control.<sb>ep</sb>is the first predetermined value V<sb>th3</sb>(here V<sb>thc</sb>) is the second integral value S for current control<sb>Vs</sb>This second predetermined value V<sb>th4</sb>(here V<sb>thc</sb>) is less than or less than the time until reaching the DC power supply E<sb>It's</sb>Current i flowing from to reactor L<sb>It's</sb>Current control signal S to turn off<sb>off</sb>occurs

That is, clock S<sb>smp2</sb>(or S<sb>smp3</sb>), reference clock S<sb>smp4</sb>At each cycle of the setpoint e<sb>c</sb>is input to the first integrating circuit 31 for current control, and the voltage V<sb>s</sb>are input to the second integrating circuit 32 for current control, and are respectively integrated to signal S<sb>Vs</sb>, S<sb>ep</sb>is converted to The integral is the synchronized clock S<sb>smp3</sb>, S<sb>smp4</sb>Starts when is input.

Output S of the first integrating circuit 31 for current control<sb>ep</sb>V by comparator 3311<sb>thc</sb>Compared with, the output S of the second integrating circuit 32 for current control<sb>Vs</sb>V by comparator 3312<sb>thc</sb>compared with clock S<sb>smp3</sb>The timing of clock S<sb>smp3</sb>Since it is delayed from the timing of , the output pulse S of the comparator 3311<sb>ep_edg</sb>A, the output pulse S of the comparator 3312<sb>Vs_edg</sb>rise more delayed. In the FF3321 and FF3322, when the input S becomes 1, the output (Q to which the overscore is given) becomes 0. Since this signal is fed back to the input of AND gate 3313, pulse S<sb>Vs_edg</sb>Even if R rises within the same period, the result is not reflected in the flip-flop. This state is sent to the flip-flop by a reset signal (reference clock S<sb>smp4</sb>) continues until the beginning of the next period in which the voltage V<sb>s</sb>is set value e<sb>c</sb>Off signal S when less than<sb>off</sb>does not occur The current control signal generating circuit 33 has a voltage V<sb>s</sb>(Voltage e corresponding to the current flowing through the reactor L<sb>s</sb>gain A on<sb>cc</sb>voltage multiplied by ) is input to the first integrating circuit 31 for current control, and this input value is a predetermined set value e<sb>c</sb>When the integral value of is reached, the current control signal S<sb>off</sb>, and the transistor switch Tr is turned off (refer to the timing diagram of FIG. 15).

In addition, Fig. 16 (a) is a configuration diagram in which the operation is increased by increasing the detection accuracy by providing a plurality of the manipulated variable signal generating circuits 25 (here, three circuits denoted by reference numerals 251, 252, 253). 16(b) shows a specific configuration of the manipulated variable signal generating circuit 25. As shown in FIG. As shown in Fig. 16B, the reference clock S<sb>amp2</sb>is branched into plural, and the signal caused by the delay by each delay element is selected by the selector Y, and S<sb>amp2</sb>is output as

17A, 17B, and 17C are diagrams showing examples of design modifications of the above-described power conversion device.

Fig. 17(a) shows an example in which a plurality of sets (two sets in Fig. 17(a)) of the first integration circuits 31 for current control are provided to increase the detection accuracy and speed up the operation. Here, S input to the second integrating circuit 312 for current control<sb>smp3</sb>is S input to the first integrating circuit 311 for current control<sb>smp3</sb>is delayed by 1/2 cycle.

Fig. 17(b) shows a plurality of sets (two sets in Fig. 17(b)) of the first integrating circuit 31 for current control and the second integrating circuit 32 for current control to increase the detection accuracy and perform the operation. A high-speed example is shown. Here, S input to the second integrating circuit 322 for current control<sb>smp4</sb>is S input to the second integration circuit 321 for current control<sb>smp4</sb>is delayed by 1/2 cycle.

Fig. 17(c) shows a plurality of sets (two sets in Fig. 17(c)) of the first integrating circuit 31 for current control and the second integrating circuit 32 for current control to increase the detection accuracy and perform the operation. A high-speed example is shown. Here, S input to the second integrating circuit 312 for current control<sb>smp3</sb>is S input to the first integrating circuit 311 for current control<sb>smp3</sb>is delayed by 1/2 cycle. In addition, S input to the second integrating circuit 322 for current control<sb>smp4</sb>is S input to the second integration circuit 321 for current control<sb>smp4</sb>is delayed by 1/2 cycle.

Further, as shown in Fig. 18(a), N<sb>RM</sb>is input to the pulse output circuit 61 to output a pulse train PS, and S to the current control integrating circuit 62<sb>smp4</sb> and voltage V<sb>s</sb>It is also possible to output the pulse train SS by inputting , and input these pulse trains PS and SS to the control signal generating circuit 33 to generate a control signal.

In addition, as shown in Fig. 18(b), N<sb>RM</sb>is input to the peak value setting circuit 71 to output a value corresponding to the peak value. On the other hand, S to the integrating circuit 72 for current control<sb>smp4</sb> and voltage V<sb>s</sb>is inputted to output the pulse train SS, and a counter 73 counts it. This count value and the output of the peak value setting circuit 71 (a value corresponding to the peak value) are compared by the digital comparator 74, and the comparison result is sent to the control signal generating circuit 33 to generate a control signal. may be

However, the circuit in the present invention is superior to the circuit described in Figs. 18A and 18B in terms of reliability and high speed.

As described above, in this embodiment, the voltage deviation is converted into the amount of time, and the current measured value is also converted into the amount of time for control. That is, since the response accuracy (control precision) substantially depends on the frequency of the clock, it is possible to provide a high-performance power converter.

The present invention comprises a signal comparison circuit for generating a target signal from an analog amount and a digital amount, an output voltage detection circuit and a current control circuit, wherein the output voltage value detected by the output voltage detection circuit and a target output voltage value are A power conversion device equipped with a signal comparator circuit capable of high-precision on-off control of the current flowing from the DC power supply to the reactor by the current control circuit based on the deviation and digitizing the control arithmetic circuit. It can be widely applied in technical fields, etc.