Nand type flash memory device and method for fabricating the same

NAND type flash memory device and method for fabricating the same

1 is a timing diagram illustrating that a voltage drop occurs in a bit line of an off-cell adjacent to the on-cell due to coupling noise of the bit line.

2 is a cross-sectional view illustrating a NAND-type flash memory device including a bit line shielding structure.

3 is a cross-sectional view illustrating a NAND-type flash memory device according to an embodiment of the present invention.

4 is a circuit diagram of a NAND-type flash memory device according to an embodiment of the present invention shown in FIG. 3 .

5 to 8 are cross-sectional views illustrating a method of manufacturing a NAND-type flash memory device according to an embodiment of the present invention shown in FIG. 3 .

9 is a cross-sectional view illustrating a NAND-type flash memory device according to another embodiment of the present invention.

10 to 12 are cross-sectional views illustrating a method of manufacturing a NAND-type flash memory device according to an embodiment of the present invention shown in FIG. 9 .

<backgroundart><p>The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a NAND-type flash memory device capable of reducing coupling noise between bit lines by changing a structure of a bit line, and a method of manufacturing the same.</p><p>Recently, semiconductor devices, whether volatile (eg, DRAM or SRAM) or non-volatile (eg, flash memory), have become highly integrated and large-capacity, and are designed to support a system operating at a high speed. Flash memory devices are generally divided into NOR-type and NAND-type. While the NOR-type flash memory is used to read a small amount of information out-of-order and high-speed, the NAND-type flash memory is mainly used to sequentially read information.</p><p>A NAND-type flash memory device is a nonvolatile memory device that can be electrically programmed and erased, and is portable for MP3 players, digital cameras, camcorders, notebook computers, PDAs, and cellular phones. It is widely used in portable electronics, computer BIOS, printers, USB drives, and the like. In order to read data stored in the memory cell of the flash memory device, it is necessary to verify the state of the programmed memory cell. That is, a signal for reading data from a memory cell selected by a decoder is applied to a corresponding word line, and accordingly, a current or voltage corresponding to the stored information appears on the corresponding bit line.</p><p>In the NAND flash memory device, a voltage higher than the voltage applied to the control gate of the selected memory cell is applied to the control gates of the unselected memory cells, and the state in which current flows or does not flow is determined according to the state of the selected memory cell. When the threshold voltage of the programmed memory cell is higher than the reference value under the predetermined voltage condition, the memory cell is read as an off-cell and a high level voltage is charged on the corresponding bit line. . Conversely, when the threshold voltage of the programmed memory cell is lower than the reference value, the memory cell is read as an on-cell and the corresponding bit line is discharged to a low level. The state of such a bit line is finally read as a data bit "1" or "0" through a sense amplifier.</p><p>Recently, as the degree of integration of memory devices increases and the capacity thereof increases, the spacing between bit lines becomes narrower, and accordingly, coupling noise of the bit lines becomes a major problem. That is, when an off-cell bit line and adjacent bit lines are connected to the on-cell, when the bias level of the adjacent bit line drops from the precharge level to 0V, the off-cell bit line The line must maintain the precharge level (Vp), but due to interference or coupling between the bit lines, the voltage of the bit line of the off-cell is also at a constant level (ΔVbl), as shown in FIG. 1 . ) will fall.</p><p>1 is a timing diagram showing that the voltage of a bit line of an off-cell adjacent to an on-cell is dropped to a certain level due to coupling between the bit lines. Reference numerals "BLe1" and "BLe3" denote an on-cell bit line, and "BLo1" denote an off-cell bit line, respectively.</p><p>However, as the capacity of the memory device increases, the pitch of the bit lines becomes smaller and the coupling coefficient has a value of 80% or more. That is, when the off-cell is placed between the on-cells, the bias level of the bit line of the off-cell is about 20% lower than the precharge level. This means that the bit line variation should be 80% or more of the pre-charge level.</p><p>In order to solve the voltage drop problem due to the coupling between adjacent bit lines, a bit line shielding structure is currently used. In the bit line shielding structure, the entire bit line is divided into an even bit line and an odd bit line, the even bit line and the odd bit line are alternately arranged, and then when the cell of the even bit line is read, the odd bit The line is grounded and used as a shielding line.</p><p>2 is a cross-sectional view illustrating a NAND-type flash memory device including a bit line shielding structure.</p><p>Referring to FIG. 2 , a device isolation layer 102 defining an active region and a non-active region is formed on a semiconductor substrate 100 , and a tunneling layer 110 , floating on the semiconductor substrate in the active region defined by the device isolation layer A gate stack including a gate 120 , an inter-gate insulating layer 130 , and a control gate 140 is disposed. An interlayer insulating layer 150 is formed to separate the gate stack from other gate stacks or conductive layers, and bit lines 160 are disposed on the interlayer insulating layer. Although not shown, impurity regions acting as source/drain through implantation and activation of impurity ions are disposed to be spaced apart from each other at a predetermined distance in the semiconductor substrate 100, and a channel region is formed in the semiconductor substrate 100 between the impurity regions. is formed A bit line contact (not shown) passing through the interlayer insulating layer 150 and connecting to an impurity region formed in the semiconductor substrate is formed under the bit line 160 . The bit line 160 is connected to the impurity region of the semiconductor substrate through the bit line contact (not shown).</p><p>The bit line 160 has a shielding structure to prevent voltage drop due to coupling between adjacent bit lines during device operation. That is, the bit lines 160 are divided into even bit lines BLe1, BLe2, and BLe3 and odd bit lines BLo1, BLo2, and BLo3, and even bit lines BLe1, BLe2, BLe3 and odd bit lines BLo1. , BLo2, BLo3) are alternately arranged. When reading the cells of the even bit lines BLe1, BLe2, and BLe3, the odd bit line is grounded and used as a shielding line. Then, when reading off-cell, coupling noise by adjacent bit lines disappears and only coupling noise between even bit lines remains.</p><p>However, as the device becomes more highly integrated and the pitch of the bit line becomes smaller, the coupling noise between the even bit line and the even bit line or between the odd bit line and the odd bit line also has a negligible value. There is a need for a technology capable of fundamentally improving coupling noise between lines.</p></backgroundart><abstractproblem><p>An object of the present invention is to provide a NAND-type flash memory device having a structure capable of improving the operating speed of the device by reducing coupling between adjacent bit lines.</p><p>Another object of the present invention is to provide a suitable method for manufacturing a NAND-type flash memory device having a structure capable of improving the operating speed of the device by reducing coupling between adjacent bit lines.</p></abstractproblem>

<p>In order to achieve the above technical object, a NAND flash memory device according to the present invention includes a selection transistor and a plurality of memory cells formed in an active region of a semiconductor substrate; an interlayer insulating film formed on the selection transistor and the plurality of memory cells; a bit line contact formed to pass through the interlayer insulating film to be connected to the semiconductor substrate; and a bit line connected to the semiconductor substrate through the bit line contact, wherein adjacent bit lines are arranged to have a step difference from each other.</p><p>In the present invention, it is preferable that an interval between the even bit line and the odd bit line is greater than a width of the bit line.</p><p>A metal silicide may be disposed between the bit line contact and the bit line. In this case, the metal may be any one of titanium (Ti), tantalum (Ta), cobilt (Co), platinum (Pt), iridium (Ir), ruthenium (Ru), or tungsten (W).</p><p>In the present invention, bit lines connected to the same page buffer may have the same height, and bit lines connected to adjacent page buffers may have different heights.</p><p>According to another aspect of the present invention, there is provided a method of manufacturing a NAND-type flash memory device, comprising: forming a selection transistor and a plurality of memory cells in an active region of a semiconductor substrate; forming a first insulating layer covering the selection transistor and the plurality of memory cells; forming first and second bit line contacts connected to the semiconductor substrate on the first insulating layer; forming a first bit line connected to the first bit line contact; forming a second insulating layer covering a resultant product in which the first bit line is formed; a Dean system for exposing the second bit line contact by patterning the second insulating layer; and forming a second bit line connected to the second bit line contact.</p><p>Among the bit lines, it is preferable that bit lines connected to the same page buffer are formed at the same height, and bit lines connected to adjacent page buffers are formed at different heights.</p><p>Another aspect of the present invention provides a method of manufacturing a NAND-type flash memory device, comprising: forming a selection transistor and a plurality of memory cells in an active region of a semiconductor substrate; forming a first insulating layer covering the selection transistor and the plurality of memory cells; forming a first bit line contact having a first height and a second bit line contact having a second height lower than the first height, the first bit line contact being connected to the semiconductor substrate through the first insulating layer; etching an upper portion of the first bit line contact to recess a predetermined depth; forming a first bit line connected to the first bit line contact; forming an insulating film on the resultant; exposing a second bit line contact by etching the insulating layer; and forming a second bit line connected to the second bit line contact.</p><p>The method may further include, before depositing the bit line conductive layer, forming a metal silicide between the second bit line contact and the bit line conductive layer.</p><p>The metal may be any one of titanium (Ti), tantalum (Ta), cobilt (Co), platinum (Pt), iridium (Ir), ruthenium (Ru), or tungsten (W).</p><p>It is preferable that bit lines connected to the same page buffer among the first and second bit lines have the same height, and bit lines connected to adjacent page buffers have different heights.</p><p>Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified in various other forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.</p><p>A flash memory device including a bit line structure for reducing coupling noise according to the present invention is shown in FIGS. 3 and 9, and a circuit diagram thereof is shown in FIG. Cross-sectional views along the lines are shown in FIGS. 5 to 8 and FIGS. 10 to 12 .</p><p>3 is a cross-sectional view illustrating a NAND-type flash memory device according to an embodiment of the present invention, showing some of a plurality of memory cells.</p><p>Referring to FIG. 3 , a NAND-type flash memory device having a novel bit line structure according to an embodiment of the present invention is formed on a semiconductor substrate 200 and includes a device isolation layer 202 for electrical isolation between devices. . The semiconductor substrate 200 is, for example, a p-type silicon (Si) substrate. Although not shown, impurity regions are formed in the semiconductor substrate 200 to be spaced apart from each other by a predetermined interval through implantation and activation of impurity ions, and a channel region is formed in the semiconductor substrate 200 between the impurity regions. The impurity region serves as a source/drain of the flash memory device.</p><p>A tunneling layer 210 is disposed on the semiconductor substrate in the active region defined by the device isolation layer 202, a floating gate 220 formed of a doped polysilicon layer disposed on the tunneling layer, and the floating gate is covered. and an inter-gate insulating film 230 formed of, for example, an oxide film-nitride film-oxide film (ONO) structure, and a control gate 240 disposed on the entire surface of the inter-gate insulating film and made of, for example, a doped polysilicon film. The formed gate stack is disposed.</p><p>Then, an interlayer insulating film 250 covering the gate stack is disposed, and on the interlayer insulating film, an impurity region of the semiconductor substrate 200 and an impurity region of the semiconductor substrate 200 by a bit line contact (not shown) formed to penetrate the interlayer insulating film 250 . A connected first bit line 260 is disposed. The first bit line 260 is made of any one of tungsten (W), tungsten nitride (WN), and aluminum (Al).</p><p>An insulating layer 270 of a predetermined thickness is disposed to separate the first bit line 260 , and a second bit line 280 is disposed on the insulating layer 270 . The insulating layer 270 separates the first bit line 260 and the second bit line 280 and has an appropriate thickness to sufficiently secure a gap between adjacent bit lines. The insulating layer 270 is formed of, for example, any one of a spin-on-glass (SOG), a PSG, or a high-density plasma (HDP) oxide layer.</p><p>The second bit line 280 is made of any one of tungsten (W), tungsten nitride (WN), and aluminum (Al).</p><p>In particular, in the NAND-type flash memory device of the present invention, bit lines arranged in one layer are divided into two layers, unlike in the related art. For example, the first even bit line BLe1, the first odd bit line BLo1, and the third even bit line BLe3 are formed of the first bit line 260, and the second even bit line BLe2, two The second odd bit line BLo2 and the fourth even bit line BLe4 may be formed as a second bit line. Although the method of disposing the first bit line 260 and the second bit line 280 may vary depending on the memory device, two adjacent bit lines are not formed on the same layer but are mutually exclusive to minimize coupling between the bit lines. They are preferably arranged in different layers. In addition, it is preferable that an interval between the even bit line and the odd bit line is greater than a width of the bit line.</p><p>Since the interval between even or odd bit lines arranged on the same layer is doubled compared to the conventional one, coupling noise between bit lines is greatly reduced.</p><p>4 is a circuit diagram of a NAND-type flash memory device according to an embodiment of the present invention shown in FIG. 3 .</p><p>Referring to FIG. 4 , the memory cell array 295 includes a plurality of cell strings connected to the corresponding bit lines BLe1 to BLo4. All of the cell strings have the same structure. Each cell string includes a string select transistor ST1, memory cells M1 to M32, and a ground select transistor GT1. The string select transistor ST1 is connected to the bit line BLe1 and the ground select transistor GT1 is connected to the common source line CSL. The memory cells are connected in series between the string select transistor ST1 and the ground select transistor GT1. The number of memory cells included in one string may vary according to the storage capacity of the memory device. Gates of the string select transistors ST1 of the cell strings are commonly connected to the string select line SSL. The string selection line SSL serves to transmit a string selection signal provided from the row decoder 291 . The gates of the ground selection transistors GT1 of the cell strings are connected to the ground selection line GSL through which the ground selection signal provided from the row decoder 291 is transmitted. Word lines WL1 to WL32 are connected to control gates of the memory cells, respectively.</p><p>All of the bit lines are composed of two layers of metal lines M1 and M2. The bit lines formed on the metal lines of the two layers may be arranged differently depending on the memory device, and two adjacent bit lines are arranged on the metal lines of the different layers. For example, the first metal line M1 constitutes the first even and odd bit lines BLe1 and BLo1 and the third even and odd bit lines BLe3 and BLo3, and the second metal line M2 is the second even and odd bit lines BLe1 and BLo1. and odd bit lines BLe2 and BLo2 and fourth even and odd bit lines BLe4 and BLo4 may be configured.</p><p>Two bit lines are connected to one page buffer. For example, as shown in FIG. 4 , the first even bit line BLe1 and the first odd bit line BLo1 are connected to one page buffer, and the second even bit line BLe2 and the second odd bit line are connected to each other. The line BLo2 is to be connected to one page buffer.</p><p>Another way to connect the bit lines to the page buffer is to connect the first even bit line (BLe1) and the second even bit line (BLe2) to one page buffer, and the first odd bit line (BLo1) and the second The odd bit line BLo2 is connected to one page buffer. Either way, adjacent bitlines are arranged in different layers. In addition, when two even bit lines or odd bit lines are connected to one page buffer, the odd bit line and the even bit line are sequentially arranged on the metal line of the same layer. An insulating layer having a predetermined thickness is interposed between even or odd bit lines connected to one page buffer.</p><p>A basic operation of the NAND type flash memory device having this structure is similar to a conventional method. For example, when an even bit line is driven, an adjacent odd bit line is precharged, and when an odd bit line is driven, an adjacent even bit line is precharged. In addition, when reading a cell of an even bit line, an adjacent odd bit line is grounded, and when a cell of an odd bit line is read, an adjacent even bit line is grounded. That is, when reading a cell of an even bit line, the odd bit line is grounded and used as a shielding line.</p><p>When the first odd bit line BLo1 is grounded to be used as a shielding line, and the first even bit line BLe1 and the third even bit line BLe3 are connected to the on-cell, the two bit lines BLe1 , BLe3) is sufficiently wide to interfere with each other so that the interference is almost negligible. Accordingly, the first odd bit line BLo1 can maintain the pre-self-charging level regardless of the change in the charging level of the adjacent even bit lines BLe1 and BLe3.</p><p>Conversely, when reading a cell of an odd bit line, the adjacent even bit line is grounded and used as a shielding line.</p><p>5 to 8 are cross-sectional views sequentially illustrating a method of manufacturing a NAND-type flash memory device according to an embodiment of the present invention shown in FIG. 3 .</p><p>Referring to FIG. 5 , for example, a thin oxide film is grown on the semiconductor substrate 300 to form a tunneling layer 302 for electron tunneling, and then a polysilicon film 304 to be used as a floating gate is formed on the tunneling layer. to form Next, a nitride layer is deposited on the polysilicon layer to form an etch stop layer 306 . The etch stop layer 306 serves to protect the underlying layers when the device isolation layer buried in the trench is planarized by a chemical mechanical polishing (CMP) process in a subsequent process, and an etch termination layer of the CMP process. is used as Next, an oxide film is deposited to a predetermined thickness on the etch stop layer 306 to form a hard mask layer 308 for protecting the underlying film quality during gate patterning, and a device isolation region is defined on the hard mask layer 308 . A photoresist pattern 310 for the following is formed.</p><p>Next, using the photoresist pattern 310 as an etch mask, the hard mask layer 308, the etch stop layer 306, the polysilicon film 304 for the floating gate, and the tunneling layer 302 in the exposed region. Anisotropic etching is performed to expose the semiconductor substrate in the region where the trench is to be formed. The exposed semiconductor substrate is anisotropically etched to a predetermined depth to form a trench 312 in the device isolation region.</p><p>Referring to FIG. 6 , an inner wall oxide layer 314 is formed on the inner wall of the trench. The inner wall oxide layer 314 is to compensate for damage to the semiconductor substrate generated in the anisotropic etching process for forming the trench, for example, BPSG (Boron Phosphorus Silicate Glass), Spin On Glass (SOG). ), or by depositing any one of PSG (Phosphorus Silicate Glass).</p><p>Next, the trench is filled with an insulating material and planarized to form a device isolation layer 316 . To this end, first, a high density plasma (HDP) oxide film is deposited on the entire surface of the semiconductor substrate on which the inner wall oxide film 314 is formed. A PSG is applied to a predetermined thickness on the HDP oxide film, planarized using a chemical mechanical polishing (CMP) process, and then the HDP oxide film is deposited again to completely fill the trench to form the device isolation film 316 . As a method of forming the device isolation layer by filling the trench, various methods other than the above-described method may be used.</p><p>Next, chemical mechanical polishing (CMP) is performed on the isolation layer buried in the trench, and the CMP is performed using the etch stop layer (306 in FIG. 5) formed in the active region as an endpoint. At this time, since the height from the semiconductor substrate to the device isolation layer 316, that is, the effective field oxide height (EFH), is determined according to the amount of CMP, the amount of CMP is appropriately adjusted. The hard mask layer (308 in FIG. 5) formed on the etch stop layer is also removed during the CMP process. Then, after the etch stop layer is removed, the upper portion of the device isolation layer 316 is etched to be recessed in order to adjust the residual height EFH of the device isolation layer 316 .</p><p>Referring to FIG. 7 , an inter-gate insulating layer 330 having an ONO structure is formed by sequentially stacking, for example, an oxide layer, a nitride layer, and an oxide layer, on the semiconductor substrate on which the device isolation layer is formed. Next, a polysilicon film doped with, for example, an n-type impurity is deposited on the inter-gate insulating film, and then the polysilicon film and the inter-gate insulating film are patterned using a photolithography process to form a control gate 340 . .</p><p>Referring to FIG. 8 , an insulating film such as BPSG is deposited on the semiconductor substrate on which the control gate 340 is formed and then planarized to separate the control gate 340 from other conductive layers. to form Next, the interlayer insulating layer 350 is etched to form a contact hole exposing the semiconductor substrate in the region where the bit line contact is to be formed. A conductive layer is deposited to fill the contact hole, and then the conductive layer is patterned to form a bit line contact (not shown) connected to the semiconductor substrate. In this case, not only a bit line contact (not shown) for connecting the first bit line to the semiconductor substrate, but also a bit line contact for connecting the second bit line to the semiconductor substrate is formed.</p><p>A metal film such as, for example, tungsten (W), tungsten nitride (WN), or aluminum (Al) is deposited on the resultant by which the bit line contact is formed, for example, by chemical vapor deposition (CVD), physical vapor deposition A metal film for the first bit line is formed by depositing using a PVD (Physical Vapor Deposition) or Atomic Layer Deposition (ALD) method. Before depositing the metal layer for the first bit line, a barrier metal layer (not shown) may be formed in order to improve the interface characteristics between the interlayer insulating layer 350 and the metal layer. The barrier metal layer may be formed of, for example, titanium nitride (TiN) or tungsten nitride (WN) by chemical vapor deposition (CVD) or atomic layer deposition (ALD).</p><p>Next, the first bit line 360 is formed by patterning the metal film for the first bit line by a photolithography process. The first bit lines 360 are formed cell by cell across one cell as shown so that the bit lines of adjacent cells are not formed on the same layer in order to maintain a sufficient distance between the bit lines of adjacent cells. do.</p><p>Next, an insulating film such as a spin-on-glass (SOG), PSG, or high-density plasma (HDP) oxide film is deposited on the entire surface of the semiconductor substrate on which the first bit line 360 is formed, and then planarized, An insulating layer 370 for separating the first bit line 360 from a second bit line to be formed in a subsequent step is formed. When the insulating film 370 is formed of an SOG film, it is preferable to deposit a nitride film (not shown) of about 10 to 5,000 Å before depositing the SOG film. The insulating layer 370 may be formed to have a flat surface by depositing the insulating layer and then performing a chemical mechanical polishing (CMP) process.</p><p>Next, chemical vapor deposition (CVD) is performed on a metal film such as tungsten (W), tungsten nitride (WN), or aluminum (Al) on the insulating film 370 in the same manner as in the method of forming the first bit line 360 . , a physical vapor deposition (PVD) or atomic layer deposition (ALD) method is deposited and then patterned by a photolithography process to form the second bit line 380 . Before forming the second bit line 380 , the insulating layer 370 is etched to expose a bit line contact to be connected to the second bit line 380 among previously formed bit line contacts (not shown). do. The subsequent process follows a conventional manufacturing process.</p><p>9 is a cross-sectional view of a NAND-type flash memory device according to another embodiment of the present invention, and the gate structure is the same as that of the first embodiment shown in FIG. 3, and thus is omitted.</p><p>Referring to FIG. 9 , a NAND type flash memory device according to another embodiment of the present invention has a structure in which an odd bit line and an even bit line have different heights, thereby reducing a capacitance between the bit lines to reduce coupling noise. .</p><p>In detail, a device isolation layer 402 for electrical isolation between devices is disposed in a trench formed in the semiconductor substrate 400 , and an inner wall oxide layer 401 is formed on an inner wall of the trench. Although not shown, a tunneling layer is formed on the semiconductor substrate in the active region defined by the device isolation layer 402 , a floating gate formed on the tunneling layer and made of a doped polysilicon layer, and the floating gate is formed to surround the floating gate. For example, an inter-gate insulating film having an oxide film-nitride-oxide (ONO) structure and a control gate formed on the entire surface of the inter-gate insulating film and made of a doped polysilicon film are disposed. An interlayer insulating film 410 for separating the gate stack is formed, and a bit line contact 420 formed to pass through the interlayer insulating film to be connected to the semiconductor substrate 400 is disposed.</p><p>Some of the bit line contacts 420 are recessed by a predetermined depth from the surface, and a first bit line 430 connected to the semiconductor substrate through the bit line contact is formed in the recessed portion. . Preferably, the recessed bit line contact is recessed to a depth of about 100 to 10,000 angstroms from the surface of the bit line contact so that the height of the recessed bit line contact is higher than that of the gate.</p><p>In addition, an interlayer insulating film 440 is disposed to separate the first bit line 430, the interlayer insulating film passes through the interlayer insulating film and is connected to the bit line contact 420, and the semiconductor substrate ( A second bit line 450 connected to 400 is formed. The first bit line 430 and the second bit line 450 are arranged to form a step difference as shown, and the bit line formed in the low area and the bit line formed in the high area may be arranged differently depending on the memory device. have. For example, as shown in the present embodiment, bit lines connected to one page buffer may be arranged at the same height, and bit lines connected to adjacent page buffers may be arranged at different heights.</p><p>The first and second bit lines 430 and 450 are made of tungsten (W) or a tungsten-based metal. A metal silicide (not shown) may be disposed between the first and second bit line contacts and the first and second bit lines 430 to improve contact with the bit line contact. Examples of the metal for forming the metal silicide include refractory metals such as titanium (Ti), tantalum (Ta), cobalt (Co), platinum (Pt), iridium (Ir), ruthenium (Ru), and tungsten (W). desirable.</p><p>In particular, in the NAND-type flash memory device according to another embodiment of the present invention, the height of the first bit line 430 and the second bit line 450 is different by recessing some bit line contacts, so that the It has a structure for reducing coupling noise by reducing capacitance. The capacitance between the bit lines is affected by the spacing and contact area of the bit lines as shown in the following equation.</p><p><maths num="1"><df><i>C = εA/d </i></df></maths></p><p>(C: capacitance, ε: permittivity, A: area, d: distance)</p><p>Accordingly, if the two adjacent bit lines are formed with different heights, the capacitance can be reduced because the area viewed between the bit lines is reduced, and as a result, the coupling noise between the bit lines is reduced, so that the off-cell adjacent to the on-cell is reduced. The voltage drop of the bit line of the cell can be prevented.</p><p>In addition, since the gap between the bit lines is widened, a margin in the process for forming the bit lines can be secured, so that not only the alignment margin but also the resistance of the bit lines are reduced to improve the sensing characteristics of the device. can</p><p>10 to 12 are cross-sectional views sequentially illustrating a method of manufacturing a NAND-type flash memory device according to another embodiment of the present invention shown in FIG. 9 . Since the device isolation process and the gate stack forming process for device isolation are the same as those described in the first embodiment of the present invention, a description thereof will be omitted.</p><p>Referring to FIG. 10 , an oxide film such as BPSG is deposited on the semiconductor substrate 500 on which the inner wall oxide film 501, the device isolation film 502, and the gate stack (not shown) are formed and then planarized, An interlayer insulating layer 510 for separating conductive patterns including a gate stack is formed. A photolithography process is performed to etch the interlayer insulating film 510 in a region where the bit line contact is to be formed, thereby forming a bit line contact hole exposing the semiconductor substrate 500 . Next, by depositing a conductive film, for example, a tungsten (W) or tungsten-based metal film on the entire surface to fill the bit line contact hole, and then performing an etch-back or chemical mechanical polishing (CMP) process, the semiconductor substrate ( A bit line contact 520 connected to the impurity region of 500 is formed. The bit line contact 520 serves to electrically connect the impurity region of the semiconductor substrate and the bit line to be formed in the next step.</p><p>Referring to FIG. 11 , a step of forming the first bit line 530 is performed after a part of the bit line contact is recessed. The first bit line 530 may be formed using a well-known damascene process. To this end, first, a portion of the bit line contact 520 is etched to a predetermined depth and recessed from the surface by a predetermined depth. The bit line contact 520 is etched to a depth of about 100 to 10,000 angstroms from the surface of the bit line contact so that the height of the remaining bit line contact is higher than the height of the gate stack. An electrode material for forming a bit line, for example, tungsten (W) or a tungsten (W)-based metal, for example, chemical vapor deposition (CVD), physical It is deposited by vapor deposition (PVD) or atomic layer deposition (ALD). Next, a chemical mechanical polishing (CVD) process is performed on the deposited bit line conductive layer, where the bit line contact in the non-recessed region is used as the CMP endpoint. As a result, the first bit line 530 having the same height as the non-recessed bit line contact is formed.</p><p>Before depositing an electrode material for forming the first bit line 530 , silicide is formed to improve the interface characteristics between the surface of the recessed bit line contact 520 and the first bit line 530 . it's good The silicide is formed by depositing a metal such as tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), platinum (Pt), iridium (Ir), or ruthenium (Ru), and then at about 450 to 1,250°C. It can be formed by performing a rapid thermal process (RTP) at a temperature of , or by annealing using a furnace.</p><p>In addition, a barrier metal layer (not shown) may be formed on the entire surface before forming the first bit line 530 in order to improve the interface characteristics between the interlayer insulating layer 510 and the first bit line 530 . . The barrier metal layer may be formed of a barrier metal such as titanium nitride (TN) or tungsten nitride (WN) by chemical vapor deposition (CVD) or atomic layer deposition (ALD). In addition, after depositing the barrier metal film, annealing using plasma activation energy is performed to asymmetrize the grain boundaries generated on the surface. In this case, nitrogen (N) as a reducing gas<sb>2</sb>), argon (Ar), an inert gas such as neon (Ne) can be used.</p><p>Referring to FIG. 12 , an interlayer insulating film 540 for separating the first bit line from another conductive layer is formed by depositing an oxide film on the entire surface of the semiconductor substrate on which the first bit line 530 is formed. Then, the interlayer insulating layer 540 is etched by a photolithography process to expose the bit line contacts in the region where the second bit line is to be formed. As with the first bit line, a second bit line 550 is formed by depositing, for example, a tungsten (W) or tungsten-based metal layer on the resultant and then etching the layer.</p><p>The second bit line 550 may also be formed by a damascene process. That is, the interlayer insulating film 540 is etched to expose the bit line contacts, and then a metal film for bit lines is deposited on the resultant, and then a chemical mechanical polishing (CMP) process is performed on the deposited metal film. At this time, when the CMP is performed using the interlayer insulating layer 540 as an etching end point, a second bit line 550 is formed.</p><p>Also, as in the case of the first bit line 530 , before forming the second bit line 550 , a metal silicide (not shown) is formed on the surface of the bit line contact 520 or a barrier metal layer (not shown) is formed. not) may be formed. Of course, both the metal silicide and the barrier metal film may be formed. The metal silicide is formed by depositing a refractory metal such as tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), platinum (Pt), iridium (Ir), and ruthenium (Ru) at 450 to 1,250° C. It can be formed by a rapid thermal process (RTP) or an annealing process using a furnace at a temperature of a certain degree. In addition, the barrier metal film is formed by depositing a barrier metal such as titanium nitride (TN) or tungsten nitride (WN) by chemical vapor deposition (CVD) or atomic layer deposition (ALD), followed by asymmetry of grain boundaries generated on the surface. Annealing is performed using plasma activation energy for<sb>2</sb>), argon (Ar), an inert gas such as neon (Ne) can be used. The subsequent process follows a conventional manufacturing process.</p><p>13 is a timing diagram illustrating that the voltage drop of the bit line of the off-cell due to the coupling noise of the bit line is prevented in the NAND flash memory devices according to the present invention.</p><p>As shown, when the bit line BLo1 of the off-cell and the adjacent bit lines BLe1 and BLe3 are connected to the on-cell, the bias level of the bit lines BLe1 and BLe3 of the on-cell is free. It can be seen that even if the charge level drops to 0V, the off-cell bit line BLo1 maintains the precharge level Vp as it is. That is, it can be seen that coupling noise between the bit lines does not occur.</p>

<p>According to the above-described NAND flash memory device and a method for manufacturing the same according to the present invention, bit lines arranged on one metal layer are divided into two metal layers with an insulating film interposed therebetween and arranged between even or odd bit lines arranged on the same layer. Since the interval between the two bit lines is doubled compared to the conventional one, coupling noise between the two bit lines is greatly reduced, thereby preventing a malfunction of the device and improving the operating speed of the device.</p><p>In addition, by forming different heights of two adjacent bit lines to reduce a viewing area between the two bit lines, capacitance can be reduced, and as a result, coupling noise between the bit lines can be minimized. In addition, a margin in a process for forming a bit line may be secured, and a resistance of the bit line may be reduced to improve sensing characteristics of the device.</p><p>Although the present invention has been described in detail with reference to a preferred embodiment, the present invention is not limited to the above embodiment, and it is natural that various modifications are possible by those skilled in the art within the technical spirit of the present invention. do.</p>