In Plane Switching mode LCD and method of fabricating of the same

Transverse electric field type liquid crystal display device and its manufacturing method {In Plane Switching mode LCD and method of fabricating of the same}

1 is an exploded perspective view schematically showing the configuration of a general liquid crystal display device;

2 is an enlarged plan view of a part of an array substrate for a transverse electric field type liquid crystal display according to the related art;

3 is a cross-sectional view of a conventional transverse electric field type liquid crystal display device taken along lines III-III and IV-IV of FIG. 2 and shown as a reference;

4 is an enlarged plan view of a part of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

5 is a cross-sectional view of a transverse electric field type liquid crystal display device according to the present invention, taken along lines V-V, VI-VI, VII-VII of FIG. 4, and shown as a reference;

6A to 6H are cut along V-V, VI-VI, VII-VII of FIG. 4, and FIGS. 7A to 7H are shown according to the process sequence of the present invention by cutting along VIII-VIII of FIG. A cross-sectional view of the process,

8A to 8C are cross-sectional views illustrating a manufacturing process of a color filter substrate according to a process sequence according to the present invention.

<A brief description of the main parts of the drawing>

100 : substrate 102: gate wiring

104 : gate electrodes 106a, 106b: first and second common wiring

108 : first common electrode 130 : data line

132 : source electrode 134 : drain electrode

136 : active layer 146: outgoing wiring

148 : pixel electrode 150: common electrode

208 : gap spacer 210: first pressed spacer

212 : 2nd pressing spacer

<backgroundart><p>The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to a transverse electric field type liquid crystal display device including a triple column spacer for maintaining a cell gap and preventing spots by pressing, and a method for manufacturing the same.</p><p>In general, a liquid crystal display device is a thin display device that expresses an image by using the optical anisotropy and birefringence characteristics of a liquid crystal filled between two bonded substrates.</p><p>Hereinafter, a general configuration of a liquid crystal display will be described with reference to the drawings.</p><p>1 is a perspective view schematically illustrating a liquid crystal display according to the related art.</p><p>As shown, a general color liquid crystal display 11 is manufactured in a state in which a color filter substrate B1 and an array substrate B2 are bonded to each other with a liquid crystal layer 14 interposed therebetween.</p><p>The color filter substrate B1 includes a transparent substrate 5 in which a plurality of pixel regions P are defined, and color filters 7a and 7b configured for each pixel region P on one surface of the substrate 5; 7c) and a black matrix 6 constructed between the color filters 7a, 7b and 7c.</p><p>The array substrate B2 includes a transparent substrate 22 on which a plurality of pixel regions P are defined, and a gate configured on one side of the pixel region P and the other side perpendicular thereto on the substrate P. The wiring 12 and the data wiring 24 are located at the intersection of the two wirings 12 and 24 , and are formed by a gate electrode 30 , an active layer 32 , a source electrode 34 and a drain electrode 36 . It includes a configured thin film transistor (T).</p><p>In addition, a pixel electrode 17 positioned in the pixel region P and in contact with the drain electrode 36 is included.</p><p>In the above configuration, the liquid crystal layer 14 is initially arranged by an alignment layer (not shown) positioned between the color filter substrate B1 and the array substrate B2 and having a surface treated with rubbing.</p><p>In addition, although not shown, a plurality of column spacers (not shown) for maintaining a gap between the two substrates are formed between the color filter substrate B1 and the array substrate B2 .</p><p>In the above configuration, when a voltage is applied between the pixel electrode 17 and the common electrode 18, an electric field is generated in the vertical direction, and the liquid crystal 14 is driven by this electric field, which changes according to An image can be expressed by the transmittance of light.</p><p>However, driving by the vertical electric field as described above has a problem in that it is difficult to realize a wide viewing angle in terms of the viewing angle of the liquid crystal panel.</p><p>Therefore, in order to solve this problem, a method of driving the liquid crystal with a horizontal electric field has been proposed. When the liquid crystal is driven by a horizontal electric field, there is an advantage of realizing a wide viewing angle compared to the conventional vertical electric field mode.</p><p>In this case, in order to drive the electric field horizontally, the pixel electrode and the common electrode must be designed in a new shape.</p><p>Fig. 2 is an enlarged plan view of a part of an array substrate for a transverse electric field type liquid crystal display according to the related art. (Column spacers constituting a counter substrate (color filter substrate) are shown).</p><p>As shown, the conventional array substrate for a transverse electric field type liquid crystal display device includes a gate wiring 52 extending in one direction on the substrate 50, and first and second common wirings ( 56a, 56b) are constructed.</p><p>At this time, the data line 72 is configured in a direction crossing the gate line and the common line 52 , 56a , and 56b .</p><p>The first and second common wirings 56a and 56b and the data wiring 72 cross each other to define a pixel region P.</p><p>At the intersection of the gate wiring 52 and the data wiring 72 , a gate electrode 54 , which is a part of the gate wiring 52 , an active layer 60 positioned above the gate electrode 54 , and the active A thin film transistor T composed of a source electrode 62 and a drain electrode 64 spaced apart from each other is positioned on the layer 60 .</p><p>On both sides of the pixel region P, a first common electrode 58 is formed of the same layer and the same material as that of the first and second common wires 56a and 56b, and is vertically connected to the two wires 56a and 56b. In the central region of the pixel region P, a transparent second common electrode 82 in the shape of a rod extending vertically while contacting the second common wiring 56b is configured.</p><p>In addition, a pixel electrode 80 is formed between the second common electrode 82 , and the pixel electrode 80 has a transparent bar shape extending from the lead part 78 in contact with the drain electrode 64 . .</p><p>At this time, the first common wiring 56a and the upper lead-out 78 together with the insulating film interposed between the two components form the storage capacitor Cst.</p><p>The design pattern of the transverse electric field type array substrate configured as described above is only an example, and the characteristic here is that the two substrates 50, A gap spacer 98a for maintaining the spaced gaps (not shown) and a pressing spacer 98b for preventing compression are configured.</p><p>The reason why the pressed column spacer 98b is necessary is to prevent light leakage due to the pressing applied to the liquid crystal panel from the outside.</p><p>In more detail, when an external force such as being pressed from the outside is applied to the liquid crystal panel, light leakage occurs. This light leakage is caused by sliding between the array substrate 50 and the color filter substrate (not shown) due to the external force. The reason is that the liquid crystal panel is warped.</p><p>That is, the rubbing directions of the array substrate 50 and the color filter substrate (not shown) in the bending direction of the liquid crystal panel are not parallel to each other, so that the liquid crystals adjacent to the substrate surface are arranged in parallel in the bending direction, so that the overall initial state and have a different arrangement.</p><p>In this case, the arrangement of the liquid crystal does not maintain the initial black state, so that the light passing through the liquid crystal layer rotates with a retardation different from that of the normal portion, resulting in light leakage.</p><p>For the above reasons, the pressed spacer 98b is required in addition to the gap spacer 98a.</p><p>Since the gap spacer 98a functions to maintain a spaced gap between the two substrates, it must be configured to contact the two substrates, and the pressed spacer 98b is spaced apart from any one of the two substrates. should be left</p><p>In this case, it is more advantageous to use the step difference of the array substrate than to manufacture the gap spacer and the pressed spacer through separate processes.</p><p>On the other hand, it is advantageous in terms of image quality that the spacers 98a and 98b are located in areas avoiding them rather than being located in the pixel area. Therefore, the step difference between the region where the thin film transistor T is located and the region where the gate wiring 52 or the common wiring 56 is located is used, and in particular, the gap spacer 98a is positioned to correspond to the thin film transistor T. , a pressed spacer 98b may be positioned to correspond to the gate wiring or the common wiring 52 and 56 .</p><p>Hereinafter, with reference to a cross-sectional view, the configuration of the gap column spacer and the pressed column spacer will be described in more detail.</p><p>FIG. 3 is a cross-sectional view of a conventional transverse electric field type liquid crystal display device taken along lines III-III and IV-IV of FIG. 2 and shown for reference.</p><p>As shown, the conventional transverse electric field type liquid crystal display 10 includes the above-described array substrate 50 , color filters 94a , 94b , and 94c , a black matrix 92 , a planarization film, and a gap spacer 96 . , 98a) and the color filter substrate 90 including the pressed spacer 98b are bonded to each other with a liquid crystal (not shown) interposed therebetween.</p><p>At this time, a step is generated between the region where the thin film transistor T is formed and the region where the wiring 56a is located. Also, the pressed spacer 98b may be configured to correspond to the common wiring or the gate wirings 56a and 52 .</p><p>However, as shown, the gap spacer 98b is designed to correspond to the gate wiring 52 and, instead, the active layer 60 and the source and drain electrodes of the thin film transistor T to use the step difference. During the process of forming (62, 64), the same material is used to form the protrusion 86 in which the semiconductor pattern and the source/drain metal patterns 86a and 86b are stacked on a portion of the gate wiring 52 .</p><p>In this case, the thickness of the gate wiring and the common wiring 52 and 56a is approximately 2000 Å to 2500 Å, the thickness of the gate insulating film GI is 4000 Å, and the thickness of the semiconductor layers 60a and 60b (active layer and ohmic contact layer) is 2000 Å. , and the source and drain electrodes 62 and 64 have a thickness of 3000 Å.</p><p>Accordingly, the difference in step between the region in which the pressed spacer 98b is positioned and the region in which the gap spacer 98a is positioned is about 5500 Å in thickness, which is the same as the thickness of the protrusion 86 .</p><p>Such a step value is considerable, but when formed with 5 masks as in the cross-sectional configuration shown in the figure, the source and drain metal patterns 86b have a structure that covers the semiconductor pattern 86a when the protrusions 86 are formed. Due to the phenomenon in which the step difference is further alleviated, the pressing defect does not occur.</p><p>However, in the conventional transverse electric field type liquid crystal display device, since both the common electrode and the pixel electrodes 80 and 82 in FIG. 2 are formed of a transparent material, a 5-mask process is required to form the array substrate. However, for producers who want to improve productivity by reducing process time and increase product competitiveness by lowering process costs, in fact, the 5-mask process is not a very small process.</p></backgroundart><abstractproblem><p>Accordingly, the first object of the present invention is to shorten the process to increase productivity and product competitiveness.</p><p>In addition, in the process of shortening the process, an excessive step is generated on the array substrate. Accordingly, in order to prevent a newly generated light leakage (painting stain), the first and second pressed spacers are formed together with the gap spacer. A second object of the present invention is to provide a high-quality transverse electric field type liquid crystal display device by solving a pressing defect by configuring a column spacer having a triple structure.</p></abstractproblem>

<p>According to an aspect of the present invention, there is provided a transverse electric field type liquid crystal display device comprising: a first substrate and a second substrate on which a plurality of pixel regions are defined; a gate line formed on one surface of the first substrate and positioned on one side of the pixel area; a common wiring spaced parallel to the gate wiring; a data line intersecting the gate line and the common line with the gate insulating layer therebetween, positioned on the other side of the pixel region, and having semiconductor layers protruding from both sides along the longitudinal direction at a lower portion thereof; a thin film transistor positioned at the intersection of the gate line and the data line; a first protrusion disposed on the gate wiring or the common wiring and having a semiconductor layer and a metal pattern stacked thereon; a second protrusion positioned in a region spaced apart from the gate wiring and the common wiring, and on which a semiconductor layer and a metal pattern are stacked; a bar-shaped transparent pixel electrode extending into the pixel region while in contact with the thin film transistor, and a transparent common electrode spaced apart from the thin film transistor in parallel; a black matrix configured to correspond to the periphery of the pixel area on one surface of the second substrate; a color filter configured in the pixel area; a gap spacer configured on a substrate on which the color filter and the pixel region are configured, a gap spacer configured to correspond to the first protrusion of the first substrate, a first pressed spacer configured to correspond to the second protrusion, and to the gate wiring or common wiring and a correspondingly configured second depressed spacer.</p><p>The common wiring may include a first common wiring and a second common wiring located below and above the pixel area.</p><p>A common electrode connecting the first and second common wirings is further included at both sides of the pixel area.</p><p>One of the gate wiring and the common wiring located on both sides of the second protrusion is configured to be drawn inward according to the shape of the second protrusion.</p><p>The first and second protrusions are characterized in that the upper metal pattern has a smaller area than the lower semiconductor layer.</p><p>A surface step of the first substrate on which the first pressing spacer and the second pressing spacer are positioned is about 2500 Å.</p><p>In the gate insulating layer, portions of the source and drain electrodes, the first and second protrusions, and a portion positioned below the data line are thicker than portions of other regions by about 1000 Å.</p><p>A method of manufacturing a transverse electric field type liquid crystal display device according to a feature of the present invention includes the steps of: preparing a first substrate and a second substrate in which a plurality of pixel regions are defined; forming a gate wiring and a common wiring spaced therefrom so as to be positioned on one side of the pixel area on one surface of the first substrate; forming a semiconductor layer disposed on the other side of the pixel region and protruding from both sides in a longitudinal direction at a lower portion thereof and data lines thereon, crossing the gate wiring and the common wiring with a gate insulating layer therebetween; forming a thin film transistor at an intersection of the gate line and the data line; The first protrusion is located on the gate wiring or the common wiring with the gate insulating film interposed therebetween, and the semiconductor layer and the metal pattern are stacked therebetween; 2 forming a protrusion; forming a bar-shaped transparent pixel electrode extending into the pixel region while in contact with the thin film transistor and a common electrode spaced apart in parallel thereto; forming a black matrix on one surface of the second substrate to correspond to the periphery of the pixel area; forming a color filter in the pixel area; Formed on the substrate on which the color filter and the black matrix are formed, a gap spacer corresponding to a first protrusion of the first substrate, a first pressed spacer corresponding to the second protrusion, and a gate line or common line corresponding to the first protrusion and forming a second depressed spacer.</p><p>The common wiring may include a first common wiring and a second common wiring located below and above the pixel area.</p><p>A common electrode connecting the first and second common wirings is further included at both sides of the pixel area.</p><p>One of the gate wiring and the common wiring located on both sides of the second protrusion may be formed to be drawn inward according to the shape of the second protrusion.</p><p>The first and second protrusions are characterized in that the upper metal pattern is formed in a smaller area than the lower semiconductor layer.</p><p>A method for manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention comprises the steps of defining a plurality of pixel regions and a switching region on the substrate; a first mask process step of forming a gate line extending in one direction on the substrate, a common line spaced apart in parallel thereto, and a gate electrode in the switching region; laminating a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a conductive metal layer on the entire surface of the substrate on which the gate wiring, the gate electrode, and the common electrode are formed; The conductive metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer are patterned to form a first semiconductor layer on the gate insulating layer corresponding to the gate electrode, and a source electrode and a drain electrode spaced apart from the first semiconductor layer. and a second semiconductor layer extending from the first semiconductor layer on one side of the pixel region, a data line formed on the second semiconductor layer, and a second semiconductor layer spaced apart from the gate line or the common line a second mask process step of forming a first protrusion in which a layer and a first metal pattern are stacked and a second protrusion in which a third semiconductor layer and a second metal pattern are stacked on the gate line or the common line; a third mask process step of forming a protective layer on the entire surface of the substrate on which the source and drain electrodes, the data wiring, and the first and second protrusions are formed, and exposing a portion of the drain electrode and the common wiring; and a fourth mask process step of forming a transparent pixel electrode extending into the pixel region while in contact with the drain electrode, and a transparent common electrode spaced apart from and in contact with the common wiring.</p><p>The second mask process step may include forming a photosensitive layer on the conductive metal layer; placing a mask comprising a transmissive part, a blocking part, and a semi-transmissive part on the upper part of the photosensitive layer spaced apart, and exposing the photosensitive layer by irradiating light; The photosensitive layer is developed to form a stepped first photosensitive pattern patterned with a low center in the switching region, a second photosensitive pattern extending from the first photosensitive pattern to one side of the pixel region, and the gate wiring or forming a third photosensitive pattern in a portion of the common wiring and a fourth photosensitive pattern in a region spaced apart from the gate wiring and the common wiring; The conductive metal layer exposed to the periphery of the first to fourth photosensitive patterns and the impurity amorphous silicon layer and pure amorphous silicon layer thereunder are removed, and the metal pattern of the same shape is below the first to fourth photosensitive patterns. and forming a semiconductor pattern; removing a lower portion of the first photosensitive pattern by ashing the first to fourth photosensitive patterns; removing a portion of the first photosensitive pattern to remove the exposed metal pattern, and removing the impurity amorphous silicon layer from the semiconductor pattern thereunder; By removing the first to fourth photosensitive patterns, an active layer corresponding to the switching region, an ohmic contact layer spaced apart from the active layer, a source electrode and a drain electrode on the ohmic contact layer, and the source a data line having a semiconductor pattern extending from an electrode to one side of the pixel area and extending to both sides at a lower portion thereof; a first protrusion having a semiconductor pattern and a metal pattern stacked on the gate line or the common line; and forming a second protrusion in which a semiconductor pattern and a metal pattern are stacked in a spaced apart region of the wiring.</p><p>The mask includes blocking portions on both sides of the transflective portion corresponding to the switching region, an arbitrary region of the gate wiring or common wiring, an arbitrary region of a spaced apart region between the gate wiring and the common wiring, and the pixel; It is characterized in that the blocking portion is configured in the longitudinal direction along one side of the region.</p><p>Hereinafter, with reference to the accompanying drawings, a preferred embodiment according to the present invention will be described.</p><p>-- Example --</p><p>The present invention is characterized in that the first feature is that an array substrate for a transverse electric field type liquid crystal display is manufactured by a four-mask process, and at the same time, a column spacer structure having a triple structure is provided as a second feature.</p><p>4 is an enlarged plan view of a part of an array substrate for a transverse electric field type liquid crystal display according to the present invention manufactured by a four-mask process. (Gap spacers and first and second pressed spacers are shown together)</p><p>As shown, a plurality of pixels P are defined on a substrate 100 , and a gate wiring 102 and first and second common wirings 106a and 106b spaced apart therefrom are formed on one side of the pixel P. , and a data line 130 crossing the gate wiring and the common wiring 102, 106a, and 106b is formed.</p><p>The first and second common lines 106a and 106b and the data line 130 cross each other to define a pixel area P.</p><p>A portion of the gate wiring 102 serves as the gate electrode 104 on the gate wiring 102 , and the active layer 136 is positioned on the gate electrode 104 , and A thin film transistor T composed of a source electrode 132 and a drain electrode 134 spaced apart from each other is formed on the upper portion.</p><p>In the pixel region P, it is positioned on both sides of the pixel region P and is formed of the same layer and the same material as the first and second common wirings 106a and 106b, and is perpendicular to the two wirings 106a and 106b. The connected first common electrode 108 and the transparent second common electrode 150 having a bar shape connected to the second common wiring 106b and extending vertically to the pixel area P are configured.</p><p>In addition, a transparent pixel electrode 148 is formed between and spaced apart from the second transparent common electrode 150 , and extends from the lead part 146 in contact with the drain electrode 134 .</p><p>At this time, a first protrusion G1 is formed on the gate line 102 or the common line 106a, and a second protrusion G1 is formed in a region spaced apart from the gate line 102 and the common line 106a and 106b. It is characterized in that it forms G2).</p><p>In this case, an insulating layer is interposed between the first common wiring 106a and the upper lead part 146 to form the storage capacitor Cst.</p><p>The transverse electric field type array substrate configured as described above is only one example, and a characteristic feature here is that the two substrates 100 (not shown) are attached to the upper color filter substrate (not shown) bonded to the array substrate 100 . A gap spacer 208 for maintaining a spaced gap, and a first pressing spacer 210 and a second pressing spacer 212 for preventing pressing are constituted.</p><p>In this case, the gap spacer is configured to correspond to the first protrusion G1 , and the first pressed spacer 208 is configured to correspond to the second protrusion G2 .</p><p>Hereinafter, the above-described configuration will be described in detail with reference to a cross-sectional view.</p><p>FIG. 5 is a cross-sectional view of a transverse electric field type liquid crystal display device according to the present invention, taken along lines V-V, VI-VI, and VII-VII of FIG. 4 and shown as a reference.</p><p>As shown, the transverse electric field type liquid crystal display device according to the present invention includes the aforementioned array substrate B2, color filters 204a, 204b, and 204c, a black matrix 202, a gap spacer 208, and the first and the color filter substrate B1 including the second pressing spacers 210 and 212 are bonded to each other with a liquid crystal layer (not shown) interposed therebetween.</p><p>Meanwhile, in order to fabricate the array substrate B2, gate wirings and common wirings 102 and 106a are formed by a first mask process, and semiconductor layers 136 and 138 and source and drain electrodes 132 and 134 are formed by a second mask process. Then, the protective layer 140 exposing the drain electrode 134 is formed by the third mask process, and the pixel electrode 148 and the common electrode ( 150 in FIG. 4 ) are formed by the fourth mask process.</p><p>At this time, in the second mask process, the source and drain electrodes 132 and 134 and the semiconductor layer 136 are simultaneously etched by dry etching, and further, the ohmic contact layer 138 of the semiconductor layers 136 and 138 is dry etched. , which inevitably leads to over-etching of the lower gate insulating layer 110 .</p><p>That is, the portion corresponding to the second pressed spacer 212 has a large step difference from about 5500 angstroms to about 6500 angstroms, so that in the four-mask process, the step becomes larger than in the prior art. As a result, the second pressing spacer 212 partially fails to function properly, so that a new light leakage defect occurs due to pressure applied from the outside.</p><p>The first pressing spacer 210 is used to solve this problem, and thus the step difference of the second pressing spacer 212 can be compensated.</p><p>That is, when an external force is applied from the outside, the first pressing spacer 210 becomes the first resistive component and the second pressing spacer 212 becomes the second resistive component in succession. To this end, the surface of the array substrate corresponding to the first pressing spacer 210 should be higher than the surface of the portion corresponding to the second pressing spacer 212 .</p><p>Accordingly, the second protrusion G2 is formed to correspond to the first pressed spacer 210 and positioned between the gate wiring 102 and the common wirings 106a and 106b.</p><p>With this configuration, the step difference between the regions corresponding to the first depressed column spacer 210 and the second depressed spacer 212 is only about 2000 Å to 2500 Å (thickness of the gate wiring and the common wiring).</p><p>Therefore, the first column spacer 210 serves to compensate for the excessive step difference between the gap spacer 208 and the second pressed spacer 212 to some extent, thereby completely preventing paint stains due to light leakage. be able to</p><p> At this time, since the first pressing spacer 210 has to be configured in a position where there are no wires, it is configured in a space spaced apart between the wires, and if the space is smaller than the cross-sectional area of the first pressing spacer 210 As shown, the second protrusion G2 may be formed after expanding the space by patterning the adjacent wiring inward to match the outer shape of the first pressing spacer 210 .</p><p>Hereinafter, with reference to the process diagram, a manufacturing process of the array substrate for a transverse electric field type liquid crystal display device according to the present invention will be described.</p><p>6A to 6H are cut along V-V, VI-VI, VII-VII of FIG. 4, and FIGS. 7A to 7H are shown according to the process sequence of the present invention by cutting along VIII-VIII of FIG. This is a cross-sectional view of the process.</p><p>6A and 7A are cross-sectional views illustrating a first mask process.</p><p>As shown, a pixel region P and a switching region S are defined on a substrate 100 , and a conductive metal is deposited on the substrate 100 on which the pixel region P and the switching region S are defined. and patterned by a first mask process to form a plurality of gate wirings 102 extending in one direction and spaced apart from each other in parallel and a part of the gate wirings 102 or a gate electrode 104 having a shape protruding therefrom. At the same time, the common wirings 106a and 106b in FIG. 4 and the common electrode 108 are formed parallel to the gate wiring 102 .</p><p>Examples of the conductive metal include aluminum (Al), aluminum alloy (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), and titanium (Ti).</p><p>The common wirings 106a and 106b and the common electrode 108 may be variously patterned, and in the present invention, first and second common wirings 106a and 106b are formed above and below the pixel region P. The first and second common wires 106a and 106b were vertically connected, and the first common electrodes 10 located on both sides of the pixel region P were formed.</p><p>The first common wiring 106a is configured to form the storage capacitor Cst, and the second common wiring 106b is in contact with a transparent common electrode (not shown) formed in a subsequent process to transmit a common signal. configuration to do</p><p>At this time, in the region between the common wiring and the gate wirings 106a, 106b, and 102, the second protrusion (G2 in FIG. 4) may be formed in a subsequent process corresponding to the first pressed spacer (210 in FIG. 5). In order to overcome this, since the spaced area between the wirings 102, 106a, and 106b may be very narrow as the resolution increases, the gate wiring or the common area in which the second protrusion (G2 in FIG. 4) is located. The wirings 102, 106a, and 106b may be patterned in such a way that they lead inward (see Fig. 4).</p><p>Hereinafter, FIGS. 6B to 6F and FIGS. 7B to 7F are cross-sectional views illustrating the second mask process. </p><p>6B and 7B, the gate insulating film 110 and pure amorphous silicon are formed on the entire surface of the substrate 100 on which the gate wiring 102, the common wiring 106, and the first common electrode 108 are formed. The layer 112 , the impurity amorphous silicon layer 114 , and the conductive metal layer 116 are stacked, and a photoresist is applied on the conductive metal layer 116 to form the photosensitive layer 118 .</p><p>The gate insulating layer 110 is a silicon oxide (SiO)<sb>2</sb>), silicon nitride (SiN<sb>X</sb>) may be formed by depositing one or more selected from the group of inorganic insulating materials, such as, the conductive metal layer may be formed by selecting from the aforementioned conductive metal group, and the amorphous silicon layer 112 and impurity amorphous silicon The layer 114 may be formed by depositing pure amorphous silicon (a-Si:H) and impurity amorphous silicon (n+a-Si:H), respectively.</p><p>Next, a mask M composed of a transmissive part B1, a blocking part B2, and a semi-transmissive part B3 is positioned on the photosensitive layer 118 spaced apart from each other.</p><p>The mask M region corresponding to the semi-transmissive portion B3 of the mask M may be a semi-transparent layer or may be configured by forming a slit pattern.</p><p>At this time, the portion corresponding to the switching region S is such that the semi-transmissive portion B3 and the blocking portions B1 are positioned on both sides of the semi-transmissive portion B3 as the center, and the blocking portions having a predetermined width on both sides of the pixel region P (B1) is located, and a first region D1 randomly defined in the gate wiring 102 or common wiring 106a, and a first region D1 defined in a region between the gate wiring 102 and the common wiring 106a. The blocking portion B1 is positioned to correspond to the second region D2.</p><p>Next, a process of exposing the lower photosensitive layer 118 by irradiating light to the upper portion of the mask M is performed.</p><p>As shown in FIGS. 6C and 7C , the first photosensitive pattern 120a has a stepped shape corresponding to the switching region S, and the first photosensitive pattern 120a extends from the first photosensitive pattern 120a to the pixel region P. A second photosensitive pattern 120b and third to fourth photosensitive patterns 120c and 120d formed to correspond to the first to second regions D1 and D2 are formed.</p><p>The conductive metal layer 116 is exposed around the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d.</p><p>6D and 7D, the conductive metal layers 116 of 6c and 7c exposed around the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d and the impurity amorphous silicon layer thereunder An etching process is performed to remove ( 114 in 6c and 7c ) and the pure amorphous silicon layer ( 112 in 6c and 7c ). </p><p>When the etching process is completed, the gate insulating layer 110 is exposed around the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d, and at this time, the lower gate insulating layer 110 is also a surface A phenomenon in which a portion is etched from the</p><p>Through the above-described etching process, the first semiconductor pattern 122a in which the first metal pattern 124 and the impurity amorphous silicon layer and the pure amorphous silicon layer patterned thereunder are stacked under the first photosensitive pattern 120a. is formed, and a data line 130 extending from the first metal pattern 124 to one side of the pixel region P and a second semiconductor pattern 122b below the second photosensitive pattern 120b this is formed</p><p>At the same time, a first protrusion G1 in which a third semiconductor pattern 122c and a second metal pattern 126 are stacked is formed in a first region D1 that is a lower portion of the third photosensitive pattern 120c, and a fourth A second protrusion G2 in which a fourth semiconductor pattern 122d and a third metal pattern 128 are stacked is formed under the photosensitive pattern 120d in the second region D2 .</p><p>Next, an ashing process of partially etching the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d from the surface is performed. The ashing process is to expose a portion of the lower first metal pattern 124 by removing a portion having a low height corresponding to the gate electrode 104 from among the stepped first photosensitive patterns 102a.</p><p>As shown in FIGS. 6E and 7E , when the ashing process is performed, the first photosensitive pattern 120a of the portion corresponding to the gate electrode 104 is completely removed, so that the lower first metal pattern 124 is removed. The central area is exposed.</p><p>In addition, although not expressed in detail in the drawings, since the photosensitive patterns 120a, 120b, 120c, and 120d are inclined from the center to the periphery during the curing process, the other photosensitive patterns 12a The region and the second to fourth photosensitive patterns 120a, 120b, 120c, and 120d are removed to the surface by a predetermined thickness through the ashing process, and at the same time, the first and second metal patterns 126 and 128 in the portion corresponding to the low-thickness periphery. ) and the data line 130 are exposed.</p><p>As shown in FIGS. 6F and 7F, the process of removing the exposed first metal pattern 124 is performed, and the impurity amorphous silicon layer 114 of the lower first semiconductor pattern (122a of FIG. 6E) is performed. A process of exposing the lower pure amorphous silicon layer 112 is performed by removing the .</p><p>Through this process, the source electrode 132 and the drain electrode 134 spaced apart corresponding to the switching region S may be formed, and the impurity amorphous silicon layer 114 patterned under the two electrodes 132 and 134 may be formed. ), an ohmic contact layer 138 having an ohmic contact function is formed, and the pure amorphous silicon layer 112 thereunder is an active layer 136 serving as a channel between the two electrodes 132 and 134. can be formed.</p><p>In this case, the semiconductor layers 122b, 122c, and 122d from which the pure amorphous silicon layer has been removed are exposed to correspond to the periphery of the first and second protrusions G1 and G2 and the data line 130 .</p><p>In particular, during the process of removing the impurity amorphous silicon layer, the gate insulating layer 100 exposed around the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d is further overetched to a thickness of about 1000 Å. become cut off</p><p>Next, a process of removing the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d is performed.</p><p>6G and 7G are process cross-sectional views illustrating the third mask process. As shown, the substrate on which the source and drain electrodes 132 and 134, the data line 130, and the first and second protrusions G1 and G2 are formed. Silicon nitride (SiNx) and silicon oxide (SiO<sb>2</sb>) to form and pattern a protective layer 140 by depositing a selected one of the group of inorganic insulating materials containing A common wiring contact hole (not shown) exposing a part of 106b) is formed.</p><p>6H and 7H are cross-sectional views illustrating the fourth mask process, as shown, indium-tin-oxide (ITO) and indium-zinc-oxide (ITO) and indium-zinc-oxide ( IZO) is deposited and patterned to form an outgoing wiring extending in a shape overlapping with the first common wiring 106b in FIG. 146 , and a bar-shaped pixel electrode 148 extending from the outgoing wiring 146 to the pixel area is formed.</p><p>At the same time, a bar-shaped second common electrode 150 extending into the pixel area while making contact with the second common wiring 4 106b through the common wiring contact hole (not shown) is formed.</p><p>In this case, a configuration of the second common electrode 150 close to the first common electrode 108 formed in the first mask process is configured to partially overlap the first common electrode 108 .</p><p>In this case, the effect of the signal flowing through the data line 130 on the pixel may be blocked by the first and second common electrodes 108 and 150 at both sides of the pixel region P. FIG.</p><p>As described above, through the above-described four-mask process, an array substrate for a transverse electric field type liquid crystal display device according to the present invention can be manufactured.</p><p>Hereinafter, a manufacturing process of the color filter substrate bonded to the array substrate manufactured as described above will be described.</p><p>8A to 8C are cross-sectional views illustrating a manufacturing process of a color filter substrate including a triple-structured column spacer according to a process sequence according to the present invention.</p><p>As shown in FIG. 8A , chromium (Cr) or chromium oxide (CrO) is formed on a substrate 200 in which a plurality of pixel regions are defined.<sb>2</sb>) are sequentially deposited and patterned to form a black matrix 202 around the pixel area P.</p><p>Next, red, green, and blue color filters 204a, 204b (not shown) are formed corresponding to the pixel area P. Referring to FIG.</p><p>The color filters 204a, 204b (not shown) are usually coated with red, green, and blue photosensitive color resins, and then patterned for each pixel area P so that the red, green, and blue color filters 240a, 204b, not shown. C) It is formed to correspond sequentially.</p><p>As shown in FIG. 8B , a transparent conductive metal group including benzocyclobutene (BCB) and an acryl-based resin is selected from the group of transparent conductive metals on the entire surface of the substrate 200 on which the color filters 204a and 204b are formed. A planarization film 206 is formed by depositing one.</p><p>Next, a selected one of the aforementioned organic insulating material groups is coated and patterned on the entire surface of the substrate 200 on which the planarization layer 206 is formed, so that the gap spacer 208 and the first pressed spacer (FIG. 4) of the same height are applied. 210) and a second pressing spacer (212 in FIG. 4) are formed.</p><p>At this time, the first pressing spacer (210 in FIG. 4) is formed at a position corresponding to the second protrusion (G2 in FIG. 1) of the array substrate, and the gap spacer (208 in FIG. 4) is the first protrusion ( It is characterized in that it is formed at a location corresponding to G1 in FIG. 4 , and the second pressed spacer ( 212 in FIG. 4 ) is formed to correspond to an arbitrary region of the gate wiring or the common wiring ( 102 and 106a in FIG. 4 ).</p><p>As described above, it is possible to form a color filter substrate including the column spacer having a triple structure according to the present invention.</p>

<p>Accordingly, in the transverse electric field type liquid crystal display including the triple structure column spacer according to the present invention, since both the common electrode and the pixel electrode are formed of a transparent material, high luminance can be realized.</p><p>Since the common electrode is widely spaced on both sides of the pixel area, a coupling phenomenon does not occur between the data line and the pixel electrode, thereby achieving high image quality.</p><p>In addition, since it is manufactured by the 4-mask process, it is possible to shorten the process time and reduce the process cost, thereby improving the production yield and at the same time increasing the price competitiveness of the product.</p><p>In addition, in the four-mask structure, in addition to the gap spacer and the pressed spacer, a separate pressed spacer is further configured to compensate for the step difference between the gap spacer and the pressed spacer. Defects can be prevented, which also has the effect of realizing high quality.</p>