semiconductor memory device and memory module including it

Semiconductor memory device and memory module including same

1 is a view showing an external view of a memory module according to the prior art.

FIG. 2 is a cross-sectional view of the semiconductor memory device of FIG. 1;

3 is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention;

Fig. 4 is a view for explaining the first embodiment of the method of forming the dummy substrate of Fig. 3;

Fig. 5 is a view for explaining a second embodiment of the method of forming the dummy substrate of Fig. 3;

6 is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 7 is a view for explaining a method of forming the dummy substrate of FIG. 6;

8 is a cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention;

Fig. 9 is a view for explaining a method of forming the dummy substrate of Fig. 8;

Fig. 10 is a view showing an external view of a memory module including a semiconductor memory device according to a technique of the present invention;

<backgroundart><p>The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a dummy substrate in which a capacitor element is embedded, thereby stabilizing power and ground voltages and protecting the semiconductor memory device from external physical shocks; It relates to a memory module having the same.</p><p>As the speed of the semiconductor memory device increases, the size of the signal is also reduced, and a problem that the value of the signal is changed even with a slight voltage difference frequently occurs. Accordingly, for stable and reliable operation of the semiconductor memory device, it is more important to provide a stabilized power supply and a ground voltage.</p><p>To this end, currently, there is a method of adding a capacitor element on a main board on which the semiconductor memory device is mounted, stabilizing the power and ground voltages through the capacitor element, and then providing the stabilized power and ground voltages to the semiconductor memory device. It is widely used. </p><p>For example, if the semiconductor memory device is mounted in a memory module (eg, a single in-line memory module (RIMM), a double in-line memory module (DIMM), etc.), the memory module is provided with capacitor elements on power and ground paths. was added and the power and ground voltages were stabilized through the added capacitor element, and then the stabilized power and ground voltages were provided to the semiconductor memory device. </p><p>1 is a view showing an external view of a memory module according to the related art. </p><p>Referring to FIG. 1 , the memory module includes a main board 1 , a plurality of semiconductor memory devices 2 mounted on the main board 1 , and a main board 1 adjacent to the corresponding semiconductor memory device 2 . ) and a plurality of capacitor elements (3) mounted on it. </p><p>The main board 1 receives power and ground voltage, and includes a connector 4 having a plurality of electrical contacts for inputting and outputting a plurality of electrical signals, and a connector between the connector 4 and the plurality of capacitor elements 3 . A circuit wiring (not shown) electrically connecting the semiconductor memory device 2 to the plurality of capacitor elements 3 and the semiconductor memory device 2 is provided. Accordingly, the main board 1 electrically connects the connector 4 , the plurality of capacitor elements 3 , and the plurality of semiconductor memory devices 2 through circuit wiring.</p><p>The plurality of semiconductor memory devices 2 receive stabilized power and ground voltage from the plurality of capacitor elements 3 , and read or write data in response to a plurality of electrical signals applied through the main board 1 . do. </p><p>The plurality of capacitor elements 3 stabilize power and ground voltage applied through the main board 1 , and apply the stabilized power and ground voltage to the corresponding semiconductor memory device 2 connected through circuit wiring. do. That is, the plurality of capacitor elements 3 removes power noise.</p><p>Accordingly, when the power and ground voltages are applied to the connector 4 of the main board 1 , the memory module stabilizes the power and ground voltages through the plurality of capacitor elements 3 , and is then applied to the plurality of semiconductor memory devices 2 . approve Then, the plurality of semiconductor memory devices 2 stably perform high-speed operation according to the stabilized power supply and ground voltage.</p><p>As described above, in the conventional memory module, a plurality of capacitors are mounted on a main board, and power and ground voltages applied to the semiconductor memory device are stabilized through the plurality of capacitors to remove power noise. However, the conventional memory module has the following problems because a plurality of capacitors must be mounted on the main board.</p><p>First, as the capacitor elements are mounted on the main board, the area of the main board increases in proportion to the number and size of the capacitor elements. Second, since a plurality of capacitor elements have to be disposed adjacent to a corresponding semiconductor memory device in order to increase the power noise removal effect, pattern routing and arrangement of the plurality of memory devices and circuit wiring becomes complicated. Third, since the plurality of capacitor elements are mounted on the main board, the capacitor elements could be separated from the main board by an external physical impact. Fourth, since the capacitor element and the semiconductor memory device are separated, the power and ground voltages from which noise is removed through the capacitor element may become unstable again while passing through the circuit wiring. That is, since the capacitor element and the semiconductor memory device are separated, voltage characteristics unsuitable for high-speed operation may be obtained.</p><p>FIG. 2 is a cross-sectional view of the semiconductor memory device of FIG. 1 . The semiconductor memory device is a chip stack type semiconductor memory device, in which first and second semiconductor chip packages 10 and 20 are disposed on a main substrate 1 . are stacked. </p><p>In the first and second semiconductor packages 10 and 20 shown in FIG. 2 , the center pad type semiconductor chip 110 in which the chip pad 111 is located at the center has a circuit forming surface on which the chip pad 111 is formed. The solder ball 130 is mounted in a face-down form facing the substrate 120 , the semiconductor chip 110 and the substrate 120 are electrically connected by wire bonding, and is attached to the substrate 120 . ) as an external connection terminal. </p><p>The structure of the semiconductor chip package 10 will be described in more detail as follows. </p><p>The substrate 120 has a rectangular window 121 penetrating through the substrate 120 in the central portion.</p><p>The window 121 is formed in such a size that the chip pads 111 of the semiconductor chip 110 to be mounted are opened from the substrate 21 . Here, as the substrate 120 , various types of substrates such as a printed circuit board (PCB), a tape wiring board, and the like may be applied.</p><p>A substrate pad 122 is formed on the lower surface of the substrate 120 , and a ball land 123 corresponding to the position of the solder ball 130 and allowing the solder ball 130 to be attached is formed, and the corresponding substrate pad 122 is formed. A circuit wiring (not shown) electrically connecting between the and the borland 123 is formed. And on the upper surface of the substrate 120, a ball land 124 to which the solder ball 130 is attached is formed corresponding to the position of the solder ball 130 of the semiconductor chip package 20 stacked on the upper side, and the substrate 120 is formed. The ball lands 124 formed on the upper surface of the substrate 120 are electrically connected to the ball lands 123 formed on the lower surface of the substrate 120 through the via 125 formed therethrough.</p><p>The semiconductor chip 110 is attached such that the chip pad 111 is positioned on the window 121 , and the chip pad 111 and the substrate pad 122 are connected to each other through a bonding wire 126 passing through the window 121 . The chip pad 111 and the substrate pad 122 are electrically connected. </p><p>The molded resin part 140 is formed in the window 121 of the substrate 120 to protect the bonding wire 126 electrically connecting the chip pad 111 and the substrate pad 122 from the external environment. </p><p>As described with reference to FIG. 2 , the semiconductor memory device mounted on the memory module of FIG. 1 has a structure in which a plurality of semiconductor chip packages are stacked. However, the semiconductor memory device according to the related art does not have any means for protecting the plurality of semiconductor chip packages from the external environment. Accordingly, when a physical shock is received from the outside, there is a problem in that the semiconductor memory device is easily damaged.</p><p>However, in the stacked semiconductor memory device as shown in FIG. 2 , a plurality of semiconductor chip packages or dummy substrates may be further stacked on top of a plurality of previously stacked semiconductor chip packages. </p><p>Accordingly, in the semiconductor memory device, a separate dummy substrate is stacked on the uppermost layer of the plurality of semiconductor chip packages to protect the plurality of semiconductor chip packages from external environments. </p><p>In addition, the dummy substrate embeds a capacitor element that was mounted on the main substrate 1, and stabilizes the power and ground voltages through the capacitor element, so that the capacitor element is mounted on the main substrate 1. to solve the above problems.</p></backgroundart><abstractproblem><p>An object of the present invention is to provide a semiconductor memory device by stacking a dummy substrate having a capacitor on top of a plurality of semiconductor chip packages to protect the plurality of semiconductor chip packages from external environments and to stabilize power and ground voltages at the same time. will be. </p><p>Another object of the present invention is to provide a memory module including the semiconductor memory device of the present invention. </p><p>A first aspect of a semiconductor memory device of the present invention for achieving the above object is at least one stacked semiconductor chip package having first and second power terminals to which first and second power are applied, respectively, and the stacking. A dummy substrate stacked on top of at least one semiconductor chip package, the dummy substrate having first and second dummy power terminals and capacitors respectively connected between the first and second dummy power terminals; Each of the first and second power terminals of the semiconductor chip package is connected to each other, and the first and second dummy power terminals are respectively connected to the first and second power terminals of the semiconductor chip package of the uppermost layer, , wherein the capacitors are formed inside the dummy substrate.</p><p>A second aspect of a semiconductor memory device of the present invention for achieving the above object is at least one stacked semiconductor chip package having first and second power terminals to which first and second power are applied, respectively, and the stacking method. first and second dummy power terminals, a first electrode connected to the second dummy power terminals, the first and second dummy power terminals and the second A dummy substrate comprising: an insulator formed on the first electrode; and a second electrode formed on the insulator and connected to the first dummy power terminals; Each of the two power terminals is connected to each other, and the second and second dummy power terminals are respectively connected to the first and second power terminals of the semiconductor chip package of the uppermost layer.</p><p>A first aspect of a memory module of the present invention for achieving the above object includes a connector to which first and second power are applied, and predetermined first and second power terminals to which the first and second power are applied. a plurality of semiconductor memory devices performing an operation according to the first and second power, and a main for applying the first and second power applied to the connector to the predetermined first and second power terminals At least one stacked semiconductor chip package including a substrate, each of the plurality of semiconductor memory devices having first and second power terminals to which first and second power are applied, respectively, and the stacked at least one or more A dummy substrate stacked on an upper portion of a semiconductor chip package and including first and second dummy power terminals and capacitors respectively connected between the first and second dummy power terminals, the adjacent semiconductor chip package Each of the first and second power terminals of the are connected to each other, The second and second dummy power terminals are respectively connected to the first and second power terminals of the semiconductor chip package of the uppermost layer, and the capacitors are formed inside the dummy substrate.</p><p>A second aspect of the memory module of the present invention for achieving the above other object includes a connector to which first and second power are applied, and predetermined first and second power terminals to which the first and second power are applied. a plurality of semiconductor memory devices performing an operation according to the first and second power, and a main for applying the first and second power applied to the connector to the predetermined first and second power terminals At least one stacked semiconductor chip package including a substrate, each of the plurality of semiconductor memory devices having first and second power terminals to which first and second power are applied, respectively, and the stacked at least one or more It is stacked on the semiconductor chip package, and includes first and second dummy power terminals, a first electrode connected to the second dummy power terminals, the first and second dummy power terminals, and an upper portion of the first electrode an insulator formed in and a dummy substrate having a second electrode formed on the insulator and connected to the first dummy power terminals, wherein each of the first and second power terminals of the adjacent semiconductor chip package are connected to each other; , wherein the second and second dummy power terminals are respectively connected to the first and second power terminals of the semiconductor chip package of the uppermost layer.</p></abstractproblem>

<p>Hereinafter, a semiconductor memory device and a memory module including the same according to the present invention will be described with reference to the accompanying drawings. </p><p>3 is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention. </p><p>Referring to FIG. 3 , the semiconductor memory device is a chip stack type semiconductor memory device, in which first and second semiconductor chip packages 10 and 20 are vertically stacked on a main substrate 1 as shown in FIG. 2 , After the plurality of solder balls 30 are further formed on the two semiconductor chip packages 20 , a dummy substrate 40 on which the plurality of capacitor elements 50 are embedded is further formed on the solder balls 30 . to be laminated. </p><p>Here, the plurality of solder balls 30 are composed of a solder ball for transferring a power voltage, a solder ball for transferring a ground voltage, and a solder ball to which an electrical signal is not applied, supporting the dummy substrate 40 and simultaneously supporting the dummy substrate 40 . Power and ground voltage are applied to the substrate 40 . Accordingly, the dummy substrate 40 is stacked on top of the plurality of semiconductor chip packages 10 and 20 to protect the plurality of semiconductor chip packages 10 and 20 from the external environment and is applied through the solder ball 30 at the same time. to stabilize the power and ground voltages of the semiconductor memory device.</p><p>In FIG. 3 , since the plurality of semiconductor chip packages 10 and 20 are configured the same as the plurality of semiconductor chip packages 10 and 20 of FIG. 2 , the same numbers are assigned to them, and detailed description thereof will be omitted. </p><p>The configuration of the dummy substrate 40 will be described in more detail as follows. </p><p>The dummy substrate 40 includes a plurality of ball lands 411 , 412 , 413 to which the plurality of solder balls 30 are attached to correspond to the positions of the solder balls 30 , and a plurality of ball lands to which a power voltage is applied from the solder balls (hereinafter, power supply). a plurality of capacitor elements 50 mounted on a plurality of ball lands (hereinafter referred to as a ground ball land) 412 to which a ground voltage applied with a power supply voltage from the solder ball is applied 411 and a plurality of The insulator 420 is formed on the ball lands 413 and the plurality of capacitor elements 50 , and a protective layer 430 is formed on the insulator 420 to protect the dummy substrate 40 . </p><p>The capacitor element 50 is the same capacitor element as the capacitor element 3 in FIG. 1, and is a passive capacitor element composed of a power electrode 51, a ground electrode 52, and a dielectric material 53. As shown in FIG. </p><p>Accordingly, the capacitor element 50 is electrically connected to the power supply ball land 411 and the ground ball land 412 through the power supply electrode 51 and the ground electrode 52, and is electrically connected to the power supply ball land 411 and the ground ball land 412 from the semiconductor. When the power and ground voltages of the memory device are applied, the applied power and ground voltages are stabilized. </p><p>Hereinafter, a method of forming a dummy substrate in which a plurality of capacitor elements of FIG. 3 are embedded will be described with reference to FIG. 4 . </p><p>In this case, the dummy substrate 40 is formed using a general PCB substrate. At this time, a metal layer is formed on the lower surface of the substrate, and an insulator is formed on the upper surface of the metal layer. </p><p>First, the metal layer formed on the lower surface of the substrate is etched through a patterning process to form a plurality of ball lands 411 , 412 , and 413 to correspond to the positions of the plurality of solder balls 41 as shown in (a). Then, only the insulator 420 formed on the plurality of power and ground ball lands 411 and 412 is etched, and the capacitor device 50 is mounted between the plurality of power and ground ball lands 411 and 412 , respectively. Accordingly, one capacitor element 50 is electrically connected to the power and ground ball lands 411 and 412 as shown in (b) to stabilize the power supply voltage and the ground voltage applied from the power and ground ball lands 411 and 412 .</p><p>If the power ball land 411 and the ground ball land 412 are formed to be spaced apart so that the capacitor element 50 cannot be mounted between the power supply and the ground ball land 411 and 412, the substrate 40 is ( Separate power and ground pads 414 and 415 on the lower surface as in a), and circuit wires connecting between the power pad 414 and the power ball land 411 and between the ground pad 415 and the ground ball land 412, respectively ( 416,417) is further formed. And as shown in FIG. 5B, the capacitor element 50 is mounted between the power supply and the ground pads 414 and 415, so that the capacitor element 50 is powered through the power and ground pads 414 and 415 and circuit wires 416 and 417. And to be electrically connected to the ground ball lands (411, 412).</p><p>Of course, if necessary, the ground pad 415 (or the power pad 414) adjacent to the power ball land 411 (or the ground ball land 412) and the ground ball land 412 and the ground pad 415 are connected. It goes without saying that the circuit wiring 417 may be further formed, and the capacitor device 50 may be mounted between the power ball land 411 and the ground pad 415 . </p><p>When the plurality of capacitor elements 50 are electrically connected to the plurality of power and ground ball lands 411 and 412 through the above process, the insulator 420 is formed again on the plurality of capacitor elements 50 . After that, as shown in (c), a passivation layer 430 of the dummy substrate 40 is further formed on the insulator 420 . </p><p>Accordingly, the dummy substrate 40 includes a plurality of capacitor elements 50 to stabilize power and ground voltages and protect the plurality of semiconductor chip packages 10 and 20 from external environments. </p><p>6 is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention. </p><p>Referring to FIG. 6 , the semiconductor memory device is a chip stack type semiconductor memory device, in which first and second semiconductor chip packages 10 and 20 are vertically stacked on a main substrate 1 as shown in FIG. 3 , and a second After the solder balls 30 are formed on the semiconductor chip packages 20 , the dummy substrate 60 is further stacked on the solder balls 30 , but the dummy substrate 60 forms a separate ground electrode. provide more </p><p>In FIG. 6, the same reference numerals as in FIG. 3 are given to components configured and operated as in FIG. 3, and detailed description thereof will be omitted. </p><p>The configuration of the dummy substrate 60 will be described in more detail as follows. </p><p>The dummy substrate 60 is disposed between a plurality of ball lands 611 , 612 , and 613 corresponding to the positions of the solder balls 30 to which the plurality of solder balls 30 are attached, and between the plurality of power and ground ball lands 611 and 612 . A plurality of capacitor elements 50 respectively mounted, a plurality of ball lands 613 and an insulator 620 formed on the plurality of capacitor elements 50, and an insulator ( A ground electrode 630 electrically connected to the ground ball land 612 through a via 621 penetrating through the 620 , and a protective film 640 protecting the dummy substrate 60 formed on the insulator 620 . do. </p><p>Preferably, in order to electrically connect the ground ball land 612 and the ground electrode 630 , the dummy substrate 60 includes a circuit wiring (not shown) between the ground ball land 612 and the ball land 613 to which no electrical signal is applied. ), and a via 621 penetrating the insulator 620 between the ball land 613 to which no electrical signal is applied and the ground electrode 630 is connected. Accordingly, the ground electrode 630 is electrically connected to the ground ball land 612 through the via 621 , the ball land 613 to which no electrical signal is applied, and circuit wiring.</p><p>At this time, the capacitor element 50 is the same capacitor element as the capacitor element 3 of FIG. 1 , and is a passive capacitor element composed of a power electrode 51 , a ground electrode 52 , and an insulator 53 . Accordingly, the capacitor element 50 electrically connects the power electrode 51 and the ground electrode 52 to the power ball land 611 and the ground ball land 612 to receive power and ground voltage, and the applied power and ground voltage. to stabilize</p><p>Hereinafter, a method of forming a dummy substrate in which the plurality of capacitor elements of FIG. 6 are embedded will be described with reference to FIG. 7 . </p><p>In this case, the dummy substrate 60 is formed using a general PCB substrate. At this time, a metal layer is formed on the lower surface of the substrate, and an insulator is formed on the upper surface of the metal layer.</p><p>First, the metal layer formed on the lower surface of the substrate is etched through a patterning process to form a plurality of ball lands 611, 612, and 613 to correspond to the positions of the plurality of solder balls 61 as shown in (a), and at the same time, an electrical signal from the predetermined solder balls is transmitted. Circuit wirings 614 that electrically connect between the unapplied ball lands (hereinafter referred to as dummy ball lands) 613 and the ground ball lands 612 are formed. </p><p>Then, only the insulator 620 formed on the plurality of power and ground ball lands 611 and 612 is etched to leave only the plurality of power and ground ball lands 611 and 612 , and then a capacitor is disposed between the plurality of power and ground ball lands 611 and 612 , respectively. The element 50 is mounted. Accordingly, one capacitor element 50 is electrically connected to the power and ground ball lands 611 and 612 as shown in (b) to stabilize the power and ground voltages applied from the power and ground ball lands 611 and 612 .</p><p>When the plurality of capacitor elements 50 are electrically connected to the power ball land 611 and the ground ball land 612 through the above process, the insulator 620 is again formed on the plurality of capacitor elements 50 . . And after forming the ground electrode 630 on the insulator 620 as shown in (c), the via 621 passing through the insulator 620 to correspond to the position of the dummy ball land 613 connected to the ground ball land 612 . ) to form</p><p>Accordingly, the ground electrode 630 is electrically connected to the ground ball land 612 through the via 621, the dummy ball land 613 connected to the ground ball land 612, and the circuit wiring 614, The stabilization effect of the power and ground voltages is increased, and the protection effect of the plurality of semiconductor chip packages 50 is also increased. </p><p>Preferably, the ground electrode 630 etches a partial region to form a slit 631 , and the thermal expansion coefficient and grounding of the plurality of ball lands 611 , 612 , 613 and the circuit wires 614 through the slit 631 . By adjusting the thermal expansion coefficient of the electrode 630 to be the same, the bending phenomenon of the substrate due to the difference in thermal expansion coefficient is prevented in advance. </p><p>Next, as shown in (d), a passivation layer 640 is further formed on the ground electrode 630 to complete the formation of the dummy substrate. </p><p>Accordingly, the dummy substrate 60 includes a plurality of capacitor elements 50 and a ground electrode 630 to stabilize power and ground voltages and protect the plurality of semiconductor chip packages 10 and 20 from external environments. . </p><p>Of course, if necessary, the dummy substrate 60 may be provided with a power electrode electrically connected to the power ball land 611 instead of the ground electrode 630 . </p><p>8 is a cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention. </p><p>Referring to FIG. 8 , the semiconductor memory device is a chip stack type semiconductor memory device, in which first and second semiconductor chip packages 10 and 20 are vertically stacked on a main substrate 1 as shown in FIG. 3 , and a first and after forming the solder ball 30 on the second semiconductor chip packages 10 and 20, stacking the dummy substrate 70 on the solder ball 30, the dummy substrate 70 is a ground electrode; A capacitor implemented through a power electrode and a dielectric is formed. </p><p>In FIG. 8, components configured and operated in the same manner as in FIG. 3 are given the same numbers as in FIG. 3, and detailed description thereof will be omitted. </p><p>The configuration of the dummy substrate 70 will be described in more detail as follows. </p><p>The dummy substrate 70 is electrically insulated from a plurality of ball lands 711 , 712 , 713 to which the plurality of solder balls 30 are attached to correspond to the position of the solder ball 30 , and is electrically insulated from the power ball land 711 , and is separated from the ground ball land 712 . A ground electrode 710 formed to be electrically connected, a plurality of ball lands 711, 712, 713 and an insulator 720 formed on the ground electrode 710, and an insulator 720 formed on the insulator 720 and passing through the insulator 720 A power electrode 730 electrically connected to the power ball land 711 through a via 721 and a protective layer 740 protecting the dummy substrate 70 formed on the insulator 720 are provided. </p><p>In this case, the insulator 720 is formed of a material capable of charging a predetermined electric charge. Accordingly, the dummy substrate 70 forms a capacitor implemented through the ground electrode 710 , the power electrode 730 , and the insulator 720 . In addition, the dummy substrate 70 may adjust the capacitor capacitance by adjusting the area of the ground electrode 710 , the area of the power electrode 730 , the thickness of the insulator 720 , and the dielectric constant of the insulator 720 .</p><p>A method of forming the dummy substrate for forming the capacitor of FIG. 8 will be described with reference to FIG. 9 .</p><p>In this case, the dummy substrate 70 is a general PCB substrate. A metal layer is formed on the lower surface of the substrate, and an insulator for charging a predetermined electric charge is formed on the upper portion of the metal layer.</p><p>First, the metal layer formed on the lower surface of the substrate is etched through a patterning process to form a plurality of ball lands 711 , 712 , and 713 to correspond to the positions of the plurality of solder balls 61 as shown in (a), and at the same time to electrically connect to the power ball land 711 . to form a ground electrode 710 electrically connected to the ground ball land and the ball land 712 and 713 to which no electrical signal is applied. Accordingly, the ground electrode 710 is electrically connected to the ground ball land 712 and receives a ground voltage from the ground ball land 712 .</p><p>And after forming the power electrode 730 on the top of the insulator 720 as shown in (b), a via 721 penetrating through the insulator 720 is formed to correspond to the position of the power ball land 711, and the power electrode The 730 is electrically connected to the power supply ball land 711 through the via 721 to receive a power supply voltage from the power supply ball land 711 . Accordingly, the dummy substrate is an insulator formed between the ground electrode 710 to which the ground voltage is applied, the power electrode 730 to which the power voltage is applied, and the ground electrode 710 and the power electrode 730 to charge a predetermined charge. A capacitor is formed through 720 to stabilize the supply and ground voltages.</p><p>Next, as shown in (c), a passivation layer 740 is further formed on the power electrode 730 to complete the formation of the dummy substrate 70 . </p><p>Accordingly, the dummy substrate 70 forms a capacitor for stabilizing the power and ground voltages through the ground electrode 710 , the power electrode 730 , and the insulator 720 to stabilize the power and ground voltages, and a plurality of semiconductor chip packages Protect the fields 10 and 20 from the external environment. </p><p>10 is a view showing an external view of a memory module including a semiconductor memory device according to the present invention. </p><p>Referring to FIG. 10 , the memory module includes a main board 5 and a plurality of semiconductor memory devices 7 mounted on the main board 5 . </p><p>In Fig. 10, the semiconductor memory device 7 is one of the semiconductor memory devices of Figs. 3, 6, and 8. In Figs.</p><p>The main board 5 receives power and ground voltage, and connects a connector 8 having a plurality of electrical contacts for inputting and outputting a plurality of electrical signals, and between the connector 8 and the plurality of semiconductor memory devices 7 . A circuit wiring (not shown) for electrically connecting is provided. Accordingly, the main board 5 electrically connects the connector 8 and the plurality of semiconductor memory devices 7 .</p><p>The plurality of semiconductor memory devices 7 includes a plurality of semiconductor chip packages having semiconductor chips embedded therein and vertically stacked on the main substrate 5, and a dummy substrate having a capacitor embedded therein and stacked on top of the plurality of semiconductor chip packages. do. Accordingly, the dummy substrate protects from external physical impact and at the same time stabilizes the power and ground voltage applied through the main substrate 1 , and at the same time protects the plurality of semiconductor chip packages from the external environment, and the plurality of semiconductor chip packages Data is read or written in response to the stabilized power/ground voltage through the dummy substrate and a plurality of electrical signals input from the main substrate 5 .</p><p>As described above, the memory module of the present invention applies power and ground voltages directly to the semiconductor memory device 7 . Then, the semiconductor memory device 7 stabilizes the power and ground voltages through the capacitor elements embedded in the dummy substrate, and the plurality of semiconductor chip packages stably performs high-speed operation in response to the stabilized power and ground voltages.</p><p>Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.</p>

<p>A semiconductor memory device according to the present invention includes a semiconductor memory device in which a dummy substrate having a capacitor embedded therein is stacked on top of a plurality of semiconductor chip packages to protect the plurality of semiconductor chip packages from external environments and to stabilize power and ground voltages. will provide </p><p>In addition, since the memory module including the semiconductor memory device of the present invention does not need to mount a separate capacitor on the main board, the size of the memory module can be reduced, and pattern routing and arrangement of a plurality of memory devices and circuit wiring can be reduced. do it more easily.</p>