Vertical conduction flip-chip device with bump contacts on single surface

VERTICAL CONDUCTION FLIP-CHIP DEVICE WITH BUMP CONTACTS ON SINGLE SURFACE

The present invention relates to a semiconductor device package and a method for manufacturing the package, and more particularly, to a chip-scale package and a method for manufacturing the same.

It is well known that semiconductor device packages housing and protecting semiconductor dies and providing output contacts to electrodes. In general, a semiconductor die is a wafer cut into small squares, and die diffusion and metal bonding are performed in a conventional wafer processing apparatus. These dies may be diodes, field effect transistors, tristers, or the like. The die is easy to break, and the die surface must be protected from the external environment. In addition, for the connection of the die in the electric circuit, a simple lead wire should be connected to the die electrode.

In general, the die is cut and separated from the wafer, and the lower part of the die is mounted and connected to a portion of a circuit board that secures a portion for accommodating each die. The upper electrode of the next die is commonly wire-connected to other parts of the circuit board, and is used for external connection. Such wire connections are delicate, thus slowing down the mounting process. They also provide relatively high resistance and inductance.

It is desirable that the package semiconductor device can be mounted on one side of the package so that it can be quickly and reliably mounted on a circuit board as well as a low resistance connection in many applications.

SUMMARY OF THE INVENTION The present invention provides a novel semiconductor die package that constitutes a "flip-chip" that can be mounted on a circuit board or other electronic interface using one side of the chip. Specifically, the package has contacts on the same side of the package, e.g., gate, source and drain contacts for MOSFETs, and a solder ball on the circuit board that interfaces with the external gate, source and drain contacts respectively on the chip. It can be formed and mounted on the surface of

The source connection to the chip is made by a solder ball on the chip's source electrode, the solder ball being positioned to interface with an appropriate source electrical connection on the circuit board. The package is configured such that the drain electrode is placed on the same surface.

In one embodiment, the active junction lies in a layer with a relatively low carrier concentration (eg, P) below the source electrode and over a substrate with a relatively high carrier concentration (eg, P+). At least one drain electrode is located on the same plane in a region separated from the source electrode. A diffusion region or "sinker" runs from the upper drain electrode down through the layer with a relatively low carrier concentration to the substrate. The diffusion region has the same carrier concentration and type (eg P+) as the substrate. Accordingly, an electrical path is established from the source electrode to the substrate through the active element and to the upper drain electrode through the diffusion region.

As mentioned, since the drain electrode is placed on the same plane as the source and gate electrodes, it can be mounted on the circuit board using solder balls corresponding to the positions of appropriate external drain connections.

In another embodiment, instead of using the diffusion region under the drain contact, a layer with a relatively low carrier concentration can be etched into the substrate to fill the drain electrode. This is performed concurrently with etching the trenches for, for example, a vertically conductive trench-like device.

In another embodiment, two vertically conductive devices are formed on a common chip, the source regions of which are laterally interdigited and have a common drain substrate. This structure forms an intrinsic bidirectional switch. All contacts may be available from the top and the contact balls may be positioned along a straight row (symmetrical about the diagonal of the rectangular chip to simplify connection to the circuit board support). The bottom of the chip may have a thick metal layer that provides a low resistance current path between adjacent devices with a common drain. This can also improve thermal conductivity when the top surface facing the printed circuit board support is mounted on the chip.

Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a plan view of the metal pattern of the device of FIG. 1 before formation of the contact protrusion;

Figure 3 shows the wafer of Figure 2 after formation of solder bumps.

FIG. 4 is a cross-sectional view of a small region corresponding to a region 4-4 dividing line in FIG. 2 , illustrating source and drain upper metal parts.

5 is a layout view showing the size and spacing of the contact balls of FIGS. 1 and 3 .

6 is a cross-sectional view taken along the dividing line 6-6 and the gate bus in FIG. 2 .

Figure 7 shows the use of a P+ sinker diffusion to enable the connection of the top contact of the drain metal to the P+ substrate.

FIG. 8 shows a modified contact structure for contacting the top drain of FIG. 4 to the P+ substrate.

9 shows a top view of a metallized top surface of another embodiment of the present invention.

FIG. 10 shows FIG. 9 having a row of contact balls at a predetermined position.

FIG. 11 is a cross-sectional view of FIG. 9 for a planar junction pattern instead of the trench structure of FIG. 4 .

12 is a cross-sectional view of another embodiment of the present invention similar to that of FIG. 4, but a cross-sectional view taken along the dividing line 12-12 of FIG. 14 using two MOSFETs on a common chip to create a bidirectional conductive device.

Fig. 13 is a circuit diagram of the device of Fig. 12;

14 is a plan view of a device like FIGS. 12 and 13 .

Fig. 15 is a front view of the device of Fig. 14;

16 to 19 show another variant of the device of FIG. 14 .

1 to 6 show a flip-chip power MOSFET type (having all electrodes in one plane and enabling contact with traces or other electrical conductors of a supporting structure such as a printed circuit board (PCB). A first embodiment of the present invention is shown as a contact bump. The device to be described may be a P/N or other type of device such as a Schottky diode, an IGBT, a thyristor, an integrated circuit die having a plurality of components, and the like. The conductivity type can be changed by making an N-channel device. Also, although the devices of FIGS. 1-6 are shown as trench-type devices, they may be planar cell or stripe structures as described below.

A finished device for mounting is shown in Fig. 1, which comprises a silicon die 30 with an upper source electrode metal part 31 (typically 2-8 microns thick aluminum), a drain electrode metal part 32, It is composed of a gate electrode metal pad 33 (FIG. 2) and a gate bus 9.

The die is processed into wafer form as partially shown in FIGS. 2 and 3 . 1, 3 and 4, contact balls are formed on the wafer. That is, the source contact ball 40 is formed on the source metal 31 , the drain contact balls 41 and 42 on the drain contact metal part 32 , and the gate contact ball 43 is formed on the gate pad metal part 33 . The dies within the wafer are separated and placed ready for assembly on a circuit board.

4 and 6 show trench-type power MOSFET geometries for the devices of FIGS. 1 and 3; Therefore, for the P-channel device, the P+ silicon substrate 50 is used and the low-concentration P-type junction receiving layer 51 is epitaxially grown on the P+ substrate 50 . Next, an N-type base or channel diffusion 52 (FIGS. 4 and 5) is formed.

Thereafter, an isolated mesa region is formed using a conventional method, i.e., a plurality of parallel trenches 60 and 61 (FIG. 4) or a row of intersecting trenches. A thin insulating layer, such as silicon dioxide, is then grown on the walls of each trench 60-64, as well as each gate insulating layer 70-74. A conductive polysilicon gate 75 is deposited into each trench and over the gate oxide layer and then etched leaving polysilicon only in the trenches, gatebus and pad regions. A TEOS layer 80 is then deposited and patterned to leave insulation caps 76 and 77 (which may be TEOS) over the polysilicon 75 in the trenches 60 and 61 (FIG. 4). .

A P+ source diffusion 53 is formed over the N diffusion 52 and etched through the layers 52 and 53 . Then contact openings 81 and 82 (FIG. 4) are etched through the P+ source layer 53 into the channel layer 52 and N+ contact diffusions are formed under the openings 81 and 82. The dielectric is then etched laterally to expose a portion of the source region of the die surface for contact. Next, a continuous layer of aluminum is deposited over the surface of the device, which contacts the P+ source diffusion 53 and the N-type channel region 52 . This aluminum layer is separated into a source contact portion 31 , a drain contact portion 32 , and a gate pad 33 by etching.

5 shows a new configuration of the contact balls 40 and 41 . This solder ball is formed by a known processing method using nickel-gold plating (then stencil printing of the solder is performed) and applying solder to form a ball. Thus, the solder ball or bump is centered at 0.8 mm, which is a wider pitch than conventionally used. By using a pitch of 0.8 mm or larger, the flip-chip structure of the present invention can perform attachment and application of conventional chip-scale packages to circuit boards with conventional traces while using conventional surface mounting techniques. . Solder balls 40 and 41 are conventionally thermosonically welded to the surface but have a larger diameter (eg 200 microns or more compared to the standard 150 microns) than those previously used. By using a larger diameter, thermal conductivity is improved and resistance to thermal fatigue is improved.

In FIG. 4 , the drain metal portion 32 is shown contacting an upwardly extending portion of the P+ substrate 50 . This is a schematic illustration, the actual contact from the source drain 32 to the P+ substrate 50 is as in FIGS. 7 and 8 . Thus, in FIG. 7 a P+ "sinker" diffusion 90 is used to make contact. In Figure 8, a trench 91 is formed and filled with metal or conductive polysilicon 92 during the trench etch to create the active region.

The operation of the device of FIGS. 1 to 8 is apparent to a person skilled in the art. Accordingly, the N-type silicon adjacent to the gate oxide layer 70-74 becomes P-type by turning on the device and applying a gate potential to the gate 75 with the appropriate potential applied to the source and drain electrodes 31 and 32. from the source electrode 31, through the source region 53, through the inversion region to the P region 51, then to the P+ substrate 50, then laterally through the P+ substrate 50 and to the region 90 or 92) to complete the circuit with the drain electrode (32) upward.

The novel device of FIGS. 1 to 8 provides a minimum size (ie, die size) of a device that can be mounted. The die itself has a very low RDSON using a vertical structure, cell trench technology. For example, in the design<sp>2</sp> 110x10 per<sp>6</sp> Use more than one cell. However, unlike standard trench FET designs, the drain connection is made in front of or above the die. There is no need to back-grind the bottom of the die or deposit metal on the bottom of the die. By not backgrinding, thicker P+ substrates allow for lower lateral resistance to the flow of drain current. The underside of the die may be rough and unpolished to increase the surface area to help dissipate heat from the chip.

After the metal, a silicon nitride (or other dielectric) passivation layer is deposited. The silicon nitride passivation layer is patterned to leave four openings per die with, for example, a 0.8 mm pitch. The die size is typically about "0.060x0.060". Larger devices (0.123x0.123) are also typical. 46.8 Ω-mm at Vgs of 4.5V for Silicon to 20V P-Channel Device<sp>2</sp>R of<sp>*</sp>It is designed to provide A.

Although a metal layer is not required on the underside of the substrate 50, it may be useful to use the metal layer as a current conductor or to make thermal contact to a thermal sink.

Other surface geometries with a large number of solder balls for higher ampacity are also available. Therefore, as shown in FIGS. 9 and 10, the larger die 100 has a source electrode 101, two drain electrodes 102 and 103 bordering opposite edges of the die 100, and a top surface thereof. It may be arranged (layout) to provide a gate pad 104 having a runner or bus 105 , 106 . As shown in Fig. 10, each of the drain electrodes 102 and 103 accommodates 5 solder balls (arranged in each row), and the source 101 receives 8 solder balls (arranged in parallel). . By aligning the solder balls in each parallel, each conductive trace on the printed circuit board that houses the device can be placed in a simple straight line.

Fig. 11 shows how the device of Fig. 9 is implemented by the planarization technique as an N-channel device. Accordingly, in FIG. 11 , the die 100 is formed with an N+ substrate 110 , an N-type epitaxial layer 111 , and polygonal P-channel diffusions 112 , 113 , and 114 having gaps. Each of the diffusions 112 , 113 , 114 accommodates an N+ source diffusion 115 , 116 , 117 and a P+ contact diffusion 118 , 119 , 120 . A suitable gate structure comprising a polysilicon gate grating 121 is overlying a conventional gate oxide and covered by an insulating layer 122 overlying the source electrode 101 (contacting the source and channel regions in a conventional manner). insulate the gate grid from The N+ sinker provides a conductive path from the N+ substrate to the drain electrode 103 .

It is also possible to make a die with bidirectional conduction characteristics in which two series-connected MOSFETs are integrated into a single chip. Accordingly, as shown in FIG. 12 , a die may be formed by the method of FIGS. 1 to 8 for a P-channel trench implementation. Thus, using the reference numerals used in FIGS. 1-8, the bidirectional die 130 of FIG. 12 integrates two devices in a single die. The two devices correspond to the reference numerals in FIG. 4 , respectively, labeled A and B, but on a common substrate 50 . Two respective gate structures are also provided, each having the structure of FIGS. 5 and 6 . A substrate metal portion 131 is also shown.

The circuit diagram of the bidirectional device is shown in FIG. 13 and consists of two MOSFETs 140 and 141 . The two MOSFETs 140 and 141 are each connected to the source terminal S<sb>1</sb>, S<sb>2</sb>), gate terminal (G<sb>1</sb>, G<sb>2</sb>) and common drains 50 and 131 to form a bidirectional conductive circuit. MOSFETs 140 and 141 are vertically conductive devices with each body diode (not shown in FIG. 13) conducting when the other MOSFET is turned on.

14 and 15 are top views of the die 130 or chip of FIG. 12 . The chip 130 may have a lower portion of the conductive drain electrode 131 ( FIG. 15 ), and a gate sphere electrode G having each gate runner or bus 142 and 143 .<sb>1</sb>, G<sb>2</sb>) has The drain electrode 131 is a thick metal layer (compared to the thickness of the conventional source electrode) and low resistance. The bottom conductor 131 may be removed if the P+ substrate 50 has sufficiently high conductivity and may be useful as a heat sink.

The source electrode of each of the FETs 140 and 141 has two or more electrode protrusions S as shown in FIG. 14 .<sb>1</sb>, S<sb>2</sb>) has S<sb>1</sb> overhang and G<sb>1</sb> The distance between the protrusions is S<sb>2</sb> overhang and G<sb>2</sb> It is equal to the distance between the protrusions.

According to another aspect of the present invention, the height of the chip or die 130 is greater than the width. Therefore, it is not a square, but a long rectangle. In addition, the die protrusion (S<sb>1</sb>, S<sb>2</sb>, G<sb>1</sb>, G<sb>2</sb>) is symmetric with respect to the diagonal of the die 130 (the dashed diagonal line 150 in FIG. 14 ). Therefore, the source and gate electrodes are in the same position regardless of the top/bottom direction of the chip. Since the die has rotational symmetry, there is no need for pin marking and a simple pattern recognition device can determine the die direction or position when attaching to the surface.

As pointed out above, according to the present invention, the source ball (S1) is in a line or column parallel to the line of the source ball (S2) spaced apart.

16, 17, 18 and 19 show arrangements that can be replaced with FET1 (FET 140) and FET2 (FET 141) of FIGS. 13, 14 and 15. Here, like numbers refer to like parts. The silicon die of FIGS. 16-19 may have an area of about 0.120"x0.120". Note that in each case, the source balls S1 and S2 are positioned vertically and parallel, respectively, making it easy to use straight conductors for parallel connection by straight metal strips or straight metal wires on the printed circuit board. In addition, the sources of the FETs 140 and 141 are alternately arranged in Figs. 17, 18 and 19 to increase their connection area. The arrangement of Figure 19 is particularly advantageous because it keeps the two source metal protrusions together while minimizing the distance the current travels in the substrate. In this way, both the substrate and metal resistance are very low, while the connection at the substrate becomes very easy.

While the present invention has been described in connection with specific embodiments thereof, many other variations, modifications and other uses will be apparent to those skilled in the art. Accordingly, the present invention is not limited to the specific disclosure herein, but only by the appended claims.