Data access circuit of semiconductor memory device

DATA ACCESS CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

1 is a conventional write data line control circuit diagram of a semiconductor memory device having multiple ports.

2 is a write timing diagram of a conventional semiconductor memory device;

3 is a read data line control circuit diagram of a conventional semiconductor memory device having multiple ports;

4 is a read timing diagram of a conventional semiconductor memory device;

5 is a write data line control circuit diagram of a semiconductor memory device having multiple ports according to an embodiment of the present invention;

6 is a read data line control circuit diagram of a semiconductor memory device having multiple ports according to an embodiment of the present invention;

7 is a detailed circuit diagram of the first to fourth read/write data controllers 210, 212, 214, and 216 according to an embodiment of the present invention.

8 is a write timing diagram of a semiconductor memory device according to an embodiment of the present invention;

9 is a read timing diagram of a semiconductor memory device according to an embodiment of the present invention;

* Explanation of the symbols for the main parts of the drawing *

200: light control unit 300: lead control unit

210, 212, 214, 216: read/write data control unit

220, 222, 224, 226: first to fourth port parts

230, 232, 234, 236: buffers for first to fourth writes

240, 340: data line 250: input/output driver

320, 322, 324, 326: buffers for first to fourth reads

350: input / output sense amplifier

<backgroundart><p>The present invention relates to a data access circuit of a semiconductor memory device, and more particularly, to a data access circuit of a semiconductor memory device that reads or writes data through all multiple ports in a semiconductor memory device having a multi-port structure.</p><p>In general, a random access memory device is a type of digital memory device having bit data and memory cells for storing digital data. In any memory cell, it is possible to perform addresses and accesses independently of other memory cells.</p><p>The random access memory (RAM) includes a read-only memory (ROM) and a read/write memory (RAM). Both ROM and RAM include various types of memory devices of static load, synchronous, and asynchronous. RAM also has a static memory structure and a dynamic memory structure. In a static memory architecture, several types of latch storage are used, while in a dynamic memory structure, several types of dynamic storage of the charge of a capacitor are used.</p><p>Dynamic RAM (DRAM) and Synchronous Dynamic RAM (SDRAM) are a kind of dynamic structure and are widely used commercially in various types of digital devices. In particular, SDRAM is very widely used because it can be accessed in a very short time. The memory cells of the memory array of the SDRAM are usually divided into banks of memory cells, and the SDRAM includes a circuit for enabling operation in the "burst mode". In this 'burst mode', access is possible at a speed much higher than the access speed achievable in a memory cell of a conventional asynchronous DRAM.</p><p>SDRAM, like other memory devices, is tested in its manufacturing process in order to confirm that the memory cell operates properly. During this test, data of known values is written into the memory cells of the memory array bank. Data is assigned by various address sequences, and is usually assigned to all of the memory cells of the memory array.</p><p>As with other memory devices, as the capacity of the SDRAM increases, the time required to write data to all memory cells of the bank of the memory array also increases. If the required time is increased in this way, the throughput (though-put) of the memory device is reduced in the test process.</p><p>SDRAM is designed to satisfy the standard and communication protocol set by JEDEC (Joint Electronic Device Engineering Counsil). In the current standard and protocol by JEDEC, the signal protocol of the execution signal of the address of the memory cell of the SDRAM is determined. For example, an address selection signal is determined. When this address selection signal is applied to the SDRAM, the address of the memory cell of the SDRAM is executed.</p><p>When testing the SDRAM, a series of address selection signals are applied to the memory, and the memory cells of the memory device are addressed in response to the values of the address selection signals. Then, data is written into the addressed memory cell. Data written to the memory cell is sequentially written to the memory cell.</p><p>Usually, an algorithm in software is executed by a processor, and an address selection signal is generated on the address selection line. The memory cells are addressed in response to the values of the address selection signals generated on all address selection lines given to the SDRAM except for the next bit of the most significant bit. Therefore, when testing the SDRAM, in the software algorithm used for generating the address selection signal, it is impossible to access all the memory cells of the SDRAM by simply generating the address selection signal incremented by one bit.</p><p>US Patent No. 5,671,392 discloses a technique capable of simultaneously addressing columns for a plurality of memory banks and simultaneously writing to memory cells in an SDRAM of a semiconductor memory device or a memory device having a plurality of memory banks to solve this problem. . U.S. Patent No. 5,671,392 makes it possible to simultaneously address columns of a memory bank and to simultaneously read or write data.</p><p>Also, a multi-port access memory capable of reducing the size of a memory by sharing a read and write data path with an address decoder for read and write is disclosed in U.S. Patent No. 6,122,218. </p><p>However, in the semiconductor memory device having such a multi-port structure, read and write ports are configured in one port, and all data input/output (Data Input/Output) lines share the same port of all ports. </p><p>1 is a circuit diagram of a write data line control of a conventional multi-port semiconductor memory device.</p><p> The write control unit 10 is enabled by the write control signal Write and receives the column cycle signal Colcyc and outputs an input/output driver enable signal, and the first to first to output serial data are converted into 512 parallel data. 512 parallel data output from the fourth port unit 20 , 22 , 24 , 26 and the first port unit 20 are buffered by the first port selection signal Load_P0 and outputted to the data line 40 . a first buffer unit 30 for writing, and a second buffering the 512 parallel data output from the second port unit 22 by a second port selection signal Load_P1 and outputting them to the data line 40 . A write buffer unit 32 and a third write buffer for buffering 512 parallel data output from the third port unit 24 by a third port selection signal Load_P2 and outputting them to the data line 40 . part 34; a fourth write buffer unit 36 for buffering 512 parallel data output from the fourth port unit 26 by a fourth port selection signal Load_P3 and outputting the buffer unit to the data line 40; and the data line It consists of an input/output driver 50 that receives 512 data input from 40 and outputs data to input/output lines IO0 to IO511 by the input/output driver enable signal output from the write control unit 10. .</p><p>2 is a write timing diagram of a conventional semiconductor memory device.</p><p>An operation of controlling a data line when writing data will be described with reference to FIGS. 1 and 2 . In order to write data to the memory cell, when an address is input like Addre of FIG. 2 and a column latch signal Collat like Collat of FIG. 2 is input, a column decoder (not shown) generates a column select signal CSL. Connect the bit line and the input/output lines (IO0~IO511). In addition, the write control unit 10 is enabled by a write control signal (Write) such as Write in FIG. 2 , receives a column cycle signal (Colcyc) such as Colcyc in FIG. 2, and transmits an input/output driver enable signal to the input/output driver 50 print out At this time, serial data for writing is applied to the first to fourth port units 20, 22, 24, and 26, and the first to fourth port units 20, 22, 24, and 26 receive the serial data and are shown in FIG. Like PORT0 to PORT3 of , each of 512 parallel data is converted and output to the first to fourth buffer units 30, 32, 34, and 36 for writing. At this time, the first to fourth port selection signals Load_P0 to Load_P3 are sequentially generated in units of one cycle of the column latch signal Collat like Collat of FIG. 2 . The first to fourth write buffer units 30 , 32 , 34 and 36 sequentially transfer 512 write data to data lines ( WD of FIG. 2 ) according to the first to fourth port selection signals Load_P0 to Load_P3. 40) is output. At this time, 512 data input from one port is mapped to one column address. The 512 pieces of data output to the data line 40 are applied to the input/output driver 50 , and the input/output driver 50 receives the data line ( 40) and output the 512 data applied to the input/output lines (I/O0 to I/O511). </p><p>3 is a read data line control circuit diagram of a conventional multi-port semiconductor memory device.</p><p>The read control unit 100 that is enabled by the inverted write control signal (Write) and receives the column cycle signal (Colcyc) to output an input/output sense amplifier enable signal, and input/output lines (I/O0 to I/O511) An input/output sense amplifier 140 that receives 512 read data input from the read controller 100 and outputs it to the data line 130 according to an input/output sense amplifier enable signal output from the read control unit 100, and the data line 130 ) buffered by the first port selection signal (Load_P0) of 512 parallel data input from the first read buffer unit 120 for outputting to the first port unit 110, and the input from the data line (130) A second read buffer unit 122 for buffering the 512 parallel data by a second port selection signal (Load_P1) and outputting it to the second port unit 112; a second read buffer unit 124 for buffering 512 parallel data input from the data line 130 by a third port selection signal Load_P2 and outputting it to the third port unit 114; A fourth read buffer 126 for buffering 512 parallel data input from 130 by a fourth port selection signal Load_P2 and outputting them to a fourth port 116, and the first to fourth It consists of first to fourth port units 110, 112, 114, and 116 that receive 512 parallel data output from the read buffer unit 120, 122, 124, and 126, convert the data into serial data, and output the converted data.</p><p>4 is a read timing diagram of a conventional semiconductor memory device.</p><p>An operation of controlling a data line when data is read will be described with reference to FIGS. 3 and 4 . In order to read data stored in the memory cell, when an address such as Addr of FIG. 4 is input and a column latch signal Collat such as Collat of FIG. 4 is input, a column decoder (not shown) generates a column selection signal CSL. to connect the bit line and the input/output lines (I/O0 to I/O511). Then, the read control unit 100 is enabled by the inverted write control signal (Write) as shown in the Write of FIG. 4, receives the column cycle signal (Colcyc) of FIG. 4, and transmits the input/output sense amplifier enable signal to the input/output sense amplifier 140. output as At this time, 512 pieces of data read from the memory cells are applied to the I/O sense amplifier 140 through the input/output lines I/O0 to I/O511. The input/output sense amplifier 140 is enabled by the input/output sense amplifier enable signal output from the read control unit 100 and outputs 512 parallel data reads to the data line 130 . At this time, the first to fourth port selection signals Load_P0 to Load_P3 are sequentially generated in units of one cycle of the column latch signal Collat as in Load_0 to Load_3 of FIG. 4 . The first to fourth read buffer units 120 , 122 , 124 , and 126 sequentially transmit the first to fourth read data as shown in RD of FIG. 4 according to the first to fourth port selection signals Load_P0 to Load_P3. It outputs to the fourth port unit (110, 112, 114, 116). The first to fourth port units 110 , 112 , 114 , and 116 sequentially output read data like Port0 to Port3 of FIG. 4 . Accordingly, during the read operation, 512 pieces of data output through any one column cycle are outputted through any one of the four first to fourth port units 110 , 112 , 114 , and 116 . For this reason, assuming that the data output during one column cycle is, for example, 512 bits, 512 data output from one port unit, through the four first to fourth port units 110 , 112 , 114 , 116 . Each 512 data is divided into 4 and outputted respectively. Therefore, if the column cycle operation time in the memory is ignored, the multi-port memory having four first to fourth port units 110 , 112 , 114 , and 116 outputs data by four column read operations. The time for outputting data from one of the four first to fourth port units 110, 112, 114, and 116 takes 2.usec if the system clock is 100 MHz, for example.</p><p>In the conventional memory device having a multi-port unit as described above, since the memory cell test equipment has a low frequency of about 25 MHz, it takes about 2 usec to output all 512 data, so that the time to test the memory is 18DQ. It is several times to several tens of times longer than that, and there is a problem in that the productivity is lowered. </p></backgroundart><abstractproblem><p>Accordingly, it is an object of the present invention to provide a data access circuit of a semiconductor memory device having a multi-port structure capable of improving productivity by reducing a memory cell test time by reducing data input/output time in order to solve the above problems. </p></abstractproblem>

<p>A data access circuit of a semiconductor memory device having multiple ports according to an embodiment of the present invention for achieving the above object is enabled by a write control signal (Write) and receives a column cycle signal (Colcyc) to enable an input/output driver A write control unit for outputting a signal, a plurality of ports for receiving serial data for writing, converting it into a predetermined number of parallel data and outputting each, and a plurality of port selection signals for selecting a corresponding port among the plurality of ports ( Load_P) and a port selection disable signal Prll_Data_en, a plurality of read/write data control units for outputting port selection buffer enable signals and port selection buffer disable signals, and from the plurality of read/write data control units A plurality of data lines are simultaneously outputted to data lines by buffering parallel data output from each port among the plurality of ports during a column latch cycle period by the output port selection buffer enable signals and port selection buffer disable signals. Light buffers and and an input/output driver that receives data input from the data lines and outputs the data to a plurality of input/output lines in response to an input/output driver enable signal output from the read/write control unit. </p><p>A data access circuit of a semiconductor memory device having multiple ports according to another embodiment for achieving the above object is enabled by an inverted write control signal (Write) and receives a column cycle signal (Colcyc) to receive an input/output sense amplifier enable signal an input/output sense amplifier for receiving read data input from a plurality of input/output lines and outputting the read data to the plurality of data lines by an input/output sense amplifier enable signal output from the read controller a plurality of read/write data controllers receiving a plurality of port selection signals Load_P and a port selection disable signal Prll_Data_en and outputting port selection buffer enable signals and port selection buffer disable signals; A plurality of reads for buffering parallel data respectively input from the data lines by the port selection buffer enable signals and port selection buffer disable signals output from the plurality of read/write data controllers and simultaneously outputting them to the plurality of ports with buffers for and a plurality of port units for receiving parallel data output from the plurality of read buffer units, converting the data into serial data, and outputting the same. </p><p>A data access circuit of a semiconductor memory device having multiple ports according to another embodiment for achieving the above object is enabled by a write control signal Write, receives a column cycle signal Colcyc, and outputs an input/output driver enable signal a write control unit that receives serial data for writing, converts it into a predetermined number of parallel data and outputs each, and a plurality of port units that receive parallel data output from a plurality of read buffer units and convert it into serial data and output; A plurality of ports receiving a plurality of port selection signals Load_P and a port selection disable signal Prll_Data_en for selecting a corresponding port among the plurality of port units and outputting port selection buffer enable signals and port selection buffer disable signals with read/write data controllers of Buffers parallel data output from each port unit among the plurality of port units in a column latch cycle period by the port selection buffer enable signals and port selection buffer disable signals output from the plurality of read/write data control units a plurality of write buffers that simultaneously output data to data lines, and output data to a plurality of input/output lines by an input/output driver enable signal output from the read/write controller after receiving data input from the data lines an input/output driver that is enabled by an inverted write control signal (Write) and receives a column cycle signal (Colcyc) and a read control unit that outputs an input/output sense amplifier enable signal; and read data input from a plurality of input/output lines an input/output sense amplifier for receiving and outputting read data to the plurality of data lines according to the input/output sense amplifier enable signal output from the read control unit; Buffering the parallel data respectively input from the data lines by the port selection buffer enable signals and the port selection buffer disable signals output from the plurality of read/write data control units, and outputting them to the plurality of port units at the same time It is characterized in that it includes a plurality of read buffer units. </p><p>The plurality of port units is 4, and one port unit among the 4 port units outputs 512-bit data.</p><p>The plurality of read/write control units output a port selection buffer enable signal for selecting 128-bit data from one port unit among the four port units.</p><p>The plurality of buffers output 128-bit data respectively output from the four ports according to the port selection buffer enable signals output from the plurality of read/write controllers.</p><p>The plurality of read/write data controllers include a plurality of MUXs connected in units of 4 so that only 128 bits of 512 bits of data output from each port are connected to a memory cell, and the plurality of MUXs are formed in units of 4 to output one port selection enable signal for selecting the corresponding port.</p><p>Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.</p><p>5 is a write data line control circuit diagram of a semiconductor memory device having multiple ports according to an embodiment of the present invention.</p><p>The write control unit 200 is enabled by the write control signal Write and receives the column cycle signal Colcyc and outputs an input/output driver enable signal, and the first receives serial data, converts it into 512 parallel data, and outputs each. to the fourth port units 220 , 222 , 224 , 226 , the first to fourth port selection signals Load_P0 to Load_P4 , and the port selection disable signal Prll_Data_en to receive the port selection buffer enable signals and the port The first to fourth read/write data control units 210 , 212 , 214 , and 216 output selection buffer disable signals, and the port selection buffer enable signal output from the first read/write data control unit 210 . a first write buffer unit 230 for buffering 128 pieces of parallel data output from the first port unit 220, respectively, and outputting them to the data lines 240 according to the port selection buffer disable signals; By buffering 128 parallel data output from the second port unit 220 by the port selection buffer enable signals and the port selection buffer disable signals output from the second read/write data control unit 212, respectively. The second write buffer unit 232 output to the data lines 240 , and the port selection buffer enable signals and the port selection buffer disable signals output from the third read/write data control units 214 . a third write buffer unit 234 for buffering 128 parallel data output from the third port unit 224 and outputting them to data lines 240, and the first read/write data control unit ( 216) by buffering the 128 parallel data output from the fourth port unit 226 by the port selection buffer enable signals and the port selection buffer disable signals outputted from the buffer and outputting them to the data lines 240 a fourth buffer unit 236 for writing; The input/output driver 250 receives the data input from the data lines 240 and outputs the data to the input/output lines I/O0 to I/O511 according to the input/output driver enable signal output from the write control unit 200 . is composed of</p><p>6 is a read data line control circuit diagram of a semiconductor memory device having multiple ports according to an embodiment of the present invention.</p><p>The read control unit 300 is enabled by the write control signal (Write) inverted through the inverter (I1) and receives the column cycle signal (Colcyc) to output the input/output sense amplifier enable signal, and the input/output line (I/ An input/output sense amplifier 350 which receives the read data input from O0 to I/O511 and outputs the read data to the data line 340 by the input/output sense amplifier enable signal output from the read control unit 300; , first to fourth read/ The write data controllers 210 , 212 , 214 , and 216 and the 128 parallel input from the data line 340 by the port selection buffer enable signals output from the first read/write data controller 210 , respectively a first read buffer unit 330 for buffering data and outputting it to the first port unit 320; 128 parallel data input from the data line 340 is buffered by the port selection buffer enable signals output from the second read/write data control unit 212 and outputted to the second port unit 322 . Buffers 128 parallel data input from the data line 340 by the second read buffer unit 332 and the port selection buffer enable signals output from the third read/write data controller 210 . and the third read buffer unit 334 outputted to the third port unit 324 and the data line 340 by the port selection buffer enable signals output from the fourth read/write data control unit 216 . A fourth read buffer unit 336 for buffering 128 parallel data inputted from each and outputting them to a fourth port unit 326, and the first to fourth read buffer units 320, 322, 324, 326 ) first to fourth port units 320, 322, 324, which receive parallel data output from 326) is composed.</p><p>7 is a detailed circuit diagram of the first to fourth read/write data controllers 210, 212, 214, and 216 according to an embodiment of the present invention.</p><p>The first to fourth read/write data control units 210 , 212 , 214 , and 216 are each composed of four MUXs M1 to M4, and when one port is configured to access 128 data, the one of the read/write data control unit should be provided with 32 parts composed of four MUXs (M1 to M4). </p><p>The first read/write control unit 210 has a first port selection signal (Load_P0) connected to the input terminal (A) of the four MUXs (M1 to M4), and the ground voltage signal (Vss) is connected to the input terminal (B). One of the first port selection signal Load_P0 and the ground voltage signal Vss is selected by the selection disable signal Prll_Data_en to output the port selection buffer enable signals and the port selection buffer disable signals. </p><p>The second read/write control unit 212 has a second port selection signal (Load_P2) connected to the input terminal (A) of the four MUXs (M1 to M4), and the ground voltage signal (Vss) is connected to the input terminal (B). One of the second port selection signal Load_P1 and the ground voltage signal Vss is selected by the selection disable signal Prll_Data_en to output port selection buffer enable signals and port selection buffer disable signals.</p><p>The third read/write control unit 214 is configured such that the third port selection signal Load_P2 is connected to the input terminal A of the four MUXs M1 to M4 and the ground voltage signal Vss is connected to the input terminal B. One of the first port selection signal Load_P2 and the ground voltage signal Vss is selected by the selection disable signal Prll_Data_en to output port selection buffer enable signals and port selection buffer disable signals. </p><p>The fourth read/write control unit 216 has a fourth port selection signal (Load_P3) connected to the input terminal (A) of the four MUXs (M1 to M4), and the ground voltage signal (Vss) is connected to the input terminal (B). One of the first port selection signal Load_P3 and the ground voltage signal Vss is selected by the selection disable signal Prll_Data_en to output port selection buffer enable signals and port selection buffer disable signals. </p><p>8 is a write timing diagram of a semiconductor memory device according to an embodiment of the present invention;</p><p>9 is a read timing diagram of a semiconductor memory device according to an embodiment of the present invention.</p><p>A data line access operation according to a preferred embodiment of the present invention will be described in detail with reference to FIGS. 5 to 9 described above.</p><p>First, the operation of controlling the data line when writing data will be described. In order to write data to the memory cell, when an address is input like Addre of FIG. 8 and a column latch signal Collat like Collat of FIG. 8 is input, a column decoder (not shown) generates a column select signal CSL. Connect the bit line and the input/output lines (IO0~IO511). In addition, the write control unit 200 is enabled by a write control signal (Write) such as Write in FIG. 8 and receives a column cycle signal (Colcyc) such as Colcyc in FIG. 8 to transmit an input/output driver enable signal to the input/output driver 250 print out At this time, serial data for writing is applied to the first to fourth port units 220, 222, 224, and 226, and the first to fourth port units 220, 222, 224, 226 receive serial data and are shown in FIG. Each of 512 parallel data is converted into PORT0 to PORT3 of , and output to the first to fourth buffers for writing (230, 232, 234, 236). At this time, the first to fourth port selection signals Load_P0 to Load_P3 are generated for each cycle of the column latch signal Collat like Collat of FIG. 8 . The first to fourth write buffer units 230 , 232 , 234 , and 236 simultaneously transmit a total of 512 write data in parallel as shown in WD of FIG. 8 according to the first to fourth port selection signals Load_P0 to Load_P3 . output to line 240 .</p><p>The operations of the first to fourth read/write data controllers 210 , 212 , 214 and 216 will be described in detail with reference to FIG. 7 , </p><p>The first port selection signal Load_P0 as shown in FIG. 8 is applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M1, respectively, and the ground voltage signal Vss is the MUX (M2 to M2). It is applied to the input terminal (B) of M4). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 8, the MUX (M1) selects the first port selection signal (Load_P0) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs M2 to M4 select the ground voltage signal Vss input to the input terminal B to respectively output the port selection buffer disable signal.</p><p>The second port selection signal Load_P1 as shown in FIG. 8 is respectively applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M2, and the ground voltage signal Vss is the MUX (M1, It is applied to the input terminal (B) of M3~M4). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 8, the MUX (M2) selects the first port selection signal (Load_P1) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs M2 to M4 select the ground voltage signal Vss input to the input terminal B to respectively output the port selection buffer disable signal.</p><p>The third port selection signal Load_P2 as shown in FIG. 8 is respectively applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M3, and the ground voltage signal Vss is the MUX (M1 to M4). It is applied to the input terminal (B) of M2 and M4). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 8, the MUX (M2) selects the third port selection signal (Load_P2) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs (M1 to M2, M4) select the ground voltage signal Vss input to the input terminal (B) to output a port selection buffer disable signal, respectively.</p><p>The fourth port selection signal Load_P3 as shown in FIG. 8 is applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M4, respectively, and the ground voltage signal Vss is the MUX (M1 to M4). It is applied to the input terminal (B) of M3). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 8, the MUX (M4) selects the fourth port selection signal (Load_P3) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs M1 to M3 select the ground voltage signal Vss input to the input terminal B to respectively output the port selection buffer disable signal.</p><p>In this way, the first buffer unit 230 for writing receives 512 data output from the first port unit 220 and transmits 128 pieces of data like Port0 of FIG. 8 which is enabled by the first port selection signal Load_P0. It is buffered and output to the data line 240 . The second buffer unit 232 for writing receives 512 data output from the second port unit 220 and buffers 128 data as in Port1 of FIG. 8 that is enabled by the second port selection signal Load_P1. output to the data line 240 . The third buffer unit 234 for writing receives 512 data output from the third port unit 224 and buffers 128 data as in Port2 of FIG. 8 that is enabled by the third port selection signal Load_P2. output to the data line 240 . The fourth buffer unit 236 for writing receives 512 data output from the fourth port unit 226 and buffers 128 data as in Port3 of FIG. 8 that is enabled by the fourth port selection signal Load_P3. output to the data line 240 . Therefore, the first to fourth buffer units 230 , 232 , 234 , and 236 buffer 128 data, respectively, and output a total of 512 data to the data line 240 at the same time as in WD of FIG. 8 .</p><p>The data output to the data line 240 is applied to the input/output driver 250 , and the input/output driver 250 responds to the input/output driver enable signal output from the write control unit 200 to the data line 240 . Outputs the applied data to the input/output lines (I/O0 to I/O511). </p><p>An operation of controlling a data line when data is read will be described with reference to FIGS. 6, 7 and 9 . In order to read data stored in the memory cell, when an address such as Addr of FIG. 9 is input and a column latch signal Collat such as Collat of FIG. 9 is input, a column decoder (not shown) generates a column selection signal CSL. to connect the bit line and the input/output lines (I/O0 to I/O511). Then, the read control unit 300 is enabled by the write control signal (Write) inverted through the inverter (I1) as shown in Write of FIG. 9 and receives the column cycle signal (Colcyc) of FIG. 9 to provide an input/output sense amplifier enable signal. It outputs to the input/output sense amplifier 350 . At this time, data read from the memory cell is applied to the I/O sense amplifier 350 through the input/output lines I/O0 to I/O511. The input/output sense amplifier 350 is enabled by the input/output sense amplifier enable signal output from the read control unit 300 and outputs the read parallel data to the data line 340 . At this time, the first to fourth port selection signals Load_P0 to Load_P3 are simultaneously generated for each cycle of the column latch signal Collat like Load_0 to Load_3 of FIG. 9 . The first to fourth read buffer units 330 , 332 , 334 , and 336 simultaneously transmit read data to the first to fourth ports according to the first to fourth port selection signals Load_P0 to Load_P3 as shown in RD of FIG. 9 . output to the units 320 , 322 , 324 , 326 . The first to fourth port units 320 , 322 , 324 , and 326 simultaneously output read data in parallel like Port0 to Port3 of FIG. 9 .</p><p>The read operation of the first to fourth read/write data controllers 210, 212, 214, and 216 will be described in detail with reference to FIG. 7, </p><p>The first port selection signal Load_P0 as shown in FIG. 9 is applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M1, respectively, and the ground voltage signal Vss is the MUX (M2 to M2). It is applied to the input terminal (B) of M4). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 9, the MUX (M1) selects the first port selection signal (Load_P0) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs M2 to M4 select the ground voltage signal Vss input to the input terminal B to respectively output the port selection buffer disable signal.</p><p>The second port selection signal Load_P1 as shown in FIG. 9 is respectively applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M2, and the ground voltage signal Vss is the MUX (M1, M1, It is applied to the input terminal (B) of M3~M4). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 9, the MUX (M2) selects the first port selection signal (Load_P0) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs M2 to M4 select the ground voltage signal Vss input to the input terminal B to respectively output the port selection buffer disable signal.</p><p>The third port selection signal Load_P2 as shown in FIG. 9 is applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M3, respectively, and the ground voltage signal Vss is the MUX (M1 to M4). It is applied to the input terminal (B) of M2 and M4). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 9, the MUX (M2) selects the third port selection signal (Load_P2) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs (M1 to M2, M4) select the ground voltage signal Vss input to the input terminal B to output a port selection buffer disable signal, respectively.</p><p>The fourth port selection signal Load_P3 as shown in FIG. 9 is applied to the input terminal A of the MUXs M1 to M4 and the input terminal B of the MUX M4, respectively, and the ground voltage signal Vss is the MUX (M1 to M4). It is applied to the input terminal (B) of M3). At this time, when the port selection disable signal (Prll_Data_en), which is the selection signal, transitions to the high state as shown in FIG. 9 , the MUX (M4) selects the fourth port selection signal (Load_P3) input to the input terminal (B) to become the port selection buffer. The enable signal is output, and the MUXs M1 to M3 select the ground voltage signal Vss input to the input terminal B to respectively output the port selection buffer disable signal.</p><p>In this way, the first read buffer 330 receives 512 data output from the data line 340 and buffers 128 data like Port0 of FIG. 9 enabled by the first port selection signal Load_P0. It outputs to the first port unit 320 . The second read buffer unit 332 receives 512 data output from the data line 340 and buffers 128 data as in Port1 of FIG. 9 which is enabled by the second port selection signal Load_P1. output to the port unit 322 . The third read buffer unit 334 receives 512 data output from the data line 340 and buffers 128 data as in Port2 of FIG. output to the port unit 324 . The fourth read buffer unit 336 receives 512 data output from the data line 340 and buffers 128 data as in Port3 of FIG. output to the port unit 326 . Accordingly, the first to fourth read buffer units 320 , 322 , 324 , and 326 buffer 128 data, respectively, and simultaneously transmit a total of 512 data pieces to the first to fourth port units 320 and 322 as shown in WD of FIG. 9 . , 324, 326) respectively.</p><p>Therefore, during the read operation, data output through any one column cycle is simultaneously outputted through the four first to fourth port units 320, 322, 324, 326, 128 bits each, for a total of 512 bits of data. . </p><p>Therefore, since the multi-port memory having four port units 320, 322, 324, 326 outputs 512 bits of data by 128 bits by one column read operation, the data output time depends on the system clock, for example. At 100 MHz, it becomes 0.5 usec. </p><p>In the present invention, data output to one port unit at a time is described as 128 bits as an example. However, in a multi-channel memory having n-bit read and write data data lines and m ports, data is divided by n/m. A corresponding MUX should be provided in each port. </p>

<p>As described above, in the present invention, in a semiconductor memory device having multiple ports, data is not accessed at once to a designated port, but data is divided and accessed to all port units at the same time. It can be shortened as much as possible, which has the advantage of improving productivity.</p>