Image processing apparatus

Image processing device {IMAGE PROCESSING APPARATUS}

1 is a block diagram of a conventional image processing apparatus;

2 is a view showing an embodiment of the present invention.

3 is a detailed block diagram of the single instruction multiple data processor of FIG. 2;

Fig. 4 is a detailed block diagram of a program memory in Fig. 2;

Fig. 5 is a detailed block diagram of the data memory unit in Fig. 2;

FIG. 6 is a detailed block diagram of a PCI interface unit in FIG. 2 .

*****Explanation of symbols for main parts of the drawing *****

100 : PCI interface part

110-1 to 110-4: 1st - 4th single instruction multiple data processor

120 : program memory 130: program memory control unit

140 : data memory unit

<background-art><p>The present invention relates to an image processing apparatus, in particular, using a single instruction multiple data (SIMD) type processor to simultaneously operate segmented image data with the same instruction, and transfer the processed data to a PCI bus. It relates to an image processing apparatus suitable for high-speed transmission using</p><p>1 is a block diagram of a conventional image processing apparatus, and as shown therein, an ISA interface unit 10 for interfacing with a host computer (not shown); 1st - 4th digital signal processing unit (20-1~20-4) of Multiple Instruction Multiple Data (MIMD) type for multi-processing input image data connected in a daisy chain method Wow; a link adapter 30 for transmitting a control signal through the AI interface unit 10 to each of the digital signal processing units 20-1 to 20-4; a memory 40 for storing the image data input through the AI interface unit 10 and the operation results of each of the digital signal processing units 20-1 to 20-4; a shared memory 50 for sharing the processing results of the digital signal processing units 20-1 to 20-4 with each other; first to fourth multiplexers (60-1 to 60-4) for controlling the flow of input/output data of each of the digital signal processing units (20-1 to 20-4); It is composed of a JTAG input unit 70 , a JTAG output unit 80 , and a JTAG adapter 90 for controlling the digital signal processing units 20-1 to 20-4 and controlling the status registers.</p><p>In the description of the drawings, unexplained reference numeral 100 denotes a digital signal processing link for connection with other external digital signal processing units, and 110 and 120 extend the additional functions of each of the digital signal processing units 20-1 to 20-4. It is a shared adapter and a specific use connector for this purpose.</p><p>The operation of the conventional apparatus configured as described above will be described as follows.</p><p>First, when image data and a control signal are input from the host computer through the ISA interface unit 10 , the ISA interface unit 10 receives the input and transmits the control signals through the link adapter 30 to the first through fourth It is applied to the digital signal processing units 20-1 to 20-4, and the image data is stored in the memory 40.</p><p>Each of the digital signal processing units 20-1 to 20-4 receiving the control signal from the link adapter 30 transfers the image data stored in the memory 40 to the first-fourth multiplexers 60-1 to 60- 4) receives input and processes it.</p><p>At this time, the data generated during processing is first stored in the shared memory 50 so that the digital signal processing units 20-1 to 20-4 share with each other, and when the processing is completed, it is stored in the memory 40 again. transmitted to the host computer.</p><p>If you want to arbitrarily adjust the operation of each digital signal processing unit 20-1 to 20-4, the control state value of each digital signal processing unit 20-1 to 20-4 is transferred to the JTAG adapter 90 and the JTAG output unit. After checking through (80), a new control value may be input through the JTAG input unit (70).</p></background-art><tech><p>As described above, in order to accelerate image data processing, a conventional device processes a general processor or a digital signal processing processor, which is a multi-instruction, multi-data type processor, in parallel. It requires segmentation work to efficiently Accordingly, there was a problem that an additional circuit was required.</p><p>It is an object of the present invention to simultaneously operate divided image data with the same instruction by using a single instruction multi-data type processor having a plurality of processors without internal memory means in order to solve this conventional problem, An object of the present invention is to provide an image processing apparatus capable of transmitting processed data at high speed using a PCI bus.</p></tech>

<p>An image processing apparatus for achieving the object of the present invention includes: a PCI interface means for an interface with a host computer; a plurality of single-instruction multi-data processors that simultaneously process input divided image data by the same instruction; a program memory storing basic instructions; a program memory control means for reading a corresponding command from the program memory according to a control signal from a host computer inputted through the PCI interface means, and applying the corresponding command to each of the single command multiple data processors; Data memory means for receiving the image data signal from the host computer inputted through the PCI interface means and applying it to the single command multiple data processor, and receiving the output signal of the single command multiple data processor and transmitting it to the host computer consist of</p><p>Hereinafter, an embodiment will be described with respect to the operation and effect of the present invention.</p><p>FIG. 2 is a view showing an embodiment of the present invention, and as shown in FIG. 2, a PCI interface unit 100 for interface with a host computer (not shown); first to fourth single command multiple data processors 110-1 to 110-4 for simultaneously processing inputted divided image data by the same command; a program memory 120 storing basic instructions; According to a control signal from a host computer input through the PCI interface unit 100, a corresponding command is read from the program memory 120 and applied to each of the single command multiple data processors 110-1 to 110-4. a program memory control unit 130; It receives the image data signal from the host computer input through the PCI interface unit 100 and applies it to the single command multiple data processors 110-1 to 110-4, and the single command multiple data processor 110 -1 to 110-4) and the data memory unit 140, which receives the input signal and transmits it to the host computer.</p><p>The single instruction multiple data processors 110-1 to 110-4 include a decoder 111 for decoding an input control signal as shown in FIG. 3; It consists of a plurality of processors PE1 to PE128 that simultaneously receive the output signal of the decoder 111 and simultaneously process the input image data.</p><p>The program memory control unit 130 includes a decoding unit 131 for decoding and outputting a control signal input through the PCI interface unit 100 and an output signal of the program memory 120 as shown in FIG. 4; a loop address register 132 that checks and outputs a loop address from the output signal of the decoding unit 131; a jump address register (133) for checking and outputting a jump address from the output signal of the decoding unit (131); a loop counter 134 for counting the number of loops according to the control signal; Address counter ( 135) and; When the command signal of the program memory 120 is input through the decoding unit 131, it is converted into a command suitable for the single command multiple data processor 110-1 to 110-4 and applied to the command register 136. make up</p><p>The data memory unit 140 includes address registers 141 and 142 for outputting address signals corresponding to control signals of the PCI interface unit 100 or the program memory 120 as shown in FIG. 5; an address counter control unit (143,144) for outputting a counter control signal according to the input control signal; address counters (145, 146) for counting and outputting the output signals of the address registers (141, 142) according to the control signals of the address counter controllers (143, 144); SRAMs 147 and 148 for storing/outputting signals input according to control signals; and SRAM control units 149 and 150 that output control signals for controlling the SRAMs 147 and 148 according to a control signal input through the PCI interface unit 100 .</p><p>An operation of an embodiment of the present invention configured as described above will be described as follows.</p><p>First, the single instruction multiple data processors 110-1 to 110-4 take the program memory 120 out of the chip and separately install it, and replace all the remaining space with the processor. Accordingly, 128 processor elements (PE1 to PE128) can be arranged in one single instruction multiple data processor (110-1 to 110-4).</p><p>First, when image data and control signals are input from the host computer through the PCI bus, the PCI interface unit 100 interfaces with them and applies them to the program memory control unit 130 and the data memory unit 140 .</p><p>For reference, the general PCI interface unit 100 is configured as shown in FIG.</p><p>When the control signal from the host computer is applied to the program memory control unit 130 through the PCI interface unit 100 , the decoding unit 131 interprets it and provides a loop address register 132 and a jump address register 133 . ) is approved.</p><p>Accordingly, the loop address register 132 outputs a loop value, and the jump address register 133 outputs a jump value.</p><p>The address counter 135 receiving the rope value and the jump value counts according to the frame start signal. At this time, the loop counter 134 counts the loop value.</p><p>When the count value is output from the address counter 135, the program memory 120 outputs a corresponding command.</p><p>Then, the decoding unit 131 also decodes it and applies it to the instruction register 136, and the instruction register 136 converts the input instruction into an instruction suitable for the single instruction multi-data processor 110-1 to 110-4. to approve</p><p>In addition, the address register 141 of the data memory unit 140 receiving the data signal through the PCI interface unit 100 outputs a corresponding address value, and the address counter control unit 143 controls the address counter 145 . output a signal for</p><p>Then, the address counter 145 counts the output signal of the address register 141 and applies it to the SRAM 147 . At this time, the SRAM control unit 149 controls the SRAM to apply the stored data to the single instruction multiple data processors 110-1 to 110-4.</p><p>As described above, the single command multiple data processors 110 - 1 to 110 - 4 receiving the data signal from the data memory unit 140 process the input data according to the control signal from the program memory control unit 130 .</p><p>At this time, since the single-instruction multi-data processors 110-1 to 110-4 simultaneously receive the same command from the program memory control unit 130, they simultaneously process the output data of the data memory as the same command.</p><p>In addition, since the single instruction multiple data processors 110-1 to 110-4 are composed of one decoder 111 and 128 processor elements PE1-PE128 as shown in FIG. 3, the processing speed is high.</p><p>The data processed by the single command multiple data processors 110 - 1 to 110 - 4 is applied to the data memory unit 140 again, stored therein, and then transmitted to the host computer through the PCI interface unit 100 .</p><p>In this case, a PCI bus is used as a transmission bus between the PCI interface unit 100 and the host computer.</p>

<p>As described in detail above, the present invention uses a single-instruction multi-data type processor having a plurality of processors without a memory means therein to simultaneously operate the divided image data with the same instruction, and the processed data is transmitted using the PCI bus, which has the effect of speeding up data processing.</p>