Synchronous digital line distribution apparatus

[Name of invention]

Synchronous digital circuit distribution unit

[Brief Description of Drawings]

1 is an overall configuration diagram of a synchronous digital circuit distribution (SDH DXC) device.

2 is an STM-N signal frame structure diagram.

3 is a block diagram of a signal input connection unit;

4 is a block diagram of an AU frame aligner.

5 is a block diagram of a signal output connection unit;

6 is a block diagram of a signal path monitor.

7 (a) is a block diagram of the unconnected signal monitoring and generator.

7 (b) is a timing diagram for monitoring a disconnection signal and occurrence of a disconnection state.

8 is a timing structure diagram according to data types;

(a) of FIG. 8 is a timing diagram of 77.76Mb/s parallel mode.

(b) of FIG. 8 is a timing diagram of 51.84 Mb/s serial mode.

FIG. 8(c) is a timing diagram of 19.44Mb/s parallel mode.

FIG. 8(d) is a 6.48Mb/s parallel mode timing diagram.

* Explanation of symbols for main parts of the drawing

100 : STM-N signal connection part 200 : AU signal monitor

300 : AU switch 210 : Downlink signal input connection part

220 : AU frame aligner 230 : Downlink signal output connection part

240 : Signal path monitor 290: Unconnected signal monitoring and generator

[Detailed Description of the Invention]

The present invention relates to a Synchronous Digital Hierarchy Digital Cross-Connection (SDH DXC) device with enhanced signal monitoring function. After connecting with the optical cable through which the optical signal is transmitted, receiving the STM-N optical signal, undergoing optical/electrical conversion, data recovery and clock extraction, and then through descrambling and reframing for STM-N, section overhead (SOH) :Section overhead) and payload are processed separately, and the AU signal is extracted from the separated STM-N payload and the phases of each frame are rearranged by the same reference timing, and then cross connect switching (XCS) in units of AU :Cross-Connect Switching), and the switched AU signal is multiplexed back to STM-N together with SOH, converted into an optical signal, and transmitted through an optical cable. In addition, it monitors the AU signal input to the switch and detects the unoccupied signal to release the contact with the switch of the corresponding signal channel and perform signal termination processing. It is to smoothly manage the synchronous signal path switching and AU level circuit distribution functions.

In the synchronous transmission network to which the SDH DXC device is applied, a spare channel for protection must always be monitored/managed for reconfiguration/recovery when a transmission network line/path is disconnected. It is necessary to thoroughly manage unconnected signals by monitoring the signal connection status for each switching unit (AU traffic light) at the front and rear ends of the .

It is an object of the present invention to facilitate the wideband switching function in AU units by aligning AU frames between the synchronous signal connection part of a synchronous digital broadband circuit distribution (SDH DXC) device and a wideband switch and monitoring and processing the VC3 path, and also An object of the present invention is to provide a synchronous digital circuit distribution device capable of monitoring an unoccupied (unconnected) signal and generating and transmitting an unconnected signal state, thereby performing path monitoring and circuit distribution of a synchronous signal.

In order to achieve the above object, the present invention provides an STM-N signal receiving unit 110 that receives an STM-N optical signal, performs optical/electrical conversion, data recovery, and clock extraction, and is connected to the signal receiving unit in a section within the STM-N. A demultiplexer that extracts and outputs N AUG (AU4) or 3xN AU3 signals by processing overhead (SOH) and 77.76Mb/s 8-bit parallel signal or 12 51.84Mb/s serial signals, or 4 19.44Mb Synchronous signal connection having a multiplexing unit that inputs an 8-bit parallel signal and multiplexes it into an STM-N signal form by inserting SOH and an STM-N signal transmission unit that converts the STM-N electrical signal into an optical signal and transmits it through an optical cable Way; AU frame phase alignment that is connected to the synchronous signal connection means and rearranges the frame phase for AU3 or AU4, and performs VC3 path monitoring, non-equipped signal state detection, signal non-equipped state generation and AU frame formation for a signal whose switching is released; signal monitoring means; and an AU switching means connected to the AU frame phase alignment and signal monitoring means to perform cross-connect switching of AU3 units or AU4 units.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of the present invention, and is a configuration example of an SDH DXC device having an STM-4 (600M)-class capacity, that is, an AU signal monitor that processes 4 AU4 or 12 AU3 signals.

First, the downlink input unit 210 receives 4 AUG signals 3 from the synchronous signal connection unit 100, separates 12 SU3 signals, and converts them into 4 signals AU frame sorter 220 and signal path monitor 240. send to The AU frame aligner 220 separates the AU pointer word from the received AU signal 4 to extract the frame offset supporting the VC3 phase, separates the VC3 signal from it, and sends it to the signal path monitor 240 . The separated VC3 signal is applied to the pointer buffer by the write clock together with the frame offset, the data once written to the buffer is read by the read clock coming from the downlink output unit 230, and the read data is newly generated by the read frame offset. It is inserted into the AU pointer frame and output as 6 signals. The signal path monitor 240 separates and processes VC3 path overhead (POH: Path Overhead) and analyzes C2 bytes to monitor the unmounted state. (250). The downlink output unit 230 multiplexes the frame rearranged AU3 signal from the AU frame aligner 220 into the AUG signal form using the external clock timing 9 to the control signal 8 coming from the CPU interface 250 . It is converted to the appropriate signal rate (7) selected by the AU switch (300). Then, the uplink input unit 280 separates the 12 AU3 signals 11 from the AUG signal 100 coming from the AU switch 300 and sends them to the selector 270 and the unconnected signal monitoring and generator 290 .

In the selector 270, whether to select the switched AU signal 11 coming from the upstream input unit 280 by the control signal 8 from the CPU interface 250, or a self-generated signal coming from the unconnected signal generator 12 Determines whether to select the AU signal. The signal 13 thus selected is transmitted to the upstream output unit 260 .

The unconnected signal monitoring and generator 290 monitors 11 signals and detects a state in which there is no signal, that is, a state in which the switch connection is released, and reports it to the CPU interface 250, and also sends the AU signal 12 by itself. generated and sent to the selector 270 .

The upstream output unit 260 multiplexes each AU3 signal received from the selector 270 in the form of AUG, and uses the external clock timing 15 and the control signal 8 of the CPU interface 250 to obtain an appropriate signal speed 14. converted and output to the synchronization signal connection unit 100 .

3 is a block diagram of the downlink and uplink signal input connection units 210 and 280, which is applied to both the uplink and the downlink, and the case of the downlink signal will be described here. The input data d3, clock c3, and frame clock f3 are applied in three modes (refer to FIG. 8) by the control signal p1 from the input mode selector 211, that is, a 77.76 Mb/s parallel signal. It operates in the connection mode (see FIG. 8 a), the 51.84 Mb/s serial signal connection mode (see FIG. 8 b), and the 19.44 Mb/s parallel signal connection mode (see FIG. 8 c). In the 78M connection mode, d3 data is a 77.76Mb/s 8-bit parallel signal in the form of an STM-4 signal, c3 is a 77.76MHz data clock, and f3 is an 8KHz reference timing clock. The selected signals (d78, f78, c78) are demultiplexed and divided at the 78M connection unit 212, so that 12 6.48Mb/s 8-bit AU3 parallel signals (d6a) and 6.48MHz AU3 parallel signal clocks (c6a) and 6.48Mb/s It is converted to an 8KHz frame clock f6a with an s pulse width. In the 52M connection mode, 12 d3 data is a 51.48Mb/s serial signal including one AU3 signal, c3 is a 51.84MHz data clock, and f3 is an 8KHz reference timing clock. The selected signals (d52, f52, c52) are demultiplexed and divided by the 52M connection unit 213, so that 12 6.48Mb/s 8-bit AU3 parallel signal (d6b) and 6.48MHz AU3 parallel signal clock (c6b) and 6.48Mb/s It is converted into an 8KHz frame clock f6b with an s pulse width.

In the case of 19M connection mode, four d3 data are input as 19.44Mb/s 8-bit parallel signals containing one AUG signal, c3 is a 19.44MHz data clock, and f3 is an 8KHz reference timing clock. The selected signals (d19, f19, c19) are demultiplexed and divided at the 19M connection unit 214 to include 12 6.48Mb/s 8-bit AU3 parallel signal (d6c) and 6.48MHz AU3 parallel signal clock (c6c) and 6.48Mb/s. It is converted to an 8KHz frame clock (f6c) with an s pulse width. The signals converted to 6.48 Mb/s data in this way select the data d4, frame clock f6, and data clock c6 of one of the three modes by the control signal p2 in the 6M data/clock selector 215. do. The selected f6 and c6 are fed to a timing generator 216 where it generates a new clock c4 and timing 14 .

4 is a block diagram of the AU frame aligner 220, and performs an AU pointer processing function.

The input AU3 data d4, frame clock f4, and data clock c4 enter the pointer interpreter 221, where the pointer interpreter 221 separates the AU pointer word from the AU3 data into three states: NORM, Detects AIS and LOP status, generates an alarm interrupt signal (p3) in case of AIS or LOP status VC3 data d5 separated from the generated frame offset timing f5 are written together in the pointer buffer 222 as a VC3 data clock C5. When the pointer justfication (PJ) state is reflected in the received pointer value, the state is reflected in the offset timing f5 and the write clock C5 of the pointer buffer. That is, in the positive adjustment (+PJ) state, the offset timing is pushed by one clock gap, and in the negative adjustment (-PJ) state, the offset timing is advanced by inserting one clock. The VC3 data dg and the frame offset fg output from the pointer buffer 222 are read by the read clock cg. The buffer monitoring circuit 224 accumulates when the speed difference between the read clock cg and the write clock c5 occurs, and when the threshold value of the pointer buffer is reached, the state bc is transferred to the pointer buffer 222 and the pointer adjustment circuit. (225). At this time, the write clock (c5) and the read clock (cg) are compared. If c5 is fast, the buffer is filled to the upper side, and in the positive threshold (+th) direction, if c5 is late, the buffer is emptied to the lower side and negative. It moves in the direction of the threshold (-th). Also, when the buffer becomes full or empty by exceeding the threshold, the buffer goes down and abnormal data is output, which is immediately reported to the CPU by signal P4. The buffer is reset to its original state by resetting itself. The initial state refers to the state in which the write address and the read address of the buffer are farthest apart.

The pointer adjustment circuit 225 receives the buffer threshold arrival signal bo generated from the buffer monitoring circuit 224, and generates the transmission pointer adjustment signal jo according to the transmission data clock c6 and the timing t6 to generate a pointer. It sends to the device 223, and reports the status (p5) to the CPU.

The pointer generator 223 generates a pointer value according to the frame offset fg passed through the pointer buffer, forms an AU3 signal d6 together with the VC3 data dg, and outputs it. In addition, the pointer generator 223 reflects the pointer adjustment signal jo based on the system clock c6 and the timing t6 to the data clock cg, the transmit pointer, and the AU3 signal d6.

FIG. 5 is a block diagram of the signal output connection units 230 and 260, which is applied to both the uplink and the downlink. Here, the case of the downlink signal will be described. The timing generating circuit 231 has different clocks c9 and f9 received from the outside depending on the operation mode, and generates the same clock timings c6 and t6 regardless of the mode. The 78M conversion unit 232 multiplexes 12 pieces of 6.48Mb/s parallel AU3 data (d6) in the STM-4 structure form and converts them into 77.76Mb/s parallel data (d78), and the 52M conversion unit 233 multiplexes 12 pieces of data. Each of the 6.48Mb/s parallel AU3 data (d6) is converted into 12 pieces of 51.84Mb/s serial data (d52), and the 19M conversion unit 234 converts 12 pieces of 6.48Mb/s parallel AU3 data (d6) into three multiplexes. After making it into AUG, it is converted into 19.44Mb/s parallel data (d19) in the form of STM-1 frame. The output mode selection circuit 235 selects one mode data by CPU or an external control signal p5 for the data and output converted to each mode, and selects the selected data d7, the frame clock f7, and the data clock ( c7) is output.

6 is a block diagram of the signal path monitoring 240, VC3 timing generating circuit 241, VC3 path overhead data extraction circuit 242, B3 error monitoring circuit 243, VC3 path and unmounted signal monitoring circuit ( 244), detects the VC3 path monitoring and unequipped status (UNEQ) and transmits it to the CPU.

7 is a block diagram of the unconnected signal monitoring and generator 290. The non-signal detector 291 monitors 12 pieces of 6.48Mb/s AU3 parallel data d11 from the upstream input unit 280 for each signal. If the state in which the signal is disconnected, that is, all 0 continues for 5 consecutive frames, the signal is detected as a no-signal state, that is, not connected, and the AU pointer generator 292 and the VC3 signal former and the CPU interface with the p10 signal. and clears the state when a continuous 5 frame signal is detected. In addition, an unconnected state is also generated by the control signal p11 of the CPU. The VC3 signal former 293 reflects the state in the C2 byte of the VC3 path overhead when no signal is input, forms a VC3 signal v11, and sends it to the AU frame former 294. At this time, the position of the first byte of the VC3 frame used is determined. The offset (f11) of the pointing frame is sent to the AU pointer generator 292 . The AU pointer generator 292 generates an AU pointer u11 with the VC frame offset received from the VC3 signal former 293 based on the system timing t11 and sends it to the AU frame former 294 . The AU frame former 294 multiplexes the AU pointer u11 and the VC3 signal v11 to form an AU signal frame d12 and sends it to the signal selector 270 .

1, the AU switch 300 separates the AU signal from the 7 signals coming from the AU monitor 200, performs AU unit switching under the control of the CPU, and outputs the output signal 10 in the same form as the input signal. and sends a value of 0 to the output for a signal path without a switching connection (ie, an AU signal with a switching connection released). This allows the AU monitor to quickly determine the state in which the switch connection is released.

As described above, this synchronous digital circuit distribution device with enhanced signal monitoring function arranges the AU signal monitor between the synchronous signal transmission unit and the AU switch to convert the signal speed, process the AU3 or AU4 pointer, VC3 or VC4 path and signal connection status. It can be flexibly applied to various signal speeds and types (77.76Mb/s parallel, 51.84Mb/s serial, 19.44Mb/s parallel) by performing functions such as monitoring and signal generation of disconnected state, and ITU-T Recommendation G Acceptance of asynchronous AU signal and absorption of jitter/wonder through AU pointer processing that satisfies .783, and realigning the frame phase of each AU signal frame included in STM-N at the same system reference timing to achieve AU unit switching It has the effect of making it possible to do this smoothly, and monitoring/managing the signal path (channel resource) that is not connected to the switch so that it can be used as a spare channel.