Semiconductor integrated circuit device with gate array and memory

[Detailed Description of the Invention]

[Summary of the Invention] It is related with the integrated circuit which has the gate array and memory which were able to provide the function to examine a memory, The form of the wiring which can constitute the number of input-and-output bottles few, and it uses at the time of examination mode is constituted in fixation, and useless leading about of wiring is lost, Test signal system wiring is considered as the fixed wiring which is fixation to all devices regardless of the specification of a device for the purpose of making eye the stage and manufacture easy, Usually, signal system wiring is considered as the automatic wiring respectively corresponding to the specification of the device, the input/output terminal of usual signal system wiring of 1 and the input/output terminal of test signal system wiring of 1 are in the input-and-output pin of 1 J3, and are considered as combination, and it consists of the input-and-output pin of 1 as composition which can usually output and input a signal and a test signal. [Industrial Application] The present invention relates to the semiconductor integrated circuit device which has a gate array and a memory, and the semiconductor integrated circuit device which was able to provide the function to do memory appearance consignee Examination etc. especially. In such integrated circuit 5A Place, memory appearance consignee Examination is done on the maker side for the improvement in reliability. In this case, it is required to constitute so that a wiring field may be used effectively, without establishing the memory test circuit in the semiconductor integrated circuit device, and being able to constitute the number of input-and-output bottles few as much as possible, and taking about wiring vainly. [Description of the Prior Art] Drawing 4 shows the schematic diagram of a device conventionally. A gate array and 3 are RAM 1*2 among the figure. As for 4, a test signal input terminal and 6 are usually output terminals a signal input terminal and 5. On the other hand, although there are usually a signal system and a test signal system as wiring which connects between gate array 1, RAM3, and gate array 2, each of these is considered as automatic wiring (wiring which it differs for every device and is suitably wired corresponding to the specification). Namely, it is formed for every product with the circuit pattern formation process formed using computers, such as intellect it was decided that the logic circuit of a gate array would be, etc. Here, usual signals, such as an address signal, a block select signal, a fortune-telling lump signal, and usual input data, are usually supplied to terminal 4 at the time of the mode. Usually, input data is supplied to RAM3 via gate array 1, is written in from the block selected with the block select signal, and is written in the memory cell array of RAM3 by a signal. The usual output data read from here is picked out from output terminal 6 via gate array 2. Next, test signals, such as an address signal, a block select signal, a write-in signal, and examination input data, are supplied to terminal 5 at the time of examination mode. Examination input data is supplied to RAM3 via gate array 1, is written in from the block selected with the block select signal, and is written in the memory cell array of RAM3 by a signal. The examination output data read from here is picked out from output terminal 6 via gate array 2. Here, the state of RAM3 can be checked with examination output data. [Problem(s) to be Solved by the Invention] The number of input-and-output bottles usually increases in that of There is no setting in an input-and-output bottle with signal input terminal 4 and separate test signal input terminal 5, and the above-mentioned conventional device is [ this ] a sake, The original number of use bottles of a gate array will be deleted for the bottle for test signals, and there was a problem that gate array 1.2 could not be used effectively. According to automatic wiring of a signal system, it is usually considered as automatic wiring, and wiring of a test signal system is [ this ] a sake, The test signal system wired, and it was influenced by the specification of the device, and had to wire for every device of the, useless leading about of wiring increased, and, moreover, there was a problem which needs much time for a design and manufacture. The present invention can constitute the number of input-and-output bottles few, and does not have useless leading about of wiring, and an object of the present invention is to provide the semiconductor integrated circuit device which can perform Establishment Si l and manufacture easily. [Means for Solving the Problem] Drawing 1 shows the whole present invention device lineblock diagram. RAM by which it is examined 12.13, and 10*11 are gate arrays among the figure. 18 is usually signal system wiring and is considered as automatic wiring, and 17 is test signal system wiring and is considered as fixed wiring. 151 and 161 are the input output sections containing an input-and-output bottle, and are input-and-output bottles which are usually considering an input/output terminal of signal system wiring, and an input/output terminal of test signal system wiring as combination. [Function] Since the input/output terminal of F M system wiring and the input/output terminal of test signal system wiring are usually made to serve a double purpose in one input-and-output bottle in the present invention, Since the number of input-and-output pins can be conventionally constituted few as compared with vtl and test signal system wiring is considered as fixed wiring, wiring is not taken about vainly and design and manufacture are performed for a short time, and it is Applaud. [Example] A present invention device is mainly concerned with Drawing 2, it shows the fixed wiring diagram of a test signal system, and draws it in a chip image. A gate array (logic composition) and 12.13 are RAM 10.11 among the figure. 14 is I10 terminal field and 15.16 is an I10 buffer part which has I10 terminal (input-and-output bottle group) in I10 terminal field 14. Among the figure, thick line 17 which carried out black-colored is fixed wiring of a test signal system, and is [ as opposed to / regardless of the specification of a device / all devices ] fixation. Usually, automatic wiring 18 of a signal system is suitably wired outside the field of fixed wiring 17 corresponding to the specification of the device. Automatic wiring 18 connects gate array 10, RAM12.13, and gate array 11, and fixed wiring 17 connects RAM12.13 without gate array io and 1i. the after-mentioned -- like -- the input terminal of fixed wiring (test signal system) 17 and automatic wiring (usually signal system) 18 -- every of I10 terminal 15 -- in I / OE Completion (input-and-output bottle), it is considered as combination. Drawing 3 (△) ~ (C) shows the concrete lineblock diagram of field A-C shown in Drawing 2 with a dashed line, respectively. Drawing 3 (A) In ~ (C), a test signal system terminal and O are connecting points for which as for - a signal system terminal and a solid line connect one-layer wiring, a dashed line connects two-layer wiring, and <> usually connects one-layer wiring and two-layer wiring. Drawing 3 (110 copy 15I in which 110 buffer parts 15 which have I10 terminal have I10 terminal 15 P andI10 buffer 15B in A>.) It consists of 152 and ... Each I10 copy 15z, 15z. Test signal system fixed wiring 17 pulled out from ... is wired in the inside of a wiring field without gate array 11. 110-copy each 151,152. ... was Draw out(ed) -- signal system automatic arm Fi118 is wired in the inside of fields other than fixed wiring 17, and is usually connected to gate array 11. in this case, fixed location! the input terminal of J17 and automatic wiring 18 -- I/002 child's 15 - -- 110 copies (input-and-output Hin) are considered as 151, 152, and - Stop combination. In Drawing 3 (B), while fixed wiring 17 by which I10 terminal 15 was Draw out(ed) is wired by RAM12, fixed wiring 17 pulled out from RAM12 is wired by 110 Asthma 16. Automatic wiring 18 pulled out from gate array 10 is wired in the inside of fields other than fixed wiring 17, and is connected to RAM12. Here, 20 is a change gate which comprises a 0R-AND circuit, fixation -- wiring -- 17 -- the mode -- a change -- a signal -- a system -- fixation -- wiring -- 17 -- ' -- from -- for example, -- L -- a level -- the mode -- a change -- a signal -- TM -- supplying -- having -- things -- RAM -- 12 -- an examination -- the mode -- one -- " -- a level -- the mode -- a change -- a signal -- supplying -- having -- things -- RAM -- 12 -- usually -- the mode -- respectively -- switching . In Drawing 3 (C), fixed wiring 17 by which automatic wiring 18 and RAM12 which were pulled out from the gate array were Draw out(ed) is wired by A NOR gate 21 of l10E child 16f7 110 copy 161, and is connected to Bud 22 of 161 110 copies. 23 is a power source line and is considered as two-layer fixed wiring. Thus, a present invention device makes the input terminal of a test signal system, and the input terminal of a usual signal system serve a double purpose in one input-and-output bottle, it constitutes them so that each signal of a signal and a test signal can usually be taken from one input-and-output bottle, and it is considering fixed wiring and wiring of a usual signal system for wiring of a test signal system as automatic wiring. Although the above-mentioned example is the composition which a gate array and RA M provided two each at a time, the composition which it provided one large Every at a time may be used. (EFFECT OF THE INVENTION) As explained above, in the present invention, an input/output terminal of Jinja system wiring and an input/output terminal of test signal system wiring are usually made to serve a double purpose in one input-and-output pin. Therefore, as compared with a device, the number of input-and-output bottles can be constituted few conventionally which constituted these from a separate input-and-output bottle, and it is [ this ] a sake, Since an original input-and-output pin of a gate array is not shaved, and a gate array can be used effectively and test signal system wiring is considered as fixed wiring, Since it is uniform and delay etc. of a signal transmitted in wiring in an examination process can set up all circuit patterns for an examination uniformly, even if it is a gate array from which useless leading about of wiring is lost, and a circuit pattern differs for every product, It examines for a short time by a process of forming a pattern for a bubble Keep it. examination in a circuit pattern which is not based on a product at a gate array, can manufacture by the ability to perform the same examination in a short time, and is different for every product becoming unnecessary, and is 1! 7 To.

[Brief Description of the Drawings]

The concrete lineblock diagram of some fields which Drawing 2 shows Drawing 1 in the whole present invention device lineblock diagram, show it in the fixed wiring diagram of a test signal system, and show Drawing 3 in Drawing 2, and Drawing 4 are formerly schematic diagrams of Purchasing. In a figure, 10.11 is a gate array and 12.13 is RAM, 15, and '16I10 terminal (input-and-output bottle group), 151.152. ... and 161 -- test signal system fixed wiring and 17' show mode change signal system fixed wiring, 18 shows signal system automatic wiring, and, as for I10 copy (input-and-output pin) and 17, ... usually shows a change gate 20. 4215B It is a 1 shoulder 94 Formation figure of Wood wax B to N43 figure (A) leather 2 old things in += 7r and a ↑ Calamity A Everyv A beak. The '3 figure (B)