Method and apparatus for digital signal with low bit transmission speed in time-slot of time-sharing multiplex signal provided for high bit rate transmission speed

[Detailed Description of the Invention]

Field of the Invention the present invention -- a transmission by a time slot sake -- ♂ Tut access speed Niji of a digital signal -- it is related with the transmission method and device of a Time-Division-Multiplexing signal which use high bit access speed. Conventional technology Set about digital signal-Multiplex [ primary ] Imitation at the apparatus of written Nice to meet you to 46th page ~ the 51st page of an appendix "digital transmission art" of telcon reportNQ2 (1979). 6 with which Is 32 synchronizes A 4 kbit/s-signal is one 'l l]. It is unified by the division multiplex signal temporarily [ 48 kbit/e ]. The problem which an invention tends to solve As for Champion of the present invention, the digital signal of the bit access speed between 0.6 k1it /theta and 19.2 kbit/s is also Si occasionally instead of a 64 kbit/s-signal, the key which can perform circuit technical cost without a loss -- Si -- it is in the thing which can be made small and can be transmitted and for which method Death and dropping Rk offer is made. The means for solving a problem The above-mentioned problem leaves the method of the form stated to the beginning, and is the transmitting side about the 1st digital signal, The 1st clock corresponding to this time slot is transmitted by the 2nd digital signal all Time-Division-Multiplexing signal that carried out the fault sampling by the item and was obtained by To Ueberabtasten and the above-mentioned Overheard-ization, and is a receiving side, after demultiplexing, the 2nd digital signal is solved by [ which are sampled except for a prohibition phase position field, and a double sampling does not generate with the 2nd clock signal corresponding to the bit access speed ] carrying out for obtaining two. In this case, are advantageous, In order to form the pulse which carries out A process overlap at an impulse and prevents a prohibition phase position field Only one cycle of the 1st clock signal is delayed in the 2nd digital signal, and it is as 3rd digital signal. only the 1st two clock [3 No. cycle being delayed in the 2nd digital signal, and forming the 4th digital signal, in processing succeedingly -- the 2nd digital signal and the 4th digital signal full-exclusive OR combination -- it carries out. EFFECT OF THE INVENTION It is composition Beautiful digital signal-1 order so that the 64 kbit/s-signal of 26 can be unified by the present invention. The digital signal of low bit access speed can also be occasionally transmitted by Multiplex apparatus. EXAMPLE Drawing 1 shows the digital signal of the bit access speed of 19.2 kbit/s. As for this, digital signal DS2 is transmitted by clock pulse T1 of the frequency of 64 kHz generating To 9 by that of sampling Sale To. It takes to a receiving side, and lever n is Engineering(ed) p sampled by clock signal T2 of the frequency of 19 to 2 kHz (an arrow shows an effective side edge). The tatami is shown at least for two Stand phases of L Scratchy lock signal T2 in T2a and T2b. Digital signal DS2 can be sampled convenient with clock signal T22L. in the sampling by T2b, it generates by the double sampling which bit error BF sometimes boils and occurs. At least digital signal DS2 and two phases of clock signal T2 show 1'1iT2C Death worn'I'2d, Drawing 2 may be in the phase position field in phase position T2C A wedding dress T2d of This n and others to which it is shown by the slash, and a double sampling may generate it. Such field prohibition phase field VB of all the is called. Drawing 3 shows the formation method of pulse P, and the pulse covers prohibition phase position field VB. For this reason, since only one cycle of clock signal T1 is shifted on the other hand in order to form digital signal DS3, and digital signal DS4 is generated on the other hand, only two cycles of clock signal T1 of digital signal DS2 are shift To 9 To. Pulse P is formation To 9 To by the exclusive OR combination with digital signals DE12 and DS4. Digital signal DIE3 is processed following on instead of [ of digital signal DS2 ]. Prohibition phase position field VB is shown below. the --a [ 4 ] figure shows the device which enforces the method of the present invention in the transmitting side. This device is provided with track bunch 4 which connects series / shift register 3 for ' parallel conversion, parallel / shift register for in-series conversion 5, and both shift registers 3 and 5. If digital signal DS1 of the bit access speed of 19.2 kbLt/s is supplied to input side 1, from input l111 i2, the Engineering 9 series / parallel conversion of this signal will be carried out, and it will be supplied to clock signal T1 of frequency 754 kHz at shift register 5. This signal is read to the clock and signal T3 of frequency 2048 kHz from input side 8 Engineering 9 here (when the channel selection signal over one of the channels of 31 of a division multiplex mode is Increase(ed) from Input II temporarily [ 2048kbit /s ] in which data communications are possible). Digital signal DS2 is transmitted via output side 6. the --b [ 4 ] figure shows the device in a receiving side which carries out the present invention. this device is called Cyst register 11 and is as exclusive as 13 and 17 -- rroRr - 21, updown counter 22, logic circuit 23, D-Flop ropes 30 and 31, and counting-down circuit 33 A wedding dress 34 and 37 -- it has :Facial expression 38 and switch 36. The 5th A shows logic circuit 23 in detail. Logic circuits 23 are AND piece"-A 40 and 42 and 47.! : it has in Pata 41, D-flip-flop 43 A wedding dress 44 Death worn 45 A wedding dress 48, and exclusive oRf*-46. digital signal DS2 which was received and was separated by the demultiplexer is supplied to shift register 11 via input (the -- it is shown inb [ 4 ] figure -- as) side 9 -- l -- series / parallel conversion is carried out by clock signal T3 from input side 10 there, and it is inputted into shift register 13 via m A roof 12. If a channel selection signal is Increase(ed) from input side 15, it will be read via output 1111114 by Cramp signal T1 from input side 16, and shift register 13 to clock signal T6 is input Scold by clock signal T1 like shift register 17. The delay described by shift register 17 based on Drawing 3 is Doing n To. exclusive -- pulse P occurs in the output side of NOR piece"-21, and the pulse dormant period of pulse P acts as a window to Crout and Signal T2. this window -- digital signal DE13 -- D-flip-flop 30 -- : -- it shifts as digital signal DS5 via Facial expression 31 output fill]32 (unless logic circuit 23 does not supply a clear signal to counting-down circuit 33 via that output side 29 but a phase position is shifted by extension). clock signal T2 being formed from the clock signal of frequency 2043 kHz taken out from input side 39, i.e., clock signal T6 being Divide(ed) by the frequency of 1536 kHz with the introduction counting-down circuit 38, and being dependent on the position of switch 36 succeedingly first, -- direct -- or After 307.2 'KHz Divide with counting-down circuit 37, the input side of counting-down circuits 33 and 34 is supplied, and it Divide by the ratio of 2n:1. They are :ToQ, 75 kHz, 1.5 kHz, 3 kHz, 6kH2, i 2kHz, and Q to this clock signal generator. - (5kHz g - calling i) 2 kHz and 2-4kHz Okinawa 4.3 kHz -- the frequency of 19.2 kHz of :Facial expression 9-6kHz b Work is generated. The last 19.2 kHz was chosen in this example. Since That Jt which bit error TF generates is during transmission of digital signal DS2, It is because this field will change also with bit error BFs immediately if it is the number of examples which is not suitable for carrying out the re-synchronization (Neusynchronisation) of the sampling time for example, whenever a sampling time is located in a prohibition phase position field. Therefore, updown counter 22 is provided and a sampling side carries out clock control of the lever n by A. the calculation -- a direction is dependent on the surrounding window of a data side edge. When pulse P is a logic value "L" (low level) (This n may occur in a double sampling), it is calculated in the count-up direction. When pulse P is logic value"H" (high level) (in this case, there is no error generating), it is calculated in the countdown direction. When only the positive phenomenon which a double sampling does not generate is calculated and it is discrete value "0", a maximum side / the minimum output side, and by extension, the logic state of AND gate 400A power side 26 serve as "H". It is prevented that updown counter 22 calculates in the countdown direction succeedingly via logic circuit 26, and, as for updown counter 22, the number remains 5' of the count-up direction in Ma value" mouth "to Doing n To again as the result. If many negative phenomena occur one by one (in this case, a double sampling may occur), Azota * Uncounter 22 will be calculated in the count-up direction until it reaches discrete value"9''. In this value, they are the maximum / the minimum output ([9 and by extension, input side 26 shift to logic state"H".). Thus, sampling frequency re-synchronizes and, on the other hand, an initial discrete value is supplied to an updown counter. Logic circuit 23 shown in Drawing 5 in detail operates as follows. Pulse P which forms a window in input side 25 of inverter 41 is supplied. the bottom of a reversal pulse is taken out from output ■ To of inverter 41, and one input side of AND piece"-40 is supplied -- l -- input side 126 of this another side of AND l'-40 -- a pulse -- the discrete value of updown counter 22 -- Know is also supplied to a "mouth" also in discrete value"9''. When the logic state by the side of both inputs is "H" in a negative phenomenon, the output side of AND gate 40 is also "H''. As for the clock of updown counter 22, output side 128 of the item-control (enabling)-input side, connection To 9 ing, and AND gate 42 is logic (when logic state of input side 25 and input side 26 is "H") state "r (it is ".) to this. This is this To fit in, when an error can be generated by pulse P and the discrete value of updown counter 22 is "0." In a negative phenomenon, output side 28 will be in a logic state "L" to This n. When the D-input side of D-flip-flop 43 is logic state"H", Q-output side serves as logic state"H" with clock signal T3, Q-output side supplying logic state *L" to output @27, and passing this output side 27 further -- set (loading)-human power @'I K supply of updown counter 22 -- it carries out. Since logic state"H" from Q-output side reverses D-Fritznovlozo 44, Q-output side of D-flip-flop 44 serves as logic state"H" similarly. digital signal DS3 supplied to input fiII 24 -- D-flip-flop 45 and exclusive OR piece" -- it differentiates by having two incomes with - A 45. In that case, D-flip-flop 45 is delayed with clock signal T3 in digital signal DS3. When the input side of the both sides of AND gate 47 is logic state"H" (this occurs when updown counter 22 overflows), this logic state"H" is part cycle 33 all A reset(ed) with an output via D-flip-flop 48 in sync with reversal input side T3. 19-2 In order to re-synchronize clock signal T2 of the frequency of kHz, counting-down circuit 33 is cleared by arbitrary data side edges. The pulse dormant period of clock signal T2 occurs after this clear operation, and nine lines from a There is a drawer pulse dormant period to a pulse occur. This clear operation is separated from the data side edge in which only abbreviation - of 18 terms generates this clear operation in time. in the case of the re-synchronization with That Ha who generates a double sampling, setting an initial value can reach a discrete value "9" at an early stage, and it can re-synchronize at an early stage -- the second -- it is for making it like. Drawing 6 shows one another device in a receiving side which enforces the method of the present invention. This device is additionally provided with change switch 50, resistance 51, switch 52, and capacitor 54 as compared with the example of the 4th the b figure. additional constituent child of This n and others, 1 4.8 kbit/s Wing - calling -- This -- n -- upsilon -- error amendment to digital signal DS3 of small bit access speed can be performed. When transmitting a 64 kbit/s-data style by a Time-Division-Multiplexing signal in the case of error amendment, distortion Generic and bit error BP which A penitence at least a sampling time by chance do not make all the bits of digital signal DS3 of low bit access speed distorted. Because, it is because capacitor 54 is charged or discharged by digital signal Ds3, and is Really. Since this capacitor 54 is an accumulation constituent child, many pulses of digital signal DS3 always control that charge at the sampling time. The permission sampling value region of a window is shortened for error amendment. For this reason, the digital warm extraction delayed as compared with the digital signal from [ from output side 49 of shift register 17 ] output side 20 is supplied to exclusive NOR gate 21 via change switch 50. Drawing 7 shows digital signal DS3, change Sister pulse P and clock signal T2 which has the maximum allowable frequency of 5.3 kHz in this case, and capacitor voltage UC in point of measurement 53.

[Brief Description of the Drawings]

The 1st four is 69 figures showing the sampling of the 1st and 2nd digital signals, and is Really. : at least a prohibition phase indicates A helmet to be in Drawing 2 -- it is a parent figure. Drawing 3 is a Viscera figure showing formation of the pulse in which at least a prohibition phase carries out Mercenary overlap, and which it prevents. the --a [ 4 ] figure is a block circuit diagram of a device in the transmitting side which enforces the method of the present invention. the --b [ 4 ] figure is the Pronk figure of the 19th device that enforces the method of the present invention divided into a receiving side. Drawing 5 -- the device of Drawing 4 -- providing -- it is a detailed circuit diagram of the logic circuit of one n ing. Drawing 6 is in the block circuit of the 2nd device that enforces the method of the present invention in a receiving side. [which shows the pulse operation to an error amendment device [ in / in Drawing 7 / the device of Drawing 6 ] -- it is an owner] figure. 1 ... The input side of shift register 3 for digital signal DS1, 2 ... the input side of shift register 3 for clock signal T1, 3 ... shift register, 4 ... track bunch, 5 ... shift register, 6 -.. output side of CIF; and register 5 for digital signal DS2, 7 ... the input side of shift register 5 for a channel selection signal, 8 ... the input side of shift register 5 for the clock 1 A word T second, 9 ... The input side of shift register 11 for digital signal DS2, 10 ... the input side of shift register 5 for clock signal T6, 11 ... shift register, 12 ... track bunch, 13 ... CIF L / District, 14 ... the input side of shift register 13 for digital signal DS2, 15 ... Input I11. 16 of shift register 13 for a channel selection signal ... The input side of shift register 13 for clock signal T1, 17 ... shift register, 18 ... the 1st output side of shift register 17, 19 ... the 2nd output side of shift register 17, and the 6th output side of 20 river shift register 17, 21 ... exclusive NOR gate, 22 ... updown counter, 23 ... logic circuit, 24 ... the input side of logic circuit 23 for digital signal DS3, 25 ... the input side of logic circuit 23 for digital signal DS5, 26 ... the maximum -- /-- the minimum -- a signal -- a sake -- a logic circuit -- 23 -- an input -- a side -- 27 - .. loading -- a signal -- a sake -- a logic circuit -- 23 -- an output side --] 28 .. output side of logic circuit 23 for an enabling signal, 29 ... output 9111 of logic circuit 23 for a clear signal, 30 ... D-flip-flop, 31 ... D-flip-flop, 32 ... output side for digital signal DS3, 33, - and a counting-down circuit, 34 ... A counting-down circuit, 35 ... Output side for clock signal T2, 36 -.. change switch, 3 T ... counting-down circuit, 38 ... counting-down circuit, 39 ... the method side of A long time of counting-down circuit 38 for clock signal T3, 40 ... AND gate, 41 ... inverter, 42 -.. AND Ke ゞ-A, 43 *44.45 .. D-Flip-flop and 46 ... Exclusive -- OR Piece 9-A, 47 .. p, NDf'-, and 48 ... D-flip-flop and 49 ... the of shift register 17 4Output Club], and 50 ... a change switch and 51 ... resistance and 52 ... a switch and 53 ... the point of measurement and 54 .. a capacitor, BP ... A A beat error, Ds1+DS2.DS3.DS4.DS5 ... Digital signal, H ... a logic state -- A "high" and L ... a logic state "low" and P ... the pulse which covers prohibition phase Head mounted and which carries out a Pulse owner, TI, T2 [ ... Capacitor voltage, VB / ... Prohibition phase Head mounted. ] ... A clock signal, T2 a-T 2c ... The 2nd clock signal of a different phase position, T3 ... The 3rd clock signal, Uc IG I IG2 IG 3 l07 RF 41-inverter 43.44, 45.48 One~Off and j Noah floor ' A 46 Three Si Tsukiya last 9-, -I06 Procedure bucket ' right document (spontaneity) the Showa 62 one-person moon / ♂ day