Cycle stealing 1/0 controller
Abstract
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Term
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Expired 15 December 2002, 23.8 years ago.
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1 claim: 1 independent, 0 dependent
- 1[Claim(s)] 【特許請求の範囲】 1 1次データ処理サブシステム、周辺装置、および前記1次データ処理サブシステムと前記周辺装置の間をインタフエースする2次データ処理サブシステムを含むデータ処理システムにおいて、前記2次データ処理サブシステムは、前記1次データ処理サブシステムから受取つた1次コマンドを記憶する手段と、各々の前記記憶された1次コマンド中のモード・ビツトに応答して高速モードまたはプログラマブル・オフライン・モードのいずれかで前記2次データ処理サブシステムを動作させる手段と、前記2次データ処理サブシステムが前記高速モードで動作している時に作動されて前記周辺装置と前記1次データ処理サブシステム中のメモリとの間でデータを高速に転送するための手段と、複数の2次コマンドのアレイを記憶する手段と、前記2次データ処理サブシステムが前記プログラマブル・オフライン・モードで動作しているときに作動されて前記貯蔵されたアレイ内のコマンドにより定められる2次データ処理動作のプログラムを前記2次データ処理サブシステムに実行させる手段と、よりなり、前記2次データ処理動作は前記1次データ処理サブシステム内で同時に実行されている動作に対してオフラインの関係で実行され、且つ前記1次データ処理サブシステムからの支援または指示なしに、前前2次データ処理サブシステムが前記周辺装置または前記1次データ処理サブシステム中の前記メモリのいずれかとデータを交換し且つ前記データを処理することを可能にすることを特徴とするデータ処理サブシステム。 1 In Data Processing System Containing Secondary Data-Processing Subsystem Which Interfaces between Primary Data-Processing Subsystem, Peripheral Equipment, and Said Primary Data-Processing Subsystems and Said Peripheral Equipment, A means by which said secondary data-processing subsystem memorizes a primary receipt Ivy command from said primary data-processing subsystem, A means to answer mode A bit in each primary command memorized [ said ], and to operate said secondary data-processing subsystem in either high speed mode or programmable off-line mode, A means for operating, while said secondary data-processing subsystem is operating by said high speed mode, and transmitting data at high speed between said peripheral equipment and a memory in said primary data-processing subsystem, A means to memorize an array of a plurality of secondary commands, It becomes a means to make said secondary data-processing subsystem run a program of secondary data-processing operation defined by a command in an array operated and stored [ said ] while said secondary data-processing subsystem is operating in said programmable off-line mode, more, Said secondary data-processing operation is performed due to off-line to operation currently simultaneously performed within said primary data-processing subsystem, And have support from said primary data-processing subsystem, or no directions, A data-processing subsystem making it possible for a secondary beforehand data-processing subsystem to exchange either and data of said memory in said peripheral equipment or said primary data-processing subsystem, and to process said data.
15 paragraphs, as filed
[Detailed Description of the Invention]
Table of contents The outline of the technical field prior art of the technological background/present invention of an invention The outline of an invention DETAILED DESCRIPTION Details of a definition of explanation DCB of Drawings 1 thru/or 5 HS mode PO mode LPO type (6th [ The ] figure explanation is included) PO mode SPO type Interruption status information Residual status block (RSB) Secondary PO mode command The classification of the format command of a secondary command (command list) Data transfer (7th [ The ] figure explanation is included) internal data transmission between the insides of the exterior Accumulator operation Conditional jump Addition card hardware control (8th [ The ] figure explanation is included) device interface format (9th [ The ] figure explanation is included) microprocessor composition and the example of memory map (10th thru/or 12th [ The ] figure explanation are included) PO mode application A conversion check sum calculation program from the hexadecimal notation to 10 Advance The technological background of example of combination application double mode application (Drawing 13 thru/or The 15th figure explanation are included) Multiplex / demultiplexing application system action outline (Drawing 16 thru/or The 18th figure explanation are included) invention of PO and HS mode The technical field of the present invention The present invention requires the I/O operation relevant to a primary data-processing subsystem for the data processing system managed by the intelligent secondary data-processing subsystem containing a programmable microprocessor etc. The outline of a prior art Today's data processing system is using the programmable processor extensively with the I/O channel and the I/O controller, Management of the data transfer between peripheral equipment and a primary data-processing (host) subsystem (memory) (it is Line intermediary To have conventionally further about the mitigation of the duty of fixed course management of a primary data-processing subsystem, and channel selection assigned to host software.) In a certain system, a microprocessor has even these things that conform so that the conventional "secondary data processing function" (namely, matrix multiplication) may be performed as a satellite of a primary data-processing subsystem. However, such satellite operation is usual, It is strictly controlled by software of a primary data-processing subsystem, The data of a "student" is sent to a secondary data-processing subsystem from a primary data-processing subsystem, A primary data-processing subsystem prepares the command which orders execution of the operation which processes these data with a secondary data-processing subsystem, and also it is required to return the data "processed" to a primary data-processing subsystem. This type of hierarchy composition is not appropriate to support of management of a real-time operation when the time to transmission, attention, i.e., control directions, corresponding from the claim of the attention by a device, may require emergency, etc. In such an environment, the circuit competition in the resource of the primary data processing system by a real-time operation may not only produce an unjust interference in other important system actions. Primary data-processing subSIMM may bar giving timely attention to other urgent processing states. The outline of an invention As for the present invention, the thing of a primary data-processing subsystem (henceforth a primary subsystem) is separate (physically). Or the secondary data-processing subsystem which has a processor and a memory mechanism logically It acts as an I/O controller relevant to a device in (hereinafter, it is called a secondary subsystem), It makes it possible to act as a completely independent processor which has the capability to show one device address to a primary subsystem, or to acquire data from a device, to process the above-mentioned data without the support from a primary subsystem, and to control a device. It is enabled for a secondary subsystem to memorize "the secondary program" of a command again, and for the present invention to order the above-mentioned independent data acquisition, and to perform processing operation without the support from a primary subsystem with slight support. It is searched as one of the features of the present invention by 1 time per every One with "a device control block" or the primary command description child-secondary subsystem called DCB (from the memory of a primary subsystem). - The mode in which A bit which calls operation of a secondary subsystem in basic high-speed-data transmission mode or programmable off-line mode is Set(ed) is included. In high speed mode, data is transmitted between the memory (direct access is possible) of a primary subsystem, and a device. In programmable off-line mode, a secondary subsystem is adjusted so that one or more programs of the secondary command contained in the "command list" beforehand memorized by the secondary subsystem may be translated. A secondary subsystem acquires and processes data without support of a primary subsystem, and can control a device by these programs. A chain is possible for a primary command so that a secondary subsystem may be switched forward and backward dynamically between high speed mode and programmable off-line mode under the fixed real time state decided beforehand as 2nd feature of the present invention. For example, by this, the system user can point to a secondary subsystem, can make a small data item able to acquire and process in off-line mode, subsequently to high speed mode can switch a secondary subsystem, and can transmit other big data sets between a primary subsystem and a device. A secondary subsystem moves data between a device multiplexer and the memory field of a primary subsystem by the middle memory of the block portion of the data in a secondary subsystem at a low speed, and by it, a secondary subsystem chooses, is inspected and can process the data under passage. As 3rd feature of the present invention, each primary command description child (DCB) who calls off-line mode contains type A bit as for which a Weave exception carries out each command as a load type or start type command. A load type command contains the "start line" "command list length" parameter which defines the command position in related command Liszt Alley. [ in case the numbers of commands other than 0000 are decided to be parameters by a related array ] When the Liszt chief parameter is not 0000, load type DCB makes a secondary subsystem memorize a start line and the Liszt chief parameter. Command Liszt Alley in the memory (direct access is possible) of a primary subsystem is made to be found, and the array is made to load to the memory of a secondary subsystem. When the Liszt chief parameter contains command Liszt to whom the memory of the secondary subsystem was loaded beforehand by 0000, only a secondary subsystem memorizes start line information. A secondary subsystem translates into a head a command with the defined start line parameter beforehand memorized in command Liszt loaded beforehand by a predetermined sequence by started type DCB. As 4th feature of the present invention, in every position in command Liszt Alley, the processing of the secondary command in off-line mode can interrupt, and is the above-mentioned position in that case, the Liszt chief of 0000 and the start line parameter that points out an interruption position are included -- the chain was carried out or an array is again loaded with a receipt Ivy load type command -- required -- it can start again to carry out. As 5th feature of the present invention, it is processing of the secondary command in off-line mode, (a) When the number of the processed secondary commands exceeds "operation length" Parameter specified by the primary start type command which started the present secondary sequence, (b) the time of exceeding the capacity of the field actually specified by the start type command with which the number of data bytes transmitted between the memory of a primary subsystem and the secondary subsystem is related -- or (c) when the end of a device or exception interruption is alike and is called by a secondary command, it can end. DETAILED DESCRIPTION Drawing 1 shows the outline of an environmental system including the example of the present invention. Primary subsystem 1 communicates with peripheral equipment or device 2 which is a device multiplexer via secondary subsystem 3. Primary subsystem 1 is the usual composition and contains a primary processor, i.e., host processor 1a, host memory 1b, and one or more host I/O channels 1c. Host interface adapter 3a for which secondary subsystem 3 exchanges host memory 1b and data by cycle Steel Mohd (host I/O channel 1c and direct access (not shown)), Device interface adapter 3b for which it interfaces with device 2 and exchanges data (a different format), respectively, Control port adapter 3d for which other control signals are exchanged to handshaking logic adapter 3c which carries out handshaking of the signal with which the timing of data movement is united, Microprocessor memory 3f accessible to secondary microprocessor 3e and the above-mentioned secondary microprocessor 3e, Bus 3g to which data is transmitted among adapters 3a and 3b, bus 3h to which the information on data and others is transmitted between primary subsystems 1 via host interface adapter 3a, Bus 3i which connects secondary microprocessor 3e to microprocessor memory 3f and adapters 3b, 3c, and 3d, and line 3j which adjusts the data transfer between adapters 3b and 3c and handshaking signal operation are included. Secondary subsystem 3 is connected to device 2 via external bus 5 at primary subsystem 1 via external bus 4, respectively. By the present invention, the exclusive Mohd A bit which the primary command description child called "a device control block" (henceforth DCB) has is answered, Secondary subsystem 3 is dynamically switched between two different operational modes, i.e., high-speed (HS) Mohd, and programmable off-line (PO) Mohd. DCB is created by primary subsystem software by host memory 1b, and search and translation with secondary subsystem 3 are possible for it, and it can link it by chaining. Therefore, secondary subsystem 3 is programmable so that HS Mohd and PO Mohd may be dynamically switched under the state of explaining later. By the present IC package art, on one multichip card, a package is possible for secondary subsystem 3, and it is displayed as an "addition card" in other parts of Drawing 1 and this specification. For primary subsystem 1, an addition card, i.e., secondary subsystem 3, and device 2 are "possible [ observation ]" as a single device address, and host I/O channel 1c can be added [ of a plurality of above-mentioned cards and other device controllers ]. Host interface adapter 3a and external bus 4 are explained by U.S. Pat. No. 4246637. Drawing 2 shows various kinds of examples 10 thru/or 14 of composition by the addition card use expected. Example 10 of composition shows one addition card which connects a host subsystem like a device like device 2, and primary subsystem 1 (passing a host channel (not shown) like host I/O channel 1c shown in Drawing 1). Example 11 of composition shows two separate addition cards to connect to one (passing each subchannel (not shown) of a host channel (not shown)) host subsystem for two devices. Example 12 of composition provides the parallel data transmission interface extended to one device 2, and shows two addition cards which connect the above-mentioned device 2 with one host subsystem. Example 13 of composition shows that two addition cards connected with one host subsystem transmit data between two subchannels of a system using the tandem linkage of a card versus a card. Example 14 of composition shows that two addition cards connect two separate and comparatively asynchronous host subsystems by the above-mentioned tandem linkage composition. As mentioned above, the Mohd A bit parameter contained in the sequential translation command description child array called DCB (device control block) is answered, and secondary subsystem 3 operates by turns by high-speed (HS) Mohd and programmable off-line (PO) Mohd. As for the process of performing such creation of DCB, extraction, and translation, the outline is shown in Drawings 3 and 4. Application software which operates by host processor 1a as blocks 20 and 21 show in Drawing 3, Operation of the device containing a subordinate addition card is scheduled by preparing start command OIO (operate I/O) and "immediate" command description child IDCB (immediate device control block). Host processor 1a translates an OIO command into timely, and searches IDCB with block 21 using the address information under command. IDCB specifies a device address (in this case, address of an addition card), and an IDCB command function. This command function specifies DPC (direct programmed control) operational mode 22 or CS (cycle Steel) operational mode 23. While having translated IDCB, host processor 1a chooses an addition card, and branches to a command function. If DPC operation is specified, host processor 1a and an addition card will synchronize, it will have a dialog, and data transfer will be performed between microprocessor memory 3f on an addition card, and the "immediate data field" portion of IDCB (block 22). Host processor 1a and secondary microprocessor 3e of an addition card this transmission, It is necessary to control an element related with each subsystem directly, and is at the host processor 1a side, In the channel / addition interface or Or et al., and addition card side, microprocessor memory 3f to Immediate value data is transmitted via host interface adapter 3a. If it opts for CS operation by IDCB, the copy of IDCB will be transmitted to microprocessor memory 3f of an addition card (block 24), Then, secondary microprocessor 3e of an addition card adjusts host interface adapter 3a (Drawing 1) using IDCB information, In microprocessor memory 3f of an addition card, a DCB command description child's "cycle Steel write-in" transmission is performed from host memory 1b. - which comprises eight 16 bit words explained after DCB- orders to perform another operation, i.e., extraction and translation (block 25 of Drawing 3) of DCB, to secondary microprocessor 3e of an addition card. The above explanation of operation has been conventionally used as a prior art, and is indicated, for example by above-mentioned U.S. Pat. No. 4246637. However, at present, DCB sets up Mohd and calls various kinds of addition operational modes it was considered that were unique novel things including the A bit parameter which carries out chaining. Secondary microprocessor 3e of an addition card switches the sequence of secondary subsystem 3 of an addition card of operation to high-speed (HS) Mohd 27 or programmable off-line (PO) Mohd 28 according to the state of the above-mentioned Mohd A bit of DCB. Device 2 (as opposed to primary subsystem 1) to which secondary microprocessor 3e is connected in HS Mohd the same device address as an addition card -- having -- it chooses, adapters 3a and 3b and device 2 are prepared (block 29), and data transfer (it has the byte count length specified by DCB) is performed between host memory 1b and device 2 (block 30). By the above-mentioned transmission, data passes along external bus 5 by one of the A bit parallel formats of shoes to be specified by DCB, and is changed into the format which can suit the transmission composition to which host interface adapter 3a was fixed by device interface adapter 3b. In PO Mohd, secondary microprocessor 3e of an addition card branches by the present specific "type A bit" in DCB (judgment block 31 of Drawing 3), "Command Liszt" preparation operation 32 or program 33 of operation defined with the "secondary command" contained in command Liszt prepared beforehand is run. When a type A bit value is 0, DCB is called "programmable off-line load" (LPO) Mohd type DCB, and when a type A bit value is 1, DCB is called "programmable off-line start" (SPO) Mohd type DCB. When translating LPO Mohd type DCB, secondary microprocessor 3e of an addition card branches with the value of 4 A bit Liszt chief factor contained in the DCB (judgment block 34). When this value is except 0000, it is secondary microprocessor 3e, In combination with the Liszt chief factor contained in DCB, from the field of host memory 1b decided using the boundary address information included in DCB, host interface adapter 3a is adjusted so that the array of "command Liszt" may be searched. Secondary microprocessor 3e loads this command Liszt's array to a microprocessor memory [ 3f ] predetermined field (block 35). The variable number of the loaded array is a command word (DCB is referred to as a primary command and the command in command Liszt is called a secondary command) "the 2nd order" 16 A bit. Holding the factor of a start line with the Liszt chief contained in above DCB (blocks 36 and 37) secondary microprocessor 3e branches with the chain A bit value included in DCB (judgment block 38). When chain A bit is 0 (chaining is not specified), secondary microprocessor 3e tells primary subsystem 1 about status interruption (block 39), and ends the present sequence of secondary subsystem 3 of an addition card of operation. When chain A bit is 1 (chaining was specified), secondary microprocessor 3e and host interface adapter 3a search 1 more set of sequences of operation by the Mohd A bit value of another DCB and its DCB together. By judgment block 34, when LPO type DCB contains the Liszt chief factor of 0000, secondary microprocessor 3e branches to "yes." Therefore, block 35 which loads command Liszt is skipped. However, by block 37, the information on a new DCB start line is held, and progresses to judgment block 38. Start line information that secondary microprocessor 3e was held by block 37 when translating SPO type DCB (33 of Drawing 3), A program of operation with the defined group of the secondary command in above-mentioned Liszt which uses for starting command Liszt beforehand remembered by microprocessor memory 3f as the first "command address", and starts with the first address is run. Secondary microprocessor 3e searches the command of a command address repeatedly, performs operation defined with the command, and carries out the increment of the command address until it meets with one of a plurality of "the end conditions" explained later. This sequence is shown in block 40. If secondary microprocessor 3e meets with end conditions, it will memorize status (block 41) and will follow it to judgment block 38. Drawings 4 and 5 show the logic composition of the system formed by primary subsystem 1 and secondary subsystem 3 about execution of the above-mentioned operation. In Drawing 4, OIO command 51 and IDCB description child 52 are 2-word (32 A bits) expressions. OIO command 51 processed by only host processor 1a contains effective address 53 in host memory 1b of IDCB. As explained above, adjusted information transfer between primary subsystem 1 and secondary subsystem 3 of an addition card is performed by IDCB by DPC or CS Mohd. IDCB contains command portion 54, device address portion 55 (this example address of an addition card), and field section 56 changed according to the information on command portion 54. Decipherment logic 57 of primary subsystem 1 inspects command portion 54, and sets up CS transmission operation via DPC transmission operation or change course 59 via change course 58. At this time, device address portion 55 is used by primary subsystem 1, and chooses an addition card. By DPC transmission, sauce Up of the immediate data in which field section 56 of IDCB is sent / received by microprocessor memory 3f of an addition card from / constitutes the "immediate data field" showing an address. In CS transmission, the address information included in field section 56 determines the boundary address in host memory 1b of the word an 8-word (128 A bits) DCB description child's beginning. This information is transmitted to an addition card (secondary subsystem 3 shown with the dashed line in Drawing 4). An addition card is behind asynchronous, operates and searches relation DCB. In Drawing 5, DCB description children 60 and 61 by the present invention contain 8 words of word 0 thru/or word 7, respectively (shown by WD1 and WD2 grade). Each word contains A bit 0 thru/or 16 A bit of A bit 15. Word 0 (WD0) includes other information defined as chain A bit (A bit 0) and the next. A bit 0 of word 1 contains the Mohd A bit (HS or PO Mohd is specified). All the A bit of other A bit of word 1, A bit 2 of word 0, two-word word [ three-word ] 6, and word 7 have the context from which the translation explained later changes according to the value of the Mohd A bit. Word 4 contains the first address in host memory 1b of the 8-word field which memorizes "a residual status block" (RSB) explained later. The sequence of operation which translates above DCB ends word 5, and it decides the chain address used when chain A bit of above DCB specifies chaining (A bit 0= 1 of word 0). Drawing 5 shows the outline of a definition, and the logical effect of the fixed important portion of DCB. All the DCB elements are more completely defined by later. When the Mohd A bit specifies HS Mohd (A bit 0= 0 of word 1) in Drawing 5, When the value of A bit 1 of word 1 is 0, it is contained in words 2 and 3, and the "device command" function shown in 63 and 64 is transmitted to device 2 by secondary subsystem 3 of an addition card (but), and A bit 1 of word 1 defines the command deterrence function shown in 62. Command transmission is deterred when the value of the above-mentioned A bit is 0. When PO Mohd is specified (A bit 0= 1 of word 1), A bit 1 of word 1 identifies the command type shown in 65 (when the value of A bit is 0, it is Type LPO and Type SPO in the case of one). If the value of A bit 2 of word 0 becomes one when HS Mohd is specified, the data transfer ("reading" transmission (RD)) from device 2 to host memory 1b will be defined, and if the value of the above-mentioned A bit becomes zero, the data transfer ("write-in" transmission (WR)) from host memory 1b to device 2 will be defined. This transmission is performed by adapters 3a and 3b (Drawing 1), without memorizing data without interference of secondary microprocessor 3e interim in microprocessor memory 3f. The data volume transmitted by this Mohd is specified by the transmission byte count contained in word 6 of DCB. When PO Mohd is specified, the meaning of A bit 2 of word 0 is influenced by the value of type A bit (A bit 1 of word 1). When a LPO type is specified, the value of A bit 2 of word 0 must be 0 (actually relating to "write-in" transmission of command Liszt from host memory 1b to microprocessor memory 3f (refer to operation of block 35 of Drawing 3)). However, also when a SPO type is specified, it may have the bidirectional context which the value of A bit 2 of word 0 must be 0, and is later explained in "double Mohd operation." When a SPO type is specified about this context, a plurality of data transfer operations may be intermittently performed between an addition card and two or more fields of host memory 1b under the fixed directions of a secondary command (command Liszt) which specify reading and write-in transmission operation. When PO Mohd and a LPO type are specified, word 2 is an idol as shown by a total of 0 Seting in 66, Words 3, 6, and 7 contain a "command Liszt start line", the "command Liszt chief", and a "command Liszt start address" parameter by 67, 68, and 69, respectively. When the command Liszt chief defined by word 68 has values other than 0000 (hexadecimal number), command Liszt start address 69 is, The beginning of the field in host memory 1b which contains in microprocessor memory 3f command Liszt transmitted (since it loads) is decided. In this case, it is used for command Liszt start address 69 and command Liszt chief 68 accessing the Liszt field of host memory 1b, and performing transmission of one command at once (operation of block 35 of Drawing 3). In the inside of command Liszt by whom processing of a secondary command is started when command Liszt start line 67 operates following the bottom of directions of secondary microprocessor 3e of SPO type DCB (loaded), It is used for determining a command line position by secondary microprocessor 3e of an addition card. When the command Liszt chief's value is 0000 (hexadecimal number), the fixed portion (a start line and the Liszt chief) of DCB is held at microprocessor memory 3f, Although secondary microprocessor 3e makes it possible to access Liszt loaded under directions of LPO type DCB translated beforehand, it is not used for LPO type DCB translated immediately transmitting command Liszt to microprocessor memory 3f. the case where PO Mohd and a SPO type are specified -- word 2 of DCB -- "reading byte count" 70 -- word 3 -- "reading start address" 71 -- word 6 -- "a write-in byte count" -- word 7 expresses "write-in start address" 73 for 72. A reading start address and a reading byte count appoint the field to which data can be transmitted from an addition card (operation of the fixed secondary command contained in command Liszt remembered by microprocessor memory 3f now) into host memory 1b. An interruption start address and a write-in byte counter appoint another field into host (usually separating from reading field) memory 1b, and from the field, data is extracted under directions of the write-in fixed command in command Liszt remembered now, and is transmitted to an addition card. When HS Mohd is specified, A bit 2 thru/or A bit 15 of DCB word 1 has the context shown in 74. It is used for 2 A bit in these A bit specifying one of the four device interface formats to related data transfer. 4 A bit in these A bit specify one of the timer waveforms of 16 chosen from timer sauce (not shown). The remaining 8 A bit specify the position in host memory 1b of the array index factor used when a fixed device interface format (B16) and related array index operation are specified. (Secondary microprocessor 3e and adapters 3a and 3b performing common operation in an array index.) Address information is transmitted to device 2 from secondary microprocessor 3e, and fixed "array data" is transmitted between host memory 1b and device 2. A total of A bit 2 thru/or 15 of word 1 being 0, as shown in 755 if DCB is a LPO type when PO Mohd is specified However, if DCB is a SPO type, these A bit should be shown in 76, One of some the handshaking formats (device interface) It is used for specifying the maximum operation length parameter which shows the number of secondary [ a maximum of ] commands which may be performed one of the timer waveforms (it is similar to the timer value defined in HS operation) of 16, and under each directions of DCB. Details of a definition of DCB HS Mohd (A bit 0= 0 of word 1) This Mohd makes possible rapid data transfer between connected device 2 and host memory 1b, without memorizing data without support of secondary microprocessor 3e or host processor 1a interim by microprocessor memory 3f. The data volume transmitted is specified as word 6. The word portion of this DCB has a following (as opposed to translation of secondary subsystem 3 of an addition card) meaning. DCB word 0 (control word): A bit 0: Chaining flag When the value of this A bit is 1, an addition card performs a chaining procedure. Although an addition card completes the present operation, an interruption demand is not sent to host processor 1a. Instead, an addition card takes out the next DCB in a chain, and performs the next operation. (DCB word 5 directs the position of the next DCB.) Chaining continues until an addition card takes out DCB by which Chan Flagg was Set(ed) by 0 and it directs operation of the last of a chain. If deterrence exception A bit (A bit 4) becomes one, a residual status block (RSB) will be memorized in each operation in a chain, unless exception interruption is reported. Exception interruption ends a chain again. (Please refer to explanation of A bit 4.) A bit 1: Programmed control interruption If DCB extraction completes this A bit when a value is 1, programmed control interruption will be performed. (Each interruption must be performed before another interruption is performed.) A bit 2: Input Flagg This A bit directs in which direction data is transmitted in HS Mohd. When the value of this A bit is 1, an addition card transmits data to host memory 1b, and when the value of A bit is 0, data is transmitted to an addition card from host memory 1b. A bit 3: This A bit is not used in HS Mohd's operation, but is 0. A bit 4: Deterrence exception When the value of this A bit is 1, Otherwise, the exception of length which produces exception interruption is reported as an end of a device permitted. The status of an addition card is memorized by the address specified by the address (DSB word 4) of the residual status block (RSB) unless exception interruption is reported. A residual status block (RSB) is sent by the end of each operation by which the deterrence exception was programmed. The format of RSB is shown by "a residual status block" explained later. A bit 5~7: Address key These 3 A bit inspect having the permission to which it is shown by the addition card between data transfer, and a program calls host memory 1b. An incorrect Ivy address key produces exception interruption. A bit 8~10: These 3 A bit must not be used in HS Mohd's operation, but must be 0. A bit 11~13:programmed control interruption ID -- as A bit 3, 4, and 5 of the interruption information byte (IIB) who explains 3 A bit of these between the next programmed control interruption and in the back -- display Scare away. (All other A bit of IIB are 0.) A bit 14:21-second timeout When this A bit is 1, the 21-second timeout of DCB operation operates. The addition card must carry out a chain or interruption within 21 seconds. When that is not right, exception interruption is reported and A bit 9 of cycle Steel status word 3 is Set(ed) by 1. When this A bit is 0, timeout is not used for 21 seconds. A bit 15: The end of chaining When this A bit is 1, an addition card deters the exception of length together with A bit 0 and 4 Set(ed) by 1. However, it appears in an exception with insufficient length, and an addition card ends chaining operation at the time of meeting Ivy (namely, when the data transmitted is less than the byte count specified by word 6). In an addition card, this A bit reports a DCB detailed inspection, when A bit 0 or A bit 4 is 0 in 1. By 0, in an addition card, this A bit continues chaining in spite of an exception with insufficient length, when A bit 4 is 1. DCB word 1 (addition card directions command): When the value of A bit 0 of this word is Set(ed) by 0, this word has a fixed specification option. HS Mohd's operation to an addition card is specified. This word specifies whether operational mode (high-speed DI/DO) and words (command) 2 and 3 are transmitted to device 2, which data format, and a timing pulse period are used. A bit 0: DI/DO specification If this A bit is Set(ed) by 0, HS (high-speed DI/DO) Mohd operation will be specified. A bit 1: Command deterrence When this A bit is 0, the command word given to DCB words 2 and 3 is sent to device 2. When this A bit is 1, the transmission to device 2 of a command word is deterred. A bit 2 and 3: Format These A bit specify the format of the interface of an addition card. A bit 2 and 3 Interface format 00 8 A bit, Single Directivity (U8) 01 16 A bit, Single Directivity (U16) 10 16 A bit, Bidirection (B16) 11 32 A bit, Bidirection (B32) A bit 4~7: The value of a timer These A bit specify the timer output period used. A bit 4~7 Timer output pulse 0000 Nothing 0001 10.4 (Microsecond) 0010 10.4 (Microsecond) 0011 20.8 (Microsecond) 0100 41.6 (Microsecond) 0101 83.3 (Microsecond) 0110 166.6 (Microsecond) 0111 333.3 (Microsecond) 1000 666.6 (Microsecond) 1001 1.333 (M Seconds) 1010 2.666 (M Seconds) 1011 5.333 (M Seconds) 1100 10.66 (M Seconds) 1101 21.33 (M Seconds) 1110 42.66 (M Seconds) 1111 85.33 (M Seconds) 0001 produces a single pulse and all others produce a continuation repetition signal. A bit 8~15: In the bidirectional format of array index boundary (port 0 counter preset) 16 A bit, at least Takayoshi of the bus by which this field is not used for data transfer is Set(ed) by the byte. A low ranking byte is Set(ed) by hexadecimal number 00. Two bytes forms an intermediary array index display together. The format of those other than the bidirection of 16 A bit has A bit 8~15 Set(ed) by hexadecimal notation 00. When that is not right, an addition card sends a DCB detailed inspection. DCB words 2 and 3 (device directions command): DCB words 2 and 3 constitute the command of 32 A bit sent to device 2, unless transmission is deterred by 1 in A bit 1 of word 1. All the 32 A bit in a command are sent by the format specified by A bit 2 and 3 of word 1. When device interface adapter 3b is 32 A bit width, word 2 is the top word and word 3 is the lowest word. Both words are simultaneously passed to device interface adapter 3b as single outbound command transmission. When device interface adapter 3b is 16 A bit width, as two separate sequential transmission, word 2 is passed first and word 3 is passed after that. Notes: When only the command of 16 A bit is required, words 2 and 3 serve as the same contents, and may be memorized by single 16 A bit register in device logic. When device interface adapter 3b is 8 A bit width, four sequential transmission is performed. - A bit 8~15 of A bit 0~7- word 3 of A bit of A bit of word 2 0~7- word 2 8~15- word 3 Data transfer between device 2 and an addition card is performed after command transmission is completed. DCB word 4 (residual status block address): This word contains the address of the beginning of the 8-word field in host memory 1b a residual status block (RSB) is remembered to be. Since the number of these addresses must be even, A bit 15 must be 0. RSB is memorized whenever the case where exception interruption is not reported for deterrence exception A bit (A bit 4) of word 0 by 1 arises. The format of RSB is later explained by "residual status block." DCB word 5: (DCB chain address): This word specifies the address in host memory 1b of the next DCB performed when Chan Flagg (A bit 0) of DCB word 0 is 1. The number of DCB chain addresses must be even (A bit 15 is 0). If the number of them is odd, interruption will arise and DCB detailed inspection A bit (A bit 3) in ISB will be Set(ed) by 1. When an error arises, condition code 2 (exception) is reported and chaining stops. DCB word 6 (byte count): This word includes an integer without the numerals of 16 A bit showing the number of data bytes transmitted in the present DCB. Cotton intermediary specification of the byte count may be carried out in all the 16 bit ranges of 0~65535. However, since partial transmission is not allowed, the byte count must be a multiple of the format width of device interface adapter 3b so that it may be specified by A bit 2 and 3 of word 1. It is larger than the maximum allowed a byte count to specific operation, or when the number of byte counts is odd to the format of 16 A bit or 32 A bit, DCB detailed inspection A bit (A bit 3) in ISB Set 1. When an interruption demand is accepted, condition code 2 (exception) is reported. DCB word 7 (data address): This word contains the first address in host memory 1b of the data relevant to the operation performed. Although the number of data addresses must be even (A bit 15 is 0) in the format of 16 A bit and 32 A bit, the number may be odd in the single directivity format of 8 A bit. In the format of 16 A bit or 32 A bit, in the case of odd number, an interruption demand is sent and, as for DCB detailed inspection A bit (A bit3') in ISB, a data address is Set(ed) by 1. When an interruption demand is accepted, condition code 2 (exception) is reported. PO Mohd's LPO type This is used for loading command Liszt and the first line access parameter which are used between operations by DCB following SPO type. DCB word 0 (control word): A bit 0: Chan Flagg It is the same context as the case of HS Mohd's DCB. A bit 1: Programmed control interruption In the case of HS Mohd, it is the same. A bit 2: Input Flagg This A bit directs in which direction data is transmitted. always Toward [ with this type of operation / from host memory 1b / to an addition card ] in data (namely, command Liszt) transmission -- since it is divided, this A bit must be 0. When that is not right, a DCB detailed inspection is conducted. A bit 3: This A bit must not be used in this operation, but must be 0. A bit 4: A deterrence check sum inharmonious addition card always transmits and inspects a check sum (word of command Liszt's last). If A bit 4 is Set(ed) by 1, a check sum inharmonious exception will not produce exception interruption. However, check sum error status is Set(ed), and when exception interruption is not reported, a residual status block is memorized by the address specified by the residual status block address (DCB word 4). Notes: This A bit does not deter Restraint which arose by the exception of length. This A bit does not produce a retry, when check sum inharmonious exception interruption is deterred. A bit 5~7: Address key Same A bit 8~10 as HS Mohd's case: These 3 A bit must not be used in this operation, but must be 0. A bit 11~13: It is the same as programmed control interruption ID HS Mohd's case. A bit 14:21-second timeout This A bit must be 1. A bit 14 operates timeout for 21 seconds in DCB operation. The addition card must carry out a chain or interruption within 21 seconds. Otherwise, exception interruption is reported. A bit 15: The end of chaining This A bit must be 0. DCB word 1 (addition card directions command): This word specifies programmable off-line load mode (LPO) type operation. A bit 0: This A bit is 1 in all the PO Mohd operations. A bit 1: This A bit is 0 in LPO type operation. A bit 2~15: These A bit must be reserves and must be 0. DCB word 2 (reserve): This word must be a reserve and must be 0 altogether. DCB word 3 (command Liszt start line): This word specifies the command Liszt line in which an addition card must start processing of a secondary command (command Liszt), when translating programmable off-line start Mohd (SPO) type DCB next. This word must be smaller than hexadecimal number 0700. Notes: Command Liszt's 1st line is line 0000. Therefore, when DCB word 3 is 0000 by this LPO type, an addition card starts processing by command Liszt's 1st line. When DCB word 3 is 0001, an addition card starts processing by the 2nd line. A process is interrupted below this word in pre- operation. When it is [ re-] under start in the following sequential command Liszt line, it is often used. (Please refer to DCB word 6.) DCB word 4 (residual status block (RSB) address): It is the same as HS Mohd's case. DCB word 5 (DCB chain address): It is the same as HS Mohd's case. DCB word 6 (command Liszt chief): This word includes an integer without the numerals of 16 A bit showing the length (byte) of the sum of command Liszt and a 2-byte check sum. When command Liszt is beforehand loaded for word 6 by 0000, an addition card re-starts a command Liszt program, after next programmable off-line start Mohd's DCB is accepted. In this case, a command Liszt program is re-started in the line directed by DCB word 3. A command Liszt program may be re-started by this method. When command Liszt is not loaded beforehand, an addition card reports end interruption of a device, and Set bit 10 of cycle Steel status word 3 to 1. A command Liszt check sum is not rechecked when a byte count is 0000. When this word is not 0, an addition card clears an I/O register, an accumulator, the register for work, and the status of a processor, and it reads command Liszt into microprocessor memory 3f until it uses up a byte count. The number of byte counters must be even and they do not exceed zero E02 (hexadecimal number) byte. (Since a command is 2 bytes, the maximum command Liszt chiefs of a check sum word are 1792 commands and 2 bytes of sum.) When a byte count is 0002 (hexadecimal number), it is considered that command Liszt is zero (byte) merit of 2 bytes of check sum. In this case, since an addition card clears the local command Liszt storage area of an addition card, subsequent SPO type DCB is denied access to Liszt loaded at the end. By it, each application program which uses PO Mohd restricts that other application programs access the command Liszt (as a safeguard). DCB word 7 (command Liszt start address): This word includes the start address of command Liszt of host memory 1b. Since a command is 2 bytes, the number of these words must be even (A bit 15= 0). Command Liszt's format memorized by host memory 1b is shown in Drawing 6. The check sum contained in 2 bytes of Liszt's last must be equal to the number of commands, and the sum of 2 (byte). PO Mohd's SPO type This is used for starting processing by secondary microprocessor 3e of the sequence of the secondary command contained in command Liszt loaded beforehand. DCB word 0 (control word): A bit 0: Chan Flagg It is the same as HS Mohd's case. A bit 1: Programmed control interruption It is the same as HS Mohd's case. A bit 2: Input Flagg In this DCB, this A bit must be 1. This DCB is used for requiring execution of the group of the command of command Liszt who may direct the data transfer of the both directions from /to host memory 1b (the following "double Mohd application" should be referred to). A bit 3 : (intact) The value of this A bit must be 0. A bit 4: Deterrence exception It is the same as HS Mohd's case. A bit 5~7: Address key It is the same as HS Mohd's case. A bit 8~10 : (reserve) These A bit must be 0. When that is not right, a DCB detailed inspection arises. A bit 11~13: It is the same as programmed control interruption ID HS Mohd's case. A bit 14:21-second timeout When this A bit is 1, programmable off-line Mohd I/O operation is ended in 21 seconds after a start of operation, when operation has not been completed yet. And the return of the status is carried out to the command Liszt program which timeout produced. Timeout is not used when this A bit is 0. the end of A bit 15:chaining (exception which runs short of length) -- when this A bit is 1, an addition card deters the exception of length conjointly with A bit 0 and A bit 4 which were Set(ed) by 1. However, it appears in the exception which runs short of length, and an addition card ends chaining operation at the time of meeting Ivy (namely, when the data transmitted is smaller than the byte count specified by programmable off-line start Mohd's word 2 or word 6 of DCB). In an addition card, this A bit reports a DCB detailed inspection, when A bit 0 or A bit 4 is 0 in 1. When this A bit is 0, an addition card continues chaining in spite of the exception of length. DCB word 1 (addition card directions command): Programmable off-line (SPO) start Mohd type operation is the specified option, and this word specifies performing. This word specifies operational mode (programmable off-line start Mohd), interface handshaking, and timing. A bit 0: This A bit is 1 to all the PO Mohd operations. A bit 1: This A bit is 1 to SPO type operation. A bit 2 and 3:handshaking code -- A bit of these specifies handshaking of device interface adapter 3b. A bit 2 controls bus 1 (Drawing 1), and A bit 3 controls bus 0 (Drawing 1). A handshaking code is defined as follows. 1= device demand (transmission control by a device) -- when one of A bit are 1, the data transfer by the bus controlled by the A bit is started by the demand from device 2. Command processing stops during programmable off-line Mohd's I/O transmission. the inside demand (transmission control by an addition card) of 0 = -- when one of A bit are 0, the demand from a device to the bus is unnecessary. A bit 4~7: It is the same as the case of value HS Mohd of a timer. A bit 8~11: Merit of operation This field includes the code which specifies the number of the maximum operation length who can approve, i.e., the secondary I/O (command Liszt) command which may be executed as a result of DCB single SPO type. When exceeding the specified maximum, a program is ended by end interruption of a device, and A bit 11 of cycle Steel status word 3 is Set(ed) by 1.
[Table]
[Table]
DCB word 2 (reading byte count): (please refer to the following "double Mohd application".) This word directs the number of data bytes transmitted to host memory 1b by the present DCB. The decrease part of the byte count directed to the each secondary command which transmits data to host memory 1b is carried out. If a byte count amounts to 0000, the data transfer to host memory 1b will stop. The number of these words must be even. When that is not right, a DCB detailed inspection is conducted. DCB word 3 (reading start address): (please refer to "double Mohd application".) This word includes the start address in host memory 1b data is remembered to be. The number of these words must be even. When that is not right, a DCB detailed inspection is conducted. DCB word 4 (residual status block address): It is the same as HS Mohd's case. DCB word 5 (DCB chain address) It is the same as HS Mohd's case. DCB word 6 (write-in byte count): (please refer to "double Mohd application".) This word directs the number of data bytes transmitted by the present DCB from host memory 1b. The each secondary command which transmits data from host memory 1b carries out the decrease part of the directed byte count. If a byte count amounts to 0000, data transfer will stop. The number of these words must be even. DCB word (write-in start address): (Please refer to "double Mohd application".) This word includes the start address in host memory 1b. Data is written in from this address. The number of these words must be even. Note: Reading in host memory 1b and a write-in field can be overlapped (it is not necessary to overlap). it -- the field in main memory 1b -- an addition card -- re--- it is usable. However, only sequential access of an ascending order is possible. Interruption status information An addition card transmits an interruption ID word to host processor 1a again, when priority interruption is shown. An interruption ID word contains a device (namely, addition card) address and an "interruption information byte" (IIB). IIB is transmitted to host processor 1a by attention interruption or end interruption of a device. A total of IIB of attention interruption containing 0 As for value 1 of A bit 0 (permissible end A bit of a device), "software" error information expresses an usable thing with end interruption of a device by residual status block (RSB). Note: In the operation by which the chain was carried out, that the value of A bit 0 is 1 means that at least one of the memorized RSB(s) includes "software" error information. A "software" error is a deterrence exception which Set bit 0 of IIB to 1, when a deterrence exception (A bit 4 of DCB word 0) is Set(ed) by 1. In interruption condition code 2 (exception) or 6 (attention or exception), IIB has a special format and is called an interruption status byte (ISB). A plurality of ISB A bit are Set(ed) at once. ISB A bit gives the next display, when 1 Set. A bit 0 (device subordinate usable status): This A bit expresses that the status information on an addition card is still more nearly usable with a cycle Steel Otters block. A bit 1 (delayed command removal): It means that this A bit has odd bytes of DCB address, or an incorrect Ivy parameter like an unsuitable function by IDCB. This A bit is Set(ed) by 1 when IDCB specifies again the DPC function which an addition card has. A bit 2 (record of unsuitable length): The byte count as which this A bit was specified by DCB (setting to programmable off-line start Mohd's DCB) word 6 (or DCB word 2), an addition card appears in the disagreement of the length of the record read or written in by device interface adapter 3b -- meeting Ivy -- things are expressed. (Please refer to the following "residual status block" for explanation of processing of the record of the unsuitable length between deterrence exceptions.) A bit 3 (DCB detailed inspection) The invalid parameter in which this A bit barred the right execution of the command expresses Find and Was it with DCB. This may exist in every portion of DCB. The byte of the last of a cycle Steel status word is pointed out. A bit 0 is also Set(ed) by 1 when this A bit is Set(ed) by 1. A bit 4 (memory data inspection): This A bit means that the position accessed between cycle Steel output operations of host memory 1b contained the parity error. The parity of a memory is not corrected and a machinery verification condition does not produce it, either. Operation is ended at once. A bit 5 (invalid memory address): This A bit means that the host memory address by which access was tried between cycle Steel operations exceeds the size of memory of host processor 1a. Operation is ended at once. A bit 6 (protection inspection): This A bit means that the addition card tried access of the host memory position without the right key. Operation is ended at once. A bit 7 (interface data inspection): This A bit means that the parity error was detected by device interface adapter 3b between cycle Steel data transfer. Operation is ended at once. The following error operation produces exception interruption. - 21-second timeout occurred between operations. - The parity error of the addition card occurred. - The device inspection arose. - Except when a deterrence exception (A bit 4 of DCB word 0) was Set(ed) by 1, the record transmission of unsuitable length arose. - Come out among programmable off-line Mohd at the conditions which produce an exception under the command of an off-line control code, and it is meeting Ivy. - One of the jump commands in BASE or programmable off-line Mohd specified the address of the outside command Liszt's boundary. - The synchronization was lost in device handshaking. For example, before the addition card (or channel) performed the first demand, device 2 required the 2nd transmission. - The "possible [ an operation ]" line of device interface adapter 3b changed into the operation impossible state. - DCB detailed Investigation was reported. When residual status block (RSB) deterrence exception A bit (A bit 4 of DCB word 0) is Set(ed) by 1 and exception interruption is not reported, a residual status block (RSB) is memorized by the host memory address specified by DCB word 4. RSB is memorized between chaining for every DCB by which a chain is carried out. The record in which unsuitable length is transmitted is reported with IIB A bit 0 Set(ed) by 1 by end interruption of a device. It may be connected in order that an interface counter may direct the total number of transmission specially. A residual byte count (RSB words 0 and 6) records on a record the number of bytes smaller than the byte count in DCB words 2 and 6 which is not transmitted. DCB of a programmable off-line load mode also reports RSB, when a check sum error is deterred and exception interruption is not reported. Notes: Immediately after completing DCB operation, before end interruption is moreover sent to primary subsystem 1, the sample of the value it was reported that RSB for every DCB was is carried out. The 8-word format included in RSB is explained below. Word 0 (residual byte count): This word, The count which subtracted the transmitted number of bytes from the byte count specified by DCB word 6 of the last cycle Steel operation (it is only the writing or reading, and the writing in the case of a bidirectional format in the case of a format of single directivity) is included. Word 1 (RSB Flagg): This word has the next format. the end (EOC) of a A bit 0:chain -- this A bit is 1 when A bit 0 of DCB word 0 is 0. A bit 1: Retry (RT) This A bit is not used but is always 0. A bit 2~7: Reserve These A bit are always 0. A bit 8: Write-in excess length (WEL) The length of transmission of device interface adapter 3b exceeds the byte count specified by DCB. A bit 9: Reading excess length (REL) The length of transmission of device interface adapter 3b exceeds the byte count specified by DCB. A bit 10~13: Reserve These A bit are always 0. A bit14: -- the record (ILR) of unsuitable length -- this A bit has the record shorter than the byte count specified by DCB which was written in device 2 or was read in device 2, or expresses a long time. A bit 15: With no error (NE): This A bit is concentration of A bit 8, 9, and 14. A bit 15 is 1 when each of A bit of This and others is 0. Word 2 (residual address): This word contains the tried host memory address of the high address byte (odd bytes of low ranking) of the last cycle Steel writing or reading transmission. A residual address may be a data address or a DCB address. Word 3 (residual addition card status): The format of this word is the same as the format of cycle Steel status word 3. A bit 0~13 expresses the status accumulated between the DCB operations to which RSB is reported. A bit 14 and 15 expresses the status of the line of device interface adapter 3b at the time of the end of DCB operation. A bit 0: Addition card parity check This A bit is device interface adapter 3b, and it means that incorrect Ivy parity was received (when parity operation is chosen). Notes: This A bit is always reported as 0. A bit 1: Cycle Steel status error This A bit means that the error was detected between processings of start cycle Steel status command operation. Notes: This A bit is always reported as 0. A bit 2: Transmission of exceptional length An addition card does not transmit all the record length, but this A bit means that the number of transmission of device interface adapter 3b exceeded the byte count. A bit 3: Check sum error It means that the check sum comparison error produced this A bit between command Liszt loads. A bit 4: Programmable off-line Mohd processing error This A bit means that a command decoder was not able to process a command line. Notes: This A bit is always reported as 0. A bit 5:excess length command Liszt -- this A bit means that the off-line code command Liszt chief exceeded the command Liszt chief specified by DCB. Notes: This A bit is always reported as 0. A bit 6: Device error This A bit means that the last operation was completed by + conversion which arose on the " line when loss of the "available-to-use" line of device interface adapter 3b or an addition card was not in use. This A bit is reported only after DCB of a programmable off-line load mode. A bit 7: Device inspection It means that this A bit detected DCB(s) other than Mohd of 16 A bit bidirection from which the addition card was received while the option switch of internal malfunction or a card versus a card was Set(ed) by ON. Notes: This A bit is always reported as 0. A bit 8: Bidirectional data transfer this A bit -- the last transmission -- bidirectional DCB transmission -- Oh -- things are expressed. A bit 9:21-second timeout It means that timeout produced this word since A bit 14 of DCB word 0 was Set(ed) by 1 and addition card operation did not complete data transfer within 21 seconds. This A bit is reported only after programmable off-line start Mohd's DCB. A bit 10: Command Liszt un-memorizing. This A bit means that command Liszt is not remembered. A bit 11: An excess of merit of operation This A bit means that the length (specified by word 1) of programmable off-line Mohd operation was exceeded. A bit 12:off-line debugging Mohd -- this A bit expresses that an off-line debug mode is ON. A bit 13: Interface Oba Laon control synchronous loss This A bit means that the interface Oba Laon demand produced control synchronous loss. Notes: This A bit is always reported as 0. A bit 14: Status which can be device operated This A bit expresses the contrary (0= operation possibility [ of ] and 1= operation is impossible) of the present status which can be device operated. This A bit is reported only after DCB of a programmable off-line load mode. A bit 15: Device status This word expresses the status of the device status line of an interface. Word 4 (the last DCB address): This word includes the start address of DCB of the last which an addition card uses. Word 5 (residual address (bidirectional reading)): When following DCB of a single directivity format: A total of this word containing 0 When following DCB of a bidirectional format: This word contains the host memory address of the high address byte (odd bytes of low ranking) of cycle Steel reading transmission of the tried last. Word 6 (residual byte count (bidirectional reading)): When following DCB of a single directivity format: A total of this word containing 0 When following DCB of a bidirectional format: This word includes the count which subtracted the transmitted number of bytes from the byte count specified by DCB word 2 of the last cycle Steel operation. Word 7 (specially interface counter value): This word specifies the number of the phenomena specially counted with the interface counter. When used for an interface counter counting the total number of transmission to an addition device specially, the value which subtracted the DCB byte count from this value is the number of bytes on the incorrect Ivy record of the read excess length (overflow byte count) which was not transmitted. Specially, the interface counter is always active and is reset by receipt of DCB of an effective start command. With CS Mohd who deals with IDCB explained above in addition to the process of generating RSB, When IDCB form (unexplained) makes an addition card produce HS Mohd DCB (unexplained) specially, an addition card is transmitted to host memory 1b by using a "cycle Steel status" (CSS) block as "reading" data. This CSS block contains all the above-mentioned RSB elements except Flagg (RSB word 1). Instead, CSS supplies a "residual command Liszt line" (RCLL) word. This word defines the command Liszt line containing the secondary command with which execution was tried at the end between precedence SPO type DCB translation sequences. It is a position relevant to [ in primary subsystem 1 ] a RCLL (LPO type DCB programmed appropriately) parameter by this, and performs a recovery procedure by selection of a re-start of command Liszt execution. Primary subsystem 1 identifies the imperfect command relevant to the end of the SPO type DCB command Liszt execution by exception interruption. PO Mohd secondary command Generally a command Liszt format is shown by Drawing 6. A command list output and a special secondary command (a format and a function) are defined as follows. In programmable off-line Mohd's operation, it is directly possible in control of device interface adapter 3b from secondary microprocessor 3e of an addition card at the rate of a low speed thru/or the degree of middle. This Mohd can also operate independently and secondary microprocessor 3e of an addition card serves as a subordinate processor of host processor 1a of primary subsystem 1. By loading command Liszt to microprocessor memory 3f of an addition card from host memory 1b, control of device interface adapter 3b is programmed via primary subsystem 1. An addition card identifies the command with which 32 differs. These commands perform the next operation. - I/O data transfer - Internal data transmission - Logic and operation processing - conditional branching - Card hardware control The I/O command can carry out cycle Steel of the data to host memory 1b, and the data from host memory 1b while being able to transmit the data of device interface adapter 3b in a 16 A bit single directivity format. On an addition card, loading is possible for a maximum of 1792 command (namely, 3584 bytes). Command Liszt is loaded to an addition card using DCB of a programmable off-line load mode. Fuyline operation is started by programmable off-line start Mohd's DCB. The row number in command Liszt by whom processing is started is placed by word 3 of DCB of a programmable off-line load mode. The address in host memory 1b of command Liszt line 0 is placed by word 7 of the same DCB as the above, and command Liszt's+2 (2-byte check sum) length (byte) is placed by word 6. If DCB of a programmable off-line load mode is taken out, command Liszt will be transmitted to an addition card and will be inspected using a check sum. Command Liszt's format memorized by host memory 1b is shown in Drawing 6. A program is started in the command Liszt line directed by DCB word 3 of DCB of a programmable off-line load mode. Command Liszt must be loaded before programmable off-line start Mohd's DCB is taken out. When that is not right, processing stops immediately and it indicates that a command Liszt program was not loaded by exception interruption and cycle Steel status. Once a command Liszt program is loaded, it can be repeatedly re-started by new SPO type PO Mohd's DCB. Command Liszt program manipulation will be ended if one of the following operations arises. - A command calls interruption of host processor 1a. - An exception condition arises. - The "end of OP" line of device interface adapter 3b is Set(ed) actively. - The merit limit of operation specified by programmable off-line start Mohd's DCB is exceeded. The format of a secondary command (command Liszt) A bit 0~5 includes a command operation code. - A bit 0~4 defines the kind of operation explained later. - A bit 5 chooses the method of addressing the data dealt with. In the case of 0: Direct addressing In the case of 1: Indirect addressing (that is, it addresses via register for work) A bit 6 and 7 specifies it, when there is an accumulator of a microprocessor with which operation is performed. A bit 8~15 - Include the immediate data field which has an address of the register for work which takes in the address of the immediate data used by command and the data used by - command, or the address of the data used by - command one by one. Although a certain command Liszt command operates by single A bit, other command Liszt commands operate at 1 byte in the whole. By explanation of each command, it becomes clear by which it shall operate between A bit with the single command or 1 byte of the whole. The classification of a command A command is functionally classified into the following five items. - Data transfer - internal data transmission between the exterior and insides - Accumulator operation - conditional jump - Data transfer between the addition card hardware control exterior and insides The data transfer command between the exterior and insides transmits data from an addition card or an addition card. Although these commands do not access the register for work, the return status to an accumulator is accessed. There is the following command in this category. DIDO DIDOI XFER XFERI DIDO (111000AG immediate data) This command transmits data. There are four types of data transfer operations. Type A: This type transmits data to a device input register from a device input bus (port 1). (A bit 8, 9= 00) Type B: This type transmits data to the host input register of secondary microprocessor 3e from host memory 1b. (A bit 8, 9= 01) Type C: This type transmits data to a device output bus (port 0) from a device output register. (A bit 8, 9= 10) Type D: This type transmits data to host memory 1b from a microprocessor output register. (A bit 8, 9= 11) It can transmit up to 8 data words per command. Data transfer to device interface adapter 3b is demulti pre [ Multiplex / ] Tux(ed) by the hardware of an addition card. Device interface adapter 3b supplies related sub-addresses S0, S1, and S2 for every transmission as follows.
[Table]
Input-and-output transmission (the above-mentioned types B and D of operation) of the primary subsystem with which this sub-address specification method is applied to all of input-and-output transmission of device in tough Aces adapter 3b (the above-mentioned types A and C of operation), It demulti pre [ Multiplex / ] Tux from an I/O register as follows. Transmission I/O register word 0 A bit 128~143 (byte 0~1) Word 1 A bit 144~159 (byte 2~3) Word 2 A bit 160~175 (byte 4~5) Word 3 A bit 176~191 (byte 6~7) Word 4 A bit 192~207 (byte 8~9) Word 5 A bit 208~223 (byte 10~11) Word 6 A bit 224~239 (byte 12~13) Word 7 A bit 240~255 (byte 14~15) The data transfer of host memory 1b is addressed by the ascending order. Each DIDO command is started in the next ascending order address of the last DIDO command. That is, a data block is transmitted by this command and the consecutive addresses of each 1 thru/or 8-word block are specified by host memory 1b. Data is transmitted by the field specified by programmable off-line start Mohd's DCB. The parity of DIDO data is generated by the addition card. A immediate data field is coded as follows. A bit 8:reading / writing (the direction of data is based on an addition card) -- in the following case, this A bit is 0. - When data is transmitted to an addition card from device 2 (type A of operation) and - data is transmitted to an addition card from host memory 1b (type B of operation) A bit 9: A device/host This A bit is 0 when data is transmitted between devices 2. This A bit is 0 when data is transmitted between host memories 1b. A bit 10~12: These A bit determine the first word transmitted and include the value (0~7) which specifies word 0 thru/or word 7. In transmission with device 2, A bit 10, 11, and 12 are the first sub-addresses S0, S1, and S2, respectively. A bit 13~15: The value which these A bit express is (number of words transmitted)-1. For example, A bit 13 and 14, 15= 0, 0, and 0 express 1-word transmission. A bit 13 and 14, 15= 0, 1, and 0 express 3-word transmission. A bit 13 and 14, 15= 1, 1, and 1 express 8-word transmission. Transmission is not completed, when A bit 14 of DCB word 0 is 1 and the DIDO command does not complete transmission within 21 seconds, or when the byte count of DCB word 2 or 6 is used up by transmission. Imperfect transmission returns the number of words which was not transmitted by the transmission command to the specified accumulator. Imperfect transmission Set again Cali Flagg who can inspect with the JFLG command, borrow Flagg, and an error flag. When that is not right, above-mentioned Flagg is reset. When device 2 requires the transmission which exceeds the number of words specified by A bit 13~15, device interface adapter 3b does not answer the demand. However, the above-mentioned demand is still undecided. Cali Flagg, borrow Flagg, an error, and Flagg are also Set(ed) in this state. DIDOI (register address for 111001AC work) -- this command is the indirect form of DIDO. XFER (100110AC immediate data) This command has the following four types of operation. Type A: This type copies data to host output register 106 (after-mentioned) from device input register 105 (after-mentioned). Type B: This type copies data to device output register 106 (after-mentioned) from host input register 104 (after-mentioned). Type C: This type transmits a data block to device interface adapter 3b from host interface adapter 3a at high speed. Type D: This type transmits a data block to host interface adapter 3a from device interface adapter 3b at high speed. Device interface sub-address A bit (S0, S1, and S2) and an accumulator are not used by this command, and do not change. Notes: XFER is used in the host by whom in-line (HS Mohd) processing is not demanded (as opposed to this transmission), and the data transfer situation between devices. By restriction of a word count, and delay of a setup of a command with an addition card, XFER is not fit for high-speed operation. However, XFER is a little more advantageous than HS in spite of such restrictions. Between XFER operations, it is transmitted via a high-speed I/O course (bus 3g) with host interface adapter 3a by a microprocessor command. Since this high-speed I/O course gives the course over byte parity and a parity check circuit continuously, the advanced completeness of data is acquired. A immediate data field is coded as follows. A type of operation: A or B Data input register 102 (after-mentioned) is copied to data output register 103 (after-mentioned). A bit 8 is 0 when copying a register. As for A bit 9, the case from device 2 to 0 and host memory 1b of the case from host memory 1b to device 2 is 1. A bit 10~12 is the first word address in data input register 102. A bit 13~15 is 2 Advance value equal to (number of words transmitted)-1. A type of operation: C or D A data block is transmitted to device 2 or host memory 1b from device 2 from host memory 1b. A bit 8 is 1 when transmitting data. As for A bit 9, the case from device 2 to 0 and host memory 1b of the case from host memory 1b to device 2 is 1. A bit 10~15 is 2 Advance value equal to (number of words transmitted)-1. Transmission is not completed, when A bit 14 of DCB word 0 is 1 and the XFER command does not complete transmission within 21 seconds, or when the byte count from DCB word 2 or 6 is used up by transmission. Imperfect transmission returns the number of words which was not transmitted by the transmission command to the specified accumulator. Imperfect transmission Set again Cali Flagg who can inspect with the JFLG command, borrow Flagg, and an error flag. When the transmission for which device 2 exceeds the byte count specified by A bit 10~15 of the XFER command is required, device interface adapter 3b does not answer the demand. However, the above-mentioned demand is still undecided. Cali Flagg, tattered Flagg, and an error flag are also Set(ed) in this state. Flagg is reset when that is not right. The data transfer with host memory 1b is addressed in ascending order. Each XFER command is started in the next ascending order address of the last XFER command. That is, by this command, a data block is transmitted and the consecutive addresses of each 1 thru/or 64-word block are specified by host memory 1b. Data is transmitted between the fields specified by programmable off-line start Mohd's DCB. XFERI (register address for 100111XX work) This command is the indirect addressing form of XFER. Drawing 7 illustrates processing of the above-mentioned exterior by secondary microprocessor 3e of an addition card, and the secondary command between insides (DIDO, XFER). Secondary microprocessor 3e assigns 32-word space 101 (not shown) by microprocessor memory 3f as a register which memorizes the data word transmitted by these commands. It is assigned to data input register 102 which receives the data from the outside 16 words in these register fields, and the 16 remaining words are assigned to data output register 103 used as output data sauce. Data input register 102 is further classified into 8 words host input register 104 which receives the external data from host memory 1b, and 8-word device input register 105 which receives the external data from device 2. Data output register 103 is also classified into 8 words host output register 106 which supplies similarly the data transmitted to primary subsystem 1, and 8-word device output register 107 which supplies the data transmitted to device 2. The operation (data transfer) called by DIDO and the specific type of the secondary XFER command is expressed as the frame of the dashed line including the display of these commands. Therefore, "DIDO type A" shown in 108 transmits data to device input register 105 chosen from device 2, "DIDO type B" shown in 109 is from host memory 1b, Transmitting data to selected host input register 104, "DIDO type C" shown in 110 transmits data to device 2 from selected device output register 107, "DIDO type D" shown in 111 transmits data to host memory 1b from selected host output register 106, "XFER type C" shown in 112 passes the course "U" shown in 113 and 114 from host interface adapter 3a, Transmitting data to device interface adapter 3b directly, "XFER type D" shown in 118 transmits data to host interface adapter 3a directly from device interface adapter 3b via the course "V" shown in 119 and 120. "XFER type A" shown in 121 transmits data to host output register 106 from device input register 105, and "XFER type B" shown in 122 transmits data to device output register 107 from host input register 104. It is reserved as other accumulators 122 of a register, objects for work or "scratch Pat" registers 123, and operation status registers 124 of microprocessor memory [ 3f (or separate microprocessor hardware) ]. There are four accumulators, a register for work of a maximum of 64, and at least eight operation status registers. The status information relevant to execution of DIDO or XFER is memorized by accumulator 122 as shown in 125, and it is transmitted to operation status register 124 by one of the internal data transmission commands explained below. Internal data transmission An internal data transmission command transmits data between the registers in an addition card. These commands access register 123 for work, and transmit data from accumulator 122 or accumulator 122. The kind of internal data transmission command is shown below. DECR DECRI GABB GABBI GABL GABLI GARB GARBI GARL GARLI GOBB GOBBI GOBL GOBLI GORB GORBI GORL GORLI INCR INCRI LDIA LDIAI PABB PABBI PABL PABLI PARB PARBI PARL PARLI DECR (register address for 011100XX work) -- this command pulls registers 123-1 for work directed in the immediate data field. when carrying out a under flow, hexadecimal FF arises -- carry/borrow -- each flag of a /error is Set(ed). Flagg is reset when that is not right. A result appears in directed register 123 for work. Accumulator 122 is not subject to the influence by this command. DECRI (register address for 011101XX work) -- this command is the indirect address form of DECR. GABB(000110AC an input register address -- this command AND(s) the byte from data input (directed by A bit 11~15 of immediate data field) register 102 with the contents of 8 A bit of accumulator 122 specified by A bit 6 and 7. GABBI (register address for 000111AC work) -- this command is the indirect address form of GABB. A bit 3~7 of the contents of directed register 123 for work is decoded, and chooses a byte from data input address 102. GABL (000100AC input register address) -- this command is AND(ed) with A bit (directed by the immediate data field) of data input register 102, and the top A bit of accumulator 122 specified by A bit 6 and 7. A result remains in the top A bit of accumulator 122. The remaining portion of accumulator 122 is not changed. GABLI (register address for 000101AC work) -- this command is the indirect address form of GABL. GARB (register address for 001110AC work) -- this command AND(s) the contents of 8 A bit of the register directed by the immediate data field with accumulator 122 specified by A bit 6 and 7. GARBI (register address for 001111AC work) -- this command is the indirect address form of GARB. GARL (register address for 001100AC work) -- this command AND(s) the top A bit of register 123 for work (directed by the immediate data field), and the top A bit of accumulator 122 specified by A bit 6 and 7. A result remains in the top A bit of accumulator 122. The remaining portion of accumulator 122 is not changed. GARLI (register address for 001101AC work) -- this command is the indirect address form of GARL. GOBB (000010AC immediate data) This command sets the byte from data input (specified by A bit 11~15 of immediate data field) register 102 to the contents of 8 A bit of accumulator 122 and OR which were specified by A bit 6 and 7. GOBBI (register address for 000011AC work) -- this command is the indirect address form of GOBB. A bit 3~7 of the contents of directed register 123 for work is decoded, and chooses the byte from data input register 102. GOBL (000000AC input register address) -- this command OR(s) A bit (directed by the immediate data field) of data input register 102, and the top A bit of accumulator 122 specified by A bit 6 and 7. A result remains in the top A bit of accumulator 122. The remaining portion of accumulator 122 is not changed. GOBLI (register address for 000001AC work) -- this command is the indirect address form of GOBL. GORB (register address for 001010AC work) -- this command OR(s) the contents of 8 A bit of register 123 for work directed by the immediate data field with accumulator 122 specified by A bit 6 and 7. GORBI (register address for 001011AC work) -- this command is the indirect address form of GORB. GORL (register address for 001000AC work) -- this command OR(s) the top A bit of register 123 for work (directed by the immediate data field), and the top A bit of accumulator 122 specified by A bit 6 and 7. A result remains in the top A bit of accumulator 122. The remaining portion of accumulator 122 is not changed. GORLI (register address for 001001AC work) -- this command is the indirect address form of GORL. INCR (register address for 011000XX work) -- this command adds 1 to register 123 for work directed in the immediate data field. when overflowing, hexadecimal notation 00 arises -- Cali/borrow -- each flag of a /error is Set(ed). Flagg is reset when that is not right. A result appears in directed register 123 for work. Accumulator 122 is not subject to the influence by this command. INCRI (register address for 011001XX work) -- this command is the indirect address form of INCR. LDIA (011010AC immediate data) This command loads a immediate data field to accumulator 122 specified by A bit 6 and 7. The LDIA command which has the immediate field of hexadecimal notation 00 clears specified accumulator 122. LDIAI (register address for 011011AC work) -- this command is the indirect address form of LDIA. This command loads the contents of 8 A bit of register 123 for work directed by the immediate data field to accumulator 122 specified by A bit 6 and 7. PABB (010010AC output register address) -- from accumulator 122 with which this command was specified by A bit 6 and 7 A data byte is put into the byte position of data output register 103 directed by A bit 11~15 of the immediate data field. PABBI (register address for 010011AC work) -- this command is the indirect address form of PABB. A bit 3~7 is decoded in the contents of directed register 123 for work, and the byte of data output address 103 is chosen. PABL (010000AC output register address) -- this command puts the top A bit of accumulator 122 specified by A bit 6 and 7 into the bit position (directed by the immediate data field) of data output register 103. The remaining portion of data output register 103 is not changed. PABLI (010001AC output register address) -- this command is the indirect address form of PABL. PARB (register address for 010110AC work) -- this command puts a data byte into register 123 for work directed by A bit 8~15 of the immediate data field from accumulator 122 specified by A bit 6 and 7. PARBI (register address for 010111AC work) -- this command is the indirect address form of PARB. PARL (register address for 010100AC work) -- this command is put into the top bit position of register 123 for work to which the top A bit of accumulator 122 specified by A bit 6 and 7 was directed by the immediate data field. The remaining portion of register 123 for work is not changed. PARLI (register address for 010101AC work) -- this command is the indirect address form of PARL. Accumulator operation Operation to data is performed in accumulator 122. The kind and its outline of operation of an accumulator motion command are shown below. AND: Add to the contents of accumulator 122 (Accn) which had the contents of accumulator 122 (0) specified. The top A bit of accumulator 122 (Accn) CLR(ed) : specified is reset to 0. The top A bit of accumulator 122 (Accn) INV(ed) : specified is reversed. The contents of accumulator 122 (Accn) SROT(ed) : specified are shifted or rotated. XOR: Carry out exclusive OR of the contents of accumulator 122 (0), and the contents of specified accumulator 122 (Accn). The details of these commands are explained below. AND: 110010AC XXXXXXXX or 110011AC XXXXXXXX This command adds the contents of 8 A bit of accumulator 122 (0) to the contents of 8 A bit of specified accumulator 122. A result remains in specified accumulator 122. If there is Cali, each flag of an error will be Set(ed). Flagg is reset when that is not right. A immediate data field is not used but the command (A bit 5= 1) of indirect form carries out the directly same operation as form. CLR: 110100AC XXXXXXXX or 110101AC XXXXXXXX This command resets to 0 the top A bit of accumulator 122 specified by A bit 6 and 7. A immediate data field is not used but the command (A bit 5= 1) of indirect form carries out the directly same operation as form. INV: 110000AC XXXXXXXX or 110001AC XXXXXXXX This command reverses the top A bit of accumulator 122 specified by A bit 6 and 7. A immediate data field is not used but the command (A bit 5= 1) of indirect form carries out the directly same operation as form. SROT: 111010AC immediate data The data of specified accumulator 122 is rotated or shifted to the left or the right by decoding of the following immediate data field. A bit 8, 9= 00: Shift to the left if shift out of one is carried out during this command execution -- Cali/borrow -- each flag of a /error is Set(ed). Flagg is reset when that is not right. A bit 8, 9= 01: Shift to the right if shift out of one is carried out during this command execution -- Cali/borrow -- each flag of a /error is Set(ed). Flagg is reset when that is not right. A bit 8, 9=10= left rotation A bit 8, 9= 11: Right rotation A bit 10~15 specifies the number of shifts or number of rotations performed. (The time which each rotation or shift takes is 100 microseconds.) SROTI:111011AC Register address for work This command is the indirect form of SROT. XOR: 110110AC XXXXXXXX or 110111AC XXXXXXXX This command carries out exclusive OR of the contents of 8 A bit of accumulator 122 (0), and the contents of 8 A bit of specified accumulator 122. A result remains in specified accumulator 122. A immediate data field is not used but the command (A bit 5= 1) of indirect form carries out the directly same operation as form. Notes: A byte's value can be reversed by carrying out exclusive OR a total of of specified accumulator 122 and 1. Conditional jump When the specified conditions are satisfied, a command line address register is reset by conditional jump, and two byte addresses of the following form are newly Set(ed). - The top byte of a new command line address is taken out from the immediate data field of the newest BASE command. - The lowest byte of a new command line address is taken out from the immediate data field of the present conditional jump command. Notes: In indirect BASE and jump command form, the byte of a new command line address is taken out from register 123 for work an address is instructed to be by the immediate data field. Note: - BASE and BASEI Set the top byte of a jump line address. - RTN returns a command line address register to the address of the command just behind the executed newest jump command. BASE: 111100XX immediate data This command Set the top byte of a BASE line address equally to the value of a immediate data field. A BASE line address is an absolute line address of 16 A bit used by all the jump commands. If BASE exceeds one half of the byte counts in load program type off-line Mohd's DCB, exception interruption will be reported and A bit 4 of cycle Steel status word 3 will be Set(ed) by 1. Accumulator 122 is not changed by this command. BASEI: 111101XX Register address for work This command is the indirect address form of BASE. JAEZ: 101010AC immediate data When accumulator 122 specified by A bit 6 and 7 is equal to 0, This command resets a command line address register to the 2-byte jump line address formed of the BASE line address (the top byte) and the immediate data field (the lowest byte). A BASE line address is Set(ed) by the BASE command. JAEZI: 101011AC Register address for work This command is the indirect address form of JAEZ. JFLG: 101110XX immediate data Cali/borrow -- if each flag of a /error is Set(ed), this command will reset a command line address register to the 2-byte jump line address formed of the BASE line address (the top byte) and the immediate data field (the lowest byte). In the following case, Flagg is Set(ed). - Cali or borrow arises between the INCR, DECR, or ADD commands. - Shift out of one is carried out from accumulator 122 between the SROT commands. - An error arises between the DIDO or XFER commands. Flagg is reset by the JFLG command and a BASE line address is Set(ed) by the BASE command. JFLGI: 101111XX Register address for work This command is the indirect address form of JFLG. JPIE: 101000AC immediate data When specified accumulator 122 is equal to accumulator 122 (0), This command resets a command line address register to the 2-byte jump line address formed of the BASE line address (the top byte) and the immediate data field (the lowest byte). A BASE line address is Set(ed) by the BASE command. JPIEI: 101001AC Register address for work This command is the indirect address form of JPIE. JPIG: 100000AC immediate data When specified accumulator 122 is larger than accumulator 122 (0), This command resets a command line address register to the 2-byte jump line address formed of the BASE line address (the top byte) and the immediate data field (the lowest byte). A BASE line address is Set(ed) by the BASE command. JPIGI: 100001AC Register address for work This command is the indirect address form of JPIG. JPIL: 100100AC immediate data When specified accumulator 122 is smaller than accumulator 122 (0), This command resets a command line address register to the 2-byte jump line address formed of the BASE line address (the top byte) and the immediate data field (the lowest byte). A BASE line address is Set(ed) by the BASE command. JPILI: 100101AC Register address for work This command is the indirect address form of JPIL. JPIN: 101100 immediate data When specified accumulator 122 is not equal to accumulator 122 (0), This command resets a command line address register to the 2-byte jump line address formed of the BASE line address (the top byte) and the immediate data field (the lowest byte). A BASE line address is Set(ed) by the BASE command. JPINI: 101101 Register address for work This command is the indirect address form of JPIN. RTN: 111110XX XXXXXXXX or 111111XX XXXXXXXX This command returns a program counter to the command just behind the jump command executed at the end. Thus, the subroutine of a single level can constitute with a jump command. Addition card hardware control It is used for these commands controlling addition card hardware. There is the following kind of these commands. STIT STITI TIME TIMEI Next, each command is explained. STIT: 011110AC immediate data This command performs the next operation. - Set the value of a hardware timer. - Make interruption to primary subsystem 1 perform on an addition card. - the fixed line of a device interface control bus -- Set and a pulse -- or clear. Hexadecimal X0, X1 and X3, and X7~XF of a immediate data field are decoded. An accumulator is not used or changed. A immediate data field is coded as follows. A bit 8~11 corresponds to A bit 4~7 of DCB word 1. Although there is an exception, the same operation of a hardware timer is attained. A hardware timer may be again initialized by 15 in the selectable timing of 16 explained by above-mentioned HS Mohd's DCB word 1. Zero decoding function carries out different operation. 0 decoding does not change the timer value Set(ed) before. A timer function changes more mostly [ it is less than 1 of the timer period after STIT command completion, and ] than one half. The value (hexadecimal value) and meaning of coding of A bit 12~15 are shown below. 0: Don't Operate. 1: Take out a "reset" pulse to device interface 3b. 2: Transmit to the top bit position of accumulator 122 which had the status of the "device status bit" line of device interface 3b specified. 3: Carry out the increment of the interface counter specially. 4: Set the top byte of an interface counter specially from specified accumulator 122. 5: Read the lowest byte of an interface counter specially to specified accumulator 122. 6: Set the lowest byte of an interface counter specially from the specified accumulator. 7: Reserve 8: Report exception interruption to a primary subsystem. 9: Report end interruption of a device to a primary subsystem. A: Report exception interruption which has attention to primary subsystem 1. B: Report end interruption of a device which has attention to primary subsystem 1. C: Set "transmission of the last" of device interface 3b. D: Set the "command" line of device interface 3b. E: Set the "status" line of device interface 3b. F: Clear all the device interface tabs. STITI: 011111AC Register address for work This command is the indirect address form of STIT. TIME: 100010XX immediate data This command gives the variable time delay under processing. This command gives the delay for 0.333 m seconds, and when a immediate data field is 00, and that is not right, delay of a 1 m second x immediate data field value is given. For example, when a immediate data field is 08, a process stands by for 8 m seconds by this command, and when a immediate data field is 00, it stands by for 0.333 m seconds. (Delay is less than ±10.0% of the values shown in the immediate data field.) Accumulator 122 is not used by this command, and is not changed. TIMEI: 100011XX Register address for work This command is the indirect address form of TIME. Drawing 8 shows the operation in secondary microprocessor 3e called by the above-mentioned command. Secondary microprocessor 3e combines theoretically the information on data input register 102, and the data of accumulator 122 by commands GABB, GABL, and GOBB shown in 141, and GOBL. Commands GABB and GOBB perform AND operation and OR operation of each specified byte in data input register 102 and accumulator 122 which were specified of a byte unit, respectively. Commands GABL and GOBL perform each AND operation and OR operation of 1 A bit in data input register 102 and accumulator 122 which were specified which were specified, respectively. Commands GARB, GARL, and GORB shown in 142 and GORL perform the logical operation of the data of register 123 for work, and accumulator 122. Commands GARB and GORB make each AND operation and OR operation of 1 byte of byte unit in the specified register which were specified perform, respectively. Commands GARL and GORL perform each AND operation and OR operation of 1 A bit in the specified register which were specified, respectively. Commands PARB and PARL shown in 143 perform the specified byte (PARB) to specified register [ accumulator / 122 / which was specified ] 123 for work, or transmission of A bit (PARL), respectively. Commands PABB and PABL shown in 144 perform transmission of specified 1 byte (PABB) or 1 A bit (PABL) to specified data output register [ accumulator / 122 / which was specified ] 103, respectively. Commands DECR and INCR shown in 145 perform the decrease part operation of a unit of data and unit increment operation which were memorized by specific register 145 for work, respectively. A result of operation is placed on the register. Command LDIA shown in 146 extracts data from the immediate data field of a command (the "memory map" explained later should be referred to), and loads it to specified accumulator 122. Command LDIAI shown in 147 extracts data from register 123 for work specified in the immediate data field of the command, and loads it to specified accumulator 122. Drawing 9 of a device interface format shows the data bus mechanism of device interface 3b, and various kinds of formats which can use these data buses. Device interface 3b contains the data line of 32. The data line of 32 comprises 16 lines of bus 0 group 201, and 16 lines of bus 1 group 202. As for bus 0 group 201, at least Takayoshi of eight lines comprises Set 203 and low ranking Set 204 of eight lines. As for bus 1 group 202, at least Takayoshi of eight lines comprises Set 205 and low ranking Set 206 of eight lines. in change course 207 -- either write-in operation (U8W or U16W) of a single directivity format of HS Mohd's 8 A bit, or 16 A bit, or write-in operation (B32W) of a bidirectional format of 32 A bit. Or at least Takayoshi can transmit a data byte to device 2 via Set 203 from an addition card between PO Mohd's output operation (POXW) or "array index" operation (B16) of a HS Mohd's format. In array index operation, the data transmitted in change course 207 is a portion of 8 A bit of 16 A bit array address. in change course 208 -- between write-in operation (U16W or B32W) of a format of the single directivity of HS Mohd's 16 A bit, or the bidirection of 32 A bit, PO Mohd's output operation, or array index operations, Ranking transmission of the output data is carried out for every byte via low ranking Set 204 to device 2. In write-in operation of HS Mohd's 16 A bit single directivity, and 32 A bit bidirection, PO Mohd's output operation, and array index operation, change courses 207 and 208 are parallel, and are used. The "data" sent out via the above-mentioned change course expresses with array index operation the addressing information relevant to the data which passes the change course relevant to bus 1 group 202, and is sent or received simultaneously. Change courses 207 and 208 are controlled by device interface adapter 3b (Drawing 1) between HS Mohd's operations, Between array index operations and these courses are controlled by secondary microprocessor 3e of an addition (passing "MICROPROC DIRECT" control) card according to operation of device interface adapter 3b about change courses 209 and 210. Since these courses carry out diagnostic operation about these courses and devices 2 via "MICROPROC DIRECT" access of secondary microprocessor 3e, they may be individually used by secondary microprocessor 3e again. Change courses 209 and 210 which send data to device interface adapter 3b from Set 205 and 206 of bus 1 group 202, respectively, At the time of the data transfer between high-speed write-in operations of a format of the bidirection of 16 or 32 A bit, it is used simultaneously (in the case of 32 A bit). Data is in parallel with the data sent via change courses 207 and 208, and it is sent via change courses 209 and 210, and in the case of 16 A bit array index, data is in parallel with the array address sent in change courses 207 and 208, and is sent. These courses are separately controlled by secondary microprocessor 3e directly again. When reading operation is performed by HS Mohd of the format of bidirectional 32 A bit, from device interface adapter 3b, change courses 211 and 212 are in parallel with change courses 213 and 214, and transmit data (byte portion of height) to bus 0 group 201. These change courses are separately usable simultaneous under direct control of secondary microprocessor 3e again. Microprocessor composition and Drawings 10 thru/or 12 of a memory map show the composition of secondary microprocessor 3e with emphasis on assignment (memory map) of memory resources required for operation of secondary subsystem 3 of an addition card. Microprocessor 250 communicates with the microprocessor memory mechanisms containing 8 K bytes of ROM251, and 4.5 K bytes of RAM252 in Drawing 10. The microprogram control mechanism Map(ed) by ROM251 of fixity is shown in Drawing 11. The memory map of other information parameters in RAM252 is shown in Drawing 12. (Volatility) Memories 251 and 252 are accessed by microprocessor R250 via 8 A bit parallel bus (bus 3i of Drawing 1). The 8085A microprocessor of INTEL may be used as microprocessor 250. ROM A tip MK36000 (each is 4 K bytes) of MOSTEK may be used as ROM251. Four INTEL8185 static-RAM modules may be used as RAM252. The power supply of all the elements of an addition card can be obtained from the main power supply of primary subsystem 1. Microprocessor 250 is an internal bus of an operation logic mechanism (ALU) and 8 A bit width, And operation and logic conversion operation are performed for the information on a byte unit including an internal register ("MCS-80/85 TM Family User's Manual of Chapter 6 (October, 1979 INTEL issue) should be referred to). Microprocessor 250 performs many of byte processing functions specified as PO Mohd's operation according to the structure of a fundamental command (page 6-15 of the above-mentioned user manual of Chapter 6 and 6-16 should be referred to). It is coded by the assembly word program which translates the secondary command (command Liszt) with which programming of the machine language instruction was specified. In Drawing 11, ROM251 is applied to memory of the micro program classified and directed into sections 261 thru/or 274. Section 261 is reserved by control and the diagnostic function of the sequence of the power supply ON which does not have direct relation in the present invention. Section 262 is reserved by the sequence of the micro program which deals with the DPC data transfer operation relevant to IDCB, and other IDCB related operations which search, inspect and translate DCB. Section 263 is used in order to indicate the command portion of HS Mohd's DCB by external (for example, DCB words 2 and 3 of Drawing 5). For various kinds of data transfer operations relevant to host interface adapter 3a, secondary microprocessor 3e, and device interface adapter 3b in section 264, It is reserved in order to prepare self-sequence operation of host interface adapter 3a (it may be called a "BASE II adapter"). Section 265 is reserved in order to prepare the timer circuit (contained in control port adapter 3b of Drawing 1) which is not illustrated. Section 266 is reserved in order to prepare self-sequence operation of device interface adapter 3b (it may be called flexible Funel). Section 267 ends HS Mohd's operation and is reserved for the subroutine which sends status to primary subsystem 1. It is reserved although section 268 controls sending to primary subsystem 1 of attention interruption and related status information. It is hit against section 269 translating PO Mohd's command (command). Section 270 contains the "command" subroutine which runs a command Liszt program. Section 271 is reserved by the interruption hair drier subroutine which processes the interruption demand which appeared in device interface adapter 3b. As for section 272, a command Liszt programmer can input directly the command listing function of on-site deployment of the operator of a command Liszt command, It is reserved by the "command Liszt deployment utility" subroutine relevant to a keyboard / display terminal utility (not shown). Section 273 is reserved by various kinds of diagnostic subroutines. Section 274 is reserved in order to process the cycle Steel status and the residual status function in which it explained above. The capacity (number of bytes) of the outline of sections 261 thru/or 274 is as follows. Section Capacity (number of bytes) 261 250 262 1000 263 150 264 500 265 100 266 1000 267 700 268 200 269 1000 270 1500 271 250 272 500 273 250 274 500 Drawing 12 means that five sections 280 thru/or 284 of RAM252 are reserved for the use specified separately. It is reserved although section 280 memorizes a command Liszt program. As explained above, the above-mentioned program is loaded between translations of LPO type DCB (micro program subroutine contained in section 269 of ROM251). The above-mentioned program is run in relation to translation of SPO type DCB (subroutine of section 269 of ROM251), and each command Liszt command / command are translated by the micro program contained in section 270 of ROM251. Section 280 has the capacity memorized to the secondary command (3584 bytes) of a maximum of 1792. As for RAM252, when the memory for longer command Liszt is demanded (specific user), it is clear that it can extend easily, without needing another invention. Section 281 is reserved by an input, the output register, the accumulator, the register for work, the status register (refer to Drawing 7 and the 8th figure), etc. Section 282 is intact, and although the command Liszt deployment terminal of arbitrary selection explained above is supported, it is usable. It is reserved although section 283 memorizes DCB variables (an address, the present byte count coefficient, etc. which access host memory 1b). It is reserved although section 284 memorizes the data collected by the diagnostic subroutine (section 273 of Drawing 11). The example of PO Mohd application The next example of PO Mohd application and related command Liszt program express the versatility of the secondary subsystem of an addition card. Conversion to 10 Advance from the hexadecimal notation In this example, a program reads a hexadecimal number in host memory 16, changes that lowest byte into an equivalent decimal number, and sends the changed number to device 2 via the top bus Set (about Takayoshi of bus 0 group 201 Set (refer to the 9th figure)) of device interface adapter 3b. Conversion by table traction is performed by the indirect addressing of a register. The following command Liszt program (the 1st table), It is loaded to RAM252 of microprocessor 250 by operation of DCB LPO type [ containing the start line parameter which points out the following command line number 00 ], and above-mentioned Liszt's access started by the above-mentioned row number is required of SPO type DCB.
[Table]
[Table]
Interruption ↓ ...................... At the 1st table, "loading immediate" command LDIA of an even number row number with which it continues from 00 to 1E (hexadecimal number) specifies transmission of the above-mentioned value as a specific accumulator "A1" in a immediate data field including 10 Advance values 0 thru/or 15. Command PARB of an odd number row number with which it continues from 01 to 1F and "which be Put(ed) from an accumulator to the register for work" transmits the contents of A1 to continuous registers R0 thru/or RF for work, and loads them to a "conversion table" by it. Command DIDO of row number 20 transmits the value of hexadecimal "argument" changed to a microprocessor memory [ 3f ] host input register (section 281 of RAM252 of Drawing 12) from host interface adapter 3a, The following command LDIA Set 0 to accumulator A1. The following command GOBB OR(s) the value of the argument of an input register, and 0 of A1, and memorizes the result (value of an argument) to A1. The next PARB transmits the value of an argument to register R20 for work from A1, and A1 is Set(ed) by zero with the following command LDIA. The following command GORBI OR(s) the contents of A1, and the contents of the register for work specified with the value (argument) of R20, by it, counts a decimal number equivalent to an argument, and memorizes the result to A1. The contents of A1 are transmitted to a device output register by the following command PABB, and also are transmitted to device interface adapter 3b by the following command DIDO. With the following command STIT, end interruption of a device is sent and operation is ended. As an example of "assembly word" microprograming required to translate a secondary command, the routine which takes out and executes the above-mentioned command LDIA is explained below using the routine word micro instruction of 8085A currently explained in the above-mentioned user manual. The address of the command Liszt command of the 1st next, It is located in the space for "address" work (if this is access of the beginning to Liszt, it is a number of this address space). Initial setting must be carried out to the value specified with the value of the start line contained in DCB of the LPO type translated at the end, It must be transmitted to the address register used for the contents accessing RAM252 (this requires one or the transfer command beyond it). Next, RAM252 is accessed in the specified position of a command Liszt row number, and the contents (namely, command LDIA) are transmitted to the register for work (for example, transfer command). Next, the "OP code" (in this case, 69XX) of the taken-out command of command Liszt is compared until a set of continuous values and a value in agreement are found using some compare instructions. After each comparison, microprocessor 250 executes a conditional jump command and carries out conditional branch to the subroutine relevant to translation of the OP code of a corresponding secondary command. Therefore, if coincidence arises, microprocessor 250 will be jumped to the taken-out command and the sequence which translates LDIA in this case. Next, if the group of operation of comparison and a conditional jump is performed in relation to A bit 6 and 7 of a command (LDIA), microprocessor 250 will investigate coincidence with the accumulator number specified by these A bits. If coincidence is found, microprocessor 250 will be jumped to the command which transmits the immediate data field of the LDIA command to the accumulator specified from the register for work. Check sum calculation program This example of application of programmable off-line Mohd calculates the check sum of command Liszt of host memory 1b. An addition card calculates command Liszt's check sum, and memorizes it at the time of command Liszt's end. In this example, a command program calculates the check sum of command Liszt of itself. LPO type DCB is coded as follows. - Chaining-on - deterrence exception ON - 21-second timeout-on -DCB word 3= 0000 (hexadecimal notation) - DCB word 5= programmable off-line start Mohd's DCB address -DCB word 6= command Liszt's X start address of byte count+2-DCB word 7= command Liszt X This information is memorized by microprocessor 250 and Liszt is also loaded (RAM252). SPO type DCB is Set(ed) as follows to check sum calculation. - Deterrence exception OFF - Chaining-off - A write-in address = command Liszt's X start address - write-in byte count = command Liszt's X byte count - reading address = write-in address + write-in byte count - reading byte count = after memorizing 0002 bytes of this information, Microprocessor 250 starts command Liszt's sequence by which partial memory was carried out by row number (specified by word 3 of LPO type DCB) 0000. A check sum program is shown in the 2nd table.
[Table]
[Table]
In order to understand how this check sum program operates, In this program, accumulator A1 Accumulation the lowest byte of a check sum, Register R0 for work Accumulation the top byte of a check sum, register R2 for work Accumulation the top byte of the changing byte counter, and it must be understood that register R3 for work Accumulation the lowest byte of the same byte counter. The check sum formed is of all the bytes' of command Liszt's sum total, and the changing byte counter is inversely proportional to the totaled number of bytes (that is, when all the bytes are totaled, set to 0). By the first seven lines (00~06) of a program, microprocessor 250 uses the command in command Liszt by whom partial memory was done (LPO type DCB), (It was contained in word 6 of LPO type DCB) An initial byte count value is put on registers R3 and R2 for work. With the command of row number 07~0A, microprocessor 250 OR(s) the contents of R2 and R3, and it is determined whether the result is 0 (that a result is 0 expresses zero byte count, therefore end conditions). Since a byte count is not 0 at this time in a program, microprocessor 250 executes the command of row numbers 0B and 0C, Accumulator A0 is cleared and a command Liszt element (beginning) is again loaded to a partial (host input) register from primary subsystem 1. By three commands of following row number 0D~0F, microprocessor 250 adds the top byte of just re-loaded command Liszt Ward to the present contents (the "beginning 0" lowest byte of a partial check sum) of A1, The conditional jump to the command of command Liszt's row number 19 is performed by row number 0F. If Cali arises in the above-mentioned addition, a jump is performed, and when that is not right, the command of row number 10 will be executed. When Cali arises, the increment only of 1 is carried out, and the contents (namely, the top byte of a check sum) of R0 are row numbers 1A, and it carries out a return to the next line (namely, row number 10) of the line which produced the jump. Microprocessor 250 meets with another conditional jump in row number 10~13. It is decided [ whether the jump to row number 19 is performed, and ] by whether in this sequence, command Liszt Ward's 2nd re-loaded byte was added to the contents (partial check sum) of A1, and Cali occurred. When Cali arises, the increment only of 1 is carried out and it carries out the return of the contents of R0 to row number 14 (the next line of a line including the last jump command). By the command of row number 14, only 1 carries out the decrease part of the contents (the lowest byte of the byte count formed partially) of microprocessor 250R3. When the amount of this decrease produces borrow, the conditional jump to row number 1B is performed by the command of row number 15, In row number 1B, the decrease part only of 1 is carried out and the contents (the top byte of a partial byte counter) of R2 carry out the return of the microprocessor 250 to row number 16 by the return command of row number 1C. by row number 16, the decrease part of the contents of R3 is carried out only 1 again (the length of Ward by whom the partial byte count was transmitted -- that is, it decreases by 2 bytes). Next, the conditional jump to row number 1B is again performed by the existence of borrow generating by row number 17. When a jump is performed, the decrease part only of 1 is carried out and it carries out the return of R2 to row number 18. When a jump is not performed, the command of row number 18 is executed immediately after the command of row number 17. Including an unconditional jump command, by it, the return of the row number 18 is carried out to row number 07, and it carries out the repetitive start of the front sequence. Therefore, command Liszt's next Ward is taken out from host memory 1b, it is re-loaded to a host input register, the byte is added to a partial check sum, and it is repeated by the wind that a byte count decreases two times. All the Ward of command Liszt is again taken out from host memory 1b by the host input register, the last check sum is formed, and this process is repeatedly continued until the decrease part of the byte count is carried out to the value of 00. If end conditions are fulfilled by row number 0A, the jump to row number 1D will be performed, 2 bytes of the last check sum will be transmitted to primary subsystem 1 by row number 1D~20, and operation will be ended. The burden placed on the host system software to calculation of the check sum relevant to each command Liszt by the above-mentioned application is eased. It is although a program calculates the check sum of command Liszt of itself in this specific example, By specifying effectively a different command Liszt boundary in SPO type DCB which operates a check sum computer style, also although different Liszt's check sum is calculated, it is easily usable. The check sum computer style of this example is although it is included in command Liszt in whom the check sum is formed, It is not necessary to express the whole Liszt, and the subset of a command of 33 is only expressed, and the command after in command Liszt is usable although other functions which can be performed by off-line Mohd are performed. Secondary subsystem 3 of an addition card is used for emulating the adapter which the device with which an addition card does not suit requires in this example called the example of combination application of PO and HS Mohd "virtual adaptation." For example, the case of the tape drive "not suiting" is considered. The host system in this case loads a command Liszt program to an addition card, and uses it effective in emulating adaptation functions (the position of the record on a tape to wish to have is found) required to prepare a tape subsystem for data transfer. And DCB is accessed by carrying out chaining of reading or the writing of HS Mohd, and a data block is transmitted between a host and a tape. And another Liszt is loaded by DCB chaining and an addition card performs "cleanup" operation (collection of the last status, determination of whether the error arose, and sending to the host system of suitable end interruption) by it. Double Mohd application This kind of example is based on the form of DCB of the SPO type shown in Drawing 5, and its modification. Ward 2, 3, 6, and 7 of the DCB gives the start address and length (byte count) which determine two fields in host memory 1b. It dissociates completely, or these fields may overlap or may be completely in agreement. As shown in Drawing 5, these fields are called "reading" and a "write-in" field. The reading field is reserved by reception of the data from an addition (under directions of command of transmission and secondary DI/DO command Liszt) card by DCB, and the write-in field is reserved by memory of the data transmitted to an addition card. By programming of these parameters and the suiting secondary level, secondary subsystem 3 (passing command Liszt who explained above) is. Or direct microprogram control operation of secondary microprocessor 3e of an addition card, Between specified host memory 1b and an addition card, or devices 2 (Using DIDO and XFER for example) and data transfer can be performed, and A bit or the byte of data can be operated logically, and various kinds of signal processing and conversion operation of a data part can be performed. The addition card can process a data set by the above-mentioned operation. The example of the above-mentioned operation for performing the encryption and the decipherment of data in the communication link which is not protected is explained in relation to Drawings 13 thru/or 15. About other application, it will become clear to a person skilled in the art by explanation about these application. It becomes clear by explanation that it is also impractical to make it perform with secondary subsystem 3 lacking in the double mode off-line capability relevant to SPO type DCB for these operations. However, it can know immediately that it is not possible to perform these transmission and a conversion operation using a plurality of DCB commands from the ability only of the portion of the data transmitted by restriction of capacity to memorize on an addition card. Drawing 13 shows double Mohd encryption Motivation using reading and the write-in field of host memory 1b which were specified by SPO type DCB. By modification of the above-mentioned operation explained in relation to Drawing 14, An addition card receives the portions of two data sets (large) from two "reading" fields in host memory 1b specified by SPO type DCB, The receipt Ivy portion of both Set is processed logically, and the 3rd data (enciphered) of the small transmission unit by the protected communication link is generated from there. Since the addition card can memorize neither of two data sets in this application again, it is not practical by transmitting a data set by one DCB and operating it by different (or it is equivalent) DCB to perform the above-mentioned operation. In another modification shown in Drawing 15, an addition card decodes receipt Ivy data by device interface adapter 3b, It puts on the field of host memory 1b specified by SPO type DCB in information two related "sheet" "write-in" of the decoded data and a future encryption session. [ each ] In Drawing 13, Ward 2 and 3 in SPO type DCB which has the form shown in Drawing 5 specifies reading field 302 in the main memory field 301 of primary subsystem 1, and Ward 6 and 7 of above DCB specifies write-in field 303. The capacity of the secondary subsystem (addition card) shown by 304 is better than which of reading field 302 or write-in field 303 at least including partial memory mechanisms 305 (for example, RAM252). As shown in 306, even if the size of reading field 302 is small to the size of write-in field 303 and it is large, it is equivalent and its Then is also good. If an addition card receives DCB which specifies fields 302 and 303 by microprograming programming of the suiting secondary command, or directly [ equivalent ] (non-assembly), (Using the command of the secondaryDIDO type explained above) It is based on the data of the small unit received and memorized, "The data which is not enciphered" shown in write-in field 303 is transmitted to partial memory mechanisms 305, Then, conversion operation which enciphers the transmitted data part (using the secondary command of logical byte operation explained above) is performed, and the enciphered data part which arose as a result is further transmitted to reading field 302 (for example, the DIDO command). The above-mentioned process is repeated until all the data sets as which write-in field 303 is not enciphered are enciphered by secondary subsystem 3 of an addition card and the enciphered data set is memorized to reading field 302. And enciphered data which was memorized to reading field 302, (Passing a different addition card combined with the channel of primary subsystem 1 via secondary subsystem 304 of an addition card, when the above-mentioned subsystem has combination with a communication link) It is high-speed write-in transmission, It can send to the communication link (for example, remote process link) which is not protected. By modification of the above-mentioned application shown in Drawing 14, the main memory of primary subsystem 1 is the beginning, The data and the key algorithm which are not enciphered shall be included to two dispersed separate write-in fields 308 and 309, and secondary subsystem 310 of an addition card shall be connected to either the I/O device which is not protected or transfer link 311. DCB of the SPO type explained in Drawing 5 shall specify beforehand two information which has undisplayed A bit beforehand and determines reading or a write-in field by Ward 2 and 3, and the information which determines reading or a write-in field by Ward 6 and 7 as the field specified that it is intact. In the example of Drawing 14, these A bit are Set(ed) by SPO type DCB which specifies fields 308 and 309 so that both fields may be appointed as a write-in (output) field. Therefore, when this DCB is sent to secondary subsystem 310 programmed appropriately, Information as which secondary subsystem 310 is enciphered from field 309 in the portion of the information on field 308 (Using for example, the DIDO command) It transmits and transmits the data which enciphered receipt Ivy data and was enciphered from field 308 using receipt Ivy information from field 309 in transfer link 311 (for example, another DIDO command). An addition card repeats the above-mentioned process until it is enciphered and all the data is transmitted by transfer link 311 in the enciphered form. Based on variable "sheet" function 312, as for an encryption process, an addition card may generate a residual seed function between encryption processes. By the end of a transmission session, the last residual seed function is sent to the other end of a system by transfer link 311, and another encryption and the transmission session based on the seed are started based on the above-mentioned seed. in this example -- change of the seed for every session, the position of a key algorithm, and each field (and protected separately potentially) of host memory 1b, Higher protection is given as long as it is prohibited to the user of primary subsystem 1 which accesses the data which is not enciphered from accessing the first seed or a key algorithm. In the application shown in Drawing 15, secondary subsystem 315 of an addition card receives the enciphered data from remote process link 316, The decipherment process of the small unit of data is performed, and the data and the seed information which were decoded are transmitted to each reading field 317 and 318 of host memory 1b, in order to start a future encryption session. In this application, DCB of the SPO type prepared by primary subsystem 319 appoints fields 317 and 318 as a reading (data input) field to an addition card. At this example, the enciphered data is received by a small unit with an addition card. Using a secondary command program (DIDO command) or the equivalent non-assembly micro program memorized before, an addition card decodes data and transmits the data which is not enciphered to reading (using DIDO or equivalent transmission operation) field 317. Reading of each portion of data will generate the key algorithm which a residual sheet is formed, the "last" residual seed is remembered to reading field 318, and primary subsystem 319 uses it, and is used in the next communication session. In this example, it may be refused again that the user of primary subsystem 319 and data accesses both a key algorithm and a seed function. It is generated by the process which cannot be used in the course of the data in which the key algorithm was enciphered, and a new key algorithm and seed can generate for every session. The person skilled in the art will understand that there is application of many potentially equivalent to the description child of such "double Mohd" SPO type DCB. For example, it is used with the addition card of the microprocessor which has the limited memory, and performs matrix multiplication, Fourier transform, or other "signal-processing" operations. The information changed is transmitted to an addition card by a small unit, and the information on the result is transmitted to a primary subsystem by a small unit. Multiple Mohd's DCB structures are used for supporting full-duplex composition or two or more data-communications session under the envelope of single DCB. It is extended easily and DCB or an equivalent thing double Mohd SPO type [ containing the parameter a person skilled in the art decides two storage areas to be ] is three or a storage area beyond it. He has to understand that (for example, one storage area transmitted to the addition card which thinks the matrices of the result formed with the addition card to be two storage areas holding the element of two matrices) can be specified. The information to which another feature of this double Mohd application was sent to the addition card from primary subsystem 1 by either of the above-mentioned operations can be saved to the original write-in field, and when an error arises (by transmission to secondary subsystem 3 of an addition card), the recovery process of primary subsystem 1 is simplified. In the system of the prior art with which the Oba light of the field containing data is carried out when data is transmitted externally, Since the original data cannot be used any longer, therefore it must be generated repeatedly [ of a "long" (that is, it cuts in that of expense) software process ] if an error is detected, recovery is complicated. A plurality of storage areas may be located in the protection location of the protection location of the same key, or a different key. When a plurality of keys are used, those keys are intact now or are specified in the field of spare SPO type DCB. Assignment of two "double Mohd" storage areas of host memory 1b can be easily defined with the signal from device 2, and the assignment this method "was postponed" may be helpful in specific application. The parameter of the residual status block (RSB) explained above, The status (it can set in the described example relevant to input-and-output transmission of host memory 1b of the type used in SPO type application/format of Drawing 13, and Or and others) of the result related with two series of double Mohd data transfer operation is memorized. An addition card runs a secondary command program without the necessity of interrupting primary subsystem 1 after each partial transmission of the data relevant to one of fields by this. It is single interruption which reports the status result of double Mohd operation under DCB single SPO type (rather than requiring separate interruption for the transmission status relevant to each specified host memory field), An addition card transmits status information to host processor 1a. Although Multiplex / demulti pre Tux application book application is not illustrated, device interface adapter 3b of secondary subsystem 3 of an addition card is connected to a device multiplexer (not shown). Even a maximum of eight devices 2 (for example, a process sensor and an actuator) control a device multiplexer. An addition card addresses these devices 2 in order of rotation by sending a "sub-address specification" signal to fixed interface rye in S0, S1, and S2 (an addition card and device 2 have common "device address" in relation to primary subsystem 1). If each device 2 is addressed, data will be sent to device 2 or will be received from device 2 (for example, DIDO or a XFER type command). If high speed mode transmission of the data from a primary subsystem or a primary subsystem is required, with device 2, end conditions are shown, and an addition card will hold device addressing status and will transmit by carrying out a chain to HS Mohd DCB. after this transmission, DCB is asked to the next, when chaining to LPO and SPO type DCB is required further and end conditions are not shown -- it is a position of intermediary There was device 2, and continues "polling" or a "question" of device 2. System action outline Drawings 16 thru/or 18 show the outline of the operation performed by primary subsystem 1 and secondary subsystem 3 of an addition card in relation to the present invention. Drawing 16 shows the process relevant to IDCB translation. By block 401, primary subsystem 1 chooses branching to IDCB, is block 402 and branches in the type of the command specified in the command field (54 of Drawing 4) of IDCB. When IDCB specifies DPC (direct programmed control) operation, secondary subsystem 3 of an addition card is chosen and a sequence branches in the transmission direction (reading (RD) or writing (WR)) specified using IDCB command field information by block 403. When IDCB (operation of block 404 or 405) is transmitted to an addition card from an addition card, respectively, data is transmitted from a immediate data field or a immediate data field. When reading (input) operation is specified, data is sent to primary subsystem 1 via host interface adapter 3a from partial memory of an addition card, and is memorized by host processor 1a in the immediate data field (inside of host memory 1b) of IDCB. When write-in (output) operation is specified, data is sent to secondary microprocessor 3e of an addition card via host interface adapter 3a, and is memorized by partial memory (RAM252 of Drawing 12) of an addition card. When CS (cycle Steel) operation is specified by IDCB, host processor 1a chooses an addition card, transmits IDCB information to an addition card, and memorizes it to partial memory (blocks 407 and 408) of an addition card. When this IDCB information is received, secondary microprocessor 3e of an addition card performs operation of block 409~412, and is search of DCB information, Transmission etc. are performed and host processor 1a is immediately released after transmission (for the attention to translation of other commands in a program, and interruption, etc.). Secondary microprocessor 3e of an addition card, It is determined that the DCB address contained in the "immediate data field" portion of the IDCB information by which the present partial memory was carried out is taken out (block 409), and host interface adapter 3a takes out DCB which occupies the address in cycle Steel operation (block 410). Host interface adapter 3 sends searched DCB to local memory of an addition card via a secondary microprocessor (block 411), and secondary microprocessor 3e starts memorized subroutine 412 which translates now DCB by which partial memory was carried out. DCB is searched and the microprocessor subroutine which translates it is contained in section 262 of ROM251 of Drawing 11. The above-mentioned DCB translation subroutine is shown in Drawing 17. By branching (block 415) by the Mohd A bit contained in DCB Ward's 1 A bit 0, secondary microprocessor 3e chooses either subroutine 416 relevant to preparation of HS Mohd's operation, or subroutine 417 relevant to PO Mohd's operation. When HS subroutine 416 is chosen, it is secondary microprocessor 3e, It branches by DCB Ward's 0 A bit 2 (block 418), and shows the direction of high-speed-data transmission (reading / input, or the writing/output from host memory 1b to host memory 1b) specified by this DCB. It responds to the value (format specification A bit) by the combination of the above-mentioned A bit and DCB Ward's 1 A bit 2 and 3 (block 419), Eight kinds of branching are obtained (block 420), and preparations of interface adapters 3a and 3b of operation are made (block 421), Data is transmitted between primary subsystem 1 and external device 2 by one of the two directions (work), and one of the four formats (bidirection of 8 or the single directivity of 16 A bit, 16, or 32 A bit) (block 422). After transmission operation is completed, a secondary microprocessor memorizes status to partial RAM (block 423), and branches by the chain flag bit of DCB Ward's 0 A bit 0 (block 424). When Ward's 0 A bit 4 is 1, an addition card transmits residual status to primary subsystem 1 (Step 423). If chaining is specified (block 424), secondary microprocessor 3e will take out the next DCB from the position of host memory 1b specified by Ward 5 of the present DCB, and will start translation of the DCB (block 425). If chaining is not specified (block 424), by interruption, termination status is transmitted to primary subsystem 1, and operation is ended (block 426). By block 415, when it branches to PO subroutine 417, an addition card is "type A bit" (Ward's 1 A bit 1), and branches to either of a LPO type or SPO type PO Mohd DCB (block 427). If a LPO type is specified, secondary microprocessor 3e will branch to the Liszt chief factor (DCB Ward 6) (block 428). By 0000 (hexadecimal notation), secondary microprocessor 3e carries out local memory of the start line information (DCB Ward 3) (block 429), and the Liszt chief factor memorizes status, when command Liszt is loaded beforehand (423). In other than 0000, it progresses to block 423 through blocks 433 and 434. By block 427, if a SPO type is specified, secondary microprocessor 3e will perform operation of block 436~442. In these operations, secondary microprocessor 3e prepares the start line information saved by Ward 3 of the command of the LPO type translated at the end with the command address register, A related command Liszt command is accessed (blocks 436 and 437), the above-mentioned command is executed (block 438), the increment of the command address is carried out (block 439), and it branches by the existence of the existence of the end conditions specified before (block 440). When end conditions exist, secondary microprocessor 3e memorizes status (block 442). When end conditions do not exist, secondary microprocessor 3e branches in command extraction operation (block 437) via course 441. This directs the command position specified by the address etc. by which increment was carried out to secondary microprocessor 3e. Although the above is overall outline explanation, the command of the jump and the return is not shown. These functions and the specific command explained above are not the portions of the present invention. The person skilled in the art understands that a jump and a return command are processed by branching or jump conditions by related judgment block. If conditions are satisfied, the address of the present command is saved. The address instruction address specified by the jump command is replaced with an instruction address register. It is saved by execution of a return command (increment carried out), and a It was address is loaded to an address register and the interrupted sequence continues it. First, it starts by preparation (block 451) of a command address, and Drawing 18 shows the command execution (in simple form) which results in the decipherment (block 453) of OP code A bit 0~4 following extraction (block 452) of a command. These 5 A bit branch the sequence of secondary microprocessor 3e to one of the subroutines of 32 shown by 454, and branching is further performed on condition of /indirect A bit (A bit 5) directly by block 455. When this A bit directs operation directly, the data of the immediate field is used as data. When this A bit expresses indirect operation form, the data of the immediate field is used as an addressing parameter. Dashed line blocks 456 and 457 express the performance and the logical data manipulation function of data transfer, respectively. Processing of the jump and the return function is not shown for simplification. As explained above, it is helpful for these considering the return to the command immediately after a jump command as conditional branching to the command contained in the jump position specified by the immediate field. the increment of the command address is carried out by block 458 after execution of each command (and -- in a jump, saved), and end conditions are inspected by block 459. When end conditions exist, status is memorized and branching by chain A bit is performed by block 460. When end conditions do not exist, he follows a sequence to extraction (block 452) of the command specified by the present contents of the command address register according to course 461. As explained above, the end conditions for ending execution of command Liszt's command are generable with either device 2 or the command under translation. As a warning about the clear end by a command, while a command sequence is in a jump subroutine, don't produce an end. This is because it becomes difficult to schedule correctly continuation of the sequence by which addressing of command Liszt has an indefinite thing, and primary subsystem 1 was interrupted when such. At the point determined by the conditions which it is at the end time and exist, command Liszt's program has an option of a re-start by specifying the next line in a Continuing sequence as the line of the performed last. A programmer has conversely an option which disregards the conditions which it is at the end time and existed to the jump command by re-starting by a jump line of code again. Above, the detailed explanation about the outstanding secondary subsystem which gives the degree of the diversity considered that it cannot attain depending on the conventional secondary subsystem by programmable off-line Mohd's operation is finished as the high speed in which a chain is possible.
[Brief Description of the Drawings]
Drawing 1 is a system block diagram showing generally an environmental system including the example of the present invention, Drawing 2 is a figure showing the outline of various kinds of system configurations with an usable secondary subsystem by the present invention, Drawing 3 is a functional flow chart showing the system operation containing the secondary subsystem by the present invention, Drawing 4 is a figure showing the process in which primary command information is created by a primary subsystem, is supplied to a secondary subsystem, and starts operation of the present invention, Drawing 5 is a figure showing the form of various kinds of models of a primary command and logical use by the present invention, Drawing 6 is a figure showing secondary command Liszt Alley's form by the present invention, Drawing 7 is a figure showing the logical construction of the secondary subsystem which answers the directed secondary command and moves data between the memory of a secondary subsystem, a primary subsystem, or a device, Drawing 8 is a figure showing the logical construction of the secondary subsystem which answers the directed secondary command and moves data internally, The figure and Drawing 10 showing the device interface whose Drawing 9 carries the variable format data about the adapter of the secondary subsystem by the high speed mode of the operation relevant to the present invention are schematic block diagrams of a secondary microprocessor, and its ROM and RAM, Drawing 11 is a figure showing the memory map of the subroutine in ROM, and a microcode, Drawing 12 is a figure showing Map of memory assignment of IDCB in RAM, DCB, data, a command Liszt parameter, etc., Drawings 15 are Drawing 13 thru/or a figure in SPO type DCB showing double Mohd's real-time application in some numbers, respectively, Drawings 16 thru/or 18 are figures showing the microprocessor translation sequence of IDCB processing, DCB search / translation, and secondary command (command Liszt) search / translation, respectively. 1 ...... A primary subsystem, 1a ...... A host processor, 1b ...... A host memory, 1c ...... A host I/O channel, 2 ...... A device, 3 ...... A secondary subsystem, 3a ...... A host interface adapter, 3b ...... A device interface adapter, 3c ...... A hand Shu king logic adapter, 3d ...... A control port adapter, 3e ...... A secondary microprocessor, 3f ...... A microprocessor memory, 3g ...... A bus, 3h ...... A bus, 3i ...... A bus, 4 ...... An external bus, 5 ...... An external bus, 101 ...... 32 Ward field, 102 ...... A data input register, 103 ...... A data output register, 104 ...... A host input register, 105 ...... A device input register, 106 [ ...... The register for work, 124 / ...... An operation status register 201 / ...... Bus 0 group, ] ...... A host output register, 107 ...... A device output register, 122 ...... An accumulator, 123 202 ...... Bus 1 group, 203 ...... At least Takayoshi is Set and 204. ...... Low ranking Set, 205 ...... At least Takayoshi is Set and 206. ...... Low ranking Set, 207, 208, 209, 210,211,212,213,214 ...... A change course, 250 ...... A microprocessor, 251 ...... ROM, 252 ...... RAM, 301 ...... The main memory field, 302 ...... A reading field, 303 ...... A write-in field, 304 ...... A secondary subsystem, 305 ...... Partial memory mechanisms, 306 ...... The variable portion of a reading field, 308 ...... A write-in field, 309 ...... A write-in field, 310 ...... A secondary subsystem and 311 ...... a transfer link and 312 ...... a variable seed function, a 315......secondary subsystem, and 316 ...... a remote process link and 317 ...... a reading field and 318 ...... a reading field and a 319......primary subsystem.
6 members in 4 offices
Priority claims1
| Document | Office | Kind | Date |
|---|---|---|---|
| 34510182 | United States of America | A |
Members6
| Document | Office | Kind | |
|---|---|---|---|
| JPS58134360A | Japan | A | |
| AU1094083A | Australia | A | |
| US4451884A | United States of America | A | |
| CA1182577A | Canada | A | |
| AU552852B2 | Australia | B2 | |
| JPS626271B2This record | Japan | B2 |
Numbers
- Application
- 21849182
Classification
- CPC, 2
- G06F13/282
- G06F13/124
- IPC, 6
- G06F15 16
- G06F13 00
- G06F13 12
- G06F13 28
- G06F15 17
- G06F15 177