Non-volatile semiconductor memory device

[Detailed Description of the Invention]

[Industrial Application] This invention relates to the structure of the memory cell of a nonvolatile semiconductor memory, especially epsilonEFROM (read-only storage cell in which rewriting/elimination is electrically possible).

[Description of the Prior Art] the -- the [A / 2 / figure thru/or ] --C [ 2 ] figure is a figure showing the composition of conventional nonvolatile semiconductor memory %NI! -- the --A [ 2 ] figure -- a plane arrangement plan -- the --B [ 2 ] figure -- the -- the section structure which met the B-B line ofA [ 2 ] figure -- the --C [ 2 ] figure is a figure showing an equivalent circuit, respectively. The composition of this nonvolatile semiconductor memory is U.S. Institute of Electrical and Electronic Engineers (IEEE), for example. Journal of Solid state Vol of a circuit (Journal or 3o1id-3tatc C1rcuits), 5O-17, No, 5.Oct It is indicated to 821 pages in 1982 thru/or 827 pages. the -- inA [ 2 ] figure, the memory cell of a nonvolatile semiconductor memory contains memory transistor 1 which memorizes information, and selection transistor 2 of It was which chooses memory transistor 1. Floating gate 4 for memory transistor 1 to accumulate an electric charge, Control gate 5 which IJIII(s) accumulation 77 discharge of the electric charge in 70-Tyng gate 4 ll1, N+ un-+1@ Expansion! It has sauce 6 and Dorain 7 who are formed in & layer, respectively, and is usually FET. MOS (F loatlng Gate E 1ectroi1 TunnelingMOS) It is called. Selection gate]2 which changes selection transistor 2 into ON or an OFF state according to the voltage on which selection transistor 2 is given there, It has sauce 7 which shares N1 impurity diffused layer which forms Dorain 7 of Memory run District 1, and is formed, and Dorain 11 formed by N+ impurity diffused layer. the -- inB [ 2 ] figure, N+ diffusion zone which serves as sauce 6 of memory transistor 1 and Dorain 7 is formed in the predetermined field of P type semiconductor substrate 3. Floating gate 4 is formed via the 1st oxidization lI8 on the semiconductor substrate of the big building of sauce 6 and Dorain 7. The Dorain field by transverse direction diffusion of N+ diffusion zone is formed directly under floating gate 4. Especially an oxide film between this floating gate 4 and a transverse direction diffusion Dorain field is called tunnel oxidization llll9. On floating gate 4, it is formed so that control gate 5 may cover floating gate 4 via the 2nd oxide film (the oxide film between poly -Poly is called hereafter) 10. On the other hand, selection gate 12 is formed via gate oxide 13 on the semiconductor substrate between sauce 7 in which selection transistor 2 is formed from N+ diffusion zone, respectively, and Dorain 11. the -- since N+ diffusion zone 7 is shared as Dorain of memory transistor 1, and sauce of selection transistor 2 so that it may be seen inC [ 2 ] figure, memory transistor 1 and selection transistor 2 are connected in series. Next, operation is explained. Memory of the information on this semiconductor memory device is performed by pouring an electric charge into floating gate 4 of memory transistor 1. Since this floating gate 4 is enclosed by the oxide film and is in an electric floating state, memory of information [ Volatilization / un-] is realized. Pouring/drawing out of the electric charge of floating gate 4 impress a high electric field with tens MV/C of 1 or more about to 1st gate oxidization 11118, and is performed by carrying out tunnel injection of the electric charge into the 1st gate oxide. Hereinafter, memory operation of a memory transistor is explained. The case where an electron is first poured in to floating gate 4 is explained. At this time, the about [ 20V ] high voltage is impressed to control gate 5, and Ov is simultaneously given to sauce 6 and Dorain 7. Voltage on which the potential of floating gate 4 was given to control gate 5, Set in the capacitive coupling circuit which comprises capacity of a between [ the capacity between control gate 5-floating gates 4, the capacity between 70-Tyng gate 4-Dorain 7, the capacity between floating gate 4-semiconductor substrates 3, and control gate 5-sauce 6 ]. It can ask by carrying out capacity division. That is, by taking such capacity suitably, floating gate 4 can be given, without seldom spoiling the high voltage given to control gate 5, and a high electric field can be generated among floating gate 4-Train 7. Generally, if a high electric field is impressed to an oxide film, the probability that an electron will tunnel the potential barrier of an oxide film will increase. Therefore, a negative electric charge is accumulated in 70-Tyng gate 4 via tunnel oxide film 9 from Dorain 7, and the threshold of memory transistor 1 is shifted to a positive value. Hereinafter, this state is called an elimination state and the memorized information is made into "1'. Next, an electron is explained about a To deal with case from floating gate 4. At this time, OV is given to control gate 5, and also the about [ 20V ] high voltage is impressed to Dorain 7, 5v is given to sauce 6, and it is carried out by making floating gate 4-Dorain 7 question produce high voltage potential. As a result of an electron's flowing out of floating gate 4 into Dorain 7 via tunnel oxide film 9 by this high electric field, a positive electric charge is accumulated in floating gate 4, and the threshold of memory transistor 1 is shifted to a negative value. Hereinafter, this state is called a write-in state and suppose that information *0'' was memorized. Successive occurrence of the information which memory transistor 1 has gives Ov to control gate 5. sauce 6, and is performed to Dorain 7 by giving about several v low voltage. Although memory transistor 1 will be in ON or an OFF state according to the electric charge accumulated in 70-Tyng gate 4 at this time, The current which flows among sauce Dorain of memory transistor 1 at this time and selection transistor 2 is amplified using a sense amplifier (not shown), and memory information is read by detecting the ON state or OFF state of memory transistor 1. Drawing 3 -- the -- the [ 2 8 figure thru/or ] -- it is a figure showing the equivalent circuit of the capacity formed between the control gate of a nonvolatile semiconductor memory and semiconductor substrate which are shown inC [ 2 ] figure. Since insulating film <Gift-ization gl is formed, respectively between control gate 5. floating gate 4. semiconductor substrates 3, Capacity ■ is formed between each. Therefore, between control gate 4 and semiconductor substrate 3, it is so that it may be seen in Drawing 3, Capacity ff1between control gate floating gates c1 is formed in Capacity 11Gbetween floating gate boards2, Capacity 1ic3 between floating gate Dorain, the parallel object of Capacity 1c4 between floating gate sauce, and series. Hereinafter, it is considered as impression high voltage VFF using Drawing 3, and is potential V of floating gate 4 at that time. It asks for potential difference Vox between floating gate 4-Dorain 7. The electric charge accumulated in 70-Tyng gate 4 now is set to Q, and potential of control gate 5. sauce 6, Dorain 7, and semiconductor substrate 3 is set to Sorely and V CG I Vs * Vo+Vs. A following formula (1) is materialized at this time. (VF-Vccl'LCI+ (potential difference ■ between floating gate Dorain at the time of elimination and writing as [ Vr -Vss'L """ (VF-Vp) -C30 (VF-Vs) and C'l =-0F lupsilon0r-] 0 C.)) 8 is given by following formula (2) and (3), respectively. At the time of elimination: Since it is Vc G=Vr F and Vo -Vs -Vs s-Ov, it is from a formula (1). Vr "Vo x -CI XVF P /CT " -- the time of -(2) writing : Vc G =Vt t-OV, Vo -VF F %Vs =Vc (5V) Since it is, it is potential difference V between (C3XVr P+C4XVs) Vr =/CT and (3) floating gate Train from a formula (1). since 8 is VF r-Vr -- Vow "[(CI"C2+C4) -- it carries out and is 'yp -CJ-V5 E /CT -= (q), however CT-C1+C2+C3+04. Potential difference ■ between floating gate Train. In order to enlarge 8 and to make higher the electric field within tunnel oxidization 119, potential V "Potential of a floating gate may be raised at the time of elimination, and potential of potential Vr of a floating gate may be made low at the time of writing. In order to realize this, it is a ratio of complete IC0T and Capacity ff1c1 between control gate floating gates from upper type (1) (4) ~, Enlarging C1/CT and making small the ratio of the amount CT of whole picture and the capacity between floating gate Dorain and C3/CT is understood. generally, greatly (small Sari), in order to enlarge capacity (small), if there is not Si thinly (thick Ri), it will not become in Si and its film thickness about the area and the dielectric constant of a field of the dielectricity and a body membrane. However, as for the area of a tunnel oxide film, since the result which enlarges capacity between 70-Tyng gate Dorain is brought about, it is desirable [ making the film thickness thin, in order to impress a high electric field to a tunnel oxide film ] to make it as small as possible. Usually, F E T In IVI OS, If this film thickness is made thin since equal film thickness is used, capacity C2 between floating gate boards will become large, therefore the amount CT of whole picture increases, and gate oxide 8 and tunnel oxidization 119 are potential difference ■ between floating gate Dorain. 8 becomes small. When film thickness of gate oxide is made thin, it becomes easy to produce degradation of transistor characteristics -- a trap unit is formed the incorrect writing by hot carrier pouring, and into an oxide film at the time of normal operation. So, in the present condition, film thickness of gate oxidization 118 and tunnel oxidization l19 is made into about 200A. It is potential difference V between floating gate Dorain from upper type (1) (4) ~. Since it is X at the writing and elimination time and it differs, the shift amounts of the threshold of a memory transistor also differ, it is at the memory time of information *0 degree * and 1'', and a difference arises in the maintenance characteristic. In order to prevent this, it is at the writing and elimination time, and must set up the value of impression high voltage VFF separately.

FET of the [Problem(s) to be Solved by the Invention] former The nonvolatile semiconductor memory using MOS is constituted as mentioned above, In order to obtain the threshold shift amount of a memory transistor enough at the time of writing and elimination, it is necessary to make the value of impression high voltage VPF high enough, and the problem that the oxide film between floating gate control gates is spoiled by this arises. In order to be at the writing and elimination time and to obtain a comparable threshold shift amount, set up the value of impression high voltage VPP separately (there was a problem that there was no Pretty much.). So, the object of this invention removes the above problems and it takes the high enough high electric field inside power I Carried out among floating gate Dorain, While this improves the certainty of writing and the elimination characteristic, it is providing a nonvolatile semiconductor memory suitable for memory maintenance and good high integration of write-in endurance.

[Means for Solving the Problem] In a memory transistor in this invention, N+ territory field formation is carried out directly under the floating gate by transverse direction diffusion from Dorain, It is between floating gate sauce between a floating gate and this field (transverse direction diffusion region), And an insulation m (dielectric film) field made it is thinner than gate insulation III (dielectric film) between floating gate semiconductor substrates, and narrower than 70-Tyng gate width is provided, and a tunnel field of minute area is formed.

[Function] Since thin tunnel am of film thickness was formed in minute area, while decreasing the capacity of the field, it becomes possible to impress a high electric field to a tunnel field.

[Example] Hereinafter, one example of this invention is described about a figure. the -- the [A / 1 / figure and ] --B [ 1 ] figure is a figure showing the composition of the nonvolatile semiconductor memory which is one example of this invention -- the --A [ 1 ] figure -- that plane arrangement -- the --B [ 1 ] figure -- the -- it is a figure showing roughly the section structure which met the A-A line ofA [ 1 ] figure. the -- the [A / 1 / figure and ] -- asB [ 1 ] figure is shown, that film thickness is made thinner than gate oxide 8 as a feature of this invention, and tunnel oxidization lll9 which that width is narrower than the width of 70-Tyng gate 4, and was carried out is formed. Formation of tunnel oxidization [19 of film thickness with this thin minute area is performed by only this field's performing etching processing and making it into predetermined film thickness and shape, after forming in the same film thickness as gate oxidization 118, for example. N+ territory field in which this tunnel field was formed by transverse direction diffusion from Dorain 7 -- a pile -- it is made like. in order to bring about high integration -- floating gate 4 and control gate 5 -- the -- it is formed so that it may conclude superficially that it is seen fromA [ 1 ] figure and the pattern may suit in A. Next, operation is explained. As shown in a formula (1> 4 which is not and to spread), the electric charge mouth which impresses a high electric field to tunnel oxidization l119, and is poured into 70-Tyng gate 4 is increased, In order to fully shift the threshold of memory transistor 1, it is required to make thin film thickness of to extend the potential difference between floating gate Dorain and tunnel oxide film 9. In this invention, it is conventional FET. Since the film thickness of MOS Different and gate oxidization MI8 and the film thickness of tunnel oxidization WA9 are set up separately, the electric field impressed to a tunnel field can be optimized easily. First, in order to enlarge potential difference between drain floating gates at the time of elimination, he is floating Gout 1 from a formula (2). --- Capacity C1 between Cong 1-roll gates may be enlarged. Although a control gate and floating Gaea 1- see superficially and the patterns overlap in the present invention, film thickness of an oxide film in the meantime is formed as usual. Therefore, the Capacity IC1 does not become small from a conventional example. Since Capacity 11G2.[ besides - ] C3 *C4 can be individually set as the optimal value, respectively, C1/'CT can be optimized. In order to enlarge potential difference between floating gate Dorain at the time of writing, he is Hiroshi in the meantime from a formula (4)! Each capacity may be optimized while making IC3 small. In the example of this invention, the y!i thickness of this tunnel oxide film 9 is a cattail (since it is carried out, capacity becomes large, but since that area is sharply made smaller than a conventional example, that capacity can be made small.). Because, it is although the area of the tunnel field is given in the conventional example by the product of the transverse direction diffusion length of N+ diffusion zone and the gate width of a floating gate which Dorain 7 forms, In this invention, that area is because the long Rough <minimum of transverse direction diffusion length and Pf mind is given by a product with the minimum processing size of a process. Since the film thickness of gate oxide 8 and the film thickness of tunnel oxide film 9 can be set up individually, respectively, each capacity can be optimized easily. The impression electric field of a tunnel field can make film thickness of this tunnel oxide film 9 higher than a conventional example by thin Cush Was it. It is because the electric field given to this tunnel field is what divided the potential difference between floating gate Dorain by 114 of the tunnel oxide film and is given. A high electric field can be impressed to a tunnel field by the above composition at the time of writing and elimination, and a nothing Burning value shift amount can be obtained enough. In Hey and the above-mentioned example, although the case where an oxide film is used for the insulating film between a floating gate and a semiconductor substrate is explained, when constituted from 2M or multilayer structure of a nitriding film, a nitriding film, and an oxide film instead of this oxide film, the same effect can be acquired.

[Effect of the Invention] as mentioned above -- making a tunnel field into minute area in the present invention, while making thin m thickness of an insulating film of a tunnel field of a memory transistor -- further -- a ratio of each capacity -- easy -- optimization -- last -- it constituted like. Therefore, capacity between floating gate boards is made small as usual, And it becomes possible by [ with possible also making capacity of a tunnel insulation film small, or an equal value of an impression high voltage at the time of writing and elimination ] optimizing a ratio of each capacity to move aside to obtain an almost equal threshold shift amount. The electric field in the tunnel insulation film at the time of writing and elimination (dielectric film), Since film thickness of [and Nellnell insulation upbringing is made thin, it becomes high, and the value of the impression high voltage can be pressed down lower than before, While being able to shorten time until it reaches the peak value and being able to shorten the time which writing and elimination take, degradation of the oxide film between the floating gate control gates by high-voltage impression can also be prevented. Since the value of the impression high voltage can be made small, it is suitable also for high integration. As mentioned above, by this invention, positive writing and elimination can be performed using the comparatively low high voltage, and nonvolatile semiconductor memory @ Place suitable for high integration with higher reliability, such as write-in endurance and the memory maintenance characteristic, can be realized.

[Brief Description of the Drawings]

the -- the [A / 1 / figure and ] --B [ 1 ] figure is a figure showing the composition of the nonvolatile semiconductor memory which is one example of this invention -- the --A [ 1 ] figure shows that plane arrangement -- the --B [ 1 ] figure is a figure showing that section structure. the -- the [ 2 8 figure thru/or ] --C [ 2 ] figure is Cause which shows the conventional nonvolatile semiconductor memory -- the --A [ 2 ] figure shows the plane arrangement -- the --B [ 2 ] figure shows the section structure -- the --C [ 2 ] figure is a figure showing an equivalent circuit. Drawing 3 is a figure showing the circuit which the capacity in the memory transistor of a nonvolatile semiconductor memory constitutes. In a figure, 1 is a memory transistor and 2 is a selection transistor, 3 -- as for an un-l@ thing diffusion zone (Dorain of a memory transistor), and 8, a flow Ding gate and 5 are [ a tunnel insulation film and 10 ] poly -Poly saponification films gate dielectric film and 9 a control gate and 7 a semiconductor substrate and 4. A same sign shows a same or considerable portion among a figure. ofCn9 - (N ? ■ 5VSSvD (The title of -/-7 A (11Ohf) (Dorain) written amendment (spontaneity) 21 invention) Nonvolatile semiconductor memory 3, those that do amendment 5, the object of amendment Eyebrows 6 of the detailed description of the invention of Ming ms, the contents of amendment (1) The 18th line with a specification of page [ 5th ] "correct number ->-MVJ in number MVJ gate Refutation-ized r!A8 at "gate oxide 8 and 9. (2) Correct 6th page of Ming IIIIB "control gate 5" of the 12th line to "70-Tin Kuge- 1-4." (3) Correct 8th page of specification "the insulating film" of the 16th line on a "dielectric film." (4) Correct 10th page of specification rVCJ of the 2nd line to rVccJ. Above