Telephone billing apparatus for a subscription television system

[Detailed Description of the Invention]

The present invention relates to the pay television system by a contract with a receiving person, especially the pay television system decided by the program which a member's fee receives. In the known fee calculation (billing) system, the fee calculation card punched when a member receives a program is used. These charge systems have made the member a great trouble -- this must be mailed to the time and effort which is when a member inserts a fee calculation card, and the back. The record space of a card has restriction. A mistake may arise by breakage of a card, a postal delay, etc. the coding fee calculation system which the object of the present invention has high reliability, and it is only requiring a comparatively small storage capacity, and operates by a member's easy operation, and has a comparatively high degree of secrecy -- it is going to provide -- it is. The present invention is a subscription television system which provides with a television program the member (ing which has a standard television receiving set each one) who accessed the communications network, This system is provided with the coding-sending set which transmits to a member the coding television signal which coded the television signal which constitutes a predetermined program and inserted the program identification number showing the above-mentioned program in a schedule instant into the above-mentioned television signal, and in which the program identification number was inserted in this way. In this system, it has a receiving set which receives the television signal transmitted as mentioned above to each member. The detecting device which detects the above-mentioned program identification number and generates the detected corresponding program discernment signal is formed. The receipt signal generation device which generates the receipt signal showing the receipt of the above-mentioned program by the above-mentioned member is formed. A receipt signal generation device generates a receipt signal only at the time of a member's operation. The main memory unit which has the 1st memory site group which memorizes the above-mentioned program identification number, and the 2nd memory site group which memorizes a member identification number is provided. The recorder connected to the above-mentioned detecting device and the above-mentioned receipt signal generation device is formed, the above-mentioned detection program discernment signal is recorded on the above-mentioned 1st memory site group by this only at the time of reception of the above-mentioned receipt signal, and only the program identification number to which a member expresses a receipt Ivy program is memorized to the 1st above-mentioned memory site. the reading device which reads a member identification number and the above-mentioned program identification number is inserted between the above-mentioned main memory unit and the above-mentioned communication circuit network, and it corresponds to it -- each -- another member and a program discernment signal are supplied to the above-mentioned communication circuit network. And the central computing device linked to the above-mentioned communication circuit network is formed, this receives a member discernment signal and a program discernment signal, and it calculates the fee to each member's receptacle I got it. program according to this. In the present invention, an address is carried out by the above-mentioned program identification number into the above-mentioned main memory unit, and it also has a memory site group of the third set which memorizes two or more program specification numbers to which each corresponds to each in two or more coding modes. of course, the one mode which chose the coding sending set described previously from two or more above-mentioned coding modes -- therefore, intermediary To have [ as ] which can code a television signal. Since the program specification number which carries out the address of the memory site expressed by the above-mentioned program identification number, and corresponds is read among the memory site group concerned of the third set according to this and the reading Ivy program specification number is outputted, The reading device connected to the above-mentioned program identification number detecting device and the above-mentioned main memory unit is also formed, the program specification number further outputted by this program specification number reading device is received in a control input terminal, and the decoding device which decodes a receiving television signal correctly is also formed under that control. Therefore, only when a central computing device receives the above-mentioned program identification number in the present invention by using such a component, Until it can supply the program specification number updated corresponding to the mode change in two or more above-mentioned coding modes, it can allow the system to the above-mentioned memory site of the third set and fee calculated data is received by the central computing device, Proper decoding of the coded television signal can be prevented. One suitable example of the present invention is described per drawing below for the composition of a present invention system, operation, and a better understanding of various advantages. First, the general matter of a present invention system is explained. In the transmitting side, the code number which occurs at random is supplied to the coding logic circuit which operates in the 1 mode in which it was chosen of two or more coding modes. a television signal -- the coding mode at that time -- therefore, it codes by answering the selected code number and reversing the polarity of a video signal. Before a code number also transmits to the decoder of a receiver, it inserts into a television signal. Before the program identification number showing the fee of the program also transmitting, it inserts in synchronization into a television signal. In a receiving side, a code number is detected and the decryption logic circuit Set(ed) by the decryption mode corresponding to the coding mode chosen [ above-mentioned ] by the program specification signal is supplied. A program specification signal is read from the memory site in the random access memory in which the address was carried out by the program identification number. A program identification number is also memorized for subsequent fee calculation in random access memory. However, the decoder does not operate until a member pushes the button in which the receipt of a program is shown. Fee calculation is made by transmitting a program identification number to a central computer with a telephone wire. A computer generates the new specification number memorized in the above-mentioned random access memory after reception of a program identification number. Unless these numbers exist, a decoder cannot be Set(ed) in the right mode. This fee calculation is performed periodically and it is necessary to enable it to start by a member. The circuit inserted into a television signal before transmitting a code number and an identification number is shown in Drawing 1. Let the code number be 2 evolution decimal number. It is necessary to insert each of these binary numbers into each line of six lines within a perpendicular retrace line period. As for a two evolution each decimal number, it is needless to say that 4 A bit are needed. Each level line which should insert a binary number in hard [ slight / this ] is divided into four slots, and 1 A bit is put into each slot. An intermediary random number generator is constituted also for oscillator 201 and counter 202 which have an output frequency higher than level drive frequency. That is, the binary number in counter 202 is transmitted to register 203, when a level drive pulse is received by the load input terminal of parallel 1 in-series output register 203. The code number inputted in this way is read in series under control of 4H oscillator 204. Oscillator 204 generates the pulse which has a trailing edge which has frequency a little higher than 4 times of level line frequency, and falls at the center of a slot mentioned above. 4H oscillator 204 is driven with the output of six line counters 206. Six line counters 206 generate a signal only the inside of the first six lines of a perpendicular retrace line period. In hard [ slight / this ], the in-series output from register 203 serves as the random number of 1~8 in each line of six lines of the beginning of a perpendicular line period. The signal of the output terminal of gate 205 is in agreement with the output of register 203, if a prohibition pulse does not exist. A prohibition pulse is supplied when it is necessary to send a validation code (effective authentication code). Although validation codes are a series of code numbers designed to examine whether a decoder is in proper mode, they are not explained any more here. The 2nd prohibition pulse, i.e., the signal from the output terminal of gate 212, occurs, when it is necessary to insert a program identification number into a television signal. If gate 212 drives, the contents in register 213 will be read in series, and will be supplied to the 3rd input terminal of OR gate 214. Other input terminals of this OR gate receive a code number and a validation code. Gate 212 in the 1st line of a perpendicular retrace line period drives, and several 9 is inserted into a television signal. The number of 6 Advance of two pieces which constitutes a program identification number after that continues. A category selection number is put into the maximum empress in the 4th line. The decoder circuit which detects a code number is shown in Drawing 2. The coding television signal which contains a code number in six lines of the beginning during the perpendicular retrace line is received by terminal 300. This signal is supplied to level detector 301. This level detector shall detect "1" and "0" signals certainly regardless of a big change of comprehensive signal amplitude. The output of this detector 301 serves as a train of impulses of "1" and "0" signals. This pulse signal sequence is supplied to the input terminal of Naoichi parallel shift register 302. However, the input terminal of this shift register 302 is supplied. However, this shift register 302 receives a pulse, only when it drives with the output of oscillator 303. It drives by 1in six lines H drive signal of the beginning in each perpendicular retrace line period, and oscillator 303 is equivalent to oscillator 204 of the transmitting side. Thus, the clock of the 4 A bit which constitute 2 evolution decimal number in each line is carried out to shift register 302. 4 A bit of a specific line are transmitted in shift register 302, and the contents of this shift register are transmitted to 4 Bitrutti 307 at the time of Finished, at i.e., the time of the trailing edge of 1H drive pulse. The code transmission pulse made to transmit to 4 Bitrutti from a shift register is taken out from 1H drive signal in the differentiation circuit containing capacitor 308, resistance 309, and diode 310. 4 Bitrutti 307 are connected to decoder 311. Decoder 311 changes 2 evolution decimal code of the input terminal into a decimal number, namely, energizes one of output lead 0~8 according to the two evolution each decimal code of an input. The signal on lead 0~8 is supplied to the input terminal of program specification logic circuit 312. The output of this circuit constitutes the signal "A" and "B" which determine the mode of the polar flip flop of a decoder, "C", and "D." The state of this flip flop determines whether whether a video signal's being reversed and a video signal are beforehand reversed by the encoder. "A", "B", and the "D" signal Set, reset and Toggle this flip flop, respectively. The "C" signal does not control the state of a flip flop at all. Drawing 3 shows program specification logic circuit 312 of 2 figure in detail. #1~#8 shown in Drawing 3 is an output lead of decoder 311 of Drawing 3. Lead PA₁,PA₂......PA₁₅,PA₁₆It is the input taken out from the program identification number so that it might explain in full detail after Is. In particular, it is program specification number PA of each set.₁,PA₂,PA₃,PA₄; etc. -- pass each appointed circuit 401~408 in one of program number 1~8 which occurred in decoder 311 -- control transmitting to one piece A, B, or D of an output terminal. Each appointed circuit 401 is shown in Drawing 4 in detail. Other appointed circuits are the same as circuit 401 except an input. In Drawing 4, it is lead PA.₁A signal turns up and it is lead PA.₂When a signal is upwards, AND gate 414 flows and AND gates 412 and 413 are prevented. If code number 1 is received in hard [ slight / this ], AND gate 417 will generate the output which energizes the "A" output terminal. Similarly, it is lead PA.₁A signal exists upwards and it is lead PA.₂When a signal does not exist upwards, an output occurs in the "B" output terminal at the time of reception of code number 1, and it is lead PA.₁And PA₂When a signal does not exist in Whichever, either, an output occurs in the "D" output terminal. Thus, specification of A from BCD-10 Advanced converter 311, B, or D output is performed under control of a program specification signal, and a program specification signal is read when an address is carried out by the program identification number from the random access memory in a decoder. As shown in Drawing 3, each program specification number is 16 bit words, and these A bit are eight pairs (PA).₁,PA₂......;PA₁₅,PA₁₆Intermediary To have. It acts as a byte of the 16 bit words, and they are taken out from the sequence of 48 A bit memorized in the random access memory in a decoder. (Memory site 0~48 of RAM shown in Drawing 5). the 1st byte -- the -- the 1~16th A bit is included. the 2nd byte -- 1 Get it bit shifted -- things are made (the 2~17th A bit). This byte of 32 is possible from 48 A bit sequences. The number to which every A bit in each program specification number is [ each other ] adjacent for 1 To shift bits reason is completely different from Mutually, although 1 A bit only becomes new in each. Of course, it is in the function of a program identification number, i.e., the number of 6 Advance of double figures, choosing the program specification number (byte) of these 32. Since 256 kinds of program identification numbers can be formed from combination OO~FF of the number of 6 Advance of double figures, eight program identification numbers are assigned to each program specification number (32x8=256). Reception of the program identification number of 00~07 will choose program specification number 1. The number of 08~15 (decimal number) chooses program specification number 2. A least significant digit expresses the number of 1 with a 6 Advance-10 Advance system, and the following beam expresses the number of 16 with it. Each beam is denoted by 4 A bit. Three low rank A bit of a this least significant digit can be disregarded when reading a program specification number from random access memory. The 6 Advance-decimal number of O~F used for category selection of six lines the 4th line that conveys the code number selected at random is included. Intermediary To have [ as ] suitable for it being convenient if it is, and the coding form of the present invention making this category selection, although category selections are not the requirements for the present invention. A bit of the 4th line is processed independently. There is a program of three types and suppose that there are three categories in two types of them. Type (a) home General Guidance for parents Limitation (parent guidance) (b) Special Doctor Lawyer Education (c) Bar The selection of the program in a decoder is as follows. The selection switch is formed on the front panel of a decoder. If this switch is generally Set(ed), only the program for viewing public can be Reproduction(ed). If it Set in a "parent guidance" position, "parent guidance" and both "usual" programs will be decoded. If it Set to "limitation", all the programs of three types are receivable. It is determined which type of program can be regarded as receiving a "special" program for a switch with the hard connection jumper in a decoder at the time of Set. For example, when the decoder is connected to the "doctor" program and the "educational" program is transmitted, in Then, a switch does not decode decoding in a special position. The decoder of a bar forbids decoding and other televiewers can make it possible to watch a program on the other hand. Random access memory is shown in Drawing 5. As mentioned above, memory site 0~48 contains a program specification number. A member identification number is memorized in memory site 64~88, and a program identification number is memorized in position 88~255. Each memory site memorizes 1 A bit. A program identification number is the number of double figures, and since each beam is denoted by 4 A bit, it can memorize the program identification number of 21 to an effective fee calculation (billing) space. The arbitrary starting points shown in Drawing 5 are the starting points by which hard connection is made at the address counter to a memory. This point is explained in full detail behind. A security number is 2 evolution decimal number of 4 figures, and each beam comprises 4 A bit. A member identification number is the number of 24 A bit. It is necessary to carry out renewal of the program specification number of periodic by a computer, and to coincide it with coding of the transmitting side. Updating by this computer does not take place until it finishes transmitting a program identification number required for fee calculation to a computer. In Drawing 6, random access memory 600 is a 256 A bit memory mentioned above. There is one copy of the function of the circuit of Drawing 6 in transmitting 16 A bit program specification number with the selected program identification number on an input television signal to 16 bit-shift register 601. The parallel output terminal of 16 bit-shift register 601 is lead PA of Drawing 3.₁......PA₁₆It constitutes. The address of the random access memory 600 is carried out with eight address leads which constitute the output terminal of Up / down counter 602. calculation of counter 602 -- an input terminal is connected to the output terminal of 6 phase clock 603. 4 bit-shift register 604 is also shown in Drawing 6. This 4 bit-shift register 604 is connected to the output terminal of detector 301 of Drawing 2. The clock input to shift registers 604 and 605 is an output of 12-pulse counter 606. calculation of counter 606 -- an input terminal is connected to the output terminal of 4H oscillator 303 of Drawing 2. This counter operates, after driving by "9" signals from decoder 311. In order to transmit a program identification number by the 2nd of a perpendicular retrace line period, and the 3rd line and to correspond to 8 pulses of the beginning from oscillator 303 after detection of "9" signals, a program identification number is shifted into shift register 605, when receiving the 12th pulse from counter 606, and it is Is finished. From this time, a category selection number is memorized in register 604. Operation of counter 606 will stop, if it finishes calculating 12 pulses. The signal which Set flip flop 607 using the overflow pulse from counter 606, and drives 6 phase clock 603 is generated. The pulse from 6 phase clock 603 is supplied to Up / down counter 602, and calculates this in Up mode. The address to memory 600 occurs in the output terminal of counter 602 thus. In comparison machine 608, 5 A bit of the higher rank memorized in shift register 605 are compared with 5 A bit of the low rank of the address which occurred at counter 602 (top 5 A bit of a program identification number determine the address to address memory 600). If the address of the memory 600 is carried out, the program specification number memorized in the memory site of the memory will be shifted to shift register 601 in series. When comparison machine 608 generates the output signal showing coincidence with top 5 A bit in shift register 605, and low rank 5 A bit of the address which occurs at the count of counter 602, clock drive flip flop 607 switches to the state of Abatement(ing) clock 603. At this time, the count of counter 603 is in agreement with the address in memory 600 which has memorized the program specification number specified by the program identification number. Next, it puts in in shift register 601 and a program specification number is lead PA of Drawing 3rd [ the ] and 4.₁~PA₁₆the same code used with the transmitter -- therefore, energize and pass the air during the next perpendicular retrace line -- the code number received is properly sent to A, B, and D output terminal. Validation, i.e., the signal showing the right reception of the right setup of a decoder and a code, is supplied to terminal 608'. Although it is preferred for these signals to make it generate for 1 second, when a program identification number is sent in 1 second, validation is performed in 1 / 2 seconds. A validation signal makes counter 606 non-operative by data lockout 609. namely, calculation of this counter -- operation is prevented. In the suitable example of the present invention, data lockout 609 is made into a single stable multi-by plater, and short worth Set the damping time constant from 1 / 6 seconds at time when a validation signal is sufficient to disappear from terminal 608'. The signal of terminal 608 supplies further the reception thru/or the receipt signal which occurred by press of reception thru/or a receipt push button to clock drive flip flop 611 through AND gate 610. Thereby, this flip flop 611 is changed into the state of putting 6 phase clock 603 into operation again, and supplying a pulse to Up / down counter 602. Since the member is pressing the receiving push button, it is necessary to input a program identification number in memory 600 for next fee calculation. It is necessary to write the identification number A bit in the empty position of the beginning of 168 positions in memory 60 allocated to fee calculation. 6 phase clock 603 supplies a pulse to Up / down counter 602 which continues calculation in Up mode following the drive by clock drive flip flop 611. The number memorized in the position by which the address was carried out with the output lead of this counter is shifted to 8 bit-shift register 612 in series. The shift to shift register 612 is a clock pulse from clock 603, when the drive signal from clock drive flip flop 611 exists, namely, it is controlled by the output of AND gate 611a. The parallel output of shift register 612 is supplied to the input of zero detector 613. In the suitable example of the present invention, only when all inputs are zero signal, let this detector be a NAND gate which generates an output signal. Zero detector 613 supplies an empty position signal to flip flop 614 at the time of reception of eight zero. Flip flop 614 is Set(ed) and makes Up / down counter 602 calculate in down mode. If flip flop 614 is Set(ed), further, it will drive 8 A bit counter 615 and will calculate eight output pulses next to clock 603. If eight pulses are calculated, counter 615 will generate the signal which resets flip flop 614, will remove the countdown control signal of counter 602, and will make counter 602 count-up mode again. Flip flop 616 is Set(ed), this energizes write-in drive circuit 617, and it permits record in memory 600. Counter 618 which is the thereby still more nearly same 8 A bit counter as counter 615 is also energized. Counter 618 starts calculation of the following eight clock pulses from clock 603. AND gate 619 is changed into a derivation state using the signal from flip flop 616, and it enables it to supply the clock pulse from clock 603 to the clock input terminal of 8 bit-shift register 605. The information in this 8 bit-shift register 605 is transmitted in series into memory 600. Further, the output pulse of flip flop 616 drives re-circulation circuit 620, and, thereby, re-supplies each A bit from shift register 605 to the input terminal. 8 A bit which constitute a program identification number in hard [ slight / this ] are re-memorized in shift register 605 at the same time they are memorized in memory 600. Subsequently, flip flop 616 is reset by calculation 8 from counter 618, connection between shift register 605 and memory 600 is severed, and the operation of write-in drive circuit 617 stops. Since flip flop 611 is in a Set state during above-mentioned operation and memory 600 is a memory of the model with which reading is performed simultaneously with write-in operation, a program identification number is memorized also in shift register 612. Comparison machine 621 compares the number in shift register 612, and the number in register 605. 8 bit-comparison machine 621 generates a coincidence signal, resets flip flop 611, and suspends clock 603 at the same time a program identification number finishes memorizing in memory 600. The coincidence signal from 8 bit-comparison machine 621 switches program drive flip flop 622 to a Set state. If flip flop 622 will be in a Set state, a control signal will be supplied to a decoder and will come to allow viewing and listening of the decoded image. Thus, before the program identification number can view and listen to a program, it is memorized in a memory. Each program identification number is only memorized once. The reason is for comparison machine 621 to reset flip flop 611, when the number is read in memory 600, when the number is memorized beforehand. If validation, i.e., an effective acknowledge signal, does not exist (i.e., if the program identification number is not properly Set(ed) so that the right program identification number may be transmitted and received in the air and the decoder of a receiver may answer this number), it is not memorizable in a memory. The number by which other features shown in Drawing 6 were Set(ed) by comparison machine 623 in shift register 604, That is, it is in comparing the category selection number transmitted in the 4th line of a perpendicular retrace line period with the number Set(ed) by operation of the hard wire jumper which was category-selection-switched, namely, the televiewer described above in the comparison machine. The signal from this comparison machine is needed also for driving write-in drive flip flop 617. When this signal does not exist, the number in shift register 605 is never inputted in memory 600, but the output signal from comparison machine 621 is also never outputted. Program drive flip flop 622 is not Set(ed) by this, but, as for a program, it is needless to say that it is not viewed and listened by the member. Since a program identification number is not inputted in memory 600, fee calculation does not take place, either. As shown in Drawing 6, a selection switch has selector arm 649 which chooses terminal G, PG, and R. G terminal constitutes one input terminal of OR gate 650, and it draws the input of the another side from R terminal. R terminal is connected to one input terminal of OR gate 651, and the input of the another side is drawn from PG terminal. The output of OR gate 650 is supplied to the lowest A bit input terminal by the side of A of comparison machine 623, and the output of OR gate 651 is supplied to A bit like that of the next by the side of A of this comparison machine. The B side of this comparison machine receives the two lowest A bit from register 604, i.e., 2 A bit from a category selection number (it is coded by 01, 10, and 11 to G, RG, and R, respectively, and the lowest A bit is right-hand side A bit). The output of comparison machine 623 is equal to B, or A takes it out from the terminal which generates "1" output, when large. When a member sets a selection machine as G terminal in hard [ slight / this ], only G program makes "1" output generate from comparison machine 623, and if it sets to R terminal, "1" output will occur from comparison machine 623 regardless of the numerical value supplied to B terminal. R terminal is chosen by the member, and a this"1" output occurs from comparison machine 623, when G, RG, or R program is broadcast. DR, LWY, and ED terminal are internal terminals by which hard wire connection is made according to which category the member chose. DR terminal constitutes one input terminal of OR gate 652, and it draws the input of the another side from a LWY terminal. A LWY terminal is connected also to the input terminal of OR gate 653, and the input of the another side is drawn from ED terminal. The output of OR gates 652 and 653 is supplied to the A side input terminal of comparison machine 624. The other, i.e., B, sides of comparison machine 624 receive the top A bit from register 604. The output of comparison machine 624 is taken out from an A=B terminal. This comparison machine 624 generates "1" output, only when the program specified by hard wire connection is transmitted. The output of comparison machine 623 and the output of comparison machine 624 are supplied to OR gate 625, and the output is made to act as one drive input of write-in drive circuit 617. Thus, when the category which the member chose, and the category of the received program are not in agreement, no signal occurs in the output terminal of selection comparison machine 624. The sequence operation of this system performed at the time of a member's reception start is as follows. (a) Decoder computer (a decoder reads data in a memory (0~255)) (1) Start signal (long tone) sending out (2) Sequence (line test) sending out of 0 and 1 of 64 A bit (3) Member identification number sending out of 24 A bit (4) Fee calculated data (program identification number) sending out of 168 A bit (b) Computer-decoder (reverse order) (1) Start signal (long tone) sending out (a decoder carries out the address of switch L and the memory to the starting points arbitrary at the time of the end of a long tone at an opposite direction.) (2) Send out the fee calculated data + member identification number of X A bit in a reverse order (a decoder compares this with memory data). (3) Send out security A bit of 16 A bit in a reverse order (the decoder is still carrying out reading and comparison.). The memory after the end of a data check is switched to write-in mode. (4) The new program code of 48 A bit (a decoder writes this in) (5) The confusion (Disturbance) signal of Y A bit (although a decoder is in write-in mode) A confusion signal is disregarded and "0" is written in a fee calculation area (X+Y=192 and a decoder (from arbitrary points to the start in a memory by which hard wire connection was made) scan a memory once to an opposite direction, and finish with arbitrary points again.). All the fee data to the starting point is eliminated from 255 positions to an opposite direction, and it leaves the data from arbitrary points to A bit 88 as it is. Although a decoder is still write-in mode, a memory counter stops calculation. (c) Decoder computer (reverse order.) This cycle happens automatically after the end of transmission of a computer. (1) Start signal (long tone) sending out (2) Confusion signal sending out of V A bit (a decoder is in memory write-in mode, and writes in "0" from the arbitrary starting points in a memory during transmission of a confusion signal at an opposite direction.) "0" is thus written in all the fee calculation areas from the arbitrary starting points to 88 bit positions. A decoder passes through a security number and a member identification number field, without performing anything in a memory. (3) The program code supplement of 48 A bit (a code of these is read from a memory and compared with the data previously transmitted by the computer.) (4) The confusion signal of W A bit (V+W=208) In Drawing 7th [ the ] and 8, a member pushes the button or switch written to be "a start", and Set a system sequence to an operating state. If a "start" button is pushed, a transmitting circuit (Drawing 9) will drive, and flip flop 40 is Set(ed) and the Q output is supplied to one input terminal of AND gate 41. The terminal of another side of AND gate 41 is connected to the output terminal of long tone oscillator 42. While flip flop 40 is Set(ed), a signal appears in the output terminal of AND gate 41. This signal is directly supplied to the input terminal of frequency shift keying (FSK) abnormal-conditions machine 42, and is transmitted to a computer through a telephone wire. The output of AND gate 41 is supplied to the Set input terminal of flip flop 44a through integration circuit 43 and threshold circuit 44. It is preferred for threshold circuit 44 to consider it as a schmitt trigger circuit. The output of threshold circuit 44 is supplied also to the reset input terminal of flip flop 40. Transmission to the computer of a long tone is thus completed in the after-start schedule time, and AND gate 45 drives. While connecting the input terminal of another side of AND gate 45 to the output terminal of clock generator 15, calculation of an address counter [ as opposed to Up / down counter 11, i.e., random access memory 10, in the output terminal ] -- calculation of an input terminal and counter 47 (the 1st circulation counter is called) -- it connects with an input terminal. Flip flop 48 is Set(ed) by the 1st count of counter 47, and the Q output terminal is connected to "0" and the drive input terminal of "1" oscillator 49. The 0-1 row for a line test which needs to supply the output of oscillator 49 to the input terminal of FSK abnormal-conditions machine 42', and needs to be supplied to a computer through a telephone wire is made to generate. Address counter 11 counts up a clock pulse and carries out the address of the memory site 0~64 of random access memory in the meantime. However, since both AND gates 50 and 51 by which the 1st input terminal was connected to the data output terminal of random access memory 10 are non-electrical connections, no data is sent out. When counter 47 becomes count 64, flip flop 52 is Set(ed). It is connected to the 2nd input terminal of AND gate 50, and Q output terminal of flip flop 52 flows through this AND gate. The data of the memory site by which the address was carried out by address counter 11 in hard [ slight / this ] is supplied to the input terminal of FSK abnormal-conditions machine 42' through AND gate 50, and is transmitted to a computer through a telephone wire. In order to flow through flip flop 52 until the count of counter 47 is set to 255, a member identification number and the fee calculated data of 168 A bit are transmitted. If counter 47 becomes count 255, flip flop 52 will be reset, and AND gate 50 will be prevented, and also flip flop 44a will be reset, and supply of the clock pulse from oscillator 46 to counters 47 and 11 will be stopped. Count 255 of counter 47 also resets self to zero. The 1st cycle of a system is completed thus. All the signals (a data signal and a synchronized signal are included) sent from the computer appear in the output terminal of frequency shift keying wave detector 52a connected to the input terminal of long tone detector 53. The output of long tone detector 53 is supplied to the Theft input terminal of flip flop 54 and flip flop 55. It connects with one ON terminal of AND gate 56, and Q output terminal of flip flop 54 connects the input terminal of the another side to clock generator 15. The output terminal of AND gate 56 is connected to the count input terminal of address counter 11 and counter 57 (the 2nd circulation counter is called). The output terminal of long tone detector 53 is connected also to the input terminal which makes the pulse which is made to Set the number of preset of counter 11, and is supplied to a count input terminal count down. since AND gate 56 is an electrical connection -- the pulse from oscillator 15 -- calculation of counters 11 and 57 -- an input terminal is supplied. Although counter 57 starts a count to an increase direction in hard [ slight / this ], counter 11 starts a count in the reduction direction from the number of preset. An address is carried out to a reverse order from the starting points with an arbitrary memory site of this random access memory 10. The data read from random access memory 10 is supplied to one input terminal of comparison machine 58, and the input terminal of the another side is connected to the output terminal of the FSK wave detector 52a. Comparison machine 58 compares the fee calculated data sent in an order reverse from a computer in hard [ slight / this ] with the data memorized by random access memory, i.e., the data which Set(ed) to the computer in the 1st cycle of a system. Comparison machine 58 sends from a computer the member identification number further memorized by random access memory, and compares it with a It has been returned member identification number. It compares with the security number to which the security number was read by the decoder and this has been sent in a reverse order by the computer. As long as comparison machine 58 generates the "yes" output showing the signal of both comparison input terminals being the same, reading and comparison are continued until "48" detection signals occur in the output terminal of "48" detector 59. Q output of flip flop 55 and the output of "48" detector circuit 59 are supplied to the input terminal of AND gate 60. AND gate 60 generates an output at the time of detection of the number of the inside of the 2nd cycle "48" expressed when a signal exists in Q output terminal of flip flop 55 in hard [ slight / this ]. The output terminal of AND gate 60 is connected to the Set input terminal of flip flop 61, and the write-in drive signal over random access memory 10 is generated from the Q output terminal. Random access memory 10 starts thus record of the data supplied to the input terminal. Input data is supplied to random access memory 10 from the output terminal of AND gate 62. AND gate 62 has the 1st input terminal connected to the output terminal of the FSK wave detector 52, and the 2nd input terminal connected to Q output terminal of flip flop 63. The Set input terminal of flip flop 63 is connected to the output terminal of AND gate 60. This data is to the input terminal of random access memory 10, Only when all the data from the arbitrary starting points to which comparison machine 58 was read from random access memory 10 to memory site 48 indicates that it is in agreement with the data which sends and carries out It has been returned correspondence from a computer, it is supplied after passage of address 48. When both inputs before this position are not in agreement, comparison machine 58 has generated the "no-" signal. This signal is supplied to the reset input terminal of flip flops 54 and 63, and the "zero Set" input terminal of counters 11 and 57. The lamp in a decoder is turned on using this signal, and a member is made to re-start all the sequences of a system. A member carries out a re-start to the inside of a short time by any cases. Since the proper program code of the "no-" signal from comparison machine 58 to random access memory which prevents the writing of a new program code, therefore sets up decoder logic is lost in random access memory, the reason is because a member cannot get an effective picture. As mentioned above, data (new program code) begins to be recorded from the address 48, when all the comparison to memory address 48 is compared. Comparison machine 58 stops in address 48. Comparison machine 58 was driven by the signal from Q output terminal of flip flop 64 which is an output of long tone detector 53, namely, was before Set(ed) at the time of the start of the 2nd cycle of a system sequence. The output of "48" detector circuit 59 resets flip flop 64, and, thereby, comparison machine 58 becomes non-operative. Record of the data to memory 10 is continued until a signal is generated from "0" detector circuit 65. The output of this detector is supplied to one input terminal of AND gate 66, and the input terminal of that another side is connected to Q output terminal of flip flop 55. An output signal is generated when a zero address is detected in the 2nd cycle in hard [ slight / this ] as for AND gate 66. Flip flop 63 is reset with this signal, and the output of AND gate 62 is carried out to zero output. The data received from the computer in hard [ slight / this ] is prevented from random access memory 10. It is necessary to remember that a computer sends out a confusion signal at this time. Since the output of AND gate 62 is 0, as for the data recorded on random access memory from a zero address, the data in logic "0", i.e., a memory, is eliminated. Elimination continues until counter 57 becomes 255 counts. At this time, flip flops 54 and 55 are reset with the output of counter 57. In hard [ slight / this ], a signal is not supplied to counter 11 and counter 57 from oscillator 15 after that. Random access memory 10 of flip flop 61 is still record mode in a Set state. The 2nd cycle of a system sequence is completed above. The signal showing count 255 of counter 57 is used also for the automatic start of the 3rd cycle of a system sequence. In Drawing 7, the signal showing count 255 from counter 57 is supplied to the Set input terminal of flip flop 67, and the output terminal is connected to one input terminal of AND gate 68. The input terminal of another side of AND gate 68 is connected to the output terminal of long tone oscillator 42. The output of AND gate 68 is directly supplied to the input terminal of frequency shift keying abnormal-conditions machine 42',, and it is supplied to the Set input terminal of flip flop 69 through integration / threshold circuit 70. The output of circuit 70 is supplied also to flip flop 67, and stops transmission of the long tone from a decoder to a computer. The output of circuit 70 is supplied also to the Set input terminal of flip flop 71. AND gate 72 which has the input terminal connected to Q output terminal of flip flop 69 by Set of flip flop 69 is driven. The 2nd input of AND gate 72 is an output of oscillator 15. the output terminal of AND gate 72 -- calculation of the 3rd circulation counter 73 and counter 11 -- it connects with an input terminal. In hard [ slight / this ], counter 11 starts count-up, and it carries out the address of the random access memory 10. Counter 73 also starts count-up. Since flip flop 61 (Drawing 8) is still Set, random access memory 10 has it in a write mode, and also it records zero on a fee calculation area. Set of flip flop 71 drives AND gate 74, and it connects the output terminal to the input terminal of FSK abnormal-conditions machine 42'. The 2nd input terminal of AND gate 74 is connected to the output terminal of confusion signal generator 75. In hard [ slight / this ], the signal from confusion signal generator 75 is transmitted for flip flop 71 to a computer through a telephone wire between Set states. Transmission of the signal from this confusion signal generator 75 continues until "48" detector 59 supplies a signal to one input terminal of AND gate 77. The input terminal of another side of AND gate 77 is connected to Q output terminal of flip flop 69. If the count of address counter 11 in the 3rd cycle is set to 48, AND gate 77 will generate the signal which resets flip flop 71, and will intercept the signal from confusion signal generator 75. The actual signal output of generator 75 is not important, and it can make it into a random noise signal. The reason is for neither a computer nor a decoder answering a confusion signal. As mentioned above, a confusion signal is transmitted until count 48 of an address counter is detected, but the writing of zero, i.e., elimination of data, needs to stop at count 88 at the time of Noodle. In Drawing 8, the output of "88" detector circuit 78 is supplied to one input terminal of AND gate 79, and the input of the another side is considered as Q output of the 3rd cycle flip flop, i.e., flip flop 69. The output of AND gate 79 is supplied to the reset input terminal of flip flop 61, and random access memory is returned to reading mode. In hard [ slight / this ], as for a decoder, record and reading pass memory site 88-48 nothing. Subsequently, the program code of 48 A bit recorded in the memory into the 2nd cycle is read again, and it transmits to a computer. For this object, the output of "48" detector circuit 59 is supplied to one input terminal of AND gate 77, and that 2nd input terminal is driven with Q output of flip flop 69. (Since the output of another side of "48" detector circuit 59, i.e., the output to AND gate 60, does not have Q output from flip flop 55, it is necessary to notice it about an invalid point here). The output of AND gate 77 is supplied to the reset input terminal of flip flop 71, and transmission to a computer from the output terminal of confusion signal generator 75 is intercepted. The output of AND gate 77 is supplied to the Set input terminal of flip flop 78. Q output of flip flop 78 drives the 2nd input terminal of AND gate 51, and the 1st input terminal receives the data from random access memory 10. It is read until flip flop 78 is reset through AND gate 51 and abnormal-conditions machine 42' in hard [ slight / this ] as for the data from random access memory 10. Reset of flip flop 78 answers the signal from "0" detector circuit 65, and takes place. Transmission to the computer which passes reading of the program code from random access memory and the telephone line of these codes at the time of reception of this signal stops. At this time, it is necessary to send out a confusion signal until it reaches the arbitrary starting points from a decoder again to a computer. For this object, the signal from "0" detector circuit 65 is supplied to one input terminal of AND gate 80 (Drawing 7). The 2nd input terminal of AND gate 80 is connected to Q output terminal of flip flop 69. The signal of the output terminal of AND gate 80 is supplied to the Set input terminal of flip flop 81, and the Q output is supplied to the 1st input terminal of AND gate 82. The 2nd input terminal of AND gate 82 is also connected to the output terminal of confusion signal generator 75. It is transmitted to output terminal 82 of AND gate 82 following the output of "0" detector circuits [ in / hard / slight / this / in the signal from confusion signal generator 75 / the 3rd cycle ]. The output terminal of AND gate 82 is also connected to the input terminal of abnormal-conditions machine 42'. In hard [ slight / this ], transmission of a confusion signal is intercepted at the time of the end of the 3rd cycle. The 255 count output of counter 73 also resets flip flop 69, and intercepts transmission of the pulse from oscillator 46 to counters 11 and 73. The 255 count output of counter 73 is used also for the reset to the zero of counters 73 and 11, and returns a device to a start state. Explanation of operation of the decoder fee computational logic circuit in a perfect system sequence is completed now. The general-purpose computer programmed to supply various data needed in a system sequence may be sufficient as a central computer, or Then of this computer is also good for the same line as the decoder logic circuit mentioned above again by the single ability computer which carried out Along composition. Drawing 9 shows the interconnection of a decoder fee computational logic circuit and a telephone wire. Saturation Transformer 20 has the 1st winding firmly coiled around the telephone wire, and the 2nd winding connected to one input terminal of operational amplifier 21. The output terminal of operational amplifier 21 is connected to the input terminal of a frequency keying detector (52, Drawing 8). The 2nd input terminal of operational amplifier 21 is grounded. This circuit portion is a portion into which a decoder receives the information from a computer. For transmission to a computer, the output terminal of the FSK abnormal-conditions machine is connected to the input terminal of operational amplifier 24, the output terminal is connected to one Polar of the sauce Dorain circuit of field effect transistor 23, and Polar of another side is connected to the secondary wind line of Transformer 20. If a member pushes a "start" button, -12 v will be removed from the base of transistor 23, and transistor 23 will be in switch-on. Saturation Transformer insulates a system from a telephone wire, and restricts a ringing signal. The FSK abnormal-conditions machine and a detector are provided with the voltage controlled oscillator which generates the 2nd frequency for the 1st frequency at the time of a logic value "0" at the time of a logic value "1." Such frequency is not located in the usual voice transmitting belt. A present invention system needs the cognition of a security number, the cognition of arbitrary starting points, the cognition of a member identification number, and the cognition of the direction of the incorrect appearance from random access memory, in order to input a new program specification number into a memory or to eliminate fee calculated data, and it is very trustworthy.

[Brief Description of the Drawings]

Drawing 1 is a block circuit diagram of the transmitting side of a present invention subscription television system, Drawing 2 is a block circuit diagram of the logic circuit controlled by the circuit which detects the code number in a receiving side, and this circuit, In Drawing 3, the detailed circuit diagram of the program specification logic circuit of Drawing 2 and Drawing 4 are a still more detailed circuit diagram of each appointed circuit of Drawing 3, It is a circuit diagram in which the block diagram of the decoder circuit where the explanatory view in which Drawing 5 shows the memory site of the random access memory in a decoder, and Drawing 6 answer a receiving television signal, and Drawing 7th [ the ] and 8 show the block diagram of a fee calculation circuit, and Drawing 9 shows the interconnection of a decoder circuit and a telephone wire. 10 ...... Random access memory, 11 ...... Up / down counter, 15 ...... A clock generator, 20 ...... Saturation Transformer, 21, 24 ...... An operational amplifier, 23 ...... A field effect transistor, 40, 44a,48,52, 54,55,61, 63,67,69, 71,78,81 ...... A flip flop, 41,45,50, 51,56,60, 62,66,72, 74,77,79, 80, 82 ...... An AND gate, 42 ...... A long tone oscillator, 42' ...... The FSK abnormal-conditions machine, 43 ...... An integration circuit, 44 ...... A threshold circuit, 47, 57, 73 ...... The 1st, 2nd, and 3rd circulation counter, 49 ...... 0, a 1-phase oscillator, 52a ...... The FSK wave detector, 53 ...... A long tone detector, 58 ...... a comparison machine and 59 ...... "48" detectors and 65 ...... "0" -- A detector and 70 ...... an integration threshold circuit and 75 ...... a confusion signal generator and 78 ...... "88" detectors and 201 ...... an oscillator and 202 ...... a counter, 203,210,213 ...... A parallel-in-series shift register, 204 ...... 4H oscillator, 205,209,212 ...... A gate, 206 ...... Six line counters, 207 ...... Four line counters, 214 ...... An OR gate, 300 ...... [ ...... 4H oscillator, 307 / ...... 4 Bitrutti, 311 / ...... A decoder, 312 / ...... A program specification logic circuit, PA ] A video input terminal, 301 ...... A level detector, 302 ...... A serial-parallel shift register, 303₁~PA₁₆...... A program identification number input lead, 600 ...... Random access memory, 601 ...... 16 bit-shift register, 602 ...... Up / down counter, 603 ...... 6 phase clock, 605 ...... 8 bit-shift register, 606 ...... A counter, 607 ...... A clock drive flip flop, 608 ...... A comparison machine, 610 ...... An AND gate, 611 ...... A clock drive flip flop, 611a ...... An AND gate, 612 ...... 8 bit-shift register, 613 ...... A zero detector, 614 ...... A flip flop, 615 ...... A counter, 616 ...... A flip flop, 617 ...... A write-in drive circuit, 618 ...... A counter, 619 ...... An AND gate, 620 ...... [ ...... A comparison machine, 625 / ...... An OR gate, 649 / ...... A switch arm, 650~653 / ...... OR gate. ] A re-circulation circuit, 621 ...... A comparison machine, 622 ...... A program drive flip flop, 623,624