Manufacture of semiconductor device

[Detailed Description of the Invention]

(Field of the Invention) The present invention relates to the lamination process art in which the laminated type integrated circuit in which various application, such as high accumulation and multi-functionalization, is possible can be manufactured for a short period of time. (PRIOR ART) The accumulation element of multilayer structure can realize the device which compounded that accumulation density can be made very high and a complicated function compared with the usual element. Light and an electronic accumulation element (OEIC) are conventionally known as such a thing. 0EIC is a thing of unifying and elaborating optical devices and an electronic circuit on the same semiconductor substrate, reducing wiring inductance and stray capacitance, and making high-speed operation perform. The international conference concerning [ Drawing 5 ] the 14th solid-state devices at the conventional example of OEIC (Proceedings of the 14 th Conference onSolid 5tate Devices) It is an accumulation element which comprises Tokyo, and GaAs-LED and three MESFET(s) which were announced by 1982. pp587~588. Although LED22 and FET23 are accumulated on the lengthwise direction on both sides of H of high resistance, R, and GaAs 21, it is unification composition and it is not easy to attain optimization of the characteristic of LED22 and FET23 that layer structures differ. Although H, R, and GaAs 21 are inserted in order to take both electric isolation, the high resistance layer which can take sufficient l5olation practical is not yet realized. The present invention is made in view of the above-mentioned fault, and it aims at providing the manufacturing method of the semiconductor device which unifies both compactly, without spoiling the characteristic of both devices. (Means for solving a problem) The manufacturing method of the semiconductor device which becomes the present invention makes the metal for fusion laminate on one side of an OPTO semiconductor device. Open-size-of-strand Tailoring of this is carried out, it is put on the fuse section of another semiconductor substrate in which the electronic circuit was formed, the above-mentioned fuse section is formed of the metaled vamp, and the above-mentioned semiconductor chip and the above-mentioned semiconductor substrate are unified by heating and fusion. (OPERATION) Since a chip comrade is formed separately and this is pasted together, it can be considered as the optimal structure and each characteristic is not spoiled compared with the method of elaborating simultaneously on the same board. Since the wire bonding of the chip comrade who pastes together is unnecessary, it becomes possible [ parasitism inductance or capacity ] to stop small. (EXAMPLE) Drawing 1 shows the sectional view of the device manufactured by one example concerning the present invention. The CMOS inverter is formed in the surface of SO8 substrate 11. 12 is Au vamp and the light emitting diode (LED) by which 13 was made from InGaAsP/InP. Drawing 2 shows the photoelectric transfer characteristic, and the electric equivalent circuit is shown in the figure. n of a CMOS inverter, and the gate width/merit of pMO8T are 9515 (pm), and is threshold voltage 1;lit Sora 0.4V, -1, and OV He was tired.. LED13 A luminescence wavelengths are 1.3pm, and it carried them in the output terminal of the inverter by p side down. The size of each terminal of 0MO8 is a 1100p mouth, and Au vamp 12 of about 111-m thickness is formed in perpendicular wiring. Among Au vamps 12, the coat of the polyimide 14 is carried out in order to perform electric insulation during the chip of the upper bottom, and surface flat-ization, but the coat of this is not carried out, and it is I do not care. Drawing 3 shows this manufacture example. LED is the usual surface-emitting type, the diameter of luminescence is 2Spmphi, and a chip size is 300micromX300pm. Au5u15 of 111-m thickness is formed in fusion by complete vapor deposition at the p side of LED ((a) figure). Au vamp 12 on SO8 attaches to a thickness of about 1 micrometer by the alternative Au plating method using a resist mask. Next, the coat of the polyimide 14 is carried out on SO8 on the whole surface ((b) figure). If viscosity of polyimide 14 is made into the suitable size, the layer thickness of polyimide 14 after the application on Au vamp 12 will become thin at about ten 1 A compared with the layer thickness of the other field. If dry etching of the whole surface is carried out by CF4 after solidifying polyimide 14 with two steps of baking powder, 200degreeC and 350 degreeC, polyimide 14 will be etched and Au vamp 12 will expose first. Etching is stopped in this state ((C) figure). LED is carried on Au vamp 12 after that, and LED is held down by a jig. Au5u solves this with 1-minute and 30-second Equipment into N2 atmosphere of 260 degreeC, and LED is fused on Au vamp 12 ((d) figure). Optical power [ in / in the driving current of LED / 100 mA ] which Drawing 4 carried LED on Au vamp of different size, and performed the drive directly, Difference deltap with the optical power of LED for reference carried on heat Synge by the usual method is taken along a vertical axis, and a vamp's length of one side is taken and shown on a horizontal axis. If the fall of optical power is seen with reduction of vamp area and carried in the vamp of a 1100p mouth of a thing, it turns out that deltap is suppressed to 1 dB. (EFFECT OF THE INVENTION) Both can be unified, without spoiling the characteristic of the device formed in two chips, chips and chips, and wafers according to the present invention.

[Brief Description of the Drawings]

The figure showing the optical power characteristic of LED that Drawing 1, Drawing 2, and Drawing 3 carried the figure of one example in connection with the present invention and Drawing 4 on Au vamp, and Drawing 5 are figures showing a conventional example. in the figure -- 11 -- as for polyimide and 15, Au vamp, and 13 and 22 are [ H, R, GaAs, and 23 ] FET Au5u and 21 a light emitting diode and 14 SO8 substrate and 12. Oh I figure Drawing 2 Drawing 3 (a) (C) ↑ (d)