Variable length data processor

[Detailed Description of the Invention]

(Field of the Invention) More particularly, this invention relates to the variable-length-data processing unit which processes the variable-length extensive data of image data etc. about a variable-length-data processing unit. (PRIOR ART) The command in the conventional data processing device has been considered based on fixed-length data (byte, word, etc.). The length of the data used as the candidate for an operation is defined beforehand, for example, this fixed length data is 1 A bit, 1 character, one word, etc. It is saving of memory capacity to be made to arbitrary length, since there is the length of the actually generated data variously according to the contents of processing, From a point of the simplification of a program, although it is desirable, since fixed length data can accelerate the composition top of the arithmetic circuit in a data processing device by Condolence, most common commercial computers are based on the operation of fixed length data. The method of the memory circuit in a data processing device also accessing to fixed length data is taken. Carrying out only (the problem which an invention tends to solve), the range of the information which should be dealt with with development of the present information processing system is expanded, and multimedia data processing, such as picture information or Musical instrument information, is becoming an important function. These data is variable length in wood quality, and the Information Mutsuki is huge. Therefore, when the conventional data processing device performs processing to such ijf strange length data, The problem of the complicatedness of a processing algorithm and the increase in processing time by always having to be conscious of the problem of Binding of the memory storage by the formation of Many arrival of data Fauna and the byte boundary (or word boundary) in data-processing operation arises. In particular, high integration of a storage cell progresses and the factor of the present latter by which the problem of fusion of memory storage is being avoided serves as a fault. In order to solve these problems in the present invention. Therefore, it aims at simplification of processing to variable length data and improvement in the speed providing Noh of strange length data processing device one. (Means for solving a problem) In order that this invention may attain the account II target of 1-, the variable length data stored in the memory storage which memorizes the variable length data used as image data like picture information, and this memory storage is read, In the variable-length-data processing unit constituted from an output mechanism which outputs the contents processed with the arithmetic unit which performs Kanji writing, and this arithmetic unit, Fixed length data from the arbitrary bit positions in memory storage arbitrary in the mask pattern generating means and this bit length data for choosing the bit length data specified from the bit position where the fixed length data in read-out, writing means, and arithmetic unit which perform read-out, and -I come lump was specified -- carrying out bit position He shift It is JJ A gay 11 Si ing about CIF] and the means of a good Obtain sake to a mask pattern generating means in the data after a shift. (OPERATION) The present invention constituted a variable-length-data processing unit as mentioned above. Therefore, memory storage which memorizes variable length data is 11 when accessing this variable length data. - It reads from a bit position fixed considering variable length data as fixed length data by bit address obtained. an arithmetic unit obtains the bit length data specified from Pittoi stand specified to the fixed length data read from the account memory storage of A, and is arbitrary in this bit length data -- bit position He shift is carried out and variable length data is processed by a focus address and effective bit length. Therefore, the above-mentioned problem is solvable. (EXAMPLE) Drawing 1 is a lineblock diagram showing the memory storage in this invention. The memory data bus which is a bidirectional bus of N bit which sends out +00 to the arithmetic unit which performs read-out / Addition T / writing of the data of this memory storage in the figure, The memory address bus to which the data from the account arithmetic unit of 1- is transmitted 101, When the address to bank 11O is chosen and access It was data is straddling bank 110 from bank lln, in order for 102 to consider it as the address which carried out the address in a memory cell plus 1 and to supply it to bank+10 n which is prepared and ranges from bank lln to bank 110 (addition circuit which makes strange length data access +i dish ability) The selection gate which 103 considers the address in a memory cell in address human power as an input, and chooses the address to bank 110, 104 considers the address in a memory cell in address human power as an input, and is a row address, The selection gate which chooses a column address and supplies data to the memory cell of bank 111~bank IIn, The write-in control circuit to which 105 supplies a write-in signal to the bit in the target memory cell at the time of write-in specification, 10[(reading control circuit which turns ON the read-out signal of 120~12 n of read-out gates to the bit in the target memory cell at the time of read-out specification) The bank which is a collection of the storage parts as which 110 to 11 n is respectively chosen in the same bank address, and 120~12 n are read-out gates which send out the required data from bank 110~tin to memory data bus 100-1- with directions of reading control circuit 108. Here, the storage part of this memory storage is divided into the unit called a bank, and also is divided into the unit called a plurality of cells according to the capacity of a storage part. The bit length of a cell is N bit and the data line of the cell of the same bank is connected to memory data bus 100 corresponding with a bit number. By the way, as for bank 110~bank 11n Scared, consecutive addresses are decided as grant of the address of this memory storage is shown in Drawing 2. The address input to this memory storage is classified into four, a memory cell selection address, address A in a memory cell, blowout address n, and dot address Q, from a higher rank, as shown in Drawing 3. A memory cell selection address is used for selection of a plurality of cells of the same bank, address A in a memory cell reaches Selection good 103.104, and it is an addition circuit! It becomes an input of 02. Bank address n and dot address l are used as an input of write-in control circuit 105. reading control circuit 10B. next, it is alike and explains operation of the memory storage of composition like an account. as an address input of as opposed to [ when accessing variable length data as shown in Drawing 3 ] bank 110 -- addition circuit 102 and selection gate 103 -- passing (A+1) -- it is inputted and A is inputted via selection gate 104 as an address input to bank lln. And reading control circuit+06 is read according to bank address n and dot address l of an address input, turns ON 11 bits of -hB(s) of good I, a +2-n low rank (N-J2) bit, and read-out gate 120, and sends out data required for it to be alike memory data bus 100. Thus, the memory storage of this example can be written in the bit position which had variable length data fixed by the bit address given, and can read the written-in variable length data from bit positions arbitrary as fixed length data. The influence of the access time to an arithmetic unit is lost by performing selection at the time of read-out at 120~12 n of read-out gates of a final stage, By taking a row address to the low rank side of the address in a memory cell, the addition delay in the address input through addition circuit 102 is suppressed as much as possible, and rapid access can be realized. Drawing 4 is a lineblock diagram showing the arithmetic unit in this invention. it sets to the figure -- it is for 200.201.202 connecting each unit -- each operand bus A Operand bus B, a result bus, and 210 are a barrel shift and a logical operation, The operation unit which performs arithmetic operation, and 211 are hard registers 2! Selection gate which specifies CIF ill of 3 and a barrel shift [ by the contents of the lower bit of address register 215 ] in operation unit 21O, The local memory 212 remembers an operation result to be temporarily, the hard register in which, as for 213, the complement data of 2 of a Seratos should bit address is set, Read-only memory for mask pattern generating which 214 makes an address the contents set in hard register 213, and sends out the data to operand bus A200, 215 is an address register in which the dot address from the above-mentioned memory storage is set, and a data buffer to which N bit data from the memory storage of the above-mentioned [ 216 ] are set. Here, the width of each bus of operand bus A200. operand bus 8201. result path 202 is a data width N bit of the above-mentioned memory storage. The rotation shift to N bit is possible for the shift function in operation unit 210, and it can perform specification of shift at via selection Gout 211 according to the contents of the lower bit of address register 215 and hard register 213. This makes it possible to carry out combination for the data read by the above-mentioned memory storage if needed. That is, the data read by performing the left rotation shift action for the dot address set in address register 215 is arranged with N bit from the most significant bit. When the data of this generated N bit is written in from arbitrary bit positions, The writing of N bit is enabled from arbitrary bit positions to the above-mentioned memory storage by setting in hard register 213 the complement data of 2 of the bit address which should be set, and performing a left rotation shift with shift amount directions. And it sends out to operand bus A200 via read-only memory 214 for mask pattern generating by making into an address the contents set in hard register 213. Correspondence of the contents of the contents of this hard register 213 and mask pattern 214, i.e., the read-only memory for mask pattern generating, read is shown in Drawing 5. The selected mask pattern is N bit and is prescribed by a mask bit starting position and mask length. Arbitrary bit position data processing to the arbitrary bit positions of the variable length data of the above-mentioned memory storage can carry out easily by this mask pattern and the above-mentioned shift function. For example, as shown in Drawing 6, when transmitting the data (however, C<=N) of C bit length of a slash part to b address from a address, data manipulation of the arithmetic unit in this example is performed by the following procedures. (1) Read a address to N bit data from (2) memory storage which sets a to attelet District 215 via memory data bus 100, and set to data buffer 216. (3) The left rotation shift for the dot address of attelet District 215 is performed for N Vint data of (2), b# ground to N bit data are read from (5) memory storage which sets storing Touched (4) b in address register 215 temporarily to local memory 212 via memory data bus 100 as data arranged with N bit, and it sets to data buffer 216. (8) They are N bit data of (5) Address register 2]

(s) which sets in hard register 213 (7) C set to data buffer 21B as data which performed the left rotation shift for the dot address of 5, and was arranged with N bit Logical product of the data and the mask pattern which are stored by (3), The reverse putter of the data and the mask pattern in data buffer 21B The complement of 2 of (8) b which carries out the logical sum of the logical product with A, and it stores in data buffer 21B is set in hard register 213. (10) Perform the shift amount part left rotation shift specified by hard register 213 in the data stored in Data Bar Nerva 216 of (8), and store in data buffer 21B again. (11) Store the contents of data buffer 218 of (10) in b address shown by address register 215. (EFFECT OF THE INVENTION) As explained above, according to the present invention, processing of variable length data is attained by unitary management called a bit address and effective bit length by the shift function and mask pattern developmental mechanics in the memory storage and the arithmetic unit which can be accessed per bit, Moreover processing of this variable length data is accelerated and simplified, and the variable-length-data processing unit which can perform effectively operation of the edit phi display-output of image data like picture information, or a data compression/extension can be provided.

[Brief Description of the Drawings]

Drawings 2 are a lineblock diagram showing memory storage [ in / in Drawing 1 / this invention ], and a figure showing address allotment of the memory storage of Drawing 1, It is a figure in which the figure showing the example to which Drawing 3 accesses the classification of the address of the memory storage of Drawing 1 and this, the lineblock diagram showing an arithmetic unit [ in / in Drawing 4 / this invention ], and Drawing 5 show the explanatory view of a mask pattern, and Drawing 6 shows the example of variable-length-data processing. 100 ... memory data bus, 101 ... memory address bus, 102 ... addition circuit. 103, 104.211 ... A selection gate, 105 ... Write-in control circuit, 10B ... A reading control circuit, 110~lln ... A bank, 120~12n read-out gate, 200 ... operand bus A 201 ... operand bus B 202 ... result bus, 210 ... operation unit, 212 ... local memory, 213 ... hard register, 214 ... read-only memory for mask pattern generating, 215 ... address District, 21 B ... data buffer.