Complementary semiconductor integrated circuit

[Detailed Description of the Invention]

[Field of the Invention] The present invention relates to the phase assistant type integrated circuit which is applied to the phase assistant type integrated circuit which used the phase assistant type MO8 Action element, especially can simplify a clock input signal. [Description of the Prior Art] When the example of the conventional C-MOS shift register circuit is shown in Drawings 1 and 2 and is explained, in a figure, (1) is a data input terminal in which a data input signal is impressed, and a data output terminal in which a data output signal is acquired (2). and the circuit shown in this Drawing 1 -- a memory circuit element (a register circuit is called hereafter) -- (31) , (3z) ... (3n) (41 (!51)) 4th conducted type MOof current 8 run District (it calls for short following NchFET) (61 joining together in series via ... the NchFET (47~ (clock input terminal+71 (constituted so that clock signal phi impressed to (Ri) in 8 and its inversion signal phi may be inputted by turns.) connected to each gate of 61 at the gate))) Instead of NCllFET of Drawing 1, Drawings 2 are NchFET and the 2nd conducted type MOof current8+-run District. It connects (hereinafter, it is called PchF and ET for short), and it is constituted so that clock signal phi of reversal and ■ may be mutually put into the gate input of NchFET, and the gate input of PchFET, respectively. Operation of the C-MOS shift register circuit constituted in this way is explained using Drawing 1. First, when clock signal phi changes into the state (H" state is called hereafter) more than the threshold voltage of NchFffT, it is NchFET (J turns on.). And ON of this Nc hFET (4) will introduce the input signal from a data input terminal (1) into the 1st register circuit (31). Since inversion signal 7 of clock signal phi is in o■ state (L" state is called hereafter) at this time, it is NchFET (51 turns off.). Next, when clock signal phi will be in the "L" state, it is Nc hFET (since it turns off and inversion signal 7 of clock signal phi will be in "H" state, 4J is NchFET (51 turns on.)). Therefore, the contents of the 1st register circuit (31) go into the 2nd register circuit (32). Hereinafter, the contents of the register circuit go into the register circuit of the right-hand side with change of the clock signal. However, in such a circuit, two kinds of clock signals, clock signal phi and its inversion signal phi, were required in the shift register as mentioned above. [Summary of the Invention] It is in providing the phase assistant type integrated circuit which the present invention solved such a problem in view of the above point, and was made that this fault should be removed, and the object can simplify a clock input signal and simplifies circuit composition in connection with this and whose degree of location also improves. In order to achieve such an object, the present invention connects NchFET and PchFET as a transmission gate between register circuits by turns. [Example] Hereinafter, based on a drawing, the example of the present invention is described in detail. Drawing 3 is a circuit diagram showing one example of the phase assistant type integrated circuit by the present invention, and shows an example at the time of applying the present invention to a shift register circuit. In this Drawing 3, the thing of the same numerals as Drawings 1 and 2 shows a considerable portion, and (10) is NchFHT (as for LIJ, PchFET1Q21 is N c h FET, and these are connected as a transmission gate between register circuit (31)~ (3n) by turns.), And this register circuit (31) ~ (3n) is NchFffTQOJ and PcbFET (lupsilon, NchFET (1Every)). ...... It is combined in series by the Passing through control type transistor, and the gate of this passage control type transistor is a clock input terminal (71 (81, (9) .... connected to --)), respectively. In the odd-numbered Painful control type transistor, NchFET and the even-numbered passage control type transistor are P c h F J (it comprises 'I1.", respectively.). Operation of the example shown in this Drawing 3 below is explained. First, a clock input terminal (71 (when clock signal phi impressed to 91 will be in "H" state, it is NchFET (101 and Nc hFET (121 shifts to an ON state.)))) And the input signal from a data input terminal (1) is inputted into the 1st register circuit (31). At this time, since it is in 'H" state, clock signal phi impressed to a clock input terminal (8) is PchFET (since IIJ turns off, the contents of a register of the 1st register circuit (31) are not spread in that next register circuit (32).). If clock signal phi impressed to a clock input terminal (8) will be in the "L" state next, PchFET (14) will shift to an ON state. And this PchFET (if lupsilon turns on, the contents of the 1st register circuit (31) will spread to the 2nd register circuit (32).) At this time, it is a clock input terminal (7) (since clock signal phi impressed to 91 is in L" state and NchFETQl and (12) turn it off), The contents of the 2nd register circuit (32) are not spread in the next register circuit, and an input signal does not go into the 1st register circuit (31) from data input terminal fil. Thus, in the circuit of the example shown in this Drawing 3, a shift register can be operated with a single clock signal. Drawing 4 shows an example of the shift register circuit whose memory circuit element in Drawing 3 it is a circuit diagram showing other examples of the present invention, and is an inverter circuit. In this Drawing 4, the same numerals are given to the same portion as Drawing 3, and explanation is omitted. Q31 (+41 is the inverter circuit constituted from 8 circuits of phase assistant type MO, and is this inverter circuit (131 (141 is NchIi'ET (to) and PchFET (Iupsilon and NchFET (combined in series by 121.))))), Operation of the example shown in this Drawing 4 below is explained. First, NCllFET (10) is turned on when clock signal phi impressed to the clock input terminal (7) is in "H" state, and the input signal from data input terminal fl goes into inverter circuit alpha~. Next, this input signal is Nc hFETalpha0 and an inverter circuit (held with the gate capacity between 131). When clock signal phi impressed to a clock input terminal (8) is in the "L" state, PchFP3Taupsilon turns on, and it is an inverter circuit (the above-mentioned data input signal is inputted into 1 (b).). Therefore, the circuits of the example shown in this Drawing 4 are a circuit shown in Drawing 3, and a shift register circuit which can operate with a single clock signal similarly. And an example shown in this Drawing 4 is the inverter circuit which a memory circuit element constituted from 8 circuits of phase assistant type MO. Memory of information is dynamically performed with input capacitance of the inverter circuit. Simplification of the clock input signal by the combined use of PchFET like an example and NchFET shown in Drawings 3 and 4 of the above can be used also in D type flip-flop circuit. And the inverter between two clock signal input transistors in D type flip-flop circuit can be omitted by PchFET and NchFET in this case, and a degree of location can be improved. [Effect of the Invention] As explained above, the present invention constituted a shift register circuit which required two kinds of clock signals for a C-MOS shift register circuit conventionally using PchFET and NchFET as a transmission gate of a simple substance respectively so that it might operate by a single clock signal. therefore, circuit composition Powern -- since it only becomes and a degree of location also improves in connection with this, a practical effect is size very much. Since the single clock signal which simplified I am talented and a clock signal is used, in the point of becoming unnecessary, adjustment between clocks is also very effective. Thus, according to the present invention, as a phase assistant type integrated circuit which there is a great effect as compared with this conventional kind of C-MOS shift register circuit, and can simplify a clock input signal, it is original.

[Brief Description of the Drawings]

The circuit diagram showing the example of the C-MOS shift register of the former [ Drawings / 1 and 2 ], the circuit diagram showing one example of the phase assistant type integrated circuit according [ Drawing 3 ] to the present invention, and Drawing 4 are circuit diagrams showing other examples of the present invention. (1) ... A life data input terminal, (2) and a fist .. A data output terminal, (31)~ (3n) .... Register circuit (memory circuit element), (71~ (9) (IIJ -- [ @@PchFET (m 2 a% type MOS transistor), 03L (14) ] .... in tweeter circuit) .... Clock input terminal (101, (12) .... NchFET (the 1st electric conduction type MOS transistor))) Representative Masuo Oiwa The Commissioner of JPO 1. Display of an incident Japanese Patent Application No. No. [ two ] 114601 [ 58 to ], title of an invention Phase assistant type integrated circuit 3, those that do amendment Relation with an incident It is a part in applicant-for-a-patent representative Hitoshi Katayama. 4 Representative The claim of the column (1) specification of the claim of an ill specification is amended like an attached sheet. (The text of "" (it is hereafter called CMO8 for short) is joined after the 2nd page of 21 said document 1 structure " of the 5th line.) (3) Amend the 8th page of writing "circuit" of the 9th line with a "transistor." Above Attached sheet it is a preparation about the clock input terminal in which the data output signal and clock signal with which the data input terminal in which [(1) data-input signal is impressed, and a data output signal are acquired are impressed -- it is a logic circuit While having at least two or more memory circuit elements consisting of a phase assistant type MOS transistor and combining this memory circuit element in series via a passage control type transistor, The gate of the above-mentioned passage control type transistor is connected to the above-mentioned clock input terminal, And the phase assistant type integrated circuit which considers as % mark that the odd-numbered passage control type transistor comprises a 1st electric conduction type MOS transistor, and the even-numbered passage control type transistor comprises 2nd Honesty type MO8I-run District. (They are 21 memory circuit elements Phase assistant type MO8) Phase assistant type integrated circuit of an application for patent, wherein it constitutes from an inverter circuit formed by run District and memory of information is dynamically performed with the input capacitance of the above-mentioned inverter circuit given in the 1st paragraph of the range. More than " -808 -