Master slice

[Detailed Description of the Invention]

[Field of the Invention] The present invention relates to a high-density reduced type electronic circuit like very large-scale integration (VLS I), and relates to the art which uses a mask slice more efficiently in manufacture of such a circuit especially. Development of overly small electronic art is shown in much literature. With for example, 5cientjf icAmerican entitled "M i c r o e] e c t r o n j c s" published in 1977, the future influence of the design of reduced type electronic devices and those elements in VLSI circuit form, manufactures, and those elements is described, and it comes out. With IBM Journal of'Re5 earch andDevelopment, "VLS T C1rcuit Design" of the May, 1981 issue, as for 'Packaging Technology" of the May, 1982 issue, and the September, 1982 issue, llSemiconcluctorManufacturing Technology"iC sets, and various overly small electronic art is described and it comes out. As production technology of a reduced type electronic circuit, there are bipolar transistor art, field effect transistor (FET) art, metal-oxide-semiconductor (M'os) art, and metal-oxide-semiconductor (CMO8) art of phase assistant type. Many production technology of such a semiconductor device is shown in 5cientific American. for example, -- using optical art for the 42 pages, controlling by a computer -- topological(topological)++ -- it is shown by many steps including the pattern thing made to generate that a dog and a scale accumulation (T, S I) circuit can be manufactured. Other matters about manufacture of a reduced type electronic circuit including the arrangement which accumulates the layout of a mask slice, the layout of a logic cell, and a reduced type electronic circuit with high density especially are shown in the following articles. I s BM TDB and Vol 8, No, 4, S ep tembe r1965, PP, and 642-.643 The cascode decoder which controls input voltage to a near value mutually, is impressed to the input of a cascode decoder in differential, and carries out high-speed operation by the minimum electric power disappearance by this is an example. IBM TDB, Vol, 14. No, 12. May 1972, PP, and 3684-3685, (6) In the current switch circuit using a bipolar transistor, by providing one pair of field effect transistor (FET) loads which carried out cross connection to those bipolar transistors, carrying out high-speed operation shows and be about both positive and negative changes with low electric power. In Ding BM TDB and Vol, 20, No, 10, March1978, PP, and 4013, it is 12I. (Integrated Injection Log, ic) The layout of a logic cell made into the channel of a master slice array and the minimum [ blocking ] is an example. IBM TDBl Vband1.22, No, 8A. It is an example by approaching a pouring field common to January 198[], PP, and 3258-3259, and providing a MT L' (Merged Transistor Lo, gic) cell in X and the direction of Y that the density of a MTL array thru/or the capability of writing can be improved. T BM TDB, Vol, 23, N'o, and '7 A. December 1980, PP, and 2833-2835, By automating combining a manual design and an automated design, it is usual (4) most quickly in the adaptability which was most excellent in the integrated circuit in maximum density 1 * manufacture-f;Sj, "* Show l-" Ah ' and 11BM TDB and Vol, 24, No, 3, August1981, Pp, and 1705-1706. The customized (Customized) cascode current switch circuit which makes generating of parity easy in the logic stage less than Circuit is an example. The trigger circuit of the high-speed operation which gives U.S. Pat. No. 3233223 an output after single transistor delay is an example. the multiple level which U.S. Pat.34469.89In issue is connected so that a bistable device may be controlled, and operates such again -- accumulation --"t Semiconductor logic circuit shows and comes out. The large-scale-integration composition which produces the compound logic function which contains combination and sequential logic in U.S. Pat. No. 3475621 is an example. the [ United States patent ] -- the latch circuitry of two or more inputs in a 3760j9D item -- business -- it shows and comes out by retaining an output signal to reset regardless of the change in °C and The, and an input signal to satisfy more a plurality of child arrangement Was done input signal conditions. The digital logic circuit which performs a digital operation function in U.S. Pat. No. 3978329 is an example. The digital decoder which decodes a digital signal in U.S. Pat. No. 4176287, and the CMOS decoder which especially one of n decoded outputs can provide with a top are examples. It is an example that the U.S. Pat.4249193In issue can provide the improved LSI device with the design technique by which structure, wiring, and the mask slice containing a manufacturing method were improved. The composition of the improved LSI semiconductor design which can But as if performance of a semiconductor device and a circuit is made the optimal while raising density to U.S. Pat. No. 4295149 is an example. In manufacture of a reduced type electronic circuit, the general method used the macro logic element until now. Usually, when needed for manufacture of a circuit, in order to access, the macro logic element was held to the library. mostly, complete a chip, i.e., logic products, -- a plurality of macro elements were combined with the sake. design and drop off separately until a macro library reaches the library entity of a criticality number -- if it is Leave, there is nothing. realize efficiently a library and the entity logic machine (it is hereafter considered as a machine) which uses and has flexibility for the first time after reaching That and h -- things should be made. It is difficult to be completing the design of a perfect set to this thing for many years, and to design the finished product of an effective request. The physical image obtained from the macro element which be used between circuit manufactures, was carried out and was referred to again is restrained as a result of a macroscopic concept. [Summary of the Invention] The object of the present invention is to provide the art of conquering restrictions of Individual received in order to use the concept of macro logic in the case of manufacture of a logic circuit. be used for manufacture of a reduced type electronic logic circuit in the present invention -- all the macro logic Sueko is decomposed into those most fundamental logic elements. This can design equivalent logic by a more nearly general-purpose and compacter method. (7) Whenever it carries out the present invention, flexible increase Burn it which can be set by circuitry j, and time are saved more, and the outstanding advantage that the problem of the complexity which the prior art had encountered is solvable is brought about. use the set of the small closed macro element -- the outstanding advantage of simplifying the automation about a process required to attain the target logic products by things, i.e., making it improve should also be brought about. use the art of the circuit/logic of a differential cascode current switch (DCC8) or a differential cascode voltage switch (DCVS) under automatic arrangement and wiring in the good example of the present invention -- it needs -- in order to carry out Into, a topological tc physics design is used. This physical design Te can be set to a master slice, and Active device arrangement is "brick wall (it is brikwallgamma" and is.). namely, a plurality of sizes -- in the prescribed area of a device arrangement field, in a dense collection, a uniform square activity device makes it regular, and is arranged like block arrangement of a concrete block wall, and it is making band-like [ which was extended for a long time to one way ]. (8) The present invention can constitute a fundamental micro block in cascode 2 Advanced decision tree. This decision tree makes a form similar to a bipolar cascode current switch (BCC3). FET cascode current switch (FCCS) logic art is brought about by this decision tree. And this FCC8 logic art can attain the same logic function as BCC8 logic art. With FCC8 logic art, since the signal level converter of the middle stage [ as / in Bccs logic art ] is omissible, raise cascode logic art. furthermore -- it can set on BCC8 logic art with FCC8 logic art -- Filtration -- since a current chic device [ like ] is omissible, the advantage superior to BCC8 logic art is brought about. l in FCC8 logic art -- the current-sinking function of BCC8 logic art -- the current source load device in depression mode -- Doing -- carry out. Preparation of the amplitude of an output logical level should be made by this device, and a setup of the current level which flows through an energization logical path should be made. It was found out by the present invention that a differential cascode current switch can be processed logically and physically on the micro block level of that. It is [ deriving logic description of logic products by the present invention about the (granular) micro block level which it subdivided very much, or ], and is * Glue. And by the present invention, on the same micro block level as it, the logic description can be transposed to a physical design, and can be processed. [Example] Describe the design concept which can make cascode logic general-purpose logic art. When this design concept is [ about a product ] logical and describes a physical element, whenever it treats logic art in that most subdivided form, it is based. The foundation for making software intensive and treating logic art by this, is brought about, and high productivity required to give flexibility to logic art is acquired. In the case of the FET circuit, it is based at the thing with which logic art is finished as the load device in Take action mode from a micro block and to do for 2 Hekkake decision tree Hekasu code. This load device makes a logic signal reveal, and sets up a Flow t Filtration current level for a decision tree. Attain high productivity in both the logic design stage about a product, and a physical design phase by developing this designing method so that a VLS I master slice can be used. A VLS T master slice is used for manufacturing DCC8 of cascode logic, or DCVS using bipolar transistor, FET, or CMO8, for example. this mask slice -- two general-purpose fields, i.e., input-and-output adjacent spaces, and a cascode logic field -- it is. If logic products are manufactured using mask slice art, mainly shorten production time. As for shortening of this processing time, a mask slice is processed through many manufacture steps. Since it is stored in a storage device, it is possible. What is necessary is just to process through few remaining manufacture steps, in order to give a function to a product. The process of manufacturing the master slice of a bipolar transistor to the one A1st m is shown. This manufacturing process comprises six steps indicated to be 11 thru/or 16. a manufacturing process is wafer semiconductor [ like /recon ] oxidization 1~ in Step 11 -- it starts from processing a thing. Of course, the wafer of other substances may be used. this -- carrying out wafer As opposed to, forming a burial collector region at Step 12, forming a separation field at Step 13, and forming a collector reach through field at Step 14 -- Step 15 -- a base -- a diffusion region -- it forms and, finally forms an emitter diffusion field at Step 16. the result of Step 16 -- a sea urchin -- a structure perpendicular about all the activity devices in .. and passive devices is completed. End postposing of Step 16, mask -/(the Juice wafer is stored in the storage device.) In the process of manufacturing the mask slice of CMO8, processing which manufactures the device which has a channel of the polarity of N and P is performed also to 1 [ wafer semiconductor / like silicon ] which oxidized, and it is formed in a CMOS array. Rye The is "HMO8-CMO8-A Low-Power High Performance Technology"by Ken Yu et al to the details of such processing, Please refer to IEEE Journal ofSolid 5tateC1rcuits, Vol, 5C-i6, No, 5, 0ctober 1981.PP, and 454-459. In such processing, it is possible to make two wiring intersect perpendicularly. the -- the process of manufacturing the master fist slice of FET is shown inB [ 1 ] figure. This manufacturing process comprises four steps indicated to be 11' thru/or 14'. this manufacturing process -- step 11' Tail Hey -- it starts from processing what [ wafer / a thing / a semiconductor like silicon / that oxidized ] and and. Of course, the wafer of other substances may be used. To this wafer, a separation field is formed by step 12', sauce / Dorain field is formed by step 13', and a gate is formed by step 14'. A perpendicular structure of a device is completed as a result of step 14'. After the end of step 14', it is storage l-Keep it to a mask slice and a wafer storage device. With, any mask slice of - To is in the state where it can use from a storage device, in this way at the time of par Sonarization (Personali-zation) to an argument W'M article. The processing step which remains opens a contact opening, is interconnection 1~ about an activity device and a passive device, and is completing the physical design about a logic function. As shown in Drawing 2, the final stage of processing, i.e., par Sonarization, picks out a required number of mask slice wafers from a storage device, and starts them from Step 20. To this wafer, the contact opening for an activity device and passive devices is opened at Step 21, and interconnection of multilevel interconnection is performed at Step 22. Subsequently, a bonding pad is provided by step 2 Filtration, the probe test of the logic function of the completion wafer which carried out bar tuna Rise at Step 24 is done, and it cuts for a wafer chip at Step 25, and chooses the chip as which Step 26 may be sufficient. And the good chip selected at Step 26 is assembled in a package at Step 27, the package is closed at Step 28, and the last test of the package is done at Step 29. Since what is necessary is to perform only Steps 20 thru/or 29 to design about the mask slice wafer of a storage device, and make it complete as each product with the above processing procedure, do [ shortening processing time per each product, or ] as a result. a bipolar master slice and the mask slice of FET -- both -- Knowledge -- the intensive designing method of the software about the cascode logic in which Apply is possible is just explained. By this method, high productivity can be attained and processing time can be shortened. In order to make an understanding of the good example of the present invention easy, cascode logic is explained briefly first. About one designing method, DCC3 art, and a cascode logic circuit, - cascode logic could not become general-purpose logic art - because of the various factor, although the characteristic of other bipolar logic circuit technical truth ratio Why and electric power performance was excellent. It becomes high productivity required for technical flexibility, or the feature, and explains the intensive designing method of °C and Filtration, and software. By considering the example of the differential cascode current switch (DCC8) using a bipolar, cascode logic should be easily made in understanding 1-To. DCC -- peculiar working speed being shown about an emitter coupled logic, and, covering the whole extended logic function on the other hand as it belongs to the logic in the current mode which carried out differential combination 8 The and the name means -- the circuit electric power -- distribution --"t Filtration. To Drawing 6, it is Showf about the DCC8 logic tree of six levels. A current generator carries out unit electric power which will be consumed when a DCC3 logic tree performs the designed logic function Tone and ready. logic -- operation -- DCC -- eight -- logic -- Kiuchi -- versatility -- a path -- flowing -- current -- two -- a One -- two -- advance -- Power division -- a point -- inside -- one -- a One -- turning -- things -- Doing -- " -- carrying out . the direction of current -- being in season -- impress a differential logic signal to each differential transistor in a logic tree, and be carried out by choosing Tabai 1 A which sends current. pool variable *A * and B' of the path shown in Drawing 6 by the arrow are true, i.e., positive, potential -- pool variable *C -- " -- when it is an imitation, i.e., negative potential, the path of Current flowing current is expressed for the logic tree. the DCC8 logic tree of Drawing 6 -- the -- the [A / 5 / figure and ] -- as shown inB [ 5 ] figure and the next table I, carry out a symbol display. Namely, table ■ ABCIIQII 000 0 0.01 0 010 0 011 1 100 1 101 1 110 1 111 0 The actual composition of a logic tree can carry out derivation directly from the truth table of three variables in Table ■. Output vector *Q' should be made from the table of perfect conditioning about Variable variable. Since six variables are contained, the DCC8 logic tree of the 5th the A figure will be used. It is crossed and formed at least in maximum - when the logic tree of output vector *Q * The and three levels is extended completely. Each output point of *Q degree Output vector and a logic tree crossed and formed at least in maximum - of a logic tree is connected with the conditional path of 1' or O'. Usually, when current flows, logic *0' will be spread. When each output point is connected to the end point, the cascode logic tree of six levels constituted so that versatility might carry out input condition Respond and a *Q * output vector might be given is profitable h Filtration. By further considering the composition of a logic tree shows that Redundancy length becomes clear and there is room to improve the composition of a logic tree from 'don't care' that a logic tree should be made the minimum. in this way, the result made into the minimum -- the -- it is shown inB [ 5 ] figure. The following thing should be suggested by this example. That is, any pool problems about three variables are that it is possible to solve by a single 6 level DCC8 logic tree. This can be illustrated still as follows. That is, given conditioning is by forming other various output vectors from a table, and constituting angle A of a logic tree like an example. And this When shows the following thing. namely, -- which -- depend -- the pool type of a *n' variable is also that it is possible to solve by a single n" level DCC8 logic tree. From these conclusions, it can say that the function capability of cascode logic is the same also about the electrical property of back side Prickly and its operation art. Moreover, this function capability can be attained within electric power disappearance of that logic gate with the working speed of the logic gate of a single level. the -- the example of the cascode logic tree of three levels carried out with CMO8FET art shows and comes out toA [ 4 ] figure. the -- the example of the cascode logic tree of three levels carried out with NMO8FET art shows and comes out toB [ 4 ] figure. these operations -- bitter The of the function characteristic and an electrical property is strictly the same in those each operation technical within the limits. If the capability of cascode logic art becomes clear, it will turn out that it is art ideal to put and for art to use a machine by VLSI. If it actually pursues the design of the machine by VLSI, it is required to have the method of generalization 1~Processing carrying out design Seikuru C and the problem of high productivity. V in the Constructing force method of the machine before L S T, a designer processes on a fundamental tc level -- the machine was made in division (partition) f To to the logic element unrelated to size and complexity. [ like ] Although split method [ this ] was rough and Standard:Jin method somewhat, it did not have big influence on Establishment of the fundamental level of the whole machine. This split method essentially has the following restrictions, and it is such IJ'rC Nagisa was done. That is, this split method can apply to a chip with a low degree of location of that time, and it is There. V L S T appears -- a single silicon chip -- 10000 pieces -- In -- use 0 logic gates -- it needs -- cope with it by a different method to the problem from become, and it is t, Age h The tC et al., and c < 1:x. V in order to fully demonstrate the capability of L S I art, constitute on a high level and carry out on a fundamental level Ha -- Something optimization is required. this -- accumulating -- the -- the [A / 6 / figure and ] -- be shown by the flow chart ofB [ 6 ] figure -- the method of the cascode logic design was developed. Re from a flow chart, or To -- like, since modeling of a high level is made easy, the designing method has been started. As [ serve as / this designing method /, in the present / a means to develop and simulate the model of the machine of a high level ] BDLC/ S (BasicDesign Language Control/Str) It suits with the language and I D L (it has the function same on an Interactive DesignLanguage 1 essence target as BDLC/S) which describe and model the hardware in a ucture Knee quantity level. In order to model and simulate a high level The machine and for the top to optimize it, the strategic high level modeling means containing the language and compiler of a high level is used. All of these means essentially Offer the same service in various efficiency, namely, a machine designer enables it to deal with the whole problem. All of these high level modeling means suit with the method of a cascode logic design by comprehensive description about the division on various functions about a machine. A comprehensive description which can be taken is jc To about the form of logic Map or the truth table of a function. fundamental logic should emulate such Map or a truth table after all, and it should drop off -- if it is Leave, about:"7'; and a complete set are expressed to the conditions of the function which is not. By a high level modeling means, 1 7 Tut of comprehensive Buo logical map should actually be given to a design system. Each of logic Map is front I f, a Zabu function, i.e., division, of a machine. These comprehensive logic Map are similar with the case of P L A (ProgrammableLogic Array) in that they express the output vector of 1 Set which becomes settled according to □ conditions of the input variable of 1 Set. A logical group's sets are processing Sari and To like the machine in which a synchronous method carries out sequential operation in the design system. that is, the machine specified by each logical group by other logical groups or the sub function of a machine, and space-time relations -- sub machine capability Execution is carried out. In Drawing 7, the composition of a machine is an example by a logical group. L S S D (Level Sensitive5can Design) a latch is Inquiry(ed) to each logical group's input, and the mechanism which carries out the clock of the system is given. if the clock of each logical group is carried out, complete the quota t It was task and give the output between the following clock stages to the divided part which the next follows. Be incorporated into the system according to stage as a logic element of T, a SSD latch, and * black box"' like other registers of a machine. By the motel-ized means of a high level, the information which exists from outside with description of a machine should be given again. That is, they are assignment of the type of a driver/receiver, a switching group, and eye Prediction of Ding 10, and an objective function of * Mann pass level. By an objective function, the relative priority about the parameter, i.e., delay, the electric power, and the field of system optimization is setting Fang Fang 1. To. When you change the comprehensive table of a high level into DCCS cascode logic Tree net, give this objective function between the stages of the beginning of a designing method, all the machine divided parts, i.e., logical group. Comprehensive tc logic Map showing the logical group who does clock operation is Completion(ed) to DCC8 logic Tree net. This decomposition is to "The Decomposition andFactorization of BooleanExpressions"by R, Brayton andCurt McMullen and TEEE TSCAS 1982 (Institut) e It is carried out by of Electricaland E]ectro and the decomposition algorithm nic EngineersTnternational Symposium onCircuits and SystemsK Shown. This algorithm acts at a time at 1 logical group of a machine. This algorithm (from C, The and the pool type of each logical group's output vector serve as A hanger, and Basis decomposition of the feasible 1 Nut is carried out by cascode logic Tree net.) * This algorithm is sensitive to the height of a logic tree, excels, if it is 1llt The, is a thing make the request maximum height about a logic tree specify, and is in a user. In this Arco * rhythm, the internal objective function of 1 exists in itself, and it can find out the solution by the logic tree of the minimum number using the device of the minimum number in it. this algorithm -- attainment of the conversion mechanism of a signal level, I, or a late signal -- consideration Fang Fang1. -- although there is nothing, assignment of various levels in each water is performed, and the device of the minimum number can be attained. So, the solution of partial cascode logic is given by this algorithm. process this solution still more skillfully so that a Appropriate logic network carries out FItK attainment -- it is a thing. About the decomposed result, it is processing \ To still more skillfully at the optimization stage in the flow of a design. In this stage of a design, it is assumed that the result of decomposition is the solution optimal about the parameter taken into consideration in that stage. bringing the result of decomposition to the minimum based on this assumption -- it is the object of a design phase. The task performed in this stage to operation by a bipolar is completing description of DCC8 by connotation of the conversion mechanism of a required signal level. Big signal load is Look(ed), and by a register resource phi module, an emitter follower is divided into each logical group's main human power to a L SS D latch, and, in addition, it shines for it. The internal objective function of this algorithm is introducing with the Limit 15 minimum number which can do the conversion mechanism of the emitter follower level which carries out power consumption. In this algorithm, it is assumed that the full-main human power variable of a logical group's LS SD clutches can be used from an excessive emitter-follower-cost-less tail and any signal levels in any way. Assignment of the main human power level which needs conversion is made into the maximum by an algorithm, taking these conversion mechanisms into consideration, and conversion about an internal tree is made into the minimum. There is an advantage which carries out cascode logic by FET as if a required signal level converter can be omitted when real # Carrying out by a bipolar transistor. obtain a cascode current switch ('ccs) in Implementation, obtain an output in a certain level by a bipolar transistor, carry out level conversion to other levels, and drop off to them -- if it is Leave, there is nothing. i because, a bipolar transistor -- voltage Vbe between base emitters, and voltage Vbcf between base collectors -- right and left -- it is because it carries out. Since Carry out in FET does not have these restrictions, if threshold level vth is kept from almost participating in operation by pinch-off territory A pirate of a device, a drive logical level can be set up easily. And all the °' Mi 3 macro *' logic elements by which the cascode was carried out can be driven with the same logical level amplitude of vcc to earth potentials, and it can provide with each function output. use the device of the minimum number from the result of decomposition -- statistics are amended about assignment of the variable level of the optimal logic Following the tree. These statistics are used in order to assign the level of Quantity suitable about the variable of each logic Tree net. The simplified example is variable 8'. Assign signal level *4 * 20 About and variable *A' among the generating segment of 25 in the logical group who is optimizing. This suggests the following thing. That is, the objective function which carries out level assignment of variable *A * at signal level *4 * is suggested only for the influence of the minimum to Exertion-less - sake at the solution of the optimal tree obtained from decomposition. An algorithm is used and the following is tried. That is, in order to raise the physical design about wiring course specification from a conversion mechanism, it is solving carrying out level assignment of variable *A * in the five remaining trees at signal level *4'. This algorithm tries to expect a stage of a physical design of the Flow Lords of a design. have disadvantageous influence on Arrangement a -- it is related with performing a plurality of signal path specification from single Point source (point 5ource) and an emitter phi follower. [ like ] By this algorithm, the load (load) about a variable is processed by a similar method. The 2nd thing will be introduced into a solution supposing specific variable load exceeds the predetermined maximum from a single emitter follower. In an algorithm, it tries so that influence of wiring by 1 by if a variable is assigned to two different single levels and the stage of a physical design is expected again, without the ability to smell excessive The A cost at all to the demand of load may be made into the minimum. Try independently two different groups about a tree with two methods of emitter follower K Il relating as much as possible in an algorithm. By heuristics search, about the number of the variables in each tree which are common, namely, were shared, wooden independency is investigated and the following thing is concluded. That is, although the tree which is sharing many variables will approach extremely and it will be provided, the tree which has only a single variable in common is provided such, and are nothing and a thing. It tries to Point source will be turned to two different addresses and ease the demand of wiring by group part Kicking in an algorithm. While attaining conversion, in order not to increase the cost of an emitter follower, the only means which is doubted by use by this segment about optimization and which remains is in-line conversion. These conversion mechanisms are devices which are in agreement with the output terminal of the cascode logic tree which changes the wooden output signal level itself. These devices are technical rule To obey a master of Individual to them like wooden height and load (loading). Before these rules apply them, they are examined by the algorithm. In this segment of the flows of a design, the solution of the optimal bipolar cascode logic is provided to the problem of a machine level. at this time of the flow of a design, both solutions about the solution about FET and a bipolar should be optimized to the objective function of the machine which the user specified -- it is [ like ] ready. Since the conversion mechanism of a signal level is not required for the result of the decomposition which is related as for FETK, it is still remaining as it is. The cascode logical levels in the tree of single FET are completely drive Sari and To at the same signal amplitude. It is reflecting the emitter follower conversion mechanism of the minimum number, and it is thought with the point of making the result of the original decomposition into the minimum that the solution about a bipolar is the optimal. Take in the objective function of a machine in a designing method with a perfect comprehensive description of a machine. This objective function makes the following forms. That is, it is a set of dignity attachment by a numerical value which determines the priority for making the optimal the parameter of About number of a device required to carry out the parameter about the working speed of a machine, the parameter about electric power disappearance of a machine, and a design. Dignity attachment by these figures should be given as The and a constant by the simultaneous formula (simultaneous equation) of 1 Set expressed in the linear optimization model. the solution of the decomposition about the bipolar after conversion mechanism introduction -- the objective function of a machine -- directions -- it is used as the foundation for optimizing h To and also a parameter. It expresses the optimal solution about the number of devices, and unit electric power among six optimization parameters. However, it does not necessarily express the optimal fIc delay of main outputs. An optimization model is used when deciding the method of making each logical group's main outputs the optimal, in order to make a logical group's delay pattern uniform. It can set in the logic and the delay in the case of being the worst about Collecting books is decided by a delay algorithm. The delay in this case of being the worst is based on the delay type about that art, and the path in the worst case in that tree. The path in the worst case in a tree is a path in which the middle node of the maximum number exists on the cascode level of the maximum number. Delay in these cases of being the worst is carried out to a list about the copies bound together in one volume in a logical group. Logic Tree net of main outputs is united in between as a graph by the following algorithms. That is, it is a course specification algorithm whose delay ? determination the longest path does about each logic Tree net. in this algorithm, it can set to calculation of delay of main outputs -- Filtration -- the early or late arrangement of a signal and delay dependence of a cascode level are Feather(ed). These delay 1 and Up, a logical group's main output (a list should be used as delay of the path C related.) In this algorithm, consider that main outputs are the longest delay, and since [ still more nearly just / a logic condition ] it is reflected, unite logic Tree net of that logic tree in between. This just logic condition is a subset of the combination of all the possible pool variables. The combination of this pool variable is a thing actually do 1 and c generating of without logical inconsistency by fixed logic Tree net. They are the logic conditions which determine h The and single variable conditions as either truth or an imitation and which may occur simultaneously. this delay that became effective is already Sweeping(ed) as delay of main outputs -- it is compared with the surviving logical group's main output delay in order to decide whether 1 and it are still delay of the longest path. Supposing it is still the longest path too, it will complete and a logical group's suitable distance will consider that the delay is delay of the longest path. If it discovers that other main outputs already exceed expected delay, the processing will be continued until it asks just logic conditions about other main outputs and delay of the longest path is discovered. It is an example by discovering the longest path of just main outputs for this order to Drawing 8. The notation of Drawing 8 is delay when the bottom is just in delay when the upper part is the worst. When it is collectively made into a table, they are as follows and To be. Namely, path Delay Just delay ABDE 12 .... >9 .. ADE 10 -- < ............. At this time of the flow of a design, the ACE 8 logical group has completely characterized about the calculation about a device and unit electric power, and delay distribution of main outputs. It is the object in this time to carry out delay of main outputs to uniform distribution with a boundary distribution law by a certain specific standard. the optimization model about cost -- directions Fang Fang 1. Filtration -- like, by level assignment of a variable, and electric power setup in a logic tree, delay of the longest path is changed so that the standard of this formation of - stock may be suited. According to the relevant cost of the parameter which requires change as compared with an initial objective function, this interactive change will be changed by the objective function of a machine. the end of this stage -- the machine model of a high level -- Emulate f To -- the design of the basic level made the optimal was expressed and it is [ processing ] further ready in Application '1-preparation to the point which a user examines. A machine diagram as shown in Drawing 7 is updated by the delay about various logical groups' longest path, and receives an inquiry of clock generation. The quickest speed that can carry out the clock of the space-time-related logical group is decided by this algorithm. The specification of a clock is decided by this algorithm about the following. namely, a clock rate, the number of phases of a clock, and the relation (it C attaches and comes out.) between logic and a phase if the speed of a clock and the requirements for a phase are determined -- algorithm The -- end in the definition of * black box * of a clock generation machine (essentially LSSD clock ring), and the side angle of the logic of clock generation should be carried out to fundamental logic. Extension of the perfect fundamental logic of a machine containing various ° "black box" elements is encoding-ized with logic description language. In order for this level of a design to serve as the foundation over the reasonableness test of fundamental logic and to realize a physical design, it is processed further. Verification of logic is performed by inspecting the design of a fundamental level to comprehensive logic Map of a high level. It is located between 1st step 11 Up of verification, a logical group's machine diagram, and the machine structure of a high level model. Various comprehensive logic Map elements perform this verification by constituting a logical group's machine diagram from machine structure of a high level model. It is determination Sari and To that related example Draw and both machine diagrams express the same composition to that by which each logical group is equivalent to comprehensive logic Map of a high level of that by an algorithm. The next stage of verification is guaranteeing comprehensive logic Map of a high level being completely Map(ed) about the fundamental level. This h is performed by clarifying the pool type of an output about each logical group's main outputs, and comparing That t with the output vector of comprehensive logic Map. Emulate- 1- This pool type is designed to carry out output vector -. Measuring this logical group's main outputs with the output vector of comprehensive logic Map is shown in Drawing 9 and the next table H. The relation between an input and an output is shown in Table H. Namely, FAW Table ■ Input Output A B CFOFI F2 Q:ABC+AB, C-1-ABCoo, and 01210DOl 110 1 010 110 1 011 001 [] 100 100 0 101 001 0 110 001 0 1 1 1020 1 Re from Drawing 9, or To -- the output pool type about the copies bound together in one volume which contribute to the formula of main outputs is clarified by the algorithm like -- i -- a finale formula should be drawn and drop off -- if it is Leave, there is nothing. it should be connected with the thing equivalent to that comprehensive logic Map by this algorithm, connection between the output vector of comprehensive logic Map and a logical group's main outputs should further be solved, and each logical group needs to drop off by it -- if it is Leave, there is nothing. Drawing 9 and the example which was shown as for table INK -- main output [ of a logical group ] *Q -- " -- it is related with comparison with clarification, and it and output vector *F1' of comprehensive ic logic Map. As a result of this stage of verification of logic, fundamental logic will be known and an imitation quantity level model will be reflected correctly. This verification connected with the extended time analysis of the optimization stage constitutes the design of a fundamental level. a user needs to Shaving this design or leave it to the physical design in the acceptance 1-Filtration case -- things should be made. The stage of a physical design is started from the mask file of B D L S (language which carries out interconnection of the Ba2.5 lCDes-ignLanguage 5tructure-logical block). This BDLS mask file should be obtained from description by which the verified fundamental logic was coded. The same BDLS master file as this should be used again in a LSSD rule and the TPG (Test Pattern Generation) stage of the flows of a design. Accumulating, it expresses the LS SD latch which makes the form of this macro element given a definition. these macro elements should be extended to the level of the micro block about front IC1 That h et al. which progresses to the arrangement stage of a physical design, and should drop off -- if it is Leave, there is nothing. This extended B D L S is also set and used by logic audit from the physical inspection about the final design. In order to interface with the Sinking arrangement stage of a design, change into the mask file (M L L) of extended B D L S The and logic. Arrangement is based on the hierarchy method. By this hierarchy method, the arrangement problem of a machine level to the micro block of cascode logic, the device of a differential pair, a load device, a current-sinking device, etc. is solved. S by which the task of arrangement was published in 5cience flume 5 magazine tc June, 1983, Kirkpatrick. Doing:l Carry out by the routine shown in the paper it is [ C, D, germanium1att, Jr, N, P, and "Optimization by SimulatedAnnealing'" of Vecchi work ] entitled. notional -- arrangement -- the algorithm of One °C and The -- a M L L file -- The -- be shown -- if I will find out the physical arrangement optimal about the micro block of cascode logic, it will try. The following arrangement is obtained by this. namely, -- the position of each micro block is optimized by Yo 5 which makes the problem of the next wiring the minimum -- t -- it is that of straw matting. cascode logic tree 1- restrictions of an element which affects a wiring stage are not received any longer. the -- the [A / 10 / figure thru/or ] -- pass the stage of a false tree from a logical group's machine diagram to be shown inC [ 10 ] figure -- hierarchical Lead out of the arrangement to the cascode logic micro block of the actual condition is carried out. An algorithm of arrangement is the Monte Carlo algorithm. so, raise the efficiency -- a thick advantage is produced from a point by reducing the number of target and seeding arrangement. The stage of of seed beginning is based on being able to set in a machine diagram and solving the relative arrangement about a Each logic group (the 10A refer to LGl of a figure thru/or LG9). the -- the [A / 10 / figure thru/or ] --C [ 10 ] figure expresses the hierarchical approach which carries out an opposite to final arrangement of the micro block which makes the following composition. That is, it is the composition which completely operates application of differential cascode current switch art physically on a chip level, and uses back side Kicking and a master slice concept. the -- some logical groups LG1 thru/or LG9 of a machine show inA [ 10 ] figure, and it comes out to it. These logical groups are stationed to the perfect mask slice logic array second. Each logical group is dimensionally connected with the demand of the fundamental logic of that by the number of wooden and the number of micro blocks which it contains. A chip image is determined as either a logical group's component demand field or a field like BAl thru/or BA4 of the 10th the A figure which does not clarify. The objects fewer than The 100 must be processed in this stage by such arrangement, and it is Fast (determination of arrangement should be made.) comparatively. The next of this stage of arrangement is the stage of opting for wooden arrangement. A logical group's false boundary is essentially replaced on the false boundary of a cascode tree. The set (the 70A refer to TS'l of a figure thru/or TS9) of a cascode tree is disassembled into a plurality of cascode trees (the 10B TS2- of a figure refer to T1 and TS2-T2 grade). Now, in the algorithm of arrangement, try to determine arrangement of This which constitutes a logical group, and the cascode tree of h and others. wooden arrangement -- between [ rc ] a logical group's arrangement stages -- it is determined relatively as follows. that is, in the space which gave a certain boundary, the resolution of all the images comes out of When so that the resolution which is not good may further be produced. This stage of arrangement is the object (it is the point of being related and carried out comparatively quickly.) with few algorithms than 1500 again. according to a final arrangement stage, the false boundary of a cascode tree should be removed and determine the final arrangement about a wooden micro block element with an algorithm -- it needs -- Into -- . A plurality of cascode trees (the 10B refer to TS2-TI [ of a figure ] and TS2~T2 grade) should be disassembled to the level (the 10C TS2-T2-/MB of a figure 1 and TS2-T2-/MB refer to the 2nd grade) of a micro block. Robust as which Arrangement covering of a micro block is again determined in this stage within the comparatively small space which gave the boundary -- many (the algorithm which processes the object is required.) Clearly, although this is an arrangement stage which takes time most, it produces arrangement of the final micro block which applies the algorithm about wiring. The algorithm about wiring used for wiring arrangement of this micro block is an improved Lee algorithm. A Lee algorithm is +An algorithm for PathConnections and Tts Applications. September [ I RE Trans on ElectronicsComputers and ] 196 top PP. It is shown in 346-365. "TheInterconnection Problem -ATutorial"by DavidW, Hightowerof, :Be1l Te1ephone Laboratories. Inc, published in Proceedings. 10 th Design Automation"Workshop. Please refer to June 1973. This algorithm is a mage runner Arco * rhythm which has 'rip-up/lay-down' capability. 'rip-up/Iay-down' capability should identify a blocking network, should remove the network, and should wire the network which went wrong before, and change it -- it comprises accumulating and wiring the network of It is picking It was excluded origin again. avoid the 'rip-up/lay-down' loop in this algorithm by assigning the channel ownership about the wiring which carried out interconnection newly -- preparation fK-t Filtration. while wiring arrangement of a micro block, the following thing should be found out by the algorithm in the field where the demand of wiring is high -- it is possible. that is, LST (Logic 5ervice Terminal) by which course specification of wiring is tried from algorithm The should be completely blocked by the 'owned' channel -- they are things. it is such a case -- the network which went wrong is constituted. At this time, execution is stopped by the program about wiring and the algorithm of arrangement is called back. A chip image is classified into rectangle 1 which has a boundary by the algorithm of arrangement, and the trial which can set on the path of the minimal spanning tree (minimum spanning tree) about the network which went wrong, and identifies Area is conducted. Next, being able to set on the path of a minimal spanning tree and re-classifying a micro block within a Filtration territory by the algorithm of arrangement, is performed. '' with this specific re-classification (it is planned to annealing 5chedule' and continues to that end.) This algorithm minces a boundary of a field in a stage of a chip image and When. A wiring requirement of origin crossed to these boundaries will be improved by this algorithm, and confusion (congestion) which produces a network which went wrong will be conquered. After ending in re-classification, this new arrangement is given to the program about wiring. It includes wiring again the network affected by re-classification in the program of although wiring is continued by the program about this wiring. This processing is continued until it will be conquered in all the networks which went wrong, and arrangement is wired completely. And a design is audited about the next. That is, it is about whether food about and it which are not against technical essential principles about whether the physical design and the logic design correspond correspond with the TPG file. A design can be submitted to a manufacture direction as a result of these audits. The flow of the design of the machine by a user's prospect was modeling and simulating a machine to a satisfactory thing on a high level. The design of a machine is moved from it to modification of cascode logic. A user examines carrying out logic of a fundamental level by a bipolar and FET, and designs still the more nearly optimal by choosing art, or puts it into a physical design. At last, this procedure will also describe software about the design of desired hardware, and commits it as an input to actual physical manufacture. By such a designing method, the case where it is the design with a designer of a machine able to, do System Foundation of the target product on the whole is expressed. Development Seikuru of a machine should further be reduced by even range which gives a role person a new opportunity to actually opt for the design of the optimal machine with such a designing method. The mask slice designed to use an above-mentioned Forming concept and cascode logic art is formally shown in Drawing 11. In mask slice 1, it is a device arrangement field (there is 3-.) of two general-purpose field, i.e., input-and-output adjacent spaces 2, and DCC8 logic, FCC8 logic, or DCVS logic. this device arrangement field -- the brick wall set of activity devices, such as a bipolar, l and run District, or FET, and the passive device of a current source - it is. These devices are arranged in Boundary exemplified device portion 6 by electric power bus 5. Portion 4 enclosed with a dotted line is a device portion in a device arrangement field. A part of this portion 4 is shown in Drawing 12. In the structure of a device portion, 5b of electric power portion 5a of vcc or vDD, the electric power portion of earth potentials, and the electric power portion of vc8 is Included-t Filtration. A device portion can be characterized as follows. That is, a line is made and it is provided, and activity device 65 of a current source brings close to electric power bus 5b most, and is arranged. The device arrangement provided in these devices at interval of the Continue minimum comprises logic device 66 arranged five lines to the column direction on the line of a current source. Following these logic devices, output resistance object Filtration 7 approaches electric power portion 5a, and is provided. the wiring channel which carries out interconnection of the device to Drawing 12 -- being based -- channel 38 of a lengthwise direction, and channel 39 of a transverse direction -- Show and ing. These channels are used, in order to carry out interconnection of the activity device and passive device of device arrangement and to attain a logic function. A physical design is attained to this logic device arrangement field used widely by arranging and carrying out interconnection of DCC3, FCC8, or the fundamental micro block of DCVS. About one example of such a micro block, it is an example in reference number 45 in Drawing 16. It is shown with the wiring channel which micro block 45 The, lengthwise direction 68, and transverse direction 39 can use. These 1 wiring channels are used for carrying out interconnection to such other micro blocks, and make the physical interconnection of logic products completed. The rectangle shape of 1 Set which expresses the contact opening of an actual mask level required for par Sonarization of the composition device to micro block 45 of Drawing 73 is shown. the example which applies a micro block to a physical image -- the -- the [A / 14 / figure and ] -- it shows and comes out toB [ 14 ] figure. the -- having applied micro block 37a of the passive device to the foundations and A] mage of the mask slice expressed with reference number 37 toA [ 14 ] figure -- it is Indicated. Micro block 37a of the device is provided in a part of basic image 37, and a perpendicular device structure is completed. in order to already do phase 1i connection of this device with other devices of a logic network (C -- the required contact opening is formed.) the -- it shows and comes out toA [ 14 ] figure to have applied micro block 45 of logic to the basic image of the mask slice denoted by Reference number 6. the -- it shows and comes out toB [ 14 ] figure to have applied micro block 35a of the current source to the basic image of the mask slice denoted by reference number 35 other than application of logic micro block 45. It is an example in Drawing 15 about the concept of this mask slice design that used dregs =+-Do logic on the level of the most subdivided micro block. In Drawing 15, Ripple carry adding machine 50 of 4 A bit is an example. This adding machine 50 is logically described by the level of the micro block. Description of a micro block is used in order to confirm the suitable arrangement about each micro block. By this suitable arrangement, each micro block is the solution to a circuit (it becomes dignity attachment To about the influence which it has on the various micro blocks of the others to attach, and the influence which other micro blocks have on that micro block.). The idea is deriving the free passage of wiring between devices which is needed based on the correlation of One 4i for all the micro Brotchimitsu that constitute a solution. By use of a mask slice, real time and on the whole, individual arrangement of each micro block required for a logic function can be caught, and can be derived the optimal. Drawing 15 shows the flexibility of this design about cascode current switch trees 51 and 52. Cascode current switch tree 51 is the same as cascode current switch tree 52 about a logic function. however, Cause and Led of these trees -- there is a he Physics design as if the design is taken into consideration in order [ which is completely required as different Huyo ] to carry out, to catch copies bound together in one volume real time and to consider them, for example. This has illustrated the following thing. That is, it is applicable [ taking the overall relation and the specific relation between each micro block and other the micro blocks of all the into consideration ] to performing optimal arrangement about each micro block in a mask slice.

[Brief Description of the Drawings]

the -- the [ the flowchart in whichA / 1 / figure manufactures the mask slice of a bipolar, l, and run District, and ] --B [ 1 ] figure, The flowchart and Drawing 2 which manufacture the mask slice of FET, The flowchart and Drawing 3 which carry out bar tuna Rise of the mask slice at the target product, the [ the figure showing the differential cascode current switch logic tree of six levels, and ] --A [ 4 ] figure, the [ the figure which the cascode logic tree of All right. 6 level shows to CMO3FET art example 2, and ] --B [ 4 ] figure, Casco 1" of six levels by NMO8FET art -- the [ the figure showing the example of argument W and a tree, and ] -- the [A / 5 / figure and ] --B [ 5 ] figure, the [ Drawing 3 and ] -- the [A / 4 / figure and ] -- the [ the figure showing the cascode logic tree ofB / 4 / figure, and ] -- the [A / 6 / figure and ] --B [ 6 ] figure, The flow chart and Drawing 7 showing the method according to cascode logic stage, The logic circuit figure of the digital machine constituted from a logical group, and Drawing 8, The figure and Drawing 9 showing the determination of the longest path in a logical group, the [ the figure showing comparison with a logical group's main outputs and the output vector of comprehensive logic Map, and ] -- the [A / 10 / figure thru/or ] --C [ 10 ] figure, The figure showing the hierarchical arrangement approach which begins from a very high machine level and results in arrangement of a micro block through a middle stage, and Drawing 11 are a figure showing a mask slice, and Drawing 12, The figure and 13th [ The ] figure 1 which show one portion of a mask slice on a device level, the [ the figure showing a micro block and wiring channel of a mask slice, and ] -- the [A / 14 / figure and ] --B [ 14 ] figure, The figures and Drawings 15 showing the example of application to the A standard image of a micro block are arrangement and a figure showing the example of the micro block by which interconnection was carried out, as the Ripple carry adding machine of 4 A bit is formed. 1 .... mask slice, 2 .... input-and-output adjacent spaces, 3 .... device arrangement field, 36 .... logic debarras Brick Maor of a chair. Applicant International business Mannos corporation representative Patent attorney hill 1 Tsuguo (Besides one person) l1'B figure Drawing 3 ND 01 11 100 * Electricity The 6A.I. Artificial Intelligence71 the 61st -- 's+' -- again 5 Drawing 18 mRow] -- "-- one -] A page [ 1st ] continuation Claim-of-priority @ June27, 1983 ■ U.S. (US1 offing 508451) A * and 1983 year 6 month 27B (offing U.S. (US, the 4686th Ming person nandu Giorgio Too United States of America Florida state Bon radon Northwest from yard"508440 Precipitation and H Kant coat))