Virtual phase charge transfer device

[Detailed Description of the Invention]

Although the present invention is generally a thing about a semiconductor electric charge transmission device, In particular, a reversal layer is contained on some semiconductor surfaces of each cell, It is related with the embedding channel type single phase electric charge joint device (CCD) which protected the cell field from potential change of gate guidance by the work as a virtual electrode (VirtualelectrOde: a virtual electrode or an effective electrode) of the reversal layer. recent-years and single phase CCD -- a well-known thing and It was since an intermediary. For example, single phase CCD which provided the continuous conductor gate layer on the signal channel of CCD is indicated by U.S. Pat. No. 4047215 given to the Robert Charles fly (RObertCharlesFrye) etc. This single phase CCD is CCD to which the signal charge packet moved the surface channel device, i.e., the semiconductor surface. Compared with usual multi-phase CCD, single phase CCD of these common knowledge has small signal-processing capability, and serves as a fault it is [ the clock pulse of large amplitude ] comparatively required it, and Doggy in it. Embedding channel type CCD was added as a kind of an electric charge transmission device recently. In embedding channel type CCD, accumulation and transmission of a movable electric charge are performed in the guidance channel in a semiconductor thin layer. Although the trapping effect usually arises in the interface between an oxide and silicon at general surface migration type CCD, since this trapping effect can be prevented, electric charge transmission efficiency improves by embedding channel type CCD. Since career dispersion in an interface is lost, electric charge transmission efficiency is also improved. As a result, operation on frequency higher than before becomes realizable. It is IEEETransactiOnsOnElectrOnDevices magazine VOl.ED.2l. of the July, 1974 issue in detail, Hamdi Elsiz published on 437~447 pages of black 7 (HamdiEl-Sissi) others -- it is explained to the paper "one-dimensional consideration of embedding channel type CCD" (0neDimensi0na1Stu Ya 0fBuriedChann1e1ChargeC0up1edDevices). Embedded channel type single phase CCD is indicated by U.S. Pat. No. 4065847. The advantage of single level structure is employed efficiently extensively, and the object of the present invention is to provide single phase embedding channel type CCD which is equal to multi-phase CCD in a performance side. The present invention provides the single phase CCD structure where it was continuous or provided the single conductor layer of pattern formation on the multiplex cell type signal channel. Each cell contained in a multiplex cell type signal channel has four fields, i.e., the 1st transmission field 1, the 1st accumulation field, the 2nd transmission field, and the 2nd accumulation field, and it is in these fields, Placing or diffusion of impurities is performed from the semiconductor surface to the suitable depth, and the impurity distribution of each field is different intermediary To have, respectively. The 2nd phase parts in which the 1st phase parts that receive an electrical change with an electric charge transmission signal do not receive an electrical change substantially with an electric charge transmission signal including the 1st transmission field 1 and the 1st accumulation field include the 2nd transmission field and the 2nd accumulation field. Each generating maximum potential in a field at the time of a gate-on state and a gate-off state is determined by impurity distribution peculiar to each field. A reversal layer is contained in the semiconductor surface of field , of each cell, and a cell portion is protected by this reversal layer from the potential change by gate guidance. By impressing a clock signal to a gate, the potential maximum of field 1, is repetitively gone up and down on the basis of the fixed potential maximum of field. And since the potential maximum of a field is higher than field 1 in both gate states and the field is maintained at high potential from the field, the directivity of charge transfer is acquired. This CCD is further provided with the uniform insulating layer stuck between the semiconductor surface and a single phase electrode. The structure for outputting and inputting a signal besides the device for supplying single phase The d Tsukubarusu to an electrode is also established. The present invention provides again the CCD manufacture process of including the ion placing stage of 4 continuation. Speaking concretely, this manufacture process's beginning from the stage which drives in the first donor impurities alternatively into the oxide layer which covers N type channel in the P conduction type silicon mother's body, and setting it in this stage, Since the impurity distribution state of the field of each cell is fixed, the 1st source of impurities supply used in a succession stage is obtained. Next, pattern formation of the impurities mixing polysilicon gate electrode is carried out on the oxide layer which covers the channel field portion in which field 1, of each cell should be formed. This polysilicon is used as a mask for removing the oxide on the channel field which should turn into a field of each cell. Then, the photoresist pattern which covers a field is formed and new donor impurities are driven into the field of each cell part. A photoresist is removed after that and donor ion is again driven into a cell field. And further, in order to perform recovery of placing damage and impurity diffusion from an oxide to a field, in order to make a field and impurity diffusion inside deep, heat treatment is performed. Finally, it is shallower than front donor depth, an acceptor impurity is driven into a field and inside, and formation of the necessary impurity distribution in each cell is completed now. In an alternative CCD manufacture process, two donor ion placing or donor ion diffusion, and two Acceptor ion placing or Acceptor ion diffusion following it is performed. Since it is not necessary to correct the object of the present invention, the impurity distribution of the field of each cell is determined by the impurities addition to an embedding channel. Unlike the pattern gate of the above-mentioned example, a continuation type gate electrode is provided in this example. The perpendicular section is shown in Drawing 1 to one section which carried out the present invention and section of the direction of a channel of monolayer CCD structure. Although the CCD channel shall be formed into P type silicon substrate 11 and the doping density of substrate 11 shall far exceed 1x1015 Brazing tau 3, the optimum range of this doping density is 1x1015CfL-3~1X1018c1rL-3. As the upper surface of substrate 11 is shown in Drawing 1, it is covered with the longitudinal direction of N type channel field by insulating layer 12 of He stretched out. uniform film thickness, and the quality of the material of this insulating layer 12 is usually 2 oxidization silicon. As for an intermediary cage and this electrode 13, Wide is connected to a Gradually continuation target for gate electrode 13 in the source of a clock pulse at the longitudinal direction of a channel. A plurality of cells are extended to the longitudinal direction of the channel in the state where it separated into Mutually, and P type reversal layer 14 is contained in the surface of field , of each cell. P type reversal layer 14 works as a virtual electrode with a shielding effect for the above-mentioned field of each cell not to receive the potential change by gate guidance. In just under a reversal layer, the potential upper limit of a field and an inner embedding channel is determined by alternative placing donors 15 and 16. Field 1, is further contained in each cell, and potential upper limit is determined as it by gate potential, an impurities mixing state, and placing donor 17 in these fields. Each cell is characterized as mentioned above by two potential upper limit which is subject to the influence of gate potential, and two potential upper limit and a total of four potential upper limit which are not subject to the influence of gate potential. With the composition of Drawing 1, the input edge structure (not shown) which has N+ field of ohmic contact structure in a channel field is included further, and a voltage signal is inputted from there. A floating N+ field is located below [ a part of ] the gate conductor of the 1st cell of this CCD structure, and this N+ field is separated into them from the above-mentioned input edge N+ field. On the insulating layer which covers each part top of these both N+ field, the conductor electrode for inputting a sampling pulse is provided. To this electrode, a sampling pulse is supplied for every ON period of a clock pulse train, and a floating N+ field is charged. And the potential of a floating N+ field goes up even on the level decided by amplitude of the signal voltage impressed to an input edge N+ field. On the other hand, during the OFF of a clock pulse train, an electric charge moves as a minority carrier packet, and flows into a field from the floating N+ field in the embedding channel under the conductor electrode of the 1st cell. This charge packet and each following charge packet are sent in the direction of a channel outgoing end by impression of the clock pulse train to a gate electrode. One pair of N+ fields divided into Mutually are included in outgoing end structure (not shown), and 1st N+ field is covered with the conductor electrode of the tail end cell of a CCD channel. Intermediary There are heavy on both N+ field in this electrode in which the electrode on an insulating layer is extended among these N+ fields. 2nd N+ field has an ohmic contact part so that reference voltage may be impressed, 1st N+ field has the ohmic contact part connected to the gate of insulating gate FET connected to load resistance within source follower composition, and the output signal of CCD is taken from the ohmic contact part. The above-mentioned input-and-output structure is indicated to Then and U.S. Pat. No. 4047215 in the example quoted as a mere explanation means. Within the limits of the present invention, it is possible to adopt, other input edge structures and outgoing end structures, for example, a floating gate. p+ type channel stop field 18 which demarcates one side of the width side interface of an electric charge transmission field is shown in the section of Drawing 1 perpendicularly extended to the channel. The width side interface of channel another side is demarcated by another p+ type channel stop field (not shown). And each cell of the channel is provided with p+ type reversal layer 14 for covering so that an electric charge transmission field may not receive the new potential change by gate guidance. It is also possible to replace one channel stop field by blooming control structure. Drawing 2 is the graph which expressed the potential state about each of four embedding channel fields in each cell on the given gate potential conditions as a function of the distance from the surface of the semiconductor mother's body. If these graphs are referred to, he can understand the method of transmission of the charge packet to other cells [ cell / a certain ]. the --a [ 2 ] figure is a graph which shows the potential state of field 1, in a gate-off state (positive or slightly negative state). These graphs are obtained, when placing diffusion of phosphorus is performed for example, to both field 1, and also arsenic is shallowly driven only into a field. the --b [ 2 ] figure is a graph which shows the potential state of field , in a gate-off state. the --c [ 2 ] figure is a graph which shows the potential state of field 1, in a gate-on state. The and a 2d figure are graphs which show the potential state of field , in a gate-on state. the potential state of field , performs a little phosphorus placing to a field -- a lot of phosphorus placing to a field -- a Line intermediary -- they are diffused, and it is obtained when an equivalent amount of boron is further driven into both fields shallowly. the --a [ 3 ] figure is an impurity density distribution graph of field 1. In this case, although phosphorus doping is an equivalent amount to both fields, arsenic doping is performed only to the field. the --b [ 3 ] figure is an impurity density distribution graph of field. In this case, although boron doping is an equivalent amount to both fields, to the field, a lot of phosphorus doping is performed alternatively. And the amount of phosphorus doping which receives field 1 is little compared with a field. If Drawing 2 is referred to, it will be thought that the following relation exists in a gate-off state. On the other hand, the following relation exists in a gate-on state. ) Electric charge transmission is performed, when gate voltage falls to an ON state from an OFF state and rises in the OFF state again. In order to explain this, the charge packet accumulated in a field is considered. In one of intermediary To have with highest phiMax of this field, electronic charge is shut up in this field. When gate voltage carries out a Okay. fall and goes to an ON state, both phiMax and phiMaxI fall. However, since the maximum potential of field , is kept constant on the surface of the reversal layer, phiMax and phiMax are substantially eternal. Therefore, the hole which came out from the channel stop is immediately attracted by the channel surface, and is covered from a field and Is gate potential. At that time, since the potential of a field becomes the highest, a signal electric charge moves to this field. The hole layer of the small range which occupies the illustrated space is extended from a channel stop, and forms a virtual electrode. Such virtual electrode formation by a reverse polarity career and its signal electric charge transfer function are the greatest features of the present invention. If gate potential is again pulled up even in the OFF state, an electric charge will flow into the field of a succession cell. phiMax of each field is expressed by the stair-like pattern of the potential well by Drawing 4. in the case of a gate-off state, it is expressed by potential well pattern shown by a thick line, and the pattern makes a field the starting point -- right-hand side -- the bottom -- four steps of intermediary go potential pattern -- intermediary ing. It comes out and reaches the minimum level. On the other hand, in the case of a gate-on state, the bottom is gradually expressed by four steps of intermediary go pattern by making field 1 into the starting point to the direction of a field. Thus, charge packet transmission of the request to each succession neighboring cell is performed by impressing a train of impulses to a simple electrode. one example about the manufacture process of a present invention device -- the -- the [a / 5 / figure~] -- it is shown ine [ 5 ] figure. this process -- the -- P conduction type single crystal silicon wafer 41 of doping density 1x1015cr1L-3~5x1016?-3 as shown ina [ 5 ] figure is used first. In this wafer, beforehand, it embeds by N type doping and p+ channel stop field formation, a channel field is demarcated, and the input means and the output means are provided in the both ends of the channel. Next, oxidization gate layer 42 is grown up into desired thickness, for example, 1000 A, by the oxidizing method. And alternative placing of donor impurities, such as arsenic, phosphorus, antimony, is performed to a layer of oxides following the pattern formation of a layer of oxides. These placing impurities are diffused on the silicon surface in the below-mentioned process step. Next, a photoresist mask is removed from the surface and impurities mixing polysilicon layer 44 is provided on a layer of oxides. in order that this polysilicon layer may provide the opening for exposing a part of placing field and a part of field which prevented placing with mask 43 -- the -- it is formed in a pattern as shown inb [ 5 ] figure. The gate oxide in an opening is removed with a well-known etching method. Oxidation treatment of the silicon wafer then exposed newly is carried out, and, simultaneously with it, a layer of oxides is formed on impurities mixing polycrystalline silicon mask 44. Next, 2nd photoresist mask 45 that covers a part of each opening and the adjoining part of each oxidization polysilicon field is formed as shown in the 5thd figure. At this time, new donor impurities are driven in into a silicon channel through a layer of oxides. and -- photoresist 45 is removed -- the -- as shown ine [ 5 ] figure, again new donor impurities are driven into a silicon channel through an oxide. All the donor-impurities placing processings required for CCD manufacture at this are completed. eye after that -- a heat treatment process -- set, placing impurities are spread to the depth suitable in silicon, and the right potential part blanket-like voice is formed, and the impurities in an oxide are diffused in silicon. Next, acceptor impurities, such as boron, gallium, and indium, are driven in in a silicon channel through an oxide from the same opening. After this placing process, it is devoted with recovery of placing damage and heat treatment is performed for the object of activation of impurities. The manufacture process for acquiring impurity distribution above required for formation of the right potential part blanket-like voice is completed. Finally impurities mixing polysilicon pattern 44 which works as a gate electrode is provided with a contact portion, and CCD is completed. Another example about the manufacture process of a present invention device is shown in Drawing 6. In this example process, single crystal P type silicon wafer 51 as shown in Drawing 6 with the same resistivity as the thing of the above-mentioned example process of It was is used. The N type embedding channel beforehand demarcated in p+ channel stop field is contained in this wafer 51, and a fundamental input-and-output end structure by conventional technology is further included in it. However, these may be added after the manufacture process of the present invention is completed. First, growth formation of the layer of oxides 52 about 800 A thick is carried out by thermal oxidation processing, for example. Continuing (- The and nitriding silicon layer 53 about 400 A thick are formed on a layer of oxides.) Next, the 2nd layer of oxides 54 about 3000 A thick is provided, and pattern formation of this layer of oxides is carried out so that selection exposure of the channel portion which should become a field may be carried out. Then, donor impurities are driven in through an exposure nitriding layer and the layer of oxides under it with suitable energy so that it may rush into the silicon surface. the [ next, ] -- as shown inb [ 6 ] figure, photoresist mask 55 is demarcated on the apex part of the structure which covers the contiguity portion of the oxidization mask by which pattern formation was carried out to the part of each opening. Next, 2nd donor-impurities placing is performed with suitable energy, and impurities penetrate an insulating layer and rush into the silicon surface. And a photoresist is removed, it is devoted by thermal diffusion processing, and impurities enter deeply inside a semiconductor. Then, placing of Acceptor ion is performed, using again the oxide mask of the 6th the c figure by which pattern formation was carried out previously. Next, in order to make the 2nd photoresist mask of the substantially same pattern as the above-mentioned photoresist mask, pattern formation of the new photoresist layer is carried out. The oxide mask demarcated previously is re-demarcated by removing a part of each division by selective etching, and the portion of nitriding layer 53 which covers field 1 of each cell shown in the 6thd figure by that cause is newly exposed. Then, the 2nd photoresist layer is removed, then 2nd acceptor impurity placing is performed on a suitable energy level, and the placing impurities penetrate a nitriding layer and the layer of oxides under it, and rush into field 1 and the silicon surface of. Then, heat treatment for impurities activation is performed and impurity distribution formation required in order to acquire the proper potential distribution within each cell structure is completed. the oxide layer and nitriding Material layer by which pattern formation was carried out are removed -- there -- continuation conductor layers 56, such as aluminum or tin oxide, -- the -- it is formed as shown ine [ 6 ] figure, and this layer serves as a single phase clock electrode. the impurity distribution figure of Drawing 3 -- the -- the impurity distribution state of the structure shown ine [ 5 ] figure is expressed. By the impurity distribution acquired from the process given in Drawing 6, potential distribution substantially equal to Drawing 2 is acquired, and suitable DC gate offset voltage arises. Drawing 7 expresses the maximum potential of each field of a cell as a function of gate voltage. When the performance of this CCD is evaluated, the curve of Drawing 7 shows it being smaller than the case where voltage amplitude required in order to move a signal charge packet to a latter-part cell is conventional CCD, and ending. The maximum potential of field , is unrelated to clock voltage, and, on the other hand, the potential of field 1, changes periodically. When gate voltage shifts and goes in the minus direction, the electric charge accumulated in the field in the state of gate-off is maintained by the state as it is until the maximum potential of a field turns into below the potential of a field, and the accumulation electric charge of a field moves to a field after that. And since the potential of a field is always higher than the maximum potential of a field, the electric charge which moved to the field moves to a field immediately. The electric charge moves to the field of a next step cell, when a gate converts into an OFF state, and the same operation is repeated henceforth. The above-mentioned CCD manufacturing method example does not limit the range of the present invention, and has described it as a suitable example for manufacturing CCD of the present invention. Probably, it will be clear to make each polarity reverse, when manufacturing CCD of P type channel by making N type silicon substrate into basic material. It is also possible to use the compound semiconductor containing V, such as antimony-ized indium and tellurium-ized mercury cadmium Nium, and - compound. A CCD imaging device with which the electric charge transmission device of the present invention contains a total frame accumulation type and a line address type, Probably, it will be obvious to a person skilled in the art that it is useful although carried out to the storage device of an analog processor, a memory, a linear shift register and serial access composition and serial parallel serial access composition, or random access composition, etc. Blooming control structure is also built in in each above-mentioned example. the process of Drawing 5 -- therefore, the result of the example which manufactured the field CCD imaging device is shown below. The chip area was set to 73.1md (117000 square Mill), and the array size was 245x338 pixels (pixel). The energy and the dose which were used for impurities placing are as follows. The characteristic acquired from the imaging device manufactured on condition of above is as follows. Potential well capacity (the number of electrons) 254000 pieces

[Brief Description of the Drawings]

Drawing 1 is an expanded sectional view showing the channel field of the CCD structure by the present invention by vertical section and a vertical section, the -- the graph which shows each potential distribution of four fields in each cell [ in / in thea / 2 / figure~2ndd figure / a gate-off state and a gate-on state ], the -- the [a / 3 / figure~] -- the graphb [ 3 ] figure indicates each impurity density distribution of four fields in each cell of the device of Drawing 1 to be, the [ the figure showing the potential well relevant to operation of a present invention device in Drawing 4, and ] -- the [a / 5 / figure~] -- the figure in whiche [ 5 ] figure shows the manufacture process of the example device of the present invention, the -- the [a / 6 / figure~] -- the figure showing a device manufacture process with alternativee [ 6 ] figure and Drawing 7 are graphs which express the maximum potential of each field of a cell as a function of gate voltage. (Explanation of a reference mark), 11 ...... A semiconductor substrate, 14 ...... A reversal layer, 41, 51 ...... Semiconductor substrate.