Nova Patents
JPS58178564A

Thin film transistor

Abstract

PURPOSE:To obtain an FET in which source and drain are effectively connected to metal electrode with less leakage current and which uses a polysilicon thin film by setting the thickness of the polysilicon of the domain formed with a channel to specific value or less. CONSTITUTION:A pattern of polysilicon 302 of the prescribed thickness is formed on an insulating substrate 301, only channel domain is etched to 2,500Angstrom or less, a recess 300 is formed, and a gate oxidized film 303 is covered. Then, a gate electrode 304 of polysilicon is formed as a mask, and N type source and drain 506 are formed by ion implantation. After an interlayer insulating film 307 is formed, a window 308 is opened, aluminum 309 is deposited to form wirings. According to this structure, the only channel forming part is reduced in thickness, wiring metal does not pass through the polysilicon layer, thereby effectively connecting and reducing a leakage current.

JPS58178564A, drawing sheet 1
Sheet 1 of 2

Term

Term ended

Projected expiry passed 13 April 2002, 24.4 years ago.

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  3. Projected expiry
  4. Today

2 claims: 2 independent, 0 dependent

  1. 1
    【特許請求の範囲】 +11 シリコン#膜を用い、ソース電惨とドレイン電極及びゲート電極を備えたIII膜トランジスタに於いて、チャンネルの形成される鎖酸のシリコン薄膜の膜厚が、ソース、ドレインの形成される憤域のシリコン薄膜の膜厚よVも小さいことを物書とする薄膜トランジスタ。
  2. 2
    (2) 篩i]Cシリコン薄膜として多結晶シリコンを用いたことを特徴とする特ff1t′iv求軛囲第1墳記載の博しトランジスタ。 (31チャンネルの形成される鎖酸のシリコン薄膜の膜厚がzsoo1以下であることを特徴とする特許請X範囲第1項紀載の薄膜トランジスタ。