Schottky gate field-effect transistor and its manufacture

[Detailed Description of the Invention]

the microwave signature of the present invention is good -- moreover -- manufacture -- :1 .. : -- it is related with an easy shot Kiguet field effect transistor. that to which the present invention is restricted in any way about material -- Then. (although it is applicable to large common semiconducting materials, such as a unit matter semiconductor or compound semiconductors, such as Si, taking the case of G a A s, it explains among the compound semiconductors which have an advantage with large working speed as a semiconducting material below.) General structure of the conventional shot Kiguet field effect transistor, After forming n type operation layer 12 of uniform thickness in the surface of half-insulation semiconductor substrates 11, such as GaAs, by epitaxial growth or ion implantation so that it may illustrate in the sectional view of Drawing 1, Sauce electrode 13, the Dorain electrode 14, and shot Kiguet electrode 15 are formed in the surface of this layer of operation by the method of making metal vapor-depositing etc. Such conventionally, in the shot Kiguet field effect transistor of structure, since resistance between gate sauce is strong, a good microwave signature is not acquired. Also in fast switching Dying, it is inferior. Therefore, To reduce and Technology should be called on for resistance between gate sauce. the thickness of layer 12' of gate direct F of operation which governs pinch-off voltage so that it may illustrate to Drawing 2, in order to solve such a problem -- a request value -- being still Do not keep it. -- layer 12 of operation near the sauce electrode -- " -- the structure which enlarges thickness is proposed. This structure forms each electrode 13.14 and 15 only for part 12' which should become directly under gate electrode 15 after thin < Si ts by etching etc., after forming the layer of the uniform thickness which is equivalent to the thickness directly under [ Dorain electrode 14 ] sauce Electricity 13 first of operation. However, in such a structure, since detailed Photolitho gruffy etc for electrode formation is not only difficult, but the layer surface of operation is not flat and very severe accuracy is required of etching control of a layer of operation, there is a fault to which the yield becomes low. In order to raise the Mana high frequency characteristic of MESFET, it is necessary to make gate length small as much as possible, therefore very detailed precision processing is required on element manufacture. However, when forming the pattern of gate electrode 15 in resist, in the conventional manufacturing method, the level difference by sauce electrode 13 and the Dorain electrode 14 very near the gate pattern, Since it existed in addition to the level difference of field 12 of operation, it was more difficult than the time in a flat face for the resolution of a photoresist pattern to fall and to form certainly the short gate pattern which is about 1 micrometer. Although alloy processing of sauce electrode 13 and the Dorain electrode 14 is performed and aiming at the fall of the contact resistance is generally especially performed by compound semiconductors, such as GaAs, before forming gate electrode 15, It is going to make contact resistance small enough, and if prolonged alloy processing is moreover performed, condensation of sauce and the Dorain electrode metal will start, and it is sufficient high temperature, is easy to produce a remarkable big level difference, and has become a cause by which this also worsens the resolution of the photoresist pattern for gates. It is necessary to form gate electrode 15 in the middle of sauce electrode 13 already formed and the Dorain electrode 14 with the accuracy of position of ±0.211 or less TrL. The interval of sauce electrode 13 and gate electrode 15, Since it is in the electrical property of 8m5FT' and 'I' and the parasitism resistance between sauce gates and parasitic capacitance are influenced directly, it is necessary to control the distance between two electrodes as small as possible and with high precision, and above-mentioned accuracy of position is needed also in respect of this inter electrode distance. However, forming such a fine pattern with high precision had the problem that the manufacture yield was remarkable and low, very difficult therefore in prior art. The present invention is made in view of the conventional problem mentioned above, and is k thing, and the place made into the object has a microwave signature and a yield in providing a good shot Kiguet field effect transistor. An example explains the details of the present invention below. Drawing 3 is a sectional view of the shot Kiguet field effect transistor of one example of the present invention, and, as for n type operation layer and 23, 21 is [ the Dorain electrode and 25 ] shot Kiguet electrodes half-insulation semiconductor substrates, such as GaAs, and 2 and 2 a sauce electrode and 24. 26 is an insulating film. the layer surface of operation of the field effect transistor of the present invention is flat so that it may illustrate to Drawing 8 -- and layer 22 of operation between sauce Dorain -- " -- they are ToL thicker than the number of careers of of operation layer 22' directly under a gate, and & structure about the number of careers per unit area and layer 22 of operation -- " -- the 22', gate electrode 25, and high impurity density layer 221, and sauce electrode 28 and the Dorain electrode 24 use what is called a self alignment method altogether formed based on the same insulating film pattern 26. For this reason, the physical relationship of each component of a field effect transistor is automatically determined with high precision mutually. According to the present invention from this, detailed processing has an advantage, such as becoming possible, at the same time a manufacturing process becomes simple and the yield improves. Drawing 4 is a sectional view showing an example of the manufacturing method of the field effect transistor of Drawing 3. As first shown in Drawing 4 (8), pattern 27 which consists of insulating materials is formed in the surface of half-insulation board 21 of Q a A s. The ion implantation of the 1st mass Kutoshi is performed for this pattern 27. '' -- in order that this pouring may 1- make resistance between gate sauce small -- high-dose quantity -- in order [ and ] to form A conductive layer in a deep position so that it may become small about gate parasitic capacitance -- big accelerating voltage -- energy -- and an injection rate -- 1. (ion implantation is performed in 11013 Dawes Active.) - As an example, it is St. 200 KeV was poured in and it formed by usual photograph ring Lafi and sputter etching, using the polyimide resin of the 1.5micro tiger in thickness as pattern 27 for masks. If pattern 27 for masks is Accomplish material and the role of the mask of ion implantation or thermal diffusion is alternatively removable to insulation $26, it will not be limited to polyimide of a right <example here. As shown in the back (C) figure of the ion implantation of the 1st time, insulating film 26' is formed all over a substrate. In this example, the SjOg film of thickness 3000A formed by a vacuum evaporation method was used. Insulating film 26' will be To satisfy about the element of the present invention, if it has tolerance in high temperature pro 7 A, such as Annealing. For this reason, it is nitriding silicon that it may be an outstanding material of the heat resistance which is not limited to oxidization silicon at all as a material, and does not produce a semiconductor and an unnecessary reaction at the temperature about 800 degreeC, either, Inorganic compound films, such as an aluminum oxide, a zirconium dioxide, oxidization titanium, and alumimium nitride, are also possible. About the forming method, if neither substrate 21 nor pattern 27 for masks is spoiled, arbitrary things, such as not only the vapor-depositing method but a CVD method, a plasma CVD method, the sputtering method, etc., are possible. Subsequently, pattern 27 for masks is removed with hydrazine or O1I gas plasma, and photoresist pattern 28 is formed newly. This is made into a mask and it is a figure (as shown in Q, insulating film 26' is punctured with CF4 gas plasma, and insulating film pattern 26 is formed.). The 2nd ion implantation is performed by using photoresist pattern 28 as a mask, and high concentration impurities layer 22'# is formed. There is nothing and, as for this ion implantation, it forms [ which makes electrode contact with a sauce electrode and the Dorain electrode, and a layer of operation low resistance ohmic nature ] a high concentration impurities layer near the surface of substrate 21. As ion implantation conditions for this, pouring energy 80 KeV and an injection-rate I X 10" Dawes layer were chosen as an example of -. It leaves insulating film pattern 26 after this, photoresist pattern 28 is removed, and another 7 Oto resist pattern 29 are formed for Yo shown in figure (C). 3rd pouring is performed as photoresist pattern 29 and an insulating film butter 726't-mask in this state. It is for this pouring forming of operation layer 22' of a field effect transistor, and the thickness and career concentration of this layer of operation are chosen as the value which a request pinch-off voltage all realizes. For example, in order to realize pinch-off voltage 0. IV, pouring energy 5 Q KeV and injection-rate 1.5X10" Dawes you (however, let the rate of activity be °100 A.) are chosen. Compared with the career total in of operation * layer 22' [ directly under ] of gate electrode 25, it is about 7 times larger, and the career total in of operation layer 22" of about 23 sauce electrode is [ the ] a sake so that clearly from the injection rate of ion implantation, The resistance between gate sauce falls to 1/at least 7 compared with the case where it is formed in of operation layer 22"1 appearance. on the other hand -- layer 22 of operation -- " -- pouring formation is deeply carried out by high accelerating voltage, and the career concentration near the surface of 22# has an effect which can make gate parasitic capacitance small enough a sufficiently low lack. . . It Annealing, after removing -729, 7 Otho, DiX"/', and, and the back activates an injection element. it touches mutually and forms -- having -- layers 22' and 22 of operation -- " -- it becomes a Ile layer of operation. Then, as shown in 4th [ The ] figure (A), insulating film pattern 26 is formed and sauce electrode 23 and the Dorain electrode 24 are formed. Finally, as shown in 4th [ The ] figure ■, gate electrode 25 is formed using the usual vapor deposition and ring Lafi art. As shown by figure (A), sauce electrode 23 and the Dorain electrode 24 have again structure which protruded gate electrode 25 rather than of operation layer 22' rather than high concentration impurities layer 221. The pattern which arises in the usual photolithography does not carry out position Fit of this, but it takes Re into consideration. In the present invention, it is this;1 qualitative factor for it to be reversed with pattern 27 for masks of the ion implantation of the 1st time ,, and to form & insulation film pattern 26. Therefore, a different formation method according to the forming method and material of insulating Wx26 is possible for insulating film pattern 26. Below, it is based on an example and explains. After the 1st pouring, a figure (photoresist pattern 28 is formed in the portion which is equivalent to a high concentration impurities layer as shown in q.) Insulating film pattern 26 can be obtained by what is called the lift turning-off method for forming insulating film 26' all over a substrate with publicly known art, such as a vacuum evaporation method, here, and removing photoresist pattern 28. At this example, it is thickness 8000A (1) by a vacuum evaporation method. The pattern of 8 ioz film was obtained. If only photoresist pattern 28 is dissolved with acetone, pattern 27 for masks which structure as shown in Drawing 0 was acquired, and was used for pouring which is the 1st time can be used as a pattern for masks for high concentration impurities layer formation as it is. The same thing as a pre-operation sequence was obtained through the process after time 0 after that. Since the window of oxidization silicon (Sin) film 26 is formed in the portion to which what should be specified here already makes a position the same correctly with of operation layer 22' in a previous process when forming gate electrode 25, As for me, gate electrode 25 hears that it is correctly formed in the same part with the portion of of operation layer 22', and layer 22 of operation does not have an overlap, the portion, i.e., the Schottky junction part, which contact a layer of operation and directly. For this reason, ■5FET which has the micro liquid characteristic that being accompanied by increase of unnecessary electric capacity so that it may explain in full detail behind loses and of having been prodigal is obtained. It is formed in the same position as high concentration impurities layer 22' of insulating film pattern 26 same also about Saw, the Sumi pole 28, and the Dorain electrode 24, and by what is called 7 Le Farra Immate, two electrodes can be formed and simplification of a manufacture process can be performed. Although the example which manufactures the field effect transistor of the structure illustrated to Drawing 3 above by ion implantation was explained, this can also be manufactured with a thermal diffusion method. namely, the thing for which the thick - dopant of a diffusing constant is first contacted to a substrate face, and thermal diffusion is performed -- layer 22 of Drawing 4 (8) of operation -- " -- a deep corresponding diffusion zone is formed. 1 [ next, ] which contacts small To 6 Dorbant of a diffusing constant in the part of the field directly under a gate by using pattern 26 for masks as a shelter, and performs thermal diffusion -- the shallow diffusion zone which is equivalent to of operation layer 22' of 4th [ The ] figure 0 by things may be formed, and, finally electrodes 28.24 and 25 may be formed according to the above-mentioned example. It is also possible to fulfill the above-mentioned conditions by selecting surface impurity density, diffusion temperature, and diffusion time using a rice cake theory and the same dopant. Although the /slot on the MFSFET becomes large and is so advantageous on the characteristic that the length of of operation layer 22' in Drawing 3 is short, It is only restricted by only the limit of the ultra-fine processing technology at the time of short-Nuclear(ing) this length short-Nuclear(ing) the length of mask 27 in the manufacturing method illustrated to Drawing 4, Generally, since it is easier than shortening the length of a gate metal, shortening this mask can create MBSFET with bigger /m than the conventional method. Although the case where GaAs was used as a semiconductor crystal was illustrated in the above example, arbitrary semiconductors, such as an InP and other ■-V fellows compound semiconductor and Si, can be used if needed. As explained to details above, the Si Tottoki gate field effect transistor of Honor 4 Ming is good. The number of careers of the layer of operation between A sauce is large, and since it is the structure where the layer of operation and gate electrode directly under a gate electrode are moreover formed in the same position, h is large, Gate reverse resisting pressure with a good high frequency characteristic with small gate parasitic capacitance can realize the good high and shot Kiguet field effect transistor of the yield at a process simpler than before.

[Brief Description of the Drawings]

In the sectional view of a conventional example, and Drawing 3, Drawing 1 and Drawing 2 are sectional views of one example of the present invention, Drawing 4 (6) 21 ~ (5) indicates an example of the manufacturing method of the field effect transistor of Drawing 3 to be ... Half-insulation semiconductor substrate, 22 ... a layer of operation and 22' ... the 1st portion of a layer of operation, and 22 -- " ... the 2nd portion of a layer of operation, 221 ... the 8th portion (high concentration impurities layer) of a layer of operation, 23 ... A '-A electrode, 24 ... Dorain electrode, 25 ... a gate electrode, 26 and a 1.:insulation film pattern, and 26'-zeta and insulating film 27 ... The pattern for masks, 28 ... Photoresist pattern representative Patent attorney Ueshiro Taroku 1 *; left 1 figure ''N2 figure