Nova Patents
JPS581202A

Controller

Abstract

PURPOSE:To reduce the power consumption more at power failure for a controller inporporated in a processor, by increasing the period of an interruption time at power failure and its waiting time. CONSTITUTION:The system in provided with a power failure clock CL2 and a clock switching circuit 9. When a power failure is detected with a power failure detecting circuit 5, a detection signal DE is given to a clock switching circuit 9, which switches the clock of a clock generating circuit 1 from CL1 to CL2. The period of the clock CL2 is taken longer than the period of the clock CL1, resulting that the WAIT state of a microprocessor is ketp longer, allowing to reduce the power consumption. Further, the signal DE is given to the microprocessor 2 via an I/O device 4, allowing the processor 2 to reduce the power consumption more with the power failure processing which has shorter processing time than the normal processing.

Term

Term ended

Projected expiry passed 26 June 2001, 25.2 years ago.

  1. Priority and filed
  2. Published
  3. Projected expiry
  4. Today

1 claim: 1 independent, 0 dependent

  1. 1
    [Claim(s)] 【特許請求の範囲】 平常時には所定周期の割込信号によって起動され、所定の処理動作が終了すると待機状態となり、次の割込信号で該待機状態を解除して所定の処理動作を行ない1停電時には平常時とは別の予備電源から電力の供給を受けて平常時と同様の手順にて動作を行なう処理装置を有してなる制御装置において、前記割込信号の時間周期を平常時と停電時とに応じて切替える手段を設け1停電時には該手段によって割込信号の時間周期を平常時よりも長くすることにより1前記処理装置の待機時間を長くするようにしたことを特徴とする制御装置0