Consecutive comparison a/d converter

Description: TECHNICAL FIELD [Detailed description of the invention]

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INDUSTRIAL APPLICABILITY The present invention relates to a successive approximation type AD converter using a capacitor array.

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FIG. 4 is a diagram showing an outline of a configuration of a 6-bit successive approximation type AD converter using a conventional capacitor array. In FIG. 4, 1 is a positive reference potential (VDD), 2 is a negative reference potential (GND), 3 is a reference potential, 4 is an analog signal, and 10 is a weighted (different capacitance) capacitors 1C to 32C. It is a capacitor array to be constructed. Reference numeral 20 denotes an analog switch group, which is an analog switch group for selecting and applying one of an analog signal 4, a positive reference potential 1, and a negative reference potential 2 to one end of each capacitor of the capacitor array 10. Is a control circuit that operates each switch of the analog switch group 20 at a predetermined timing, and 40 is a comparator. SW0 is an analog switch that turns ON / OFF between the common end of the weighted capacitor array 10 and the reference potential 3.

The analog switch SW0 is turned on and the reference potential 3 (usually the potential at the midpoint between the positive side reference potential 1 and the negative side reference potential 2) is applied to the weighted capacitor arrays 1C to 32C to be applied to the capacitor array. With 10 as the reference potential, the analog switches SW1 to SW7 are operated to charge (sample) the analog signal to each capacitor. Next, the analog switch SW0 is turned off, the switches SW1 to SW7 are operated, and the charged analog signal is applied according to the weighting, that is, the positive side reference potential 1 or the negative side reference potential 2 is applied to each capacitor, respectively. The converted digital signal is obtained by repeating the comparison of the output with the reference potential 3 and the comparator 40 6 times.

That is, at the time of sampling, each capacitor is charged with the potential of the analog signal 4 with respect to the reference potential 3, and then in the first bit determination, the switches SW1 to SW7 are set to the positive reference potential 1 or negative for each capacitor. A digital signal is obtained while connecting to and holding the side reference potential 2 and determining whether the analog signal is higher or lower than the reference potential 3 by the comparator 40.

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[Problems to be Solved by the Invention] In the conventional sequential comparison type AD converter, as described above, the positive side reference potential or the negative side reference potential is simultaneously applied to each capacitor by the analog switch, so that the potential corresponding to the previously charged analog signal is output. It has become. However, since the timing of applying the positive side reference potential and the negative side reference potential by the analog switch cannot be completely simultaneous due to deviations such as element matching, either the positive side reference potential or the negative side reference potential is applied first. Therefore, a potential obtained by adding the charged analog signal to the reference potential 3 when the analog signal is charged is generated at the output of the capacitor array only during the period when the switch timing is deviated. At this time, when the substrate potential of the analog switch is the same as the positive side reference potential and the negative side reference potential, respectively, the electric charge of the capacitor array is released to the substrate through the PN junction of the transistors constituting the analog switch. As a result, the charge changes according to the previously charged analog signal, causing a conversion error. Sequential comparison type AD converters that use capacitor arrays are often used because it is easy to obtain accuracy between capacitors, especially when they are converted to ICs, but integrated circuits usually use PN junctions to separate the substrate and transistors. Therefore, when a potential exceeding the power supply voltage range is generated, a current flows through the substrate as a leak current, which causes a problem of conversion error.

The present invention has been made to solve such a problem, and provides a high-precision successive approximation type AD converter that prevents charge loss of a capacitor array and enables accurate conversion with low power consumption. The purpose is.

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[Means for solving problems] The sequential comparison type AD converter according to the present invention includes a capacitor array composed of a plurality of weighted capacitors, a switch SW0 for turning on / off a reference potential at one end of each capacitor of the capacitor array, and the capacitor array. A group of switches for selecting and applying one of an analog signal, a positive reference potential or a negative reference potential to the other end of each capacitor, and turning on the switch SW0 at the time of sampling to apply the reference potential. At the same time, the switch group is operated to supply an analog signal to all the capacitors, the switch SW0 is turned off at the time of sequential comparison, and the switch group is operated to the other end of each capacitor with the positive reference potential or the positive reference potential. It is composed of a control circuit that controls the application of the negative reference potential and a comparator that compares the sampling potential output from one end with the reference potential, and sequentially converts the analog signal into an N-bit digital signal. The sequential comparison type AD converter for conversion is characterized by including a means for configuring the switch SW0 with an N-channel transistor, and a means for dividing the capacitor on the MSB side of the capacitor and controlling each of them separately at the time of the sequential comparison. ..

Further, in the control circuit, at the time of the first sequence at the time of the sequential comparison, the capacitor on the LSB side is connected to the positive reference potential, and then one of the divided capacitors on the MSB side is connected to the negative reference potential. It is characterized by having a means to do so.

Further, in the control circuit, at the time of the first sequence at the time of the sequential comparison, the capacitor on the LSB side is connected to the positive side reference potential, and then one of the divided MSB side capacitors is connected to the negative side reference potential. If the sampling potential output from the one end is lower than the reference potential, the process proceeds to the next sequence, and if the potential output from the one end is higher than the reference potential, the other of the divided MSB-side capacitors One of them is characterized in that it is connected to the negative reference potential, and in this state, a means for comparing whether the sampling voltage is higher or lower than the reference potential and proceeding to the next sequence is provided.

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BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration for explaining an embodiment of the sequential comparison type AD converter of the present invention, and shows a state at the time of sampling of the 6-bit sequential comparison type AD converter. In FIG. 1, 1 is a positive reference potential (VDD), 2 is a negative reference potential (GND), 3 is a reference potential, 4 is an analog signal, and 10 is a weighted (different capacitance) capacitors 1C to 16C. It is a capacitor array to be constructed. Reference numeral 20 denotes an analog switch group, which performs an operation of selecting and applying one of an analog signal 4, a positive reference potential 1, and a negative reference potential 2 to each capacitor of the capacitor array 10. Reference numeral 30 denotes a control circuit for operating each switch of the analog switch group 20 at a predetermined timing, and 40 is a comparator. Further, SW0 is an analog switch composed of only N-channel transistors that turn ON / OFF between the common end of the weighted capacitor array 10 and the reference potential 3. In the weighting of the capacitor in the present embodiment, the most significant bit 32C of the conventional configuration is divided into two to make 16C into two (the division ratio of the capacitance on the MSB side is arbitrary).

Next, the operation will be described. As shown in FIG. 1, at the time of sampling, all the analog switches SW1 to SW8 are connected in a state of supplying the analog signal 4 to each weighted capacitor array 10. Further, the analog switch SW0 is in the ON state, and the reference potential 3 is supplied to the capacitor array 10. In this state, the capacitor array 10 is charged with the analog signal 4 with reference to the reference potential 3, and the sequential comparison is started when the charging is completed.

FIG. 2 is a diagram showing a state in which sequential comparison is performed. In the sequential comparison, the analog switches SW0 are turned off, the switches SW1 to SW6 are connected to the positive reference potential 1, the switch SW7 is connected to the negative reference potential 2, and the switches SW8 are all turned off. In addition, when shifting to this sequential comparison state, SW1 to SW6 are connected first and SW7 is connected with a delay so that undershoot does not occur in the present embodiment. In this state, the output from the capacitor array 10 and the reference potential 3 are compared by the comparator 40.

As described above, in the present embodiment, the weighting of the capacitor 32C is divided into two to obtain the capacitor 16C + the capacitor 16C, and the other capacitor 16C has all SW8s turned off, so that the capacitor array 10 is (1). It is output with an offset of 16/64). Therefore, with respect to the undershoot that occurs when the capacitor array 10 is switched, (16/64)×There will be a margin of (positive reference potential 1-negative reference potential 2). Further, since the analog switch SW0 is composed of only N-channel transistors, even if an overshoot occurs, the PN junction is in the opposite direction with respect to the positive reference potential 1, so the cause of charge loss is It doesn't become.

Then, in this state, the reference potential 3 and the output from the capacitor array 10 are compared by the comparator 40. As a result, if the output from the capacitor array 10 is lower than the reference potential 3, the analog signal is higher than the reference potential 3 even if the above-mentioned offset is added (the analog signal and the output of the capacitor array have the opposite relationship. The first bit is "1" because it is clear.

If the output of the capacitor array 10 is higher than the reference potential 3, the first bit is either "1" or "0". In this case, SW8 is operated as shown in FIG. The other capacitor 16C and the negative reference potential 2 are connected. At this time, the output from the capacitor array 10 is (16/64).×Since it is known that it is higher than (positive reference potential 1-negative reference potential 2), it does not fall below the negative reference potential 2 even if undershoot occurs, so that it is also relative to the negative reference potential 2. No charge loss occurs.

In this state, the reference potential 3 and the output from the capacitor array 10 are compared by the comparator 40. As a result, if the output from the capacitor array 10 is lower than the reference potential 3, the first bit becomes "1", and if it is higher, the first bit becomes "1". The first bit is "0". For the subsequent bits, for undershoot, (16/64)×Since there is a margin of (positive side reference potential 1-negative reference potential 2) or more, there is no problem in the ratio of the parasitic capacitance such as the parasitic capacitance of the switches SW1 to 8 and the analog switch SW0 to the capacitance value of the capacitor array 10. By setting the level, it is possible to perform a comparison operation while accurately holding the charged analog signal without causing charge loss.

That is, in the successive approximation type AD converter of the present invention, a switch composed of only N-channel transistors is used for the switch SW0 used for the output unit of the capacitor array 10, and the capacitance on the MSB side of the capacitor array 10 is, for example. The configuration is divided in half. By using the switch SW0 composed of only N-channel transistors, charge loss due to overshoot is eliminated. The switch SW0 used for this output unit is a switch for supplying a reference potential at the time of sampling, but there is no problem if the reference potential 3 is selected in the ON region of the N-channel transistor. Also, during the first sequence of sequential comparisons, half of the capacitor array is connected to the positive reference potential (VDD) and then only part of the rest is connected to the negative reference potential (GND). By doing so, even if undershoot occurs, the potential does not drop until the PN junction of the back gate of the N-channel transistor is turned on, and charge loss is eliminated.

Further, since the positive reference potential (VDD) 1 is connected first in order, a potential of 1 or higher as the positive reference potential (VDD) 1 may be generated, but the output unit of the capacitor array 10 Since the switch SW0 of the above is composed of only an N-channel transistor, no charge loss occurs. In this state, the output from the capacitor array 10 is compared with the reference potential 3. As a result of this comparison, if it is lower than the reference potential 3, it is clear that the sampling potential is in the vicinity of the negative reference potential (GND) 2, and the process proceeds to the next sequence. If it is higher than the reference potential 3, the capacitor that was not connected to the negative reference potential (GND) 2 is connected to the negative reference potential (GND) 2. Even if undershoot occurs at this time, since the sampling potential is not in the vicinity of the negative reference potential (GND) 2, the PN junction of the back gate of the N-channel transistor of the switch SW0 described above does not turn on. In this state, it is compared whether the sampling voltage is higher or lower than the reference potential 3, and the process proceeds to the next sequence.

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[Effects of the Invention] As described above, the successive approximation type AD converter of the present invention has an effect of being able to prevent charge loss, which is a drawback of this type of AD converter. In addition, it can be realized with the same configuration as the conventional configuration, and it is easy to macroize because it is not affected by the timing shift due to the process, and it is possible to realize a high-precision sequential comparison AD converter circuit with low power consumption on the integrated circuit. There is.

[Simple explanation of drawings]

FIG. 1 is a diagram showing a state at the time of sampling in one embodiment of the successive approximation type AD converter of the present invention.

FIG. 2 is a diagram showing a first state at the time of sequential comparison of the first bit in one embodiment of the sequential comparison type AD converter of the present invention.

FIG. 3 is a diagram showing a second state at the time of sequential comparison of the first bit in one embodiment of the sequential comparison type AD converter of the present invention.

FIG. 4 is a diagram for explaining a conventional sequential comparison type AD converter.

[Explanation of symbols]

1 Positive reference potential (VDD) 2 Negative reference potential (GND) 3 Reference potential 4 Analog signal 10 Capacitor array consisting of weighted capacitors 1C to 16C 20 Analog switch group 30 Control circuit 40 Comparator