Graphics controller circuit, and method for executing command on computer system and graphics controller chip

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates broadly to computer graphics systems. Specifically, the present invention relates to a method and an apparatus for executing a command in a graphics controller chip.

【0002】

[Conventional technology]

The graphics controller is designed to display a video image on a display system by receiving commands and display data from the host system and generating display signals from those display data and commands. FIG. 1 is a block diagram of a computer system 100 having such a graphics controller 120, a host 110, and a display unit 130.

【0003】

The graphics controller 120 receives commands and display data from the host 110 via the system bus 112, and executes commands in the process of generating display signals on the display bus 123 to produce a video image composed of the display data. It can be displayed on the display unit 130. The graphics controller 120 may generate additional display data while executing commands received from the host 110. The display data includes, for example, text data and graphics / video data in RGB format.

【0004】

The graphics controller 120 may store the display data in the display memory 140 before generating the corresponding display signal on the display bus 123. Each element of the display data stored in the display memory 140 may correspond to one pixel on the display unit. In the following description, such a data element will be referred to as a "pixel datum", and an aggregate of such pixels will be referred to as "pixel data".

【0005】

The command received from the host 110 can specify various operations such as a mobile display block operation. The mobile display block operation refers to a display block (hereinafter referred to as source display block) to be moved from one area of the display memory 140 to another area (destination display) on the display memory 140 with respect to the graphics controller 120. It is an operation to instruct to move to (block). In some cases, the source display block may be located within host 110. In such a case, the host 110 can also send the display data of the source display block via the system bus 112. In response, the graphics controller 120 can move the pixel data of the source display block to a memory location in the display memory 140 that corresponds to the destination display block.

【0006】

The host 110 can send some commands to the graphics controller 120 to perform each operation. For example, to perform a mobile display block operation, host 110 sends a command to specify the X / Y coordinates of the starting position of the source display block, and the X range of the source display block (that is, the X of the display block with respect to the starting address). After sending another command to specify the axial length) and Y range, you can send yet another command to specify the X / Y coordinates of the starting address of the destination display block. Finally, the host 110 can send yet another command to specify the start of moving the display data to the memory location corresponding to the destination display block in the display memory 140.

【0007】

With the advent of graphics-only applications (commonly referred to as "graphics user interfaces (GUIs)"), computer systems 100 will need to perform some graphics operations in a short period of time. There is. For example, a mouse click by a computer user may require the computer system 100 to perform some graphics operations. Since each operation requires the execution of several commands, the host 110 may send a corresponding number of commands to the graphics controller 120 via the system bus 112.

【0008】

[Problems to be Solved by the Invention]

A problem with computer system 100 with prior art is, for example, the performance of computer system 100 because the system bus 112 may not have enough bandwidth to support the transfer of such a large number of commands and display data. There is a point that it may become a bottleneck. Such a performance bottleneck causes a decrease in the performance throughput of the computer system 100.

【0009】

The performance bottleneck in system bus 112 becomes even more severe when the host 110 and graphics controller 120 operate faster and with wider bandwidth than system bus 112. For example, a host 110 with a Pentium (TM) processor may operate at a clock speed of 75 MHz and a 64-bit internal bus, and a graphics controller 120 may operate at a clock speed of 62.5 MHz and a 64-bit internal bus. In contrast, system buses 112, such as the PCI bus, may operate on buses with a clock speed of 33 MHz and a 32-bit width. Such differences in clock rate and bus width in GUI applications dedicated to graphics operations create a data throughput bottleneck on system bus 112 and reduce the performance of computer system 100.

【0010】

The present invention has been made to solve the above problems, and an object of the present invention is to provide a graphics system having improved performance by eliminating a bus bottleneck.

【0011】

[Means for solving problems]

A graphics controller circuit used in a computer system having a bus and a host according to the invention and to which the host is coupled to the bus receives commands from the host on the bus and receives multiple instructions from the commands. It includes a host interface to be generated and an execution circuit that executes the plurality of instructions in order to execute the command, thereby achieving the above object.

【0012】

In one embodiment, a graphics controller circuit further comprising a register file containing a plurality of registers, the host interface if the command accesses a first register in the register file. Generates a first instruction set, and if the command accesses a second register, the host interface generates a second instruction set and the number of instructions contained in the first instruction set. However, the number of instructions contained in the second instruction set is different from that of the first instruction set, and the first instruction set includes access to the first register.

【0013】

In certain embodiments, the second register comprises a virtual register and the second instruction set comprises at least one instruction to access the first register.

【0014】

In one embodiment, the host interface examines the data on the system bus to determine if the command is addressing to the first register or to the second register. A command encoder coupled to the system bus, if the command is addressed to the first register, produces the first instruction set and if the command is to the second register. If it is addressing, it comprises a command encoder that generates the second set of instructions and a FIFO queue that stores the instructions generated by the command encoder and feeds the instructions to the execution block. There is.

【0015】

In certain embodiments, the command is contained within a plurality of commands for the mobile display block operation, and the host is the host data and the plurality of commands for the mobile display block operation. Is sent via the host bus.

【0016】

In certain embodiments, the command encoder stores the host data, a set of instructions corresponding to the plurality of commands, and the FIFO queue containing the plurality of entries, and the command encoder stores the host data, the instruction corresponding to the plurality of commands, and the plurality of entries, respectively. Generates a tag bit indicating whether the data stored in is containing a host datum or an instruction.

【0017】

In certain embodiments, the tag bit of each of the plurality of entries is examined, and if the tag bit indicates that the data contained in the corresponding one of the plurality of entries includes host data. It also includes a FIFO output control circuit that sends the data contained in the entry to the execution block.

【0018】

The computer system according to the present invention includes a host that sends a set of commands and pixel data via a bus, a display unit, a display memory that stores a set of pixel data corresponding to a display image on the display unit, and the pixel data. A graphics controller circuit that supplies a set of the above to the display memory, a host interface that receives the set of commands and the pixel data from the host on the bus, and a plurality of instructions from each of the set of commands. A graphics controller circuit, including a host interface for generating the above, and an execution circuit for executing the plurality of instructions for storing the pixel data in the display memory, thereby achieving the above object. Will be done.

【0019】

In one embodiment, the graphics controller circuit is a computer system further comprising a register file containing a plurality of registers, if the command accesses a first register in the register file. If the host interface generates a first instruction set and the command accesses a second register, the host interface generates a second instruction set and the first instruction set The number of instructions included is different from the number of instructions contained in the second instruction set, and the first instruction set includes accessing the first register.

【0020】

In certain embodiments, the second register comprises a virtual register and the second instruction set comprises at least one instruction to access the first register.

【0021】

In one embodiment, the host interface examines the data on the system bus to determine if the command is addressing to the first register or to the second register. A command encoder coupled to the system bus, if the command is addressed to the first register, produces the first instruction set and if the command is to the second register. If it is addressing, it comprises a command encoder that generates the second set of instructions and a FIFO queue that stores the instructions generated by the command encoder and feeds the instructions to the execution block. There is.

【0022】

In certain embodiments, the set of commands includes the commands, and the set of commands is designed to perform mobile display block operations.

【0023】

In certain embodiments, the command encoder stores the host data and a set of instructions corresponding to the set of commands in the FIFO queue containing the plurality of entries, and the command encoder stores the set of instructions in each of the plurality of entries. Generates a tag bit indicating whether the stored data contains a pixel datum or an instruction.

【0024】

In certain embodiments, the tag bit of each of the plurality of entries is examined, and if the tag bit indicates that the data contained in the corresponding one of the plurality of entries comprises a pixel datum. It further includes a FIFO output control circuit that sends the data contained in the entry to the execution block.

【0025】

The graphics controller circuit according to the present invention accesses a physical register, an addressable memory location, a first command to access the physical register, and a virtual register, which stores parameters for graphics operations. An encoder that receives a second command and generates a first instruction set in response to the first command and a second instruction set in response to the second command. An encoder and an encoder in which both the first instruction set and the second instruction set contain an instruction to access the physical register, and the second instruction set contains the first instruction set. A FIFO that stores the first instruction set and the second instruction set, and a physical register and a FIFO output control circuit coupled to the FIFO in response to the instruction that accesses the physical register. , A FIFO output control circuit that generates a control signal to access the physical register, thereby achieving the above object.

【0026】

The method of executing a command in the graphics controller chip according to the present invention includes a step of receiving the command, a step of generating a plurality of instructions from the command, a step of storing the plurality of instructions in a command queue, and the command queue. Includes a step of executing the plurality of instructions in the above, whereby the above object is achieved.

【0027】

In one embodiment, a method further comprises examining the command to determine whether the command accesses a physical register or a virtual register, if the command goes to the physical register. The step of generating multiple instructions creates a first set of instructions, and if the command accesses the virtual register, the step of generating a second set of instructions. Further included, the first instruction set and the second instruction set both contain instructions to access the physical register, and the second instruction set includes the first instruction set. I'm out.

【0028】

The action will be described below.

【0029】

The graphics controller circuit of the present invention includes a host interface capable of receiving a command from a host and generating a plurality of instructions from the command. The execution circuit executes multiple instructions in order to actually execute the command received from the host.

【0030】

This graphics controller circuit may further include a register file composed of a plurality of registers. The host interface produces a first set of instructions if the command accesses the first register in the register file, and a second set of instructions if the command accesses the second register. be able to. The first set of instructions may include access to the first register. The second register according to the present invention can be a virtual register. The second set of instructions may include instructions that order access to the first register.

【0031】

By providing such a command to be issued to a virtual register and generating a number of instructions including a command to access the register in the register file, the graphics controller according to the present invention provides access to a register. Commands can be combined with several other commands into a single command on the system bus. Since several commands can be combined on the system bus into a single command, the amount of data transferred on the system bus can be minimized.

【0032】

The host interface according to the present invention may include a command encoder that examines the data on the bus and determines whether the command is addressed in the first register or the second register. This command encoder will generate the first set of instructions if the command is addressed to the first register, and if the command is addressed to the second register, the second set of instructions. Instructions can be generated.

【0033】

The host interface may also include a FIFO queue that stores the instructions generated by the command encoder and gives those instructions to the execution block. When the host interface generates a large number of instructions from each command, the instruction path for the graphics controller and the path for the data supplied to the host can operate on a narrower bus width, so silicon. You can save space. The graphics controller can thus perform more instructions, even if it operates faster than the system bus.

【0034】

In the present invention, the plurality of commands for performing the mobile display block operation may include data supplied to the host. The host can send multiple commands for host data and mobile display block operations over the host bus. The command encoder can store host data and a set of instructions corresponding to multiple commands in a FIFO queue containing multiple entries. The command encoder can generate tag bits that indicate whether the data stored in each entry contains a host datum or instructions.

【0035】

The FIFO output control circuit in the graphics controller circuit examines the tag bits of each entry, and if that tag bit indicates that the data contained in the corresponding entry contains instructions, that entry. If the tag bit indicates that the data contained in the corresponding entry contains host data, then the data contained in that entry is sent to the execution block. Send to the pixel processing block.

【0036】

BEST MODE FOR CARRYING OUT THE INVENTION

This application was filed on June 23, 1995 and claims priority under Provisional Application No. 60 / 000,490 entitled "Byte Enable FIFO Architecture".

【0037】

The graphics controller 120 according to the present invention is designed so that the number of commands received via the system bus 112 can be reduced, as illustrated in FIGS. 4A to 4D. As shown in (a) of FIG. 4, in performing the graphics operation, the host 110 by the conventional technique sends three commands. That is, a first command (410) that orders a set of registers A, a second command (420) that orders a set of registers B, and a third command (430) that orders the start of an operation using A and B. There are three.

【0038】

In the present invention, the host 110 only needs to send two commands to perform equivalent graphics operations. That is, there are two commands: a command (411) that orders a set of registers A, and a command (412) that orders a set of registers B and starts execution using A and B. Therefore, according to the present invention, two commands according to the conventional technique can be combined into one command. (B) to (d) of FIG. 4 will be described in the same manner as (a) of FIG. That is, in each figure, in the conventional technique, two commands are combined into one command.

【0039】

For example, in the prior art, the graphics controller 120 may receive four commands from the host 110 to perform a mobile display block operation. That is, the first command specifies the address of the source display block, the second command specifies the address of the destination display block, and the third command specifies the X and Y ranges of the source display block. However, the fourth command may instruct the graphics controller 120 to start execution with parameters that can be set by the first three commands. In response to the fourth command, the graphics controller 120 transfers the pixel data of the source display block (specified by the first and third commands) to the destination display block (specified by the second command). May be moved to a memory location within the display memory 140 that corresponds to.

【0040】

On the other hand, in the present invention, the graphics controller 120 only needs to receive three commands from the host 110 when performing the mobile display block operation. The first and second commands specify the addresses of the source and destination blocks, as in conventional techniques. However, the third command not only specifies either the X range and / or the Y range, but also causes the graphics controller 120 of the present invention to start moving pixel data in the source display block. In the graphics controller 120 of the present invention, the number of commands received to perform the mobile display block operation is reduced, so that the amount of data sent by the host 110 on the system bus 112 can also be reduced. In addition, since the virtual register space is used, the space of such a virtual register does not require an additional physical register, and silicon space can be further saved.

【0041】

The graphics controller 120 can achieve such a reduction in the amount of data transferred by storing the X and Y ranges in registers. The graphics controller 120 can receive one type of command that orders the X and Y ranges to be stored in these registers, and another type of command that is addressed to the virtual register. In response to such a command addressed to a virtual register, the host interface 210 (shown in Figure 2) provides not only instructions that order the X and Y ranges to be stored in the register, but also other instructions. It can also be generated. In the example described above, in response to a command commanding access to a virtual register, host interface 120 orders the X and Y ranges to be stored in the corresponding registers, commanding the start of movement of pixel data in the source display block. Many instructions can be generated. Therefore, in the present invention, by using the virtual register, the third and fourth commands according to the conventional technique can be combined into one command on the system bus 112.

【0042】

In the present invention, since many commands used in the conventional technique can be combined into one command, the amount of data on the system bus 112 can be reduced. Although the present invention has been described herein as being applicable to mobile display block operations, it should be understood that performing other types of operations is also within the scope and spirit of the present invention.

【0043】

FIG. 2 is a block diagram of a graphics controller 120 according to the present invention having a host interface 210, an execution block 220, and a pixel processing block 230. The host interface 210 can receive commands and host data from the host 110 via the system bus 112 and generate a large number of instructions corresponding to each command. By generating such a large number of instructions corresponding to each command, the graphics controller 120 can reduce the amount of data transferred from the host 110 to the graphics controller 120. Host interface 210 can receive commands at one clock rate (ie, the clock rate of system bus 112) and generate instructions at another rate (ie, the internal clock rate of the graphics controller 120).

【0044】

The execution block 220 performs the operation specified by the command from the host 110 by executing the instruction generated by the host interface 210. The instructions executed by the execution block 220 include various operations such as moving the pixel data of the source display block to the memory location corresponding to the destination display block in the display memory 140. The host 110 can also send pixel data of the source display block via the system bus 112, and the host 110 specifies a memory location in the display memory 140 where the pixel data of the source display block resides. You can also do it. The execution block 220 controls the movement of pixel data from the host 110 or the display memory 140 via the control bus 114.

【0045】

The pixel processing block 230 generates additional pixel data by processing the pixel data. Such processing may include performing raster operations that are well known in the art. The pixel processing block 230 can store the pixel data generated by such processing in the memory position designated by the execution block 220.

【0046】

FIG. 3 is a detailed block diagram of a host interface 210 according to the invention, including an address register 333, a data register 336, a command encoder 330, and a command / data FIFO 340. The encoder 330 of the present invention can generate a large number of instructions from each of the received commands and store those instructions in the command / data FIFO 340.

【0047】

FIG. 3 further includes a detailed block diagram of the execution block 220 according to the invention, including a FIFO output control circuit 360, an execution engine 370, and a register file 350. The FIFO output control circuit 360 can control when data is stored in the register file 350. The FIFO output control circuit 360 can also determine when to start executing various operations and control the operations of the execution engine 370 via the bus 366. The FIFO output control circuit 360 performs each of these operations based on the command / tag information received on the buses 213 and 214 of the command / data FIFO bus 212.

【0048】

The register file 350 may include a plurality of registers, each storing a value corresponding to a predetermined parameter. For example, registers 0 and 1 can store the X and Y coordinates of the start addresses of the source display block and the destination display block for moving display block operations, respectively. Register 2 can store the X and Y ranges of the source display block. In the present specification, the register included in the register file 350 is also referred to as a "physical register".

【0049】

In a preferred embodiment, each register in the register file 350 can store 32 bits. In that case, the X and Y ranges and the X and Y coordinates are stored in 16 bits, respectively. The register file 350 may contain a large number of registers that can be addressed as a memory-mapped register set (ie, each register has a given memory address). In a preferred embodiment, the register file 350 comprises eight registers.

【0050】

Thus, a command, such as a command that specifies the starting address of a source and destination display block, involves writing data to the corresponding register in register file 350. The system bus 112 may include a 32-bit wide PCI bus. Thus, the host 110 may send 32-bit address information during one clock cycle (on system bus 112) and the corresponding 32-bit data during the subsequent one clock cycle to send commands. it can.

【0051】

For example, host 110 may send a 32-bit memory address of register 0 during one clock cycle and the corresponding data during the subsequent one clock cycle to set the start address of the source display block. it can. The 32-bit data may contain 16 bits corresponding to each of the X and Y coordinates of the starting address. Similarly, the host 110 can send the address of register 2 and the corresponding data to set the X and Y ranges of the source display block for the move operation.

【0052】

Host 110 can also send memory addresses for a number of virtual registers (eg, 8 when register file 350 contains 8 registers numbered 0-7). In response to receiving such a number of virtual registers, the graphics controller 120 according to the present invention generates an instruction and stores the data received in the next clock cycle in any of the predetermined registers 0 to 7. The pixel data can be moved to a memory location in the display memory 140 that corresponds to the destination display block.

【0053】

By using such virtual register addressing to generate an instruction to order storage / movement, the graphics controller 120 does not need to add a command to order the start of movement of pixel data. As a result, the amount of command data transferred via the system bus 112 can be reduced. It will be understandable that the graphics controller 120 according to the prior art needs such an additional command to initiate the movement of pixel data to the memory address of the destination display block. It will also be appreciated that the generation of different instructions in response to such virtual register addressing does not deviate from the scope and spirit of the invention.

【0054】

Further referring to FIG. 3, the address register 333 and the data register 336 can each store the address and data information received via the system bus 112 during each bus cycle. The address from host 110 may include the memory-mapped address of the register in the register file 350, or may include the address of a virtual register.

【0055】

The command encoder 330 can generate the corresponding instruction by examining the address stored in the address register 333. For example, if the address corresponds to register 0, the command encoder 330 can generate two instructions. The first instruction stores the Y coordinate, which occupies 16 bits of the 32-bit data (stored in the data register 336), in register 0, and the second instruction stores the X coordinate, which occupies the remaining 16 bits. Can be stored in register 0.

【0056】

If the address stored in address register 333 corresponds to a virtual register, the command register can generate additional instructions other than the stored instruction. For example, in a preferred embodiment, the graphics controller 120 has three virtual registers (range / execute / X register, range / execute / Y register and range / execute) that can be used by the host 110 while performing a mobile display block operation. X and Y registers) may be included.

【0057】

Since the range / execution / write operation to the X virtual register (register number 8) indicates that only the X range needs to be changed, the pixel data movement operation uses the changed X range. It will start immediately. In response to such a range / execute / X write operation, the command encoder 330 generates an instruction to change the X range, and another command to start the operation of moving the display data to the address specified by the register 1. Generate instructions. Similarly, the command encoder 330 can generate two instructions for range, execute, and write operations to the Y register.

【0058】

The command encoder 330 can generate three instructions corresponding to the range / execute / X / Y virtual register (register number 10) write command. The first instruction causes the 16-bit X component of the 32-bit data to be written, and the second instruction causes the remaining 16-bit Y component of the 32-bit data to be written. The third instruction can be a movement instruction that orders the start of movement of the pixel data of the source display block to the destination display block.

【0059】

Each instruction generated by the command encoder 330 can contain 32 bits. 16 bits of them are allocated to any one of the X range, Y range, X coordinate, and Y coordinate. The remaining 16 bits can specify an instruction code that can indicate the type of instruction (eg, store in register 1, start of display data move operation, etc.). The command encoder 330 can send such 32-bit instructions via the instruction / data bus 334.

【0060】

The command encoder 330 also sends a tag bit on the signal line 343 to indicate whether the information sent on the instruction / data bus 334 corresponds to the instruction or the host datum. Can be shown. The command encoder 330 can send a logical value 0 as a tag bit while sending an instruction via an instruction / data bus 334, and can send a logical value 1 while sending a host datum.

【0061】

Such host data is received from the host 110 via the system bus 112 and corresponds to the pixel data of the source display block. Register 0 can have a value indicating that the pixel data of the source display block is supplied by the host 110. In such a case, the host 110 can send pixel data of the source display block for the mobile display block operation.

【0062】

The command / data FIFO 340 can store each instruction or host datum received via the instruction / data bus 334 and the corresponding tag bits received via the signal line 343. The command / data FIFO 340 can contain 32 entries in a preferred embodiment. Here, each entry contains 33 bits. That is, each entry can store a 32-bit instruction or host datum and the corresponding 1-tag bit. Each tag bit in the command / data FIFO 340 (stored in the tag bit field 346) can indicate whether the corresponding 32 bits represent an instruction or a host datum.

【0063】

If the 33 bits in the command / data FIFO 340 entry represent an instruction, the instruction code field 347 can store the 16 bits corresponding to the instruction code. In addition, the data field 348 can store the remaining 16 bits corresponding to the data portion of the instruction. If the 33 bits in the command / data FIFO 340 entry represent host data, the command / data FIFO 340 can store 32 bits of host data in the entry using data fields 347 and 348. If host data is supplied, the data is processed by the pixel processing block 230 via the bus 212, as indicated by the tag bits on the bus 213.

【0064】

It should be appreciated that by generating multiple instructions from a single command, the command / data FIFO 340 according to the invention can operate effectively with a narrower data width (33 bits) than the system bus 212. Without generating such a large number of instructions, the command / data FIFO would have to operate with a 64-bit data width. The graphics controller 120 can operate at a higher clock rate than the system bus 112, resulting in the graphics controller 120 being able to perform more instructions. For example, a system bus 112, such as a PCI bus, operates at 33MHz, while a graphics controller 120 can operate at 62.5MHz.

【0065】

Further referring to FIG. 3, the FIFO output control circuit 360 retrieves 33 bits of data in each entry of the command / data FIFO 340, and by examining the tag bit 346, does the retrieved data correspond to the instruction? It is possible to determine whether it corresponds to the host data. If the 33-bit entry represents an instruction, the FIFO output control circuit 360 examines the instruction code (stored in field 347) so that the instruction stores the data in a register in the register file 350. Determine if it is an instruction to do. If so, the FIFO output control circuit 360 stores 16 bits in the data field 348 in the register indicated by the instruction code by generating the assert signal 365.

【0066】

If the 33-bit entry represents an execution instruction, the FIFO output control circuit 360 can start execution via the execution engine 370 on control bus 366. The execution engine 370 properly processes the host data by generating a control signal to the pixel processing block 230. For example, the host data may correspond to the pixel data of the preceding mobile display block command. In that case, the execution engine 370 can store the pixel data at the memory location indicated by the register in the register file 350. The graphics controller 120 can generate a display signal from the pixel data stored in the display memory 140 to the display unit 130.

【0067】

Therefore, the host interface 210 according to the present invention can generate a large number of instructions from each command received from the host 110. This can reduce the amount of data that the host 110 sends to the graphics controller 120. By generating such a large number of instructions, the graphics controller 120 can effectively operate in a narrow bus width.

【0068】

In the above description, the present invention has been applied to the display block moving operation, but other types of operations can be performed without departing from the scope and spirit of the present invention. For example, a large number of instructions can be generated during read access to a register. Such a register may be a virtual register or a physically existing register as described above (for example, one of registers 0 to 7 in the register file 350). Good). Read and write commands are collectively referred to as "access commands" herein.

【0069】

It will be readily appreciated by those skilled in the art that the present invention can achieve all of the above mentioned objects. After reading the above detailed description, those skilled in the art may make various modifications to the present invention widely disclosed in the present specification, replace it with an equivalent configuration, and others not mentioned herein. It will be possible to carry out various aspects. Thus, the scope of protection to be provided to the present invention is intended to be limited only by the definitions contained within the appended claims and their equivalent.

【0070】

[Effect of the invention]

According to the present invention, it is possible to provide a graphics system with improved performance by eliminating a bus bottleneck.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of a computer system including a graphics controller, a host, a display memory, and a display unit.

[Figure 2]

FIG. 3 is a block diagram of a graphics controller according to the present invention including a host interface, an execution block, and a pixel processing block.

[Fig. 3]

It is a block diagram which shows the more detailed architecture of the host interface and execution block by this invention.

[Fig. 4]

It is a figure which shows the difference between the prior art and the present invention in the number of commands used to perform a graphics operation.

[Explanation of symbols]

112 System bus 114 Control bus 210 host interface 212 Command / Data FIFO Bus 213, 214, 215 buses 220 execution block 230 pixel processing block 330 command encoder 333 Address register 334 Instruction / Data Bus 334 336 data register 340 Command / Data FIFO 343 signal line 346 tag bit field 347 Instruction Code Field 348 data field 350 register file 360 FIFO output control circuit 365 assert signal 366 Control bus 370 execution engine