Signal transmission system, semiconductor device module, input buffer circuit, and semiconductor device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention generally relates to a data transmission system using a bus, and more particularly to a data transmission system using a high-speed bus wiring having termination.

【0002】

[Conventional technology]

As the speed of microprocessors increases, higher-speed data transfer using higher frequencies is also required for data transfer between LSI chips. However, at the TTL level and CMOS level, which are the input / output levels of conventional LSIs, the effects of signal reflection and crosstalk become greater when the signal frequency exceeds 50 MHz, making normal data transfer difficult. ..

【0003】

To solve this, input / output interfaces such as CTT (Center Tapped Termination) and GTL (Gunning Trasnceiver Logic) that use small amplitude signals with signal levels suppressed to 1V or less have been proposed. Figure 8 shows the GTL system. The GTL system in Figure 8 has a characteristic impedance of Z.₀Bus 10, the terminating resistor Rt that connects the end of the bus 10 to the terminating voltage Vtt, and the characteristic impedance Z that branches off from the bus 10.₁Includes the stub (wiring branch portion) 11 and the device 20 such as a memory and a controller connected to the end of the stub 11. Here, the terminating voltage Vtt is 1.2 V and the terminating resistor Rt is 50 Ω.

【0004】

The output circuit and input buffer circuit of the device 20 are connected to the I / O terminal of the device 20 connected to the stub 11. The output circuit of the device 20 includes a damping circuit 21 and a driver transistor 22. The input circuit of the device 20 includes a current mirror type differential amplifier consisting of transistors 23 to 27 and an inverter 28. The current mirror type differential amplifier compares the signal voltage input to the I / O terminal with the reference voltage Vref, and supplies a low potential to the inverter 28 when the signal voltage is higher than the reference voltage Vref. Conversely, when the signal voltage is lower than the reference voltage Vref, a high potential is supplied to the inverter 28. The inverter 28 inverts the input potential and supplies it to the internal circuit of the device 20.

【0005】

There are several advantages of GTL, but the first is that it uses an open-drain type driver circuit (output circuit) as shown in Fig. 8, so it can provide wired or logical functions on the bus. .. Secondly, since the logical state on the bus exists only either high or low, the logical state on the bus is fixed to high when all the drivers sharing the bus are in the off state. On the other hand, in a tri-state type bus such as CTT, when all the drivers are turned off, the logical state on the bus becomes an intermediate level between high and low. Therefore, the input buffer circuit connected to the bus receives a signal in which high and low cannot be distinguished, and becomes an unstable state in which high and low are randomly detected according to noise. In order to prevent this, in CTT, when all the drivers are turned off, it is necessary to input a command prohibiting the operation to the input buffer circuit.

【0006】

[Problems to be Solved by the Invention]

The disadvantage of GTL is that the driver is off when the stub 11 is long and there is a distance between the bus 10 and the driver (driver transistor 22), for example, when the signal frequency is 200 MHz and the length of the stub 11 is 2 mm or more. After that, a violent ringing waveform may occur. This phenomenon becomes particularly remarkable in the presence of parasitic inductance of lead frames and bonding wires.

【0007】

Figure 9 shows the parasitic inductance L present in the lead frame and bonding wire.₁And C₁Is a diagram schematically showing. In FIG. 9, when the switch S, which models the on and off of the driver transistor 22, changes from on to off, a counter electromotive force is generated due to a sudden current cutoff, and a pulsed voltage waveform is busted through the stub 11. Head to 10. Since there is an impedance mismatch between the stub 11 and the bus 10, this pulsed voltage waveform is reflected at the connection point between the stub 11 and the bus 10 and returns to the driver transistor 22 side of the stub 11. Head. Since the driver transistor 22 is turned off here, it becomes an open end, and the pulsed voltage waveform is completely reflected and returns to the inside of the stub 11. In order to repeat such a cycle, a violent ringing waveform is generated between the branch point of the stub 11 from the bus 10 and the driver transistor 22.

【0008】

FIG. 10 shows the ringing waveform obtained by computer simulation. Fig. 10 (A) shows the case where the stub length is zero, Fig. 10 (B) shows the case where the stub length is 1 cm, and Fig. 10 (C) shows the case where the stub length is 2 cm. Indicates the case where the length of the stub is 5 cm. The simulation conditions are shown in Fig. 11. Driver DV and 8 memories M₁To M₈Driver DV is memory M under the condition that is connected to the bidirectional data bus₁It is assumed that data is written to at a frequency of 100 MHz.

【0009】

In FIGS. 10A to 10D, the solid line is the memory M.₁The waveform of the driver end on the DV side of the device that writes data to is shown, and the wavy line is the memory M.₁The waveform of the receiver end on the side is shown. As shown in FIGS. 10 (A) to 10 (D), it can be seen that as the length of the stub increases, a more intense ringing waveform occurs.

【0010】

In order to prevent this, the driver transistor 22 may be controlled so that the turn-off is performed gently. The damping circuit 21 of FIG. 8 is provided for this purpose, and the damping circuit 21 slowly turns off the driver transistor 22 over time. However, using such a damping circuit 21 limits the maximum frequency at which the device 20 can operate, which is not preferable.

【0011】

It has been thought that the only way to solve this problem is to improve the waveform at turn-off by making the length of the stub 11 extremely short. However, in order to sufficiently suppress the ringing waveform, it is necessary to eliminate the stub 11 and connect the device 20 directly to the bus 10. For example, if the device 20 is a memory IC, it is necessary to attach the memory IC directly to the bus wiring on the motherboard. In this case, it becomes impossible to use the memory IC in the module form. That is, since the memory IC is directly connected to the bus wiring, it becomes impossible to freely attach / detach the memory IC, for example, it becomes impossible to add a new memory IC.

【0012】

Further, when the memory IC is directly connected to the bus 10 by eliminating the stub 11, there is a problem that the memory chip cannot be miniaturized (shrinked). Memory makers achieve cost reduction by downsizing memory chips. However, when the chip is miniaturized, it is necessary to lengthen the lead frame that connects the external lead-out pin of the package and the memory chip inside the package without changing the wiring shape of the motherboard. However, if the lead frame is lengthened, stubs will eventually occur. Therefore, when the memory IC is directly connected to the bus, such shrink technology cannot be used.

【0013】

Another disadvantage of GTL is that the termination voltage is as low as 1.2 V, so one selected device outputs low output, another device is selected and this newly selected device outputs low output. When switching to, the signal level on the bus becomes an intermediate level between high and low.

【0014】

FIG. 12 is a diagram for explaining the process of generating an intermediate level voltage on the bus. In the first state, as shown in FIG. 12 (A), the driver D1 is selected from the driver D1 and the driver D2 connected to the bus 10 and is in the on state (low output state). In this state, the bus 10 is kept at a low potential (0.4 V), and the receiver R detects this low potential. At this time, a current of 32 mA flows through the driver D1.

【0015】

Next, as shown in FIG. 12B, the driver D1 is deselected and turned off, and at the same time, the driver D2 is selected and turned on (low output state). In this state, the bus 10 near the driver D1 is pulled up by the terminating resistor Rt1 to become a high potential (1.2 V), and this high potential is detected by the receiver R. However, in this state, the information that the driver D1 is turned off is not transmitted to the position of the driver D2. That is, the high potential pulled up by the terminating resistor Rt1 has not yet appeared at the position of the driver D2. Therefore, since the bus 10 near the driver D2 remains at a low potential (0.4 V), a sufficient current (32 mA) does not flow through the driver D2. That is, in the vicinity of the driver D2, the current supplied from the terminating resistor Rt2 flows into the driver D2 and at the same time in the direction of the driver D1 which is apparently still on. Therefore, it is equivalent to the state where both the driver D1 and the driver D2 are on, and the potential near the driver D2 of the bus 10 is slightly lower than 0.4 V.

【0016】

The state of FIG. 12 (C) is a state in which a little time has passed from FIG. 12 (B), the driver D1 is turned off, and the high potential pulled up by the terminating resistor Rt1 has reached the position of the driver D2. Is. In this state, it is detected that the device D1 is in the off state even at the position of the device D2, so that a sufficient current (32 mA) flows through the device D2 and the device D2 is completely turned on. The potential of bus 10 near device D2 is low potential (0.4 V). However, at this time, the information that the device D2 is completely turned on has not yet arrived at the receiver R. That is, the information in which the device D1 is turned off reaches the device D2, is folded back, and is heading toward the receiver R. That is, the state in which the receiver R can be detected is a state in which the driver D1 is turned off but the driver D2 is turned on halfway. In this state, the potential of the bus 10 near the driver D1 is at an intermediate level between the high potential and the low potential.

【0017】

FIG. 12 (D) shows a state in which the driver D1 is off and the driver D2 is on constantly. In this state, the information that the driver D2 is completely turned on is distributed throughout the bus 10, and the potential of the bus 10 and the potential detected by the receiver R are low potentials (0.4 V).

【0018】

In this way, the potential of the bus 10 instantaneously shows an intermediate level. Figure 13 shows the appearance of the intermediate level obtained by computer simulation. The waveform shown in FIG. 13 is a waveform detected by the receiver R in FIG. 12, and an intermediate level that is neither a high potential nor a low potential appears as shown by an arrow in the figure. As can be seen from the above description, it is inevitable that the waveform detected by the receiver R momentarily shows a high potential. However, the intermediate potential following the high potential unnecessarily limits the switching speed from device D1 to device D2. That is, since the signal voltage on the bus is not correct during the period indicated by T1 in the figure, it is necessary to wait for the operation of the system during the period of T1.

【0019】

The appearance of this intermediate potential can be avoided by increasing the terminal voltage 1.2 V of the bus 10 to about 2.5 V. For example, if a termination voltage of about 2.5 V is used, a high voltage will be applied to the drains of the transistors of drivers D1 and D2, and in the state shown in Fig. 12 (B), the driver D2 already has a sufficient current of 32 mA. Flows. Therefore, since the driver D2 is in a completely on state that draws in a sufficient amount of current from the beginning, an intermediate potential does not appear on the bus. In this way, if the system is operated in a range in which the driver transistor becomes a constant current source in the on state, the appearance of an intermediate potential can be avoided.

【0020】

However, if the terminating voltage is set to 2.5 V in GTL, the power consumption of the driver will increase significantly, which is not preferable. Therefore, an object of the present invention is to suppress ringing due to driver turn-off in a bus transmission system using an open-drain type driver and a terminating resistor without shortening the stub length.

【0021】

Another object of the present invention is to raise the terminating voltage in a bus transmission system using an open drain type driver and a terminating resistor to eliminate the intermediate potential state at the time of device switching and to avoid an increase in device power consumption. And.

【0022】

[Means for solving problems]

In the invention of claim 1, the signal transmission system includes a signal transmission line connected to a terminating potential via a terminating resistor, an open-drain type transistor that outputs a signal to the signal transmission line, and the open-drain type. It is characterized by including a branch wiring branched from the signal transmission line connecting the drain of the transistor and the signal transmission line, and a resistor inserted in the branch wiring in the vicinity of the signal transmission line.

【0023】

In the invention of claim 2, in the signal transmission system according to claim 1, the signal transmission line has a characteristic impedance Z.₀The branch wiring has a characteristic impedance Z₁And the resistance is (Z₁-Z₀It is characterized by having a resistance value in the range of + 100% to -50% of / 2).

【0024】

In the invention of claim 3, in the signal transmission system according to claim 1 or 2, the terminating resistor has the characteristic impedance Z.₀It is characterized by having a resistance value in the range of + 100% to -50%. The invention of claim 4 is characterized in that, in the signal transmission system according to claim 3, the termination potential is 2.5 V ± 0.25 V.

【0025】

The invention of claim 5 is characterized in that, in the signal transmission system according to claim 3 or 4, the resistance has a resistance value in the range of 24Ω to 51Ω. In the invention of claim 6, the semiconductor device module is a semiconductor device module connected to a signal transmission line connected to a terminal potential via a terminating resistor, and is arranged on a substrate and a side surface of the substrate. An electrode connected to the signal transmission line, a semiconductor device including an open-drain transistor that outputs a signal to the signal transmission line and mounted on a substrate, a drain of the open-drain transistor of the semiconductor device, and the electrode. It is characterized by including a connection wiring for connecting to and a resistor inserted in the vicinity of the signal transmission line in the connection wiring.

【0026】

In the invention of claim 7, in the semiconductor device module according to claim 6, the characteristic impedance of the signal transmission line is set to Z.₀As a result, the connection wiring has a characteristic impedance Z.₁And the resistance is (Z₁-Z₀It is characterized by having a resistance value in the range of + 100% to -50% of / 2).

【0027】

The invention of claim 8 is characterized in that, in the semiconductor device module according to claim 7, the resistance has a resistance value in the range of 24Ω to 51Ω. In the invention of claim 9, the signal transmission system is connected to a bus connected to a terminal potential via a terminating resistor and a first bus connected to the bus via a first branch wiring longer than a predetermined length. It is characterized by including a chip, a second chip connected to the bus via a second branch wiring shorter than a predetermined length, and a resistor inserted into the first branch wiring in the vicinity of the bus. ..

【0028】

In the invention of claim 10, in the signal transmission system according to claim 9, the first chip is a memory controller stored in a PGA package or a BGA package, and the second chip is the bus. Is a memory chip that is mounted vertically on a wired board.

【0029】

In the invention of claim 11, the input buffer circuit that receives the signal voltage having the center of the signal fluctuation in the vicinity of the power supply voltage includes a level shift circuit that shifts the voltage level between the signal voltage and the reference reference voltage, and the above-mentioned. Voltage of level shift circuit Includes a target voltage setting circuit that sets the target voltage after level shift, and a differential amplification circuit that amplifies the difference between the signal whose voltage level has been shifted by the level shift circuit and the reference reference voltage. It is characterized by that.

【0030】

In the invention of claim 12, the input buffer circuit that receives the signal voltage having the center of the signal fluctuation in the vicinity of the power supply voltage includes a differential amplification circuit that detects the voltage difference between the signal voltage and the reference reference voltage. It is characterized by including a current-voltage conversion circuit that receives a current corresponding to the voltage difference flowing through the differential amplification circuit and converts the current into a voltage.

【0031】

In the invention of claim 13, the input buffer circuit according to claim 12 further includes a current mirror circuit that duplicates the current flowing through the differential amplification circuit and provides it to the current-voltage conversion circuit. It is characterized by. In the invention of claim 14, the input buffer circuit that receives the signal voltage having the center of the signal fluctuation at the voltage close to the ground potential by a predetermined ratio or more between the power supply voltage and the ground potential is the signal voltage. It is characterized by including a differential amplification circuit that detects a voltage difference from a reference reference voltage and a current-voltage conversion circuit that receives a current corresponding to the voltage difference flowing through the differential amplification circuit and converts the current into a voltage. To do.

【0032】

In the invention of claim 15, the input buffer circuit according to claim 14 further includes a current mirror circuit that duplicates the current flowing through the differential amplification circuit and provides it to the current-voltage conversion circuit. It is characterized by. In the invention of claim 16, the semiconductor device connected to the signal transmission line connected to the termination potential via the terminating resistor transmits a signal to the electrode connected to the signal transmission line and the signal transmission line to the signal transmission line. It is characterized by including an output open-drain transistor, a connection wiring connecting the drain of the open-drain transistor and the electrode, and a resistor inserted in the vicinity of the signal transmission line in the connection wiring.

【0033】

In the invention of claim 17, in the semiconductor device according to claim 16, the characteristic impedance of the signal transmission line is set to Z.₀As a result, the connection wiring has a characteristic impedance Z.₁And the resistance is (Z₁-Z₀It is characterized by having a resistance value in the range of + 100% to -50% of / 2).

【0034】

In the invention of claims 1 to 3, 5 to 10, 16 and 17, a resistor is inserted in series with the wiring branched from the bus to achieve impedance matching between the branched wiring and the bus, thereby branching. Signal reflection at the junction between the wiring and the bus can be suppressed. Therefore, it is possible to suppress the generation of a violent ringing waveform due to the turn-off of the driver, so that high-speed and stable signal transmission can be performed. Further, by inserting a series resistor, the power consumption of the driver transistor can be reduced.

【0035】

In the invention of claim 4 above, by using a voltage of about 2.5 V as the terminating voltage, an intermediate potential state at the time of device switching in a signal transmission system using an open drain type driver transistor and a terminating resistor Can be eliminated. Further, by inserting a series resistor, the power consumption of the driver transistor can be reduced.

【0036】

In the inventions of claims 11 to 13, the signal voltage is referred to by performing level shift or current-voltage conversion in an input buffer circuit that receives a signal voltage having a center of signal fluctuation in the vicinity of the power supply voltage. The signal voltage can be detected as a high-level or low-level signal depending on the magnitude relationship with the reference voltage.

【0037】

In the inventions of claims 14 and 15, the signal voltage is referred to by performing level shift or current-voltage conversion in an input buffer circuit that receives a signal voltage having a center of signal fluctuation in the vicinity of the ground potential. The signal voltage can be detected as a high-level or low-level signal depending on the magnitude relationship with the reference voltage.

【0038】

BEST MODE FOR CARRYING OUT THE INVENTION

The principles and examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a bus transmission system based on the principle of the present invention. The bus transmission system of FIG. 1 includes series resistors Rs inserted in series between bus 10 and stub 11. The device 30 connected to the bus 10 includes an open-drain type driver transistor 31 having a drain connected to the stub 11, an output buffer 32, and an input buffer 33.

【0039】

The series resistance Rs is set so that the characteristic impedance when the direction from the stub 11 to the bus 10 is seen matches the characteristic impedance of the stub 11. Here, the characteristic impedance of the stub 11 is Z.₁The characteristic impedance when the direction from the stub 11 to the bus 10 is expected is the sum of the series resistance Rs and the characteristic impedance of the bus 10 extending in both directions. The characteristic impedance of bus 10 is Z.₀Therefore, the characteristic impedance of the bus 10 extending in both directions is Z.₀It becomes / 2. Therefore, the value of the series resistance is Rs = Z₁-Z₀/twenty one) Is set to. By inserting such a series resistor Rs, when the signal reflected at the end of the device goes to the bus 10, the impedance is matched between the stub portion 11 and the tip thereof, so that the reflection does not occur. Therefore, the ringing waveform as shown in FIG. 10 does not occur. In order to suppress the occurrence of ringing, it is desirable to insert the series resistor Rs as close as possible to the branch point where the bus 10 branches to the branch wiring (stub 11).

【0040】

By inserting this series resistor Rs, the voltage applied to the driver transistor 31 can be suppressed even when a voltage higher than 1.2 V of GTL is used for the terminating voltage Vtt. Therefore, the power consumed by the driver transistor 31 can be suppressed to the same extent as in the case of GTL. It is preferable to suppress the power consumption of the driver transistor 31 in this way when considering the heat dissipation of the chip on which the device 30 is mounted.

【0041】

In general, the characteristic impedance Z of bus 10₀About 50Ω, characteristic impedance Z of stub 11₁Is about 50Ω, and the value of the series resistance Rs is preferably about 25Ω. Actually, the value of series resistance Rs is (Z₁-Z₀If it is set in the range of -50% to + 100% with respect to the value of / 2), ringing can be suppressed satisfactorily. In addition, the characteristic impedance Z is used as the terminating resistor Rt.₀When a resistance value in the range of -50% to + 100% is used, and 2.5 V ± 0.25 V is used as the terminating resistance Vtt, the value of the series resistance Rs is 24 Ω to 51 Ω. Appropriate in terms of conditions and bus driving force. The value of this series resistance Rs is not so severe with respect to the quality of the bus transmission waveform.

【0042】

FIG. 2 shows the result of signal waveform simulation when the series resistor Rs is inserted under the same conditions as in FIG. However, it is assumed that the terminating voltage Vtt is 2.5 V and the series resistance Rs is 25 Ω. Fig. 2 (A) shows the case where the stub length is zero, Fig. 2 (B) shows the case where the stub length is 1 cm, and Fig. 2 (C) shows the case where the stub length is 2 cm. Indicates the case where the length of the stub is 5 cm. The solid line shows the waveform at the driver end on the device DV side that writes data to the memory, and the wavy line shows the waveform at the receiver end on the memory side. It can be seen that, unlike the case of GTL shown in FIG. 10, the occurrence of ringing is suppressed by inserting the series resistor Rs. Also, as shown in Figure 2 (D), the system is operational even if the stub is as long as 5 cm.

【0043】

As shown in FIG. 2, even when the series resistor Rs is inserted, an overshoot is observed on the driver side when shifting from the low potential to the high potential due to the turn-off of the driver transistor. In GTL, the damping circuit 21 shown in FIG. 1 was used to suppress the occurrence of this overshoot at the expense of operating speed. However, when the series resistor Rs is inserted as in the present invention, there is no concern about ringing, so it is not necessary to suppress overshoot. Rather, it is preferable that an overshoot occurs because it has the effect of accelerating the transition of the input signal and accelerating the switching speed as a result. In other words, if there is a slight inductance component in series with the driver, the transient voltage at the driver end at the time of switch-off will be higher, and the reception waveform will be faster.

【0044】

In the explanation so far, a voltage value of 2.5 V is used as an example when the terminating voltage Vtt is increased. In fact, this voltage value of 2.5 V is an appropriate value for the termination voltage Vtt, and the rationality of this value will be explained below. First, consider the sensitivity of the input receiver circuit (input circuit 33 in FIG. 1) as a limiting factor. Considering that the input signal circuit operates at a higher speed when the amplitude of the input signal is larger, in reality, the input signal needs to have an amplitude of about ± 0.2 V with respect to the center voltage.

【0045】

In order to reliably realize this input amplitude condition, the output signal must have an amplitude of about ± 0.4 V (amplitude of about 0.8 V peak-to-peak) on bus 10 (Fig. 1). is there. The high level of the output signal is equal to the termination voltage Vtt, so the low level is equal to (Vtt-0.8 V). That is, when the driver transistor 31 (FIG. 1) is on, the potential of the bus 10 becomes (Vtt-0.8) V, and when the driver transistor 31 is off, the potential of the bus 10 becomes Vtt. In this way, in order to realize an amplitude of 0.8 V by switching the driver transistor 31 on / off, the terminating resistor Rt is set to 50 Ω, and the driver transistor 31 has a drive current of 32 mA (= 0.8 V / (50 / 2 Ω)). Is required.

【0046】

When the driver transistor 31 is on, the potential of bus 10 is (Vtt-0.8 V), and the voltage drop at the series resistance Rs (25 Ω) is 0.8 V (= 32 mA × 25 Ω). Therefore, the drain voltage of the driver transistor 31 is (Vtt-1.6 V). Conversely, the terminating voltage Vtt needs to be about 1.6 V higher than the drain voltage.

【0047】

In addition, in order for the driver transistor 31 to have sufficient driving force, this drain voltage must be in the range of about 0.4 V to 0.9 V. Since the termination voltage Vtt needs to be 1.6 V higher than the drain voltage, the proper range for the termination voltage Vtt is about 2 V to 2.5 V after all.

【0048】

In practice, the drain voltage of the transistor is preferably closer to 0.9 V than 0.4 V. The first reason is that the driving force of the transistor can be increased by using a drain voltage close to 0.9 V, so that the driving force within a desired range can be obtained even by using a small transistor. .. Second, if two driver transistors connected to the bus are turned on at the same time (occurred in the process of switching devices that output transiently), it is better to use a higher drain voltage to draw current in parallel to the two driver transistors. It is easy to supply.

【0049】

Therefore, the preferred termination voltage Vtt value is 2.5 V. If a voltage higher than this is used, the performance is further improved, but at the same time, the power consumption is increased, which is not preferable. Therefore, in reality, it is desirable that the terminating resistor Vtt is about 2.5 V ± 0.25 V. On the other hand, if there is a strong demand to reduce power consumption, it is desirable that the Vtt value is about 2.0 V ± 0.2 V, allowing some deterioration in response characteristics. However, if the terminal voltage is lower than this, sufficient driving force cannot be obtained due to the fact that a series resistor is inserted in the output, which is not preferable.

【0050】

However, in the present invention, the terminating voltage Vtt is not limited to 2.5 V. As shown in Examples described later, for example, the terminating voltage Vtt may be set as the ground potential by reversing the high-low relationship of the voltage. FIG. 3 shows a first embodiment of the bus transmission system according to the present invention. In FIG. 3, the same components as those in FIG. 1 are referred to by the same number, and the description thereof is omitted.

【0051】

In FIG. 3, the output buffer 32 includes a MOSFET transistor 41 and an MIMO transistor 42. The MOSFET transistor 41 and the NMOS transistor 42 form an inverter circuit and operate so as to invert the output signal. That is, when the output signal is high, low is supplied to the gate of the driver transistor 31 to turn off the driver transistor 31. On the contrary, when the output signal is low, high is supplied to the gate of the driver transistor 31 to turn on the driver transistor 31.

【0052】

The input buffer 33 includes IMS transistors 51 to 54, MOSFETs 55 and 56, IMS transistors 57 to 61, differential amplifiers 62, resistors R1 and R2, MOSFET transistors 71, and NMOS transistors 72. Here, the NMOS transistors 51 to 54 form a level shifter circuit, and the MIMO transistors 55 and 56 and the NMOS transistors 57 to 59 form a differential amplifier. Further, the NMOS transistors 60 and 61, the differential amplifier 62, and the resistors R1 and R2 form an automatic level adjuster. This level automatic adjuster automatically adjusts the magnitude of the level shift of the level shifter circuit. Further, the MIMO transistor 71 and the MIMO transistor 72 constitute an inverter.

【0053】

The reason why the input buffer 33 requires the level shift function is that the input signal fluctuates in a narrow range centered on 2.2 V with respect to the power supply voltage of the input buffer 33 of 2.5 V. When an input signal whose signal fluctuates in a range close to the power supply voltage is given in this way, high / low judgment is performed by an input buffer using a normal differential amplifier (for example, the input buffer circuit in FIG. 1). I can't. Therefore, in the input buffer circuit 33 of FIG. 3, the input signal voltage and the reference reference voltage are once leveled down by the level shifter circuit, and the high / low determination is performed for the leveled down voltage by using a differential amplifier. ..

【0054】

In the level shifter circuit consisting of the NMOS transistors 51 to 54, the NMOS transistors 53 and 54 operate as a constant current source adjusted to an appropriate current amount by the adjusting voltage Vadj. Therefore, a constant current flows through the NMOS transistors 51 and 53, and the same constant current flows through the NMOS transistors 52 and 54. In this state, the input signal voltage, which is the gate input of the NMOS transistor 51, and the reference reference voltage Vref, which is the gate input of the NMOS transistor 52, are voltage-shifted by the threshold voltage of the NMOS transistor, respectively, to nodes A and B. Appears. The level-shifted voltage appearing at the nodes A and B is supplied to the lower differential amplifier. Here, the adjusting voltage Vadj is generated by a level automatic regulator composed of NMOS transistors 60 and 61, a differential amplifier 62, and resistors R1 and R2. First, resistors R1 and R2 form a voltage divider to generate a level shift target voltage. For example, if you want to level shift the reference reference voltage Vref (2.2 V) to 1.3 V with the level shift circuit described above, 1.3 with a voltage divider. Generate a voltage of V. The NMOS transistors 60 and 61 form the same circuit (replica circuit) as the NMOS transistors 52 and 54 of the level shifter circuit. The voltage appearing at the node C between the NMOS transistors 60 and 61 and the target voltage generated by the voltage divider are input to the differential amplifier 62. The differential amplifier 62 amplifies the difference between the two voltages and outputs it as the adjustment voltage Vadj. The adjustment voltage Vadj is input to the gate of the NMOS transistor 61. By this feedback, the voltage appearing at the node C and the target voltage are controlled to be the same.

【0055】

That is, the adjustment voltage Vadj input to the gate of the NMOS transistor 61 of the replica circuit is a voltage that matches the voltage of the node C of the replica circuit with the target voltage. Since this adjusting voltage Vadj is supplied to the NMOS transistors 53 and 54 of the level shifter circuit as a gate input, a downshift voltage equal to the target voltage appears at the node B.

【0056】

The differential amplifier consisting of the MOSFET transistors 55 and 56 and the MIMO transistors 57 to 59 compares the downshifted input signal voltage with the reference reference voltage Vref and supplies the output to the inverter consisting of the MOSFET transistors 71 and the MIMO transistors 72. To do. The inverter inverts the supplied signal and supplies it to the internal circuit as an input signal.

【0057】

As described above, in the first embodiment, the input signal voltage and the reference reference voltage are level-shifted by the level shifter circuit, and the level-shifted voltages are compared with each other by the differential amplifier to high / low the input signal. Make a judgment. At this time, the downshift voltage of the level shift circuit is set to the target voltage by performing feedback control so that the replica circuit of the level shift circuit generates a voltage equal to the target voltage of the level shift.

【0058】

FIG. 4 shows a second embodiment of the bus transmission system according to the present invention. In FIG. 4, the same components as those in FIG. 3 are referred to by the same number, and the description thereof is omitted. The input buffer 33A of FIG. 4 includes IMS transistors 81 to 83, MIMO transistors 84 to 87, IMS transistors 88 to 90, and a MOSFET transistor 91. Here, the NMOS transistors 81 to 83 operate as a differential amplifier. Each pair of the photoresist transistors 84 and 85 and the MIMO transistors 86 and 87 operates as a current mirror circuit. Further, the MIMO transistors 84 and 87 and the NMOS transistors 88 and 89 operate as a circuit for converting a current into a voltage. The NMOS transistor 90 and the MIMO transistor 91 constitute an inverter.

【0059】

The input signal voltage input to the gate of the NMOS transistor 81 is compared with the reference reference voltage Vref which is the gate input of the NMOS transistor 82. That is, a voltage difference appears between the drains of the NMOS transistors 81 and 82 according to the difference between the two voltages. However, as described above, since the input signal is a signal that fluctuates around a voltage close to the power supply voltage, the voltage appearing in the drains of the NMOS transistors 81 and 82 does not have a sufficient voltage amplitude. That is, since the gate voltage of the NMOS transistors 81 and 82 is high, the drain voltage has a small amplitude fluctuation at a high voltage. Therefore, this drain voltage cannot be supplied to the internal circuit as a signal.

【0060】

Here, the drain voltage of the NMOS transistors 81 and 82 has a small amplitude, but the current flowing through each transistor fluctuates with a sufficient amplitude. Therefore, in the second embodiment, the drain current is supplied to the current-voltage conversion circuit via the current mirror circuit instead of the small-amplitude drain voltage of the MIMO transistors 81 and 82, and the current fluctuation is performed by this current-voltage conversion circuit. Is converted into a large amplitude voltage fluctuation.

【0061】

As shown in FIG. 4, the drain of the NMOS transistor 81 is connected to the current input (gate input) of the current mirror circuit composed of the MOSFETs 84 and 85, and the drain of the NMOS transistor 82 is the current mirror composed of the MOSFETs 86 and 87. It is connected to the current input (gate input) of the circuit. Therefore, the same current as the PMOS transistor 85 flows through the PMOS transistor 84, and the same current as the PMOS transistor 86 flows through the PMOS transistor 87. The current-voltage conversion circuit including the MOSFET transistors 84 and 87 and the NMOS transistors 88 and 89 generates a voltage at the node D according to the difference between the current flowing through the MOSFET transistor 84 and the current flowing through the MOSFET transistor 87. That is, a voltage corresponding to the difference between the input signal voltage and the reference reference voltage Vref appears in the node D. Here, the drain voltages of the MIMO transistors 84 and 87 and the MIMO transistors 88 and 89 have a margin sufficient to allow a sufficiently large fluctuation. Therefore, the voltage appearing at the node D becomes a high level or a low level depending on the magnitude relationship between the input signal voltage and the reference reference voltage Vref.

【0062】

The voltage appearing on this node D is inverted by an inverter including an NMOS transistor 90 and a MOSFET transistor 91, and the inverted voltage is supplied to an internal circuit. Thus, in the second embodiment, when the input signal is a signal that fluctuates around a voltage close to the power supply voltage, the difference between the input signal voltage detected by the differential amplifier and the reference reference voltage A corresponding current having a sufficient amplitude is supplied to a current-voltage conversion circuit via a current mirror circuit to convert it into a voltage having a sufficient amplitude. As a result, a voltage signal obtained by amplifying the difference between the input signal voltage and the reference reference voltage can be obtained, and a high or low signal can be supplied according to the magnitude relationship between the input signal voltage and the reference reference voltage. ..

【0063】

FIG. 5 shows a third embodiment of the bus transmission system according to the present invention. In FIG. 5, the same components as those in FIG. 4 are referred to by the same number, and the description thereof is omitted. The third embodiment of the bus transmission system according to the present invention reverses the high-low relationship of the voltage with the second embodiment of FIG. That is, in the bus transmission system of FIG. 5, the termination of the bus 10 is performed by connecting to the ground via a terminating resistor Rt of 50Ω. The driver transistor 31A has been changed to a MIMO transistor. Even with such a configuration, it is clear that the effects of ringing suppression and power consumption suppression by inserting the series resistors Rs can be obtained in the same manner as in the above-described embodiment. Achieving termination by grounding in this way is advantageous in that it is not necessary to change the system design even if the power supply voltage is changed in the future.

【0064】

The input buffer 33B of FIG. 5 includes the MIMO transistors 81A to 83A, the NMOS transistors 84A to 87A, the MOSFETs 88A to 90A, and the NMOS transistors 91A. Here, the MIMO transistors 81A to 83A operate as a differential amplifier. Each pair of the NMOS transistors 84A and 85A and the NMOS transistors 86A and 87A operates as a current mirror circuit. Further, the MIMO transistors 84A and 87A and the MIMO transistors 88A and 89A operate as circuits that convert current into voltage. The facsimile transistor 90A and the MMOS transistor 91A constitute an inverter.

【0065】

Since the operation of the input buffer 33B of FIG. 5 is the same as the operation of the input buffer 33A of FIG. 4, the description thereof will be omitted. In this case, since the input signal is a signal that fluctuates around a voltage (0.3 V) close to the ground potential, the reference reference voltage Vref supplied to the input buffer 33B is 0.3 V.

【0066】

Thus, in the third embodiment, the input signal detected by the differential amplifier when the bus termination is provided by grounding and the input signal is a signal that fluctuates around a voltage close to the ground potential. A current having a sufficient amplitude corresponding to the difference between the voltage and the reference reference voltage is supplied to the current-voltage conversion circuit via the current mirror circuit to convert the voltage into a voltage having a sufficient amplitude. As a result, a voltage signal obtained by amplifying the difference between the input signal voltage and the reference reference voltage can be obtained, and a high or low signal can be supplied according to the magnitude relationship between the input signal voltage and the reference reference voltage. ..

【0067】

In realizing the bus transmission system according to the present invention, it is not always necessary to insert the series resistor Rs into the driver end of all devices. Some devices inevitably have long stub lengths, while others can achieve relatively short stub lengths. Therefore, if the series resistor Rs is inserted into the device having a long stub length, stable system operation can be realized without inserting the series resistor Rs into the device having a relatively short stub length.

【0068】

For example, in a BGA (Ball Grid Array) package or a PGA (Pin Grid Array) package, a long lead wire connects the I / O circuit arranged around the semiconductor chip to the output electrode (ball or pin). There is a need. Therefore, since the stub length is inevitably quite long, it is desirable to insert a series resistor Rs in order to suppress ringing. On the other hand, for example, in the case of a memory chip package or the like that is vertically erected and attached to the board, the stub length can be considerably shortened. Therefore, there is no problem even if the series resistor Rs is not inserted for the vertically mounted memory chip package. However, even in such a memory chip package, when the internal memory chip is reduced by shrink technology, the stub length becomes long, and it is necessary to insert a series resistor Rs.

【0069】

FIG. 6 schematically shows a fourth embodiment of the bus transmission system according to the present invention. This bus transmission system includes a memory and a controller, inserting series resistors Rs into the controller chip mounted in the BGA package and in series with the memory chip housed in the vertically mounted package. Do not insert resistors Rs.

【0070】

The bus transmission system of FIG. 6 includes a bus 10 connected to a terminating voltage Vtt by a terminating resistor Rt, a printed board 120 to which the bus 10 is wired, and a controller chip 100 mounted on the printed board 120 and connected to the bus 10. Includes a plurality of memory chips 110. The controller chip 100 is mounted on the board 102 and is connected to the ball electrode 104 via the bonding wire 101 and the lead 103. The ball electrode 104 is connected to the bus 10 via the resistor Rs. The bus 10 naturally consists of a plurality of wires, and the ball electrode 104 and the series resistance Rs exist for the number of wires of the bus 10, but only one for one bus wire is shown in consideration of the legibility of the drawing.

【0071】

Each of the plurality of memory chips 111 is stored in the memory package 110 and connected to the bus 10 via the output pin 112. Since the output pin 112 is short, severe ringing does not occur even if the series resistor Rs is not inserted. If a series resistor Rs is inserted for a chip stored in a package that requires a long stub such as a BGA package or PGA package in this way, a short stub length such as a vertically mounted memory chip is sufficient. Even if a series resistor Rs is not inserted in the stub, stable system operation can be realized without the occurrence of severe ringing in the entire bus transmission system.

【0072】

FIG. 7 shows a semiconductor device module according to the present invention. In the semiconductor device module according to the present invention, series resistors Rs are inserted into the wiring (corresponding to a stub) between the electrodes on the side surface of the printed circuit board and the chips mounted on the printed circuit board. In FIG. 7, for example, a DIMM is assumed, and the DIMM 130 is mounted on the bus 10. The DIMM 130 includes a printed circuit board 131, memory chips 132 and 133 mounted on the printed circuit board, electrodes 140 for bus connection, wiring 141 connecting the electrodes 140 and memory chips 132 and 133, and series resistors inserted in the wiring 141. Including Rs. Since the series resistors Rs are inserted, it is possible to suppress ringing and power consumption in the chip.

【0073】

As shown in FIG. 7, in a semiconductor device module such as a DIMM or SIMM in which a series resistor is inserted, even if the length of the wiring 141 fluctuates due to a change in the size of the chip mounted on the printed circuit board, The signal transmission characteristics are unchanged. Therefore, if the shrink technology enables the production of smaller chips, the manufacturer can achieve cost reduction.

【0074】

The present invention is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the scope of claims.

【0075】

[Effect of the invention]

In the inventions of claims 1 to 3, 5 to 10, 16 and 17, a resistor is inserted in series with the wiring branched from the bus to match the impedance between the branch wiring and the bus, thereby performing the branch wiring. It is possible to suppress signal reflection at the junction between the bus and the bus. Therefore, it is possible to suppress the generation of a violent ringing waveform due to the turn-off of the driver, so that high-speed and stable signal transmission can be performed. Further, by inserting a series resistor, the power consumption of the driver transistor can be reduced.

【0076】

In the invention of claim 4, by using a voltage of about 2.5 V as the terminating voltage, an intermediate potential state at the time of device switching can be obtained in a signal transmission system using an open drain type driver transistor and a terminating resistor. It can be eliminated. Further, by inserting a series resistor, the power consumption of the driver transistor can be reduced.

【0077】

In the inventions of claims 11 to 13, the signal voltage and the reference reference are obtained by performing level shift or current-voltage conversion in the input buffer circuit that receives the signal voltage having the center of the signal fluctuation in the vicinity of the power supply voltage. The signal voltage can be detected as a high-level or low-level signal depending on the magnitude relationship with the voltage.

【0078】

In the inventions of claims 14 and 15, the signal voltage and the reference reference are obtained by performing level shift or current-voltage conversion in the input buffer circuit that receives the signal voltage having the center of the signal fluctuation in the vicinity of the ground potential. The signal voltage can be detected as a high-level or low-level signal depending on the magnitude relationship with the voltage.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the principle of the signal transmission system by this invention.

[Figure 2]

(A) to (D) are signal waveform diagrams by computer simulation showing the effect of ringing suppression according to the present invention.

[Fig. 3]

It is a figure which shows the 1st Example of the signal transmission system by this invention.

[Fig. 4]

It is a figure which shows the 2nd Example of the signal transmission system by this invention.

[Fig. 5]

It is a figure which shows the 3rd Example of the signal transmission system by this invention.

[Fig. 6]

It is a figure which shows the 4th Example of the signal transmission system by this invention.

[Fig. 7]

It is a figure which shows the semiconductor device module by this invention.

[Fig. 8]

It is a figure which shows the structure of the conventional GTL transmission system.

[Fig. 9]

It is a figure for demonstrating the ringing occurrence in the conventional GTL transmission system.

[Fig. 10]

(A) to (D) are signal waveform diagrams by computer simulation showing the state of ringing occurrence in the conventional GTL transmission system.

[Fig. 11]

It is a figure which shows the computer simulation condition of FIG.

[Fig. 12]

(A) to (D) are diagrams for explaining the mechanism of intermediate potential generation in the conventional GTL transmission system.

[Fig. 13]

It is a signal waveform diagram by a computer simulation which shows the state of the intermediate potential generation in the conventional GTL transmission system.

[Explanation of symbols]

10 buses 11 stub 20 devices 21 Damping circuit 22 driver transistor 30 devices 31 driver transistor 31A driver transistor 32 output buffer 33 Input buffer 33A input buffer 33B input buffer 100 controller chip 101 bonding wire 102 board 103 lead 104 ball electrode 110 package 111 Memory chip 112 pins 120 printed circuit board 130 DIMM 131 printed circuit board 132 Memory chip 133 Memory chip 140 electrodes 141 Wiring