Data driver of liquid display panel

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a data driver for a liquid crystal display panel suitable for use in performing a display test of an active matrix type liquid crystal display panel that displays by causing each pixel arranged in a matrix to perform a storage operation.

【0002】

[Conventional technology]

The active matrix type liquid crystal display panel forms pixel electrodes in a matrix and is connected between a data line (signal electrode), a scan line (scan electrode), and the data line and the pixel electrode to form a scan line. A pixel electrode substrate (TFT substrate) formed by forming a TFT (thin film transistor) forming a switching element in which conduction and non-conduction are controlled via a common electrode substrate and a common electrode substrate formed by forming a common electrode common to all pixel electrodes. It is constructed by enclosing a liquid crystal between the two.

【0003】

The peripheral circuit that drives the active matrix liquid crystal display panel configured in this way has a data driver that applies the gradation voltage required for image display to the data line, and the conduction and non-conduction of the TFT via the scan line. It consists of a scan driver to control.

【0004】

Then, the scan driver makes the TFT of each line conductive in order through the scan line of each line, and the gradation voltage applied to the data line from the data driver is written to the pixel electrode of each line via the conductive TFT. By doing so, the display is performed.

【0005】

Here, the data driver can be roughly classified into an analog data driver to which an analog signal is supplied and a digital data driver to which a digital signal is supplied as display data from the display data source. FIG. 52 shows the main part of an example of a conventional digital data driver.

【0006】

In Fig. 52, 1 is the clock signal CLK of the start pulse SP supplied at a rate of 1 in 1 horizontal period that determines the start of acquisition of the display data DATA of the 6-bit configuration D0 to D5 supplied from the display data source. This is a shift register unit that sequentially outputs the display data capture signals SB1, SB2 ... SB240 synchronized with the clock signal CLK by shifting in synchronization with.

【0007】

Reference numeral 2 denotes a data register unit that is controlled by the display data capture signals SB1, SB2 ... SB240 output from the shift register unit 1 and sequentially captures display data DATA for 240 pixels.

【0008】

In addition, 3 is a latch unit that latches the display data DATA of 240 pixels captured in the data register unit 2 by the latch pulse LP at the same time, and 4 is the display data DATA of 240 pixels latched by the latch unit 3. This is a decoder unit that decodes.

【0009】

Reference numeral 5 denotes a gradation voltage generator that generates the gradation voltages VB63, VB62 ... VB0 required for displaying 64 gradations from the DC voltages VA8, VA7 ... VA0 supplied from the outside.

【0010】

Further, 6 selects the gradation voltage VB63, VB62 ... VB0 output from the gradation voltage generation unit 5 based on the output of the decoder unit 4, and sets the gradation voltage corresponding to the display data DATA as an active matrix. It is a selector part that outputs to the data lines DB1, DB2 ... DB240 of the liquid crystal display panel of the system.

【0011】

[Problems to be Solved by the Invention]

In order to guarantee the display quality of the active matrix type liquid crystal display panel, it is necessary to perform a display test by displaying a test pattern, but conventionally, this display test is necessary for displaying the test pattern. This is done by preparing a display tester that generates test data, supplying the test data generated by this display tester to the data driver, and displaying the test pattern on the active matrix liquid crystal display panel. Was there.

【0012】

However, when creating an active matrix type liquid crystal display panel with different operating conditions such as operating frequency, a display tester must be created for each, and the display tester itself needs to be tested. Therefore, there is a problem that a large amount of time and cost are required for the display test.

【0013】

In view of this point, the present invention eliminates the need for a display tester that generates test data necessary for displaying a test pattern, and easily and inexpensively performs a display test of an active matrix type liquid crystal display panel. It is an object of the present invention to provide a data driver for a liquid crystal display panel that enables the user.

【0014】

[Means for solving problems]

In the present invention, the first invention (the data driver of the liquid crystal display panel according to claim 1) forms pixel electrodes in a matrix and between the data line, the scan line, and the data line and the pixel electrode. Between the first substrate, which is connected and forms a switching element whose conduction and non-conduction are controlled via a scan line, and the second substrate, which forms a common electrode common to all pixel electrodes. A test that generates test data necessary for displaying a test pattern on the liquid crystal display panel in a data driver of the liquid crystal display panel that applies a gradation voltage to the data line of the liquid crystal display panel configured by enclosing the liquid crystal. Data generation unit, gradation voltage generation unit that generates multiple gradation voltages with different voltage values, and gradation voltage corresponding to the test data are selected from the plurality of gradation voltages and applied to the data line. It is said that it is provided with a gradation voltage selection unit.

【0015】

In the first invention, since the liquid crystal display panel includes a test data generator that generates test data necessary for displaying the test pattern, the test pattern is displayed in addition to the data driver. There is no need for a display tester to generate the test data required for.

【0016】

Further, in the second invention (the data driver of the liquid crystal display panel according to claim 2), in the first invention, the test data generator is used as a vertical synchronization signal, a horizontal synchronization signal or a clock signal supplied from the outside. Based on the test data generator that generates multiple types of test data required to display multiple types of test patterns, and test data that selects one type of test data from multiple types of test data. It is equipped with a selection unit.

【0017】

Further, in the third invention (the data driver of the liquid crystal display panel according to claim 3), in the second invention, the test data generation unit performs all or a part of a plurality of types of test data at regular time intervals. It is to generate test data that reverses the display polarity.

【0018】

Further, in the fourth invention (the data driver of the liquid crystal display panel according to claim 4), in the first invention, the test data generator is required to display a plurality of types of test patterns. The test data storage unit and the test data storage unit, which stores the test data for each data unit to be output at consecutive addresses and specifies the test data to be output by the test pattern selection signal supplied from the outside, and the test An address signal for addressing to an address area in the address area of the test data storage unit based on the test pattern selection signal, in which test data corresponding to the test pattern specified by the test pattern selection signal is stored. It is said that it is provided with an address signal generation unit that generates data.

【0019】

Further, according to the fifth invention (the data driver of the liquid crystal display panel according to claim 5), in the fourth invention, the address signal generation unit includes an addressing direction switching means for switching the addressing direction at regular time intervals. It is a thing.

【0020】

Further, the sixth invention (the data driver of the liquid crystal display panel according to claim 6) is the second, third, fourth or fifth invention in which the plurality of types of test patterns include a horizontal grayscale pattern. , Vertical grayscale pattern, horizontal stripe pattern, vertical stripe pattern, checkered pattern or full-scale solid pattern.

【0021】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the first and second embodiments of the embodiment of the present invention will be described with reference to FIGS. 1 to 51.

【0022】

First form ... Fig. 1 to Fig. 27 FIG. 1 is a circuit diagram showing a main part of the first embodiment of the present invention. In the first embodiment of the present invention, instead of supplying the display data DATA supplied from the outside to the data register unit 2, a test pattern is created based on the vertical synchronization signal VS, the horizontal synchronization signal HS, or the clock signal CLK. A test data generation unit 9 for generating test data TDATA of 6-bit configuration D0 to D5 required for display is provided, and test data TDATA is supplied to the data register unit 2. Others are shown in FIG. 52. It is configured in the same way as the conventional data driver shown.

【0023】

FIG. 2 is a circuit diagram showing the configuration of the test data generation unit 9. In FIG. 2, 10 shows horizontal stripe pattern display data or vertical stripe pattern display data, horizontal grayscale pattern display data, and vertical grayscale as test data TDATA based on the vertical synchronization signal VS, horizontal synchronization signal HS, or clock signal CLK. -A test data generation unit that generates pattern display data, checkered pattern display data, and full-scale solid pattern display data.

【0024】

Further, in the test data generation unit 10, 11 is a 12-bit counter in which the vertical synchronization signal VS is input to the counted signal input terminal IN as a counted signal, and Q0 to Q11 are the 1st to 12th bits, respectively. This is the output terminal from which the eye count value is output. In this example, the output terminals Q0 to Q5 are not used, and only the output terminals Q6 to Q11 are used.

【0025】

FIG. 3 is a waveform diagram showing the operation of the 12-bit counter 11, and FIG. 3 (A) shows the logic levels of the vertical synchronization signal VS and the output terminals Q0 to Q6 input to the counted signal input terminal IN. , Fig. 3 (B) shows the output signals output to the output terminals Q6 to Q11 with the time axis reduced.

【0026】

Further, in FIG. 2, in FIG. 12, the horizontal synchronization signal HS or the clock signal CLK is input to the counted signal input terminal IN as a counted signal, and the output signal output to the output terminal Q6 of the 12-bit counter 11 is up / down. Up / down control signal input terminal as a control signal This is a 6-bit up / down counter that is input to the U / D, and Q0 to Q5 are output terminals that output the count values of the 1st to 6th bits, respectively. is there.

【0027】

The 6-bit up / down counter 12 performs an up / count operation when the logic level of the up / down control signal input terminal U / D is set to "0", and inputs the up / down control signal. When the logic level of the terminal U / D is set to "1", it is configured to perform a down count operation.

【0028】

FIG. 4 is a waveform diagram showing the operation of the 6-bit up / down counter 12, and FIG. 4 (A) shows the case where the horizontal synchronization signal HS is up-counted (when U / D = "0"). The logical level of the output terminals Q0 to Q6 in the above, and Fig. 4 (B) shows the logical level of the output terminals Q0 to Q6 when the horizontal synchronization signal HS is down-counted (when U / D = "1"). ing.

【0029】

Here, when the horizontal synchronization signal HS is input to the counted signal input terminal IN of the 6-bit up / down counter 12, the 12-bit counter 11 and the 6-bit up / down counter 12 are used. , The horizontal stripe pattern display data generation unit that generates the horizontal stripe pattern display data necessary for displaying the horizontal stripe pattern is configured.

【0030】

On the other hand, when the clock signal CLK is input to the counted signal input terminal IN of the 6-bit up / down counter 12, the 12-bit counter 11 and the 6-bit up / down counter 12 Therefore, the vertical stripe pattern display data generation unit that generates the vertical stripe pattern display data necessary for displaying the vertical stripe pattern is configured.

【0031】

Further, in FIG. 2, 13 is a D flip-flop circuit constituting a 1/2 divider in which the reverse phase output terminal / Q is connected to the data input terminal D and the horizontal synchronization signal HS is input to the clock signal input terminal C. Is.

【0032】

Reference numeral 14 denotes an AND circuit that AND processes the output signal output to the output terminal Q6 of the 12-bit counter 11 and the output signal output to the positive phase output terminal Q of the D flip-flop circuit 13.

【0033】

Further, 15 is a NOT circuit that inverts the output signal output to the output terminal Q6 of the 12-bit counter 11, and 16 is output to the output signal of the NOT circuit 15 and the reverse phase output terminal / Q of the D flip-flop circuit 13. An AND circuit that performs AND processing with the output signal, and 17 is an OR circuit that OR processes the output signal of the AND circuit 14 and the output signal of the AND circuit 16.

【0034】

Here, the 12-bit counter 11, the D flip-flop circuit 13, the AND circuits 14, 16 and the NOT circuit 15 and the OR circuit 17 are used to display the horizontal grayscale pattern. A horizontal grayscale pattern display data generation unit that generates pattern display data is configured.

【0035】

Reference numeral 18 denotes a D flip-flop circuit constituting a 1/2 divider in which the opposite phase output terminal / Q is connected to the data input terminal D and the clock signal CLK is input to the clock signal input terminal C.

【0036】

Reference numeral 19 denotes an AND circuit that AND processes the output signal output to the output terminal Q6 of the 12-bit counter circuit 11 and the output signal output to the positive phase output terminal Q of the D flip-flop circuit 18.

【0037】

Further, 20 is a NOT circuit that inverts the output signal output to the output terminal Q6 of the 12-bit counter 11, and 21 is output to the output signal of the NOT circuit 20 and the reverse phase output terminal / Q of the D flip-flop circuit 18. The AND circuit that AND-processes the output signal, and 22 is an OR circuit that OR-processes the output signal of the AND circuit 19 and the output signal of the AND circuit 21.

【0038】

Here, the vertical grayscale pattern required to display the vertical grayscale pattern with the 12-bit counter 11, the D flip-flop circuit 18, the AND circuits 19, 21, the NOT circuit 20, and the OR circuit 22. A vertical grayscale pattern display data generation unit that generates pattern display data is configured.

【0039】

Further, 23 performs EOR (exclusive OR) processing of the output signal output to the positive phase output terminal Q of the D flip-flop circuit 13 and the output signal output to the positive phase output terminal Q of the D flip-flop circuit 18. The EOR circuit 24 is an EOR circuit that EOR-processes the output signal output to the output terminal Q6 of the 12-bit counter 11 and the output signal of the EOR circuit 23.

【0040】

Here, the 12-bit counter 11, the D flip-flop circuits 13 and 18, and the EOR circuits 23 and 24 form a checkerboard pattern display data generation unit that generates the checkerboard pattern display data necessary for displaying the checkerboard pattern. Has been done.

【0041】

Further, the 12-bit counter 11 constitutes a full-face solid pattern display data generation unit that generates full-face solid pattern display data necessary for displaying the full-face solid pattern.

【0042】

In addition, 25 is a selector, XA0 to XA5, XB0 to XB5, XC0 to XC5, XD0 to XD5, XE0 to XE5 are input terminals, Q0 to Q5 are output terminals, and SL0, SL1 and SL2 are select control signals.

【0043】

The output signal output to the output terminals Q0 to Q5 of the 6-bit up / down counter 6 is input to the input terminals XA0 to XA5, and the output signal of the OR circuit 17 is input to the input terminals XB0 to XB5. , The output signal of the OR circuit 22 is input to the input terminals XC0 to XC5, the output signal of the EOR circuit 24 is input to the input terminals XD0 to XD5, and the output terminal of the 12-bit counter 11 is input to the input terminals XE0 to XE5. The output signal output to Q6 to Q11 is input.

【0044】

When the select control signals SL0 = "0", SL1 = "0", and SL2 = "0" are set here, the input terminals XA0 to XA5 are selected, and the input terminals XA0 to XA5 and the output terminals Q0 to Q5 are selected. And are connected.

【0045】

When the select control signals SL0 = "1", SL1 = "0", and SL2 = "0" are set, the input terminals XB0 to XB5 are selected, and the input terminals XB0 to XB5 and the output terminals Q0 to Q5. Is connected.

【0046】

When the select control signals SL0 = "0", SL1 = "1", and SL2 = "0" are set, the input terminals XC0 to XC5 are selected, and the input terminals XC0 to XC5 and the output terminals Q0 to Q5. Is connected.

【0047】

When the select control signals SL0 = "1", SL1 = "1", and SL2 = "0" are set, the input terminals XD0 to XD5 are selected, and the input terminals XD0 to XD5 and the output terminals Q0 to Q5. Is connected.

【0048】

When the select control signals SL0 = "0", SL1 = "0", and SL2 = "1" are set, the input terminals XE0 to XE5 are selected, and the input terminals XE0 to XE5 and the output terminals Q0 to Q5. Is connected.

【0049】

When the first embodiment of the present invention configured as described above is used, the active matrix type liquid crystal display panel has a horizontal gray scale pattern, a vertical gray scale pattern, a horizontal stripe pattern, and a vertical stripe as test patterns. Six types of patterns, pattern, checkered pattern, and full-scale solid pattern, can be selectively displayed.

【0050】

Here, when displaying a horizontal grayscale pattern as a test pattern, as shown in FIG. 5, a horizontal synchronization signal HS is input to the counted signal input terminal IN of the 6-bit up / down counter 12. At the same time, the select control signals SL0 = "0", SL1 = "0", and SL2 = "0" are set, and the input terminals XA0 to XA5 are selected in the selector 25.

【0051】

In this way, during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as during the 1st to 64th vertical periods, the 6-bit up / down counter 12 uses the horizontal synchronization signal HS. Will be up-counted.

【0052】

That is, the logic levels of the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the 6-bit up / down counter 12 are [000000] [100000] [010000] [110000] for each horizontal period. ] ... [011111] [111111], and such changes will be repeated.

【0053】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [000000] for each horizontal period. ] [100000] [010000] [110000] ... [011111] [111111], and such changes will be repeated.

【0054】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the 1st horizontal line = [000000], 12 bits such as the 1st to 64th vertical periods are used. During the period when the logic level of the output terminal Q6 of the counter 11 is "0", as shown in FIG. 6 (A), the first, second, third, fourth ... 63rd, 64th, Test data TDATA (D0, D1, D2, D3, D4, D5) = [000000], [100000], [for each pixel electrode of the 65th, 66th, 67th horizontal lines ... Since the gradation voltage corresponding to [010000], [110000] ... [011111], [111111], [000000], [100000], [010000] ... can be supplied, FIG. 6 (B) As shown in, a horizontal grayscale pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0055】

On the other hand, during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods, the 6-bit up / down counter 12 uses the horizontal synchronization signal HS. Will be down-counted.

【0056】

That is, the logic levels of the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the 6-bit up / down counter 12 are [111111] [011111] [101111] [001111] for each horizontal period. ] ... [100000] [000000], and such changes will be repeated.

【0057】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [111111] for each horizontal period. ] [011111] [101111] [001111] ... [100000] [000000], and such changes will be repeated.

【0058】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the first horizontal line = [111111], the 65th to 128th vertical periods, etc., are 12 bits. During the period when the logical level of the output terminal Q6 of the counter 11 is "1", as shown in FIG. 7 (A), the first, second, third, fourth ... 63rd, 64th, Test data TDATA (D0, D1, D2, D3, D4, D5) = [111111], [011111], [011111], for each pixel electrode of the 65th, 66th, 67th horizontal lines ... Since the gradation voltage corresponding to [101111], [001111] ... [100000], [000000], [111111], [011111], [101111] ... can be supplied, FIG. 7 (B) As shown in FIG. 6, a horizontal grayscale pattern having a display polarity opposite to that shown in FIG. 6B can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0059】

When displaying a vertical grayscale pattern as a test pattern, as shown in FIG. 8, the clock signal CLK is input to the counted signal input terminal IN of the 6-bit up / down counter 12. , Select control signal SL0 = "0", SL1 = "0", SL2 = "0", and input terminals XA0 to XA5 are selected in the selector 25.

【0060】

In this way, the 6-bit up / down counter 12 sets the clock signal CLK during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as during the 1st to 64th vertical periods. It will be up-counted.

【0061】

That is, the logic levels of the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the 6-bit up / down counter 12 are set to [000000] [for each cycle of the clock signal CLK, so-called 1 dot period. It changes in the order of 100000] [010000] [110000] ... [011111] [111111], and such changes are repeated.

【0062】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [000000] for each dot period. ] [100000] [010000] [110000] ... [011111] [111111], and such changes will be repeated.

【0063】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the 1st vertical line = [000000], 12 bits such as the 1st to 64th vertical periods are used. During the period when the logic level of the output terminal Q6 of the counter 11 is "0", as shown in FIG. 9A, the first, second, third, fourth ... 63rd, 64th, Test data TDATA (D0, D1, D2, D3, D4, D5) = [000000], [100000], [for each pixel electrode of the 65th, 66th, 67th vertical lines ... Since it is possible to supply the gradation voltage corresponding to [010000], [110000] ... [011111], [111111], [000000], [100000], [010000] ..., FIG. 9 (B) As shown in, a vertical grayscale pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0064】

On the other hand, during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods, the 6-bit up / down counter 12 sets the clock signal CLK. It will be down-counted.

【0065】

That is, the logic levels of the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the 6-bit up / down counter 12 are [111111] [011111] [101111] [001111] for each dot period. ] ... [100000] [000000], and such changes will be repeated.

【0066】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [111111] for each dot period. ] [011111] [101111] [001111] ... [100000] [000000], and such changes will be repeated.

【0067】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the first vertical line = [111111], 12 bits such as the 65th to 128th vertical periods are used. During the period when the logic level of the output terminal Q6 of the counter 11 is "1", as shown in FIG. 10 (A), the first, second, third, fourth ... 63rd, 64th, Test data TDATA (D0, D1, D2, D3, D4, D5) = [111111], [011111], [011111], for each pixel electrode of the 65th, 66th, 67th vertical lines ... Since it is possible to supply the gradation voltage corresponding to [101111], [001111] ... [100000], [000000], [111111], [011111], [101111] ..., FIG. 10 (B) As shown in FIG. 9B, a vertical grayscale pattern in which the display polarity is reversed from the vertical grayscale pattern shown in FIG. 9B can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0068】

When displaying a horizontal stripe pattern as a test pattern, as shown in FIG. 11, the select control signals SL0 = "1", SL1 = "0", and SL2 = "0" are set, and in the selector 25, the selector 25 is set. Select the input terminals XB0 to XB5.

【0069】

Here, FIG. 12 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is 0, such as in the 1st to 64th vertical periods, and FIG. 12 (A) ) Is the logic level of the output terminal Q6 of the 12-bit counter 11, FIG. 12 (B) is the horizontal synchronization signal HS input to the clock signal input terminal C of the D flip-flop 13, and FIG. 12 (C) is the D flip-flop 13. The logic level of the positive phase output terminal Q, FIG. 12 (D) is the logic level of the negative phase output terminal / Q of the D flip-flop 13, FIG. 12 (E) is the output signal of the AND circuit 14, and FIG. 12 (F) is. The output signal of the AND circuit 16 and FIG. 12 (G) show the output signal of the OR circuit 17.

【0070】

That is, in the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0" such as the 1st to 64th vertical periods, the logic level of the output signal of the OR circuit 17 is "1 horizontal period". It changes in the order of "0"-> "1"-> "0"-> "1"-> ...-> "0"-> "1", and such a change is repeated.

【0071】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [000000] for each horizontal period. ] [111111] [000000] [111111] ... [000000] [111111], and such changes will be repeated.

【0072】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the 1st horizontal line = [000000], 12 bits such as the 1st to 64th vertical periods are used. During the period when the logical level of the output terminal Q6 of the counter 11 is "0", as shown in FIG. 13 (A), the first, second, third, fourth ... 63rd, 64th, Display test data TDATA (D0, D1, D2, D3, D4, D5) = [000000], [111111], for each pixel electrode of the 65th, 66th, 67th horizontal lines ... Since the gradation voltage corresponding to [000000], [111111] ... [000000], [111111], [000000], [111111], [000000] ... can be supplied, FIG. 13 (B) ), The horizontal stripe pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0073】

Further, FIG. 14 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is 1, such as in the 65th to 128th vertical periods, and FIG. 14A is a waveform diagram. Is the logic level of the output terminal Q6 of the 12-bit counter 11, FIG. 14 (B) is the horizontal synchronization signal HS input to the clock signal input terminal C of the D flip-flop 13, and FIG. 14 (C) is the D flip-flop 13. The logic level of the positive phase output terminal Q, FIG. 14 (D) is the logic level of the negative phase output terminal / Q of the D flip-flop 13, FIG. 14 (E) is the output signal of the AND circuit 14, and FIG. 14 (F) is the AND. The output signal of the circuit 16 and FIG. 14 (G) show the output signal of the OR circuit 17.

【0074】

That is, in the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1" such as the 65th to 128th vertical periods, the logic level of the output signal of the OR circuit 17 is "1" for each horizontal period. It changes in the order of "1"-> "0"-> "1"-> "0"-> ...-> "1"-> "0", and such a change is repeated.

【0075】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [111111] for each horizontal period. ] [000000] [111111] [000000] ... [111111] [000000], and such changes will be repeated.

【0076】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the first horizontal line = [111111], the 65th to 128th vertical periods, etc., are 12 bits. During the period when the logical level of the output terminal Q6 of the counter 11 is "1", as shown in FIG. 15 (A), the first, second, third, fourth ... 63rd, 64th, Display test data TDATA (D0, D1, D2, D3, D4, D5) = [111111], [000000], for each pixel electrode of the 65th, 66th, 67th horizontal lines ... Since the gradation voltage corresponding to [111111] [000000] ... [111111], [000000], [111111], [000000], [111111] ... can be supplied, FIG. 15 (B) As shown in FIG. 13B, the horizontal stripe pattern shown in FIG. 13B and the horizontal stripe pattern having the opposite display polarity can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0077】

When displaying a vertical stripe pattern as a test pattern, as shown in FIG. 16, the select control signals SL0 = "0", SL1 = "1", and SL2 = "0" are set in the selector 25. Select the input terminals XC0 to XC5.

【0078】

Here, FIG. 17 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is 0, such as in the 1st to 64th vertical periods, and FIG. 17 (A). ) Is the logic level of the output terminal Q6 of the 12-bit counter 11, FIG. 17 (B) is the clock signal CLK input to the clock signal input terminal C of the D flip-flop 18, and FIG. 17 (C) is the clock signal CLK of the D flip-flop 18. The logic level of the positive phase output terminal Q, FIG. 17 (D) is the logic level of the negative phase output terminal / Q of the D flip-flop 18, FIG. 17 (E) is the output signal of the AND circuit 19, and FIG. 17 (F) is the AND. The output signal of the circuit 21, FIG. 17 (G) shows the output signal of the OR circuit 22.

【0079】

That is, during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the 1st to 64th vertical periods, the logic level of the output signal of the OR circuit 22 is set to "1 dot period". It changes in the order of "0"-> "1"-> "0"-> [1]-> ...-> [0]-> [1], and such a change is repeated.

【0080】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [000000] for each dot period. ] [111111] [000000] [111111] ... [000000] [111111], and such changes will be repeated.

【0081】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the 1st vertical line = [000000], 12 bits such as the 1st to 64th vertical periods are used. During the period when the logic level of the output terminal Q6 of the counter 11 is "0", as shown in FIG. 18 (A), the first, second, third, fourth ... 63rd, 64th, Test data TDATA (D0, D1, D2, D3, D4, D5) = [000000], [111111], [ Since the gradation voltage corresponding to [000000], [111111] ... [000000], [111111], [000000], [111111], [000000] ... can be supplied, FIG. 18 (B) As shown in the above, a vertical stripe pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0082】

Further, FIG. 19 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is 1, such as in the 65th to 128th vertical periods, and FIG. 19A is shown in FIG. Is the logic level of the output terminal Q6 of the 12-bit counter 11, FIG. 19 (B) is the clock signal CLK input to the clock signal input terminal C of the D flip-flop 18, and FIG. 19 (C) is the positive of the D flip-flop 18. The logic level of the phase output terminal Q, FIG. 19 (D) is the logic level of the opposite phase output terminal / Q of the D flip-flop 18, FIG. 19 (E) is the output signal of the AND circuit 19, and FIG. 19 (F) is the AND circuit. The output signal of 21 and FIG. 19 (G) show the output signal of the OR circuit 22.

【0083】

That is, during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods, the logic level of the output signal of the OR circuit 22 is set to "1 dot period". It changes in the order of "1"-> "0"-> "1"-> "0"-> ...-> "1"-> "0", and such a change is repeated.

【0084】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is [111111] for each dot period. ] [000000] [111111] [000000] ... [111111] [000000], and such changes will be repeated.

【0085】

Therefore, when controlling so that the test data TDATA (D0, D1, D2, D3, D4, D5) of the first vertical line = [111111], the 65th to 128th vertical periods, etc., are 12 bits. During the period when the logic level of the output terminal Q6 of the counter 11 is "1", as shown in FIG. 20 (A), the first, second, third, fourth ... 63rd, 64th, Test data TDATA (D0, D1, D2, D3, D4, D5) = [111111], [000000], [ Since it is possible to supply gradation voltages corresponding to 111111], [000000] ... [111111], [000000], [111111], [000000], [111111] ... As shown in FIG. 20 (B), a vertical stripe pattern having a display polarity opposite to that shown in FIG. 18 (B) can be displayed on the display surface 27 of the display panel.

【0086】

When displaying a checkered pattern as a test pattern, as shown in FIG. 21, select control signals SL0 = "1", SL1 = "1", SL2 = "0" are set, and in the selector 25, the selector 25 is set. Select the input terminals XD0 to XD5.

【0087】

Here, FIG. 22 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is 0, such as in the 1st to 64th vertical periods, and FIG. 22 (A). ) Is the horizontal synchronization signal HS input to the clock signal input terminal C of the D flip-flop 13, FIG. 22 (B) is the logic level of the positive phase output terminal Q of the D flip-flop 13, and FIG. 22 (C) is the D flip-flop. The clock signal CLK input to the clock signal input terminal C of 18, FIG. 22 (D) shows the logic level of the positive phase output terminal Q of the D flip-flop 18, and FIG. 22 (E) shows the output signal of the EOR circuit 23. (F) shows the logic level of the output terminal Q6 of the 12-bit counter 11, and FIG. 22 (G) shows the output signal of the EOR circuit 24.

【0088】

That is, in the odd horizontal period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "0" such as the 1st to 64th vertical periods, the logic level of the output signal of the EOR circuit 24 is "0". "1" "0" "1" ... "0" "1", and in the even horizontal period, the output signal of the EOR circuit 24 is "1" "0" It changes in the order of "1"-> "0"-> ...-> "1"-> "0", and such a change is repeated.

【0089】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is 1 dot in the odd horizontal period. It changes in the order of [000000] [111111] [000000] [111111] ... [000000] [111111] for each period, and in the even horizontal period, for each dot period, [111111] [000000] [111111] [000000] [111111] [000000], and such changes will be repeated.

【0090】

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) = [000000] of the first vertical line in the odd horizontal period, and the test data TDATA (D0, D1) of the first vertical line in the even horizontal period. , D2, D3, D4, D5) = [111111], the logical level of the output terminal Q6 of the 12-bit counter 11 such as the 1st to 64th vertical periods is set to "0". During the period, as shown in Fig. 23 (A), in the odd horizontal line, the 1st, 2nd, 3rd, 4th ... 63rd, 64th, 65th, 66th, 67th vertical Test data TDATA (D0, D1, D2, D3, D4, D5) = [000000], [111111], [000000], [111111] ... Gradation voltage corresponding to [000000], [111111], [000000], [111111], [000000] ... can be supplied, and in the even horizontal line, the first, second, third, ... Test data TDATA (D0, D1, D2, D3, D4, D5) for each pixel electrode of the 4th ... 63rd, 64th, 65th, 66th, 67th vertical line ... ) = [111111], [000000], [111111], [000000] ... [111111], [000000], [111111], [000000], [111111] ... Therefore, as shown in FIG. 23 (B), the checkered pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0091】

Further, FIG. 24 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is 1, such as during the 65th to 128th vertical periods, and FIG. 24A is a waveform diagram. Is the horizontal synchronization signal HS input to the clock signal input terminal C of the D flip-flop 13, FIG. 24 (B) is the logic level of the positive phase output terminal Q of the D flip-flop 13, and FIG. 24 (C) is the D flip-flop 18. The clock signal CLK input to the clock signal input terminal C of the above, FIG. 24 (D) is the logic level of the positive phase output terminal Q of the D flip-flop 18, and FIG. 24 (E) is the output signal of the EOR circuit 23. F) shows the logic level of the output terminal Q6 of the 12-bit counter 11, and FIG. 24 (G) shows the output signal of the EOR circuit 24.

【0092】

That is, in the odd horizontal period in the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods, the output signal of the EOR circuit 24 is output every 1 dot period. It changes from "1" "0" "1" "0" ... "1" "0", and in the even horizontal period, the output signal of the EOR circuit 24 is "0" " It changes in the order of "1"-> "0"-> "1"-> ...-> "0"-> "1", and such a change is repeated.

【0093】

As a result, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, and Q5 of the selector 25 is 1 dot in the odd horizontal period. It changes in the order of [111111] [000000] [111111] [000000] [111111] [000000] for each period, and in the even horizontal period, for each dot period, [000000] ] [111111] [000000] [111111] ... [000000] [111111], and such changes will be repeated.

【0094】

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) = [111111] of the first vertical line in the odd horizontal period, and the test data TDATA (D0, D1) of the first vertical line in the even horizontal period. , D2, D3, D4, D5) = [000000], the logical level of the output terminal Q6 of the 12-bit counter 11 such as the 65th to 128th vertical periods is set to "1". During the period, as shown in Fig. 25 (A), in the odd horizontal line, the 1st, 2nd, 3rd, 4th ... 63rd, 64th, 65th, 66th, 67th vertical Test data TDATA (D0, D1, D2, D3, D4, D5) = [111111], [000000], [111111], [000000] ... Gradation voltage corresponding to [111111], [000000], [111111], [000000], [111111] ... can be supplied, and in the even horizontal line, the first, second, third, ... Test data TDATA (D0, D1, D2, D3, D4, D5) for each pixel electrode of the 4th ... 63rd, 64th, 65th, 66th, 67th vertical line ... ) = [000000], [111111], [000000], [111111] ... [000000], [111111], [000000], [111111], [000000] ... As shown in FIG. 25 (B), the checkered pattern shown in FIG. 23 (B) and the checkered pattern having the opposite display polarity should be displayed on the display surface 27 of the active matrix liquid crystal display panel. Can be done.

【0095】

When displaying a solid pattern on the entire surface as a test pattern, as shown in FIG. 26, the select control signals SL0 = "0", SL1 = "0", and SL2 = "1" are set in the selector 25. Makes the input terminals XE0 to XE5 selected.

【0096】

Here, the 12-bit counter 11 operates as shown in FIG. 3. In this case, the logic level of the output terminals Q6, Q7, Q8, Q9, Q10, and Q11 of the 12-bit counter 11 is 64. Every vertical period, it changes in the order of [000000] [100000] [010000] [110000] ... [011111] [111111], and such a change is repeated.

【0097】

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) output from the output terminals Q0, Q1, Q2, Q3, Q4, Q5 of the selector 25 is [000000] every 64 vertical periods. [100000] [010000] [110000] [011111] [111111], and such changes will be repeated.

【0098】

As a result, as shown in FIG. 27 (A), the 1st to 64th frames, the 65th to 128th frames, the 129th to 192nd frames, the 193rd to 256th frames ... 3969th to 4032th frames, In the 4033th to 4096th frames, test data TDATA (D0, D1, D2, D3, D4, D5) = [000000], [100000], [010000], [110000] for all pixel electrodes, respectively. ... Since the gradation voltage corresponding to [011111] and [111111] can be supplied, as shown in FIG. 27 (B), 64 vertical periods are applied to the display surface 27 of the active matrix liquid crystal display panel. It is possible to display a solid pattern on the entire surface by changing the gradation for each.

【0099】

When inverting the output signals output to the output terminals Q6 to Q11 of the 12-bit counter 11, the full-face solid pattern shown in FIG. 27 (B) and the full-face solid pattern in which the direction of gradation change is reversed. The pattern can be displayed.

【0100】

As described above, according to the first embodiment of the present invention, the active matrix type liquid crystal display panel has a horizontal stripe pattern, a vertical stripe pattern, a horizontal gray scale pattern, a vertical gray scale pattern, a checkered pattern, and the entire surface as test patterns. Since the solid pattern can be selectively displayed, it is possible to eliminate the need for a display tester that generates the test data necessary for displaying the test pattern, and the active matrix method is easy and inexpensive. The display test of the liquid crystal display panel can be performed.

【0101】

Second form ... Fig. 28-Fig. 51 In the second embodiment of the present invention, the test data generation unit shown in FIG. 28 is provided in place of the test data generation unit 9 provided in the first embodiment of the present invention shown in FIG. It is configured in the same manner as the first embodiment of the present invention.

【0102】

Here, the test data generation unit shown in FIG. 28 can be selected as test data TDATA (D0 to D5), that is, a vertical stripe pattern, a horizontal stripe pattern, a vertical gray scale pattern, a horizontal gray scale pattern, and a solid pattern on the entire surface. , Generates test data for displaying checkered patterns.

【0103】

In FIG. 28, 30 is a ROM for storing test data TDATA (D0 to D5), A0 to A8 are address signal input terminals, and Q0 to Q5 are data outputs for outputting test data TDATA (D0 to D5). It is a terminal.

【0104】

FIG. 29 is a diagram showing the contents of the test data TDATA (D5 to D0) stored in the ROM 30, and in this figure, the addresses A8 to A0 and the test data D5 to D0 are shown in hexadecimal.

【0105】

That is, in ROM30, addresses 000h to 03Fh are used as test data for storing vertical stripe pattern display data, and addresses 000h, 001h, 002h ..., 03Eh, and 03Fh are 00h and 3Fh, respectively. , 00h 00h, 3Fh are stored.

【0106】

Addresses 040h to 07Fh are used to store horizontal stripe pattern display data as test data, and addresses 040h, 041h, 042h ... 07Eh and 07Fh are 00h, 3Fh, 00h ..., respectively. 00h and 3Fh are stored.

【0107】

Addresses 080h to 0BFh are used to store vertical grayscale pattern display data as test data, and addresses 080h, 081h, 082h ... 0BEh and 0BFh are 00h, 01h, and 02h, respectively. ... 3Eh and 3Fh are stored.

【0108】

Addresses 0C0h to 0FFh are used to store horizontal grayscale pattern display data as test data, and addresses 0C0h, 0C1h, 0C2h ... 0FEh and 0FFh are 00h, 01h, and 02h, respectively. 3Eh and 3Fh are stored.

【0109】

In addition, addresses 100h to 13Fh are used as test data to store solid pattern display data on the entire surface, and addresses 100h, 101h, 102h ... 13Eh and 13Fh are 00h, 01h, 02h, respectively. 3Eh and 3Fh are stored.

【0110】

Addresses 140h to 17Fh are used to store checkered pattern display data as test data, and addresses 140h, 141h, 142h ... 17Eh and 17Fh are 00h, 3Fh, 00h ..., respectively. 00h and 3Fh are stored.

【0111】

Further, in FIG. 28, 31, 32, and 33 are test pattern selection signal input terminals to which the test pattern selection signals SL3, SL4, and SL5 supplied from the outside are input, and FIG. 30 is the test pattern selection signal SL3. , SL4, SL5 and the selected test pattern.

【0112】

That is, in this example, when the test pattern selection signals SL3 = "0", SL4 = "0", and SL5 = "0" are set, the vertical stripe pattern is selected as the test pattern.

【0113】

When the test pattern selection signals SL3 = "1", SL4 = "0", and SL5 = "0" are set, the horizontal stripe pattern is selected as the test pattern.

【0114】

When the test pattern selection signals SL3 = "0", SL4 = "1", and SL5 = "0" are set, the vertical grayscale pattern is selected as the test pattern.

【0115】

When the test pattern selection signals SL3 = "1", SL4 = "1", and SL5 = "0" are set, the horizontal grayscale pattern is selected as the test pattern.

【0116】

Further, when the test pattern selection signals SL3 = "0", SL4 = "0", and SL5 = "1" are set, the entire solid pattern is selected as the test pattern.

【0117】

When the test pattern selection signals SL3 = "1", SL4 = "0", and SL5 = "1" are set, the checkered pattern is selected as the test pattern.

【0118】

Further, in FIG. 28, 34 is a clock signal CLK, a horizontal synchronization signal HS, a 2-divided horizontal synchronization signal 2HS obtained by dividing the horizontal synchronization signal HS by 1/2, a vertical synchronization signal VS, and a vertical synchronization signal VS of 1/64. It is a timer circuit that outputs a 64-divided vertical sync signal 64VS divided by.

【0119】

Here, FIG. 31 is a waveform diagram showing the clock signal CLK, the horizontal synchronization signal HS, the 2-divided horizontal synchronization signal 2HS, the vertical synchronization signal VS, and the 64-divided vertical synchronization signal 64VS output by the timer circuit 34.

【0120】

Further, in FIG. 28, 35 selects and outputs the clock signal CLK, the horizontal synchronization signal HS, or the vertical synchronization signal VS output from the timer circuit 34, using the test pattern selection signals SL3, SL4, and SL5 as select control signals. It is a selector, and FIG. 32 is a diagram showing the relationship between the test pattern selection signals SL3, SL4, SL5 and the signal output from the selector 35.

【0121】

That is, the selector 35 has the test pattern selection signal SL3 = "0", SL4 = "0", SL5 = "0" or SL3 = "0", SL4 = "1", SL5 = "0" or SL3 = " When 1 , SL4 = 0 , SL5 = 1 , select the clock signal CLK, and test pattern selection signal SL3 = 1 , SL4 = 0 , SL5 = 0 or SL3 = When "1", SL4 = "1", SL5 = "0", select the horizontal synchronization signal HS, and test pattern selection signal SL3 = "0", SL4 = "0", SL5 = "1". In some cases, it is configured to select the vertical sync signal VS.

【0122】

Further, in FIG. 28, 36 selects the 2-divided horizontal synchronization signal 2HS or the 64-divided vertical synchronization signal 64VS output from the timer circuit 34 using the test pattern selection signals SL3, SL4, and SL5 as select control signals. It is a selector to be output, and FIG. 33 is a diagram showing the relationship between the test pattern selection signals SL3, SL4, SL5 and the signal output from the selector 35.

【0123】

That is, the selector 36 has the test pattern selection signal SL3 = "0", SL4 = "0", SL5 = "0" or SL3 = "1", SL4 = "0", SL5 = "0" or SL3 = " 0 ", SL4 =" 1 ", SL5 =" 0 "or SL3 =" 1 ", SL4 =" 1 ", SL5 =" 0 "or SL3 =" 0 ", SL4 =" 0 ", SL5 =" 1 " In the case of, select the 64-divided vertical sync signal 64VS, and in the case of the test pattern selection signal SL3 = "1", SL4 = "0", SL5 = "1", select the 2-divided horizontal sync signal 2HS. It is configured to do.

【0124】

Further, in FIG. 28, 37 is input to the counted signal input terminal IN with the clock signal CLK, the horizontal synchronization signal HS or the vertical synchronization signal VS output from the selector 35 as the counted signal, and is output from the selector 36 for 2 minutes. It is a 6-bit up / down counter that is input to the up / down control signal input terminal U / D with the peripheral horizontal synchronization signal 2HS or the 64 division vertical synchronization signal 64VS as the up / down control signal, and Q0 to Q5 are 1. This is an output terminal that outputs the count value from the 6th bit to the 6th bit.

【0125】

The 6-bit up / down counter 37 has the same configuration as the 6-bit up / down counter 12 shown in FIG. 2, and the logic level of the up / down control signal input terminal U / D = ". When it is set to "0", an up-count operation is performed, and when the logic level of the up / down control signal input terminal U / D is set to "1", a down-count operation is performed.

【0126】

Further, in this example, the address signal generator is composed of the timer circuit 34, the selector 35, the selector 36, and the 6-bit up / down counter 37, and the 6-bit up / down counter 37 The output terminals Q0 to Q5 are connected to the address signal input terminals A0 to A5 of the ROM30, respectively, and the test pattern selection signal input terminals 31 to 33 are connected to the address signal input terminals A6 to A8 of the ROM30, respectively. ..

【0127】

When the second embodiment of the present invention including the test data generation unit configured as described above is used, the active matrix type liquid crystal display panel has a vertical stripe pattern, a horizontal stripe pattern, and a vertical gray as test patterns. A scale pattern, a horizontal grayscale pattern, a solid pattern on the entire surface, or a checkered pattern can be selectively displayed.

【0128】

Here, when a vertical stripe pattern is displayed as the test pattern, the test pattern selection signals SL3 = "0", SL4 = "0", and SL5 = "0" are set as shown in FIG. 34.

【0129】

In this way, the selector 35 selects and outputs the clock signal CLK, and the selector 36 selects and outputs the 64-divided vertical synchronization signal 64VS, so that the 6-bit up / down counter 37 Will count the clock signal CLK with the 64-divided vertical sync signal 64VS as the up / down control signal.

【0130】

35 and 36 are waveform diagrams for explaining the operation in this case. FIG. 35 shows the logic of the 64 division vertical synchronization signal 64VS when 64VS = "0", and FIG. 36 shows the logic of the 64 division vertical synchronization signal 64VS. The case where level = "1" is shown.

【0131】

Here, Fig. 35 (A) and Fig. 36 (A) show the 64-divided vertical synchronization signal 64VS, Fig. 35 (B), and Fig. 36 (B) show the clock signal CLK, Fig. 35 (C), and Fig. 36 (C). Is the logic level of the address signal input terminals A0 to A8 of ROM30, Fig. 35 (D) and Fig. 36 (D) are the accessed addresses ADD, and Fig. 35 (E) and Fig. 36 (E) are the tests output from ROM30. Data for TDATA is shown.

【0132】

The address ADD shown in FIGS. 35 (D) and 36 (D) and the test data TDATA shown in FIGS. 35 (E) and 36 (E) are displayed in hexadecimal numbers.

【0133】

That is, as shown in FIG. 35, during the period when the 64-divided vertical synchronization signal 64VS is "0", the 12-bit up / down counter 37 counts up, so that the address signal input terminal of the ROM 30 The logical levels of A0 to A8 are as shown in Fig. 35 (C), and the accessed address ADD is 000h 001h 002h ... It changes to 03Fh, and such a change will be repeated.

【0134】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 00h 3Fh 00h ... 3Fh for each dot period, and such changes are repeated. ..

【0135】

Therefore, when controlling the pixel electrodes of the first vertical line to supply the gradation voltage corresponding to the test data at the address 000h, the period when the 64-divided vertical synchronization signal 64VS is "0", Similar to the case shown in FIG. 18, the vertical stripe pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0136】

On the other hand, as shown in FIG. 36, during the period when the 64-divided vertical synchronization signal 64VS is "1", the 6-bit up / down counter 37 counts down, so the address of ROM30. The logic levels of the signal input terminals A0 to A8 are as shown in Fig. 36 (C), and the accessed address ADD is 03Fh 03Eh 03Dh for each dot period as shown in Fig. 36 (D). ... 000h, and such changes will be repeated.

【0137】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 3Fh 00h 3Fh ... 00h for each dot period, and such changes are repeated. ..

【0138】

Therefore, when controlling the pixel electrodes of the first vertical line to supply the gradation voltage corresponding to the test data at the address 03Fh, the period when the 64-divided vertical synchronization signal 64VS is "1", Similar to the case shown in FIG. 20, a vertical stripe pattern having a display polarity opposite to that shown in FIG. 18 can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0139】

When a horizontal stripe pattern is displayed as the test pattern, the test pattern selection signals SL3 = "1", SL4 = "0", and SL5 = "0" are set as shown in FIG. 37.

【0140】

In this way, the selector 35 selects and outputs the horizontal sync signal HS, and the selector 36 selects and outputs the 64 division vertical sync signal 64VS, so that the 6-bit up / down counter is used. 37 counts the horizontal synchronization signal HS with the 64-division vertical synchronization signal 64VS as the up / down control signal.

【0141】

38 and 39 are waveform diagrams for explaining the operation in this case. FIG. 38 shows the 64-divided vertical synchronization signal 64VS = "0", and FIG. 39 shows the 64-divided vertical synchronization signal 64VS = ". The case of "1" is shown.

【0142】

Here, FIGS. 38 (A) and 39 (A) show a 64-divided vertical sync signal 64VS, FIG. 38 (B), and FIG. 39 (B) show a horizontal sync signal HS, FIG. 38 (C), and FIG. 39 (C). ) Is the logic level of the address signal input terminals A0 to A8 of ROM30, Fig. 38 (D) and Fig. 39 (D) are the accessed addresses ADD, and Fig. 38 (E) and Fig. 39 (E) are output from ROM30. The test data TDATA is shown.

【0143】

The address ADD shown in FIGS. 38 (D) and 39 (D) and the test data TDATA shown in FIGS. 38 (E) and 39 (E) are displayed in hexadecimal numbers.

【0144】

That is, as shown in FIG. 38, during the period when the 64-divided vertical synchronization signal 64VS is "0", the 6-bit up / down counter 37 performs up-counting, so that the address signal input terminal of the ROM 30 The logical levels of A0 to A8 are shown in Fig. 38 (C), and the accessed address ADD is 040h 041h 042h ... for each horizontal period, as shown in Fig. 38 (D). It changes to 07Fh, and such a change will be repeated.

【0145】

As a result, the test data TDATA (D5 to D0) output from ROM30 changes in the order of 00h 3Fh 00h ... 3Fh for each horizontal period, and such changes are repeated. ..

【0146】

Therefore, when controlling so that the gradation voltage corresponding to the test data at the address 040h is supplied to the pixel electrodes of the first horizontal line, the period when the 64-divided vertical synchronization signal 64VS is "0". , As shown in FIG. 13, the horizontal stripe pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0147】

On the other hand, as shown in FIG. 39, during the period when the 64-divided vertical synchronization signal 64VS is "1", the 6-bit up / down counter 37 counts down, so the address of the ROM 30. The logic levels of the signal input terminals A0 to A8 are as shown in Fig. 39 (C), and the accessed address ADD is 07Fh 07Eh 07Dh for each horizontal period as shown in Fig. 39 (D). ... 040h, and such changes will be repeated.

【0148】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 3Fh 00h 3Fh ... 00h for each horizontal period, and such changes are repeated. ..

【0149】

Therefore, when controlling so that the test data at the address 07Fh is supplied to the pixel electrodes of the first horizontal line, when the 64-divided vertical synchronization signal 64VS is "1", as shown in FIG. Similarly, on the display surface 27 of the active matrix type liquid crystal display panel, a horizontal stripe pattern having a display polarity opposite to that shown in FIG. 13 can be displayed.

【0150】

When displaying a vertical grayscale pattern as a test pattern, the test pattern selection signals SL3 = "0", SL4 = "1", and SL5 = "0" are set as shown in FIG. 40. ..

【0151】

In this way, the selector 35 selects and outputs the clock signal CLK, and the selector 36 selects and outputs the 64-divided vertical synchronization signal 64VS, so that the 6-bit up / down counter 37 Will count the clock signal CLK with the 64-divided vertical sync signal 64VS as the up / down control signal.

【0152】

41 and 42 are waveform diagrams for explaining the operation in this case. FIG. 41 shows the case where the 64 division vertical synchronization signal 64VS = "0", and FIG. 42 shows the 64 division vertical synchronization signal 64VS = ". The case of "1" is shown.

【0153】

Here, FIGS. 41 (A) and 42 (A) show the 64-divided vertical synchronization signal 64VS, FIG. 41 (B), and FIG. 42 (B) show the clock signal CLK, FIG. 41 (C), and FIG. 42 (C). Is the logic level of the address signal input terminals A0 to A8 of ROM30, Fig. 41 (D) and Fig. 42 (D) are the accessed addresses ADD, and Fig. 41 (E) and Fig. 42 (E) are the tests output from ROM30. Data for TDATA is shown.

【0154】

The address ADD shown in FIGS. 41 (D) and 42 (D) and the test data TDATA shown in FIGS. 41 (E) and 42 (E) are displayed in hexadecimal numbers.

【0155】

That is, as shown in FIG. 41, during the period when the 64-divided vertical synchronization signal 64VS is "0", the 6-bit up / down counter 37 performs up-counting, so that the address signal input terminal of the ROM 30 The logical levels of A0 to A8 are shown in Fig. 41 (C), and the accessed address ADD is 080h 081h 082h ... It changes to 0BFh, and such a change will be repeated.

【0156】

As a result, the test data TDATA (D5 to D0) output from ROM30 changes in the order of 00h 01h 02h ... 3Fh for each horizontal period, and such changes are repeated. ..

【0157】

Therefore, when controlling so that the gradation voltage corresponding to the test data at the address 080h is supplied to the pixel electrodes of the first vertical line, the period when the 64-divided vertical synchronization signal 64VS is "0". , The vertical grayscale pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel as in the case shown in FIG.

【0158】

On the other hand, as shown in FIG. 42, during the period when the 64-divided vertical synchronization signal 64VS is "1", the 6-bit up / down counter 37 counts down, so the address of ROM30. The logic levels of the signal input terminals A0 to A8 are as shown in Fig. 42 (C), and the accessed address ADD is 0BFh 0BEh 0BDh for each dot period as shown in Fig. 42 (D). ... 080h, and such changes will be repeated.

【0159】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 3Fh 3Eh 3Dh ... 00h for each dot period, and such changes are repeated. ..

【0160】

Therefore, when controlling so that the gradation voltage corresponding to the test data at address 0BFh is supplied to the pixel electrodes of the first vertical line, the period when the 64-divided vertical synchronization signal 64VS is "1". , The vertical grayscale pattern in which the display polarity is reversed from the vertical grayscale pattern shown in FIG. 9 can be displayed on the display surface 27 of the active matrix type liquid crystal display panel as in the case shown in FIG. ..

【0161】

When displaying a horizontal grayscale pattern as a test pattern, the test pattern selection signals SL3 = "1", SL4 = "1", and SL5 = "0" are set as shown in FIG. 43. ..

【0162】

In this way, the selector 35 selects and outputs the horizontal sync signal HS, and the selector 36 selects and outputs the 64-divided vertical sync signal 64VS, so that the 6-bit up / down counter is used. 37 counts the horizontal synchronization signal CLK with the 64-division vertical synchronization signal 64VS as the up / down control signal.

【0163】

44 and 45 are waveform diagrams for explaining the operation in this case. FIG. 44 shows the case where the 64 division vertical synchronization signal 64VS = "0", and FIG. 45 shows the 64 division vertical synchronization signal 64VS = ". The case of "1" is shown.

【0164】

Here, FIG. 44 (A) and FIG. 45 (A) are 64 division vertical synchronization signals 64VS, FIG. 44 (B), and FIG. 45 (B) are horizontal synchronization signals HS, FIG. 44 (C), and FIG. 45 (C). ) Is the logic level of the address signal input terminals A0 to A8 of ROM30, Fig. 44 (D) and Fig. 45 (D) are the accessed addresses ADD, and Fig. 44 (E) and Fig. 45 (E) are output from ROM30. The test data TDATA is shown.

【0165】

The address ADD shown in FIGS. 44 (D) and 45 (D) and the test data TDATA shown in FIGS. 44 (E) and 45 (E) are displayed in hexadecimal numbers.

【0166】

That is, as shown in FIG. 44, during the period when the 64-divided vertical synchronization signal 64VS is "0", the 6-bit up / down counter 37 counts up, and the address signal input terminal A0 of the ROM 30 The logical level of ~ A8 is as shown in Fig. 44 (C), and the accessed address ADD is 0C0h 0C1h 0C2h ... for each horizontal period as shown in Fig. 44 (D). It changes to 0FFh, and such changes will be repeated.

【0167】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 00h 01h 02h ... 3Fh for each horizontal period, and this change is repeated.

【0168】

Therefore, when controlling so that the gradation voltage corresponding to the test data at address 0C0h is supplied to the pixel electrodes of the first horizontal line, the period when the 64-divided vertical synchronization signal 64VS is "0". , The horizontal grayscale pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel as in the case shown in FIG.

【0169】

On the other hand, as shown in FIG. 45, during the period when the 64-divided vertical synchronization signal 64VS is "1", the 6-bit up / down counter 37 counts down, so the address of ROM30. The logic levels of the signal input terminals A0 to A8 are as shown in Fig. 45 (C), and the accessed address ADD is 0FFh 0FEh 0FDh for each horizontal period, as shown in Fig. 45 (D). ... 0C0h, and such changes will be repeated.

【0170】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 3Fh 3Eh 3Dh ... 00h for each horizontal period, and this change is repeated.

【0171】

Therefore, when controlling so that the gradation voltage corresponding to the test data at the address 0FFh is supplied to the pixel electrodes of the first horizontal line, the period when the 64-divided vertical synchronization signal 64VS is "1". As in the case shown in FIG. 7, a horizontal gray scale having a display polarity opposite to that shown in FIG. 6 can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

【0172】

When displaying a solid pattern on the entire surface as the test pattern, the test pattern selection signals SL3 = "0", SL4 = "0", and SL5 = "1" are set as shown in FIG.

【0173】

In this way, the selector 35 selects and outputs the vertical sync signal VS, and the selector 36 selects and outputs the 64-divided vertical sync signal 64VS, so that the 6-bit up / down counter is used. 37 counts the vertical synchronization signal VS using the 64 division vertical synchronization signal 64VS as an up / down control signal.

【0174】

47 and 48 are waveform diagrams for explaining the operation in this case. FIG. 47 shows the case where the 64 division vertical synchronization signal 64VS = "0", and FIG. 48 shows the 64 division vertical synchronization signal 64VS = ". The case of "1" is shown.

【0175】

Here, FIGS. 47 (A) and 48 (A) show a 64-divided vertical sync signal 64VS, FIG. 47 (B), and FIG. 48 (B) show a vertical sync signal VS, FIG. 47 (C), and FIG. 48 (C). ) Is the logic level of the address signal input terminals A0 to A8 of ROM30, Fig. 47 (D) and Fig. 48 (D) are the accessed addresses ADD, and Fig. 47 (E) and Fig. 48 (E) are output from ROM30. The test data TDATA is shown.

【0176】

The address ADD shown in FIGS. 47 (D) and 48 (D) and the test data TDATA shown in FIGS. 47 (E) and 48 (E) are shown in hexadecimal numbers.

【0177】

That is, as shown in FIG. 47, during the period when the 64-divided vertical synchronization signal 64VS is "0", the 6-bit up / down counter 37 performs up-counting, so that the address signal input terminal of the ROM 30 The logical levels of A0 to A8 are as shown in Fig. 47 (C), and the accessed address ADD is 100h 101h 102h ... for each vertical period, as shown in Fig. 47 (D). It changes to 13Fh, and such a change will be repeated.

【0178】

As a result, the test data TDATA (D5 to D0) output from ROM30 changes in the order of 00h 01h 02h ... 3Fh for each vertical period, and such changes are repeated. ..

【0179】

Therefore, during the period when the 64-divided vertical synchronization signal 64VS is "0", the gradation is changed every 64 vertical periods on the display surface 27 of the active matrix type liquid crystal display panel as in the case shown in FIG. 27. -Patterns can be displayed.

【0180】

On the other hand, as shown in FIG. 48, during the period when the 64-divided vertical synchronization signal 64VS is "1", the 6-bit up / down counter 37 counts down, so the address of ROM30. The logic levels of the signal input terminals A0 to A8 are as shown in Fig. 48 (C), and the accessed address ADD is 13Fh 13Eh 13Dh for each vertical period, as shown in Fig. 48 (D). ... It changes from 100h, and such a change will be repeated.

【0181】

As a result, the test data TDATA (D5 to D0) output from ROM30 changes in the order of 3Fh 3Eh 3Dh ... 00h for each vertical period, and such changes are repeated. ..

【0182】

Therefore, during the period when the 64-divided vertical sync signal 64VS is "1", the entire solid pattern shown in FIG. 27 and the direction of gradation change are reversed on the display surface 27 of the active matrix liquid crystal display panel. The pattern can be displayed.

【0183】

When the checkered pattern is displayed as the test pattern, the test pattern selection signals SL3 = "1", SL4 = "0", and SL5 = "1" are set as shown in FIG. 49.

【0184】

In this way, the selector 35 selects and outputs the clock signal CLK, and the selector 36 selects and outputs the 2-divided horizontal synchronization signal 2HS, so that the 6-bit up / down counter 37 Counts the clock signal CLK with the 2-divided horizontal synchronization signal 2HS as the up / down control signal.

【0185】

50 and 51 are waveform diagrams for explaining the operation in this case. FIG. 50 shows a 2-divided horizontal synchronization signal 2HS = 0, and FIG. 51 shows a 2-divided horizontal synchronization signal 2HS = 0. The case of "1" is shown.

【0186】

Here, FIGS. 50 (A) and 51 (A) show a 2-divided horizontal synchronization signal 2HS, FIG. 50 (B), and FIG. 51 (B) show a clock signal CLK, FIG. 50 (C), and FIG. 51 (C). Is the logic level of the address signal input terminals A0 to A8 of ROM30, Fig. 50 (D) and Fig. 51 (D) are the accessed addresses ADD, and Fig. 50 (E) and Fig. 51 (E) are the tests output from ROM30. Indicates the data TDATA for.

【0187】

The address ADD shown in FIGS. 50 (D) and 51 (D) and the test data TDATA shown in FIGS. 50 (E) and 51 (E) are displayed in hexadecimal numbers.

【0188】

That is, as shown in FIG. 50, during the period when the 2-divided horizontal synchronization signal 2HS is "0", the 6-bit up / down counter 37 performs up-counting, so that the address signal input terminal of the ROM 30 The logical levels of A0 to A8 are as shown in Fig. 50 (C), and the accessed address ADD is 140h 141h 142h ... for each horizontal period, as shown in Fig. 50 (D). It changes to 17Fh, and such a change will be repeated.

【0189】

As a result, the test data TDATA (D5 to D0) output from ROM30 changes in the order of 00h 3Fh 00h ... 3Fh for each horizontal period, and such changes are repeated. ..

【0190】

On the other hand, as shown in FIG. 51, during the period when the 2-divided horizontal synchronization signal 2HS is 1, the 6-bit up / down counter 37 counts down, so the address of the ROM 30. The logic levels of the signal input terminals A0 to A8 are as shown in Fig. 51 (C), and the accessed address ADD is 17Fh 17Eh 17Dh for each horizontal period, as shown in Fig. 51 (D). ... It changes from 140h, and such a change will be repeated.

【0191】

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes in the order of 3Fh 00h 3Fh ... 0h for each horizontal period, and such changes are repeated. ..

【0192】

Therefore, for example, the test data TDATA (D5 to D0) = 00h of the first vertical line in the odd horizontal period and the test data TDATA (D5 to D0) = 3Fh of the first vertical line in the even horizontal period are controlled. In this case, the checkered pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel as in the case shown in FIG.

【0193】

As described above, according to the second embodiment of the present invention, as a test pattern on the active matrix type liquid crystal display panel, a vertical gray scale pattern, a horizontal gray scale pattern, a vertical stripe pattern, a horizontal stripe pattern, and a solid pattern on the entire surface are used. And since the checkered pattern can be selectively displayed, it is possible to eliminate the need for a display tester that generates the test data necessary for displaying the test pattern, and the active matrix method is easy and inexpensive. The display test of the liquid crystal display panel can be performed.

【0194】

[Effect of the invention]

As described above, according to the present invention, the test pattern is provided by providing the test data generation unit for generating the test data necessary for displaying the test pattern on the active matrix type liquid crystal display panel. It is possible to eliminate the need for a display tester that generates test data necessary for display, and it is possible to easily and inexpensively perform a display test of an active matrix type liquid crystal display panel.

[Simple explanation of drawings]

[Figure 1]

It is a circuit diagram which shows the main part of the 1st Embodiment of this invention.

[Figure 2]

It is a circuit diagram which shows the structure of the test data generation part provided with 1st Embodiment of this invention.

[Fig. 3]

It is a waveform diagram which shows the operation of the 12-bit counter provided in the test data generation part provided with the 1st Embodiment of this invention.

[Fig. 4]

It is a waveform diagram which shows the operation of the 6-bit up / down counter provided in the test data generation part provided with the 1st Embodiment of this invention.

[Fig. 5]

It is a circuit diagram for demonstrating the case where the horizontal grayscale pattern is displayed using the 1st Embodiment of this invention.

[Fig. 6]

It is a figure for demonstrating the case where the horizontal grayscale pattern is displayed using the 1st Embodiment of this invention.

[Fig. 7]

It is a figure for demonstrating the case where the horizontal grayscale pattern is displayed using the 1st Embodiment of this invention.

[Fig. 8]

It is a circuit diagram for demonstrating the case where the vertical grayscale pattern is displayed using the 1st Embodiment of this invention.

[Fig. 9]

It is a figure for demonstrating the case where the vertical grayscale pattern is displayed using the 1st Embodiment of this invention.

[Fig. 10]

It is a figure for demonstrating the case where the vertical grayscale pattern is displayed using the 1st Embodiment of this invention.

[Fig. 11]

It is a circuit diagram for demonstrating the case where the horizontal stripe pattern is displayed using the 1st Embodiment of this invention.

[Fig. 12]

It is a waveform diagram for demonstrating the operation when the logic level of the output terminal Q6 of a 12-bit counter is "0" in the case of displaying a horizontal stripe pattern by using the 1st Embodiment of this invention.

[Fig. 13]

It is a figure for demonstrating the case where the horizontal stripe pattern is displayed using the 1st Embodiment of this invention.

[Fig. 14]

It is a waveform diagram for demonstrating the operation when the logic level of the output terminal Q6 of a 12-bit counter is "1" in the case of displaying a horizontal stripe pattern by using the 1st Embodiment of this invention.

[Fig. 15]

It is a figure for demonstrating the case where the horizontal stripe pattern is displayed using the 1st Embodiment of this invention.

[Fig. 16]

It is a circuit diagram for demonstrating the case where the vertical stripe pattern is displayed using the 1st Embodiment of this invention.

[Fig. 17]

It is a waveform diagram for demonstrating the operation when the logic level of the output terminal Q6 of a 12-bit counter is "0" in the case of displaying a vertical stripe pattern by using the 1st Embodiment of this invention.

[Fig. 18]

It is a figure for demonstrating the case where the vertical stripe pattern is displayed using the 1st Embodiment of this invention.

[Fig. 19]

It is a waveform diagram for demonstrating the operation when the logic level of the output terminal Q6 of a 12-bit counter is "1" in the case of displaying a vertical stripe pattern by using the 1st Embodiment of this invention.

[Fig. 20]

It is a figure for demonstrating the case where the vertical stripe pattern is displayed using the 1st Embodiment of this invention.

[Fig. 21]

It is a circuit diagram for demonstrating the case where the checkered pattern is displayed using the 1st Embodiment of this invention.

[Fig. 22]

It is a waveform diagram for demonstrating the operation when the logic level of the output terminal Q6 of a 12-bit counter is "0" when the checkered pattern is displayed by using the 1st Embodiment of this invention.

[Fig. 23]

It is a figure for demonstrating the case where the checkered pattern is displayed using the 1st Embodiment of this invention.

[Fig. 24]

It is a waveform diagram for demonstrating the operation when the logic level of the output terminal Q6 of a 12-bit counter is "1" when the checkered pattern is displayed by using the 1st Embodiment of this invention.

[Fig. 25]

It is a figure for demonstrating the case where the checkered pattern is displayed using the 1st Embodiment of this invention.

[Fig. 26]

It is a circuit diagram for demonstrating the case where the whole surface solid pattern is displayed using the 1st Embodiment of this invention.

[Fig. 27]

It is a figure for demonstrating the case where the whole surface solid pattern is displayed using the 1st Embodiment of this invention.

[Fig. 28]

It is a circuit diagram which shows the test data generation part provided with the 2nd Embodiment of this invention.

[Fig. 29]

It is a figure which shows the storage content of ROM provided in the 2nd Embodiment of this invention.

[Fig. 30]

It is a figure which shows the relationship between the test pattern selection signal and the selected test pattern in the 2nd Embodiment of this invention.

[Fig. 31]

It is a waveform diagram which shows the signal output by the timer circuit provided in the 2nd Embodiment of this invention.

[Fig. 32]

It is a figure which shows the relationship between the test pattern selection signal and the signal output from the selector which outputs the counted signal in the 2nd Embodiment of this invention.

[Fig. 33]

It is a figure which shows the relationship between the test pattern selection signal and the signal output from the selector which outputs the up / down control signal in the 2nd Embodiment of this invention.

[Fig. 34]

It is a circuit diagram for demonstrating the case where the vertical stripe pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 35]

It is a waveform diagram for demonstrating the case where the vertical stripe pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 36]

It is a waveform diagram for demonstrating the case where the vertical stripe pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 37]

It is a circuit diagram for demonstrating the case where the horizontal stripe pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 38]

It is a waveform diagram for demonstrating the case where the horizontal stripe pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 39]

It is a waveform diagram for demonstrating the case where the horizontal stripe pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 40]

It is a circuit diagram for demonstrating the case which displays the vertical grayscale pattern using the 2nd Embodiment of this invention.

[Fig. 41]

It is a waveform diagram for demonstrating the case of displaying a vertical grayscale pattern using the 2nd Embodiment of this invention.

[Fig. 42]

It is a waveform diagram for demonstrating the case of displaying a vertical grayscale pattern using the 2nd Embodiment of this invention.

[Fig. 43]

It is a circuit diagram for demonstrating the case which displays the horizontal grayscale pattern using the 2nd Embodiment of this invention.

[Fig. 44]

It is a waveform diagram for demonstrating the case of displaying a horizontal grayscale pattern using the 2nd Embodiment of this invention.

[Fig. 45]

It is a waveform diagram for demonstrating the case of displaying a horizontal grayscale pattern using the 2nd Embodiment of this invention.

[Fig. 46]

It is a circuit diagram for demonstrating the case where the whole surface solid pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 47]

It is a waveform diagram for demonstrating the case where the whole surface solid pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 48]

It is a waveform diagram for demonstrating the case where the whole surface solid pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 49]

It is a circuit diagram for demonstrating the case where the checkered pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 50]

It is a waveform diagram for demonstrating the case where the checkered pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 51]

It is a waveform diagram for demonstrating the case where the checkered pattern is displayed using the 2nd Embodiment of this invention.

[Fig. 52]

It is a circuit diagram which shows the main part of an example of the conventional data driver of a digital system.

[Explanation of symbols]

1 Shift register section 2 Data register section 3 Latch part 4 Decoder section 5 Gradation voltage generator 6 Selector section 9 Test data generator