Data signal output circuit and image display device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a data signal output circuit that selectively outputs predetermined data based on an input digital signal, and in particular, a data signal output circuit suitable for outputting image display data and this data signal output circuit are used. It relates to an image display device.

【0002】

[Conventional technology]

As one of the conventional liquid crystal display devices, an active matrix drive type liquid crystal display device is known. As shown in FIG. 19, this liquid crystal display device is composed of a pixel array 1, a scanning signal line drive circuit (hereinafter referred to as a gate driver) 2, and a data signal line drive circuit (hereinafter referred to as a source driver) 3. It has become. The pixel array 1 is provided with a large number of scanning signal lines GL ... and a large number of data signal lines SL ... that intersect each other, and pixels (PIX in the figure) 4 ... Arranged in a matrix. Has been done.

【0003】

As shown in FIG. 20, the above pixel 4 includes a pixel transistor SW which is a switching element and a liquid crystal capacity C._LPixel capacity C including_P(Auxiliary capacity C if necessary_SIs added) and. In such a pixel 4, the liquid crystal capacity C_LWhen a voltage is applied to, the transmittance or reflectance of the liquid crystal is modulated, and an image corresponding to the video signal DAT is displayed on the pixel array 1 ...

【0004】

The source driver 3 samples the input video signal DAT and writes the corresponding gradation display data to each data signal line SL. The gate driver 2 sequentially selects the scanning signal line GL ... and controls the opening and closing of the pixel transistor SW provided in the pixel 4. As a result, the video signal (data) output to each data signal line SL is written and held in each pixel 4.

【0005】

By the way, in the conventional active matrix type liquid crystal display device as described above, an amorphous silicon thin film formed on a transparent substrate such as glass has been used as a material for the pixel transistor SW. In addition, the gate driver 2 and the source driver 3 were each composed of an external integrated circuit (IC).

【0006】

On the other hand, in recent years, due to demands such as improvement of driving force of pixel transistor SW due to larger screen, reduction of mounting cost of drive IC, reliability in mounting, etc., pixel array 1 and drivers 2 and 3 are made of polycrystalline silicon. A technique for forming monolithically using a thin film has been developed and reported. Further, with the aim of increasing the screen size and reducing the cost, it has been attempted to form the element with a polycrystalline silicon thin film on a glass substrate at a process temperature below the distortion point of glass (about 600 ° C).

【0007】

For example, in the liquid crystal display device shown in FIG. 21, a pixel array 1, a gate driver 2, and a source driver 3 are mounted on a glass substrate 5, and a timing signal generation circuit 6 and a power supply voltage generation circuit 7 are further connected to these. The structure is adopted.

【0008】

Next, the configuration of the source driver 3 will be described. The source driver 3 is roughly classified into an analog type and a digital type according to the difference in the input video signal. In a polycrystalline silicon TFT panel in which a driver and a pixel are integrated, an analog type driver, particularly a point-sequential drive type driver, is often used because of the simplicity of the circuit configuration. On the other hand, in mobile information terminals and the like, which have been remarkably popular in recent years, since the video signal is a digital signal, it is desirable that the source driver 3 is also a digital type from the viewpoint of system configuration, power consumption, and the like.

【0009】

In the following, a point-sequential drive type source driver will be described as an example of an analog driver, and a multiplexer type source driver will be described as an example of a digital driver.

【0010】

In the point-sequential drive type analog source driver, as shown in FIG. 27, the sampling switch 13 ... Opens and closes in synchronization with the pulse signal output from the scanning circuit 11 constituting each stage of the shift register. Outputs the analog video signal DAT (signal corresponding to the three primary colors of R, G, B) input to the video signal line to the data signal line SL (SL (R), SL (G), SL (B)). Will be done. Here, the buffer circuit 12 is a circuit that takes in the pulse signal output from the scanning circuit 11, holds and amplifies the pulse signal, and generates an inverted signal thereof as needed.

【0011】

As described above, in the point-sequential drive type source driver, it is necessary to output the analog video signal DAT to the data signal line SL within the time of the pulse signal width (several tens to several hundreds nsec). A transistor with very good characteristics (large driving force) is required as the sampling switch 13. In addition, since analog signals are handled, variations in the characteristics of each transistor must be kept extremely small.

【0012】

On the other hand, the multiplexer type digital source driver operates as follows. As shown in FIG. 24, the input 9-bit digital video signal DIG (3-bit signal for each of the three primary colors R, G, and B) is latched 14 in synchronization with the pulse signal from the scanning circuit 11. ... is sampled bit by bit.

【0013】

Then, the sampled 1-bit signal is collectively transferred to the decoder 16 ... within the horizontal blanking interval by the transfer circuit 15 ..., and is decoded here. As a result, eight decoded signals are output from the decoder 16 ... for each RGB and supplied to each of the eight analog switches 17 ... Then, one of the eight gradation voltage VGSs is selected for each RGB by the analog switch 17 ... based on the above-mentioned decoded signal, and the data signal lines SL (R), SL (G), and SL (B) are selected. ) Is output.

【0014】

[Problems to be Solved by the Invention]

By the way, in the drive system as described above, an analog circuit having a large power consumption such as an amplifier is not used inside the drive circuit. Therefore, the ratio of power consumption related to an external input signal such as a clock signal is relatively large. This is because, after the shift register, only one stage of circuit (a circuit of several stages when operating several stages in parallel) operates at the same time, whereas an external input signal is input to all stages of circuits at the same time. Therefore, the capacitive load of the input line for the external input signal becomes extremely large.

【0015】

In particular, in the above-mentioned driver / pixel integrated image display device, a polycrystalline silicon thin film transistor is often used as an active element thereof. The polycrystalline silicon thin film transistor has a larger element size and a higher drive voltage than the single crystal silicon transistor, and therefore tends to consume more power based on the above-mentioned external input signal.

【0016】

Therefore, in an image display device that adopts the drive method as described above, it is effective to reduce the load of the external input signal in order to reduce the power consumption. As a technique for realizing this, for example, in Japanese Patent Publication No. 63-50717, in a point-sequential analog data signal line drive circuit (data sample circuit), a shift register is divided into a plurality of groups at regular time intervals. Discloses a method of selectively supplying a clock signal to each group. As a result, the power consumption of the shift register can be significantly reduced.

【0017】

On the other hand, even in the multiplexer type digital data signal line drive circuit, it is possible to reduce the power consumption related to the clock signal by using the above-mentioned method. However, since the multiplexer method requires a large number of video signal lines, the power associated with these video signal lines cannot be ignored.

【0018】

For example, when displaying a 512-color image, the number of digital video signals is nine (3 bits each for RGB), so nine video signal lines are required to input these. In such a configuration in which a large number of video signal lines are provided, the power consumption related to the video signal lines is likely to exceed the power consumption related to the clock signal lines, although it depends on the display pattern. Needless to say, this effect becomes even more pronounced in an image display device that displays in more colors.

【0019】

The present invention has been made to solve such a problem of the prior art, and uses a data signal line drive circuit capable of reducing power consumption related to a digital video signal line and a clock signal line, and a data signal line drive circuit thereof. It is an object of the present invention to provide an image display device.

【0020】

[Means for solving problems]

The data signal output circuit according to claim 1 of the present invention has the following means (1) to (3), that is, ( 1) A shift register that is divided by the above block and sequentially outputs a scan signal in synchronization with the clock signal, (2) A shift register that is divided in the same way as the shift register and samples the input digital signal in synchronization with the scan signal. , A selective output unit that outputs a data signal corresponding to the sampled digital signal to a plurality of output lines, and (3) a selective output unit provided in each of the above blocks, and at least a divided selective output unit in each block operates. It is characterized in that it is provided with a first supply circuit that supplies a digital signal to the divided selective output unit during a period of time.

【0021】

In the above configuration, since the first supply circuit is provided in each block, each block is digitally input from the outside by the first supply circuit at least during the period when the selective output unit in the block should operate. The signal is supplied. Therefore, the digital signal is supplied to only some blocks, but not to all blocks at all times. Therefore, the load on the signal line (digital signal line) for supplying the digital signal can be effectively reduced.

【0022】

The data signal output circuit according to claim 2 of the present invention is the data signal output circuit according to claim 1, and the supply of the digital signal by the first supply circuit is a block selection signal input from the outside. It is controlled based on.

【0023】

In the above configuration, the supply of the digital signal by the first supply circuit is controlled based on the block selection signal. Therefore, by appropriately setting the optimum block selection signal for each block, the digital signal is supplied at the same time. It is possible to minimize the number of blocks required.

【0024】

The data signal output circuit according to claim 3 of the present invention is based on a pulse signal output from a predetermined output stage in the shift register by the first supply circuit in the data signal output circuit according to claim 1. It has a selection circuit that generates a block selection signal for controlling the supply of digital signals.

【0025】

In the above configuration, since each first supply circuit has a selection circuit, the supply of the digital signal is controlled by the block selection signal based on the pulse signal from the shift register. As a result, if the block selection signal is set using the optimum pulse signal for each block, it is possible to minimize the number of blocks to which the digital signal is simultaneously supplied. As a result, it is not necessary to input the block selection signal from the outside, so that a signal line for inputting the block selection signal becomes unnecessary.

【0026】

The data signal output circuit according to claim 4 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least the divided shift registers in each block operate. A second supply circuit that supplies a clock signal to the divided shift register is further provided during the period to be specified, and the digital signal and the clock signal supply by each of the first and second supply circuits are input from the outside in common. It is controlled by the block selection signal of.

【0027】

In the above configuration, since the second supply circuit is provided in each block, each block is a clock signal input from the outside by the second supply circuit at least during the period in which the shift register in the block should operate. Is supplied. Therefore, the clock signal is supplied only to some blocks, but not always to all blocks. Therefore, the load on the signal line (clock signal line) for supplying the clock signal can be effectively reduced.

【0028】

Further, in the first and second supply circuits, the supply of the digital signal and the clock signal is commonly controlled based on the block selection signal from the outside. As a result, by appropriately setting the block selection signal for each block, it is possible to minimize the number of blocks to which the digital signal and the clock signal are simultaneously supplied.

【0029】

The data signal output circuit according to claim 5 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least the divided shift registers in each block operate. A second supply circuit that supplies a clock signal to the divided shift register is further provided during a period of time, and the digital signal and the clock signal supply by each of the first and second supply circuits are input differently from the outside. It is controlled independently by the first and second block selection signals.

【0030】

In the above configuration, since the second supply circuit is provided in each block, the load on the clock signal line can be effectively reduced as in the data signal output circuit according to claim 4. Moreover, since the signal supply by the first and second selection circuits is independently controlled by the different first and second block selection signals, it is possible to optimally control the supply of the digital signal and the supply of the clock signal, respectively. It will be possible.

【0031】

The data signal output circuit according to claim 6 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least the divided shift registers in each block operate. A second supply circuit for supplying a clock signal to the divided shift register is further provided during a period of time, and the first and second supply circuits are used as pulse signals output from a predetermined output stage in the shift register. Based on this, it shares a selection circuit that generates a block selection signal to control the supply of digital and clock signals.

【0032】

In the above configuration, since the first and second supply circuits in one block share the selection circuit, the supply of the digital signal and the clock signal is controlled by the block selection signal based on the pulse signal from the shift register. Will be done. As a result, if the block selection signal is set using the optimum pulse signal for each block, it is possible to minimize the number of blocks to which the digital signal and the clock signal are simultaneously supplied. Further, since it is not necessary to input the block selection signal from the outside, a signal line for inputting the block selection signal becomes unnecessary. Further, by sharing the selection circuit between the first and second supply circuits, the circuit scale of the data signal output circuit can be reduced.

【0033】

The data signal output circuit according to claim 7 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least the divided shift registers in each block operate. A second supply circuit that supplies a clock signal to the divided shift register during the period to be provided is further provided, and the first supply circuit is based on a pulse signal output from a predetermined output stage in the shift register. It has a first selection circuit that generates a first block selection signal for controlling the supply of digital signals, and the second supply circuit is based on a pulse signal output from a predetermined output stage in the shift register. It has a second selection circuit that generates a second block selection signal for controlling the supply of a clock signal independently of the first selection circuit.

【0034】

In the above configuration, since the first supply circuit in one block has the first selection circuit, the supply of the digital signal is controlled by the first block selection signal based on the pulse signal from the shift register. On the other hand, since the second supply circuit in the same block has the second selection circuit, the supply of the clock signal is controlled by the second block selection signal based on the pulse signal from the shift register. As a result, if the first and second block selection signals are set using the optimum pulse signal for each block, it is possible to minimize the number of blocks to which the digital signal and the clock signal are simultaneously supplied. Further, since it is not necessary to input the block selection signal from the outside, a signal line for inputting the block selection signal becomes unnecessary. Further, since the first and second selection circuits independently generate different first and second block selection signals, it is possible to optimally control the supply of the digital signal and the supply of the clock signal, respectively.

【0035】

The image display device according to claim 8 of the present invention receives a plurality of pixels arranged in a matrix and a digital video signal as the digital signal, and displays a data signal corresponding to the video signal in each pixel. The data signal output circuit according to any one of claims 1 to 7 supplied as a data signal for display and a write control circuit for controlling writing of a data signal for display to each pixel are provided. ..

【0036】

In the above configuration, when the display data signal is supplied to each pixel by the data signal output circuit, the display data signal is written to each pixel by the control by the write control circuit. As a result, the pixels display based on the display data signal.

【0037】

Further, since the data signal output circuit is the data signal output circuit according to any one of claims 1 to 7, at least as described above, the digital video signal is supplied only to a part of the blocks. However, it is not always supplied to all blocks. Therefore, the load on the signal line for supplying the video signal can be effectively reduced. Further, when the data signal output circuit is the data signal output circuit according to any one of claims 4 to 7, the load on the signal line for supplying the clock signal can be effectively reduced.

【0038】

The image display device according to claim 9 of the present invention is the image display device according to claim 8, wherein at least the data signal output circuit and the transistors constituting the pixels are formed on the same substrate as a thin film transistor. Is.

【0039】

In the above configuration, when a circuit having a large power consumption such as an amplifier is not built in the data signal output circuit, the ratio of the power consumption associated with the supply of the video signal, the clock signal, etc. becomes large in the power consumption of the data signal output circuit. .. Further, since a thin film transistor generally has a large element size and a high drive voltage, a shift register and a selective output unit composed of such a thin film transistor become a load on the signal line and tend to consume a large amount of power. .. However, even if the data signal output circuit and the transistors constituting the pixel array are thin film transistors formed on the same substrate, the load on the signal line is effectively reduced as described above, so that the data signal output circuit can be used. Power consumption can be reduced.

【0040】

The image display device according to claim 10 of the present invention is the image display device according to claim 9, wherein the transistor is a polycrystalline silicon thin film transistor formed at a temperature of 600 ° C. or lower.

【0041】

In the above configuration, since the transistor is a polycrystalline silicon thin film transistor formed at a temperature of 600 ° C. or lower, an inexpensive glass substrate can be used as the substrate.

【0042】

The image display device according to claim 11 of the present invention is the image display device according to any one of claims 8 to 10, and the selective output unit in the data signal output circuit has a plurality of gradations from the outside. A voltage is input, and by selecting one from a plurality of gradation voltages according to a plurality of bits of video signal, the selected gradation voltage is supplied to each pixel as a display data signal.

【0043】

In the above configuration, since the display data signal is supplied in response to the input multi-bit digital video signal, the data signal output circuit does not include a circuit having a large power consumption such as an amplifier. Therefore, in the power consumption of the data signal output circuit, the ratio of the power consumption associated with the supply of the video signal, the clock signal, and the like becomes large. However, as described above, since the load on the signal line is effectively reduced, the power consumption of the data signal output circuit can be reduced.

【0044】

The image display device according to claim 12 of the present invention is the image display device according to any one of claims 8 to 10, wherein the pixels are a plurality of subordinates corresponding to the number of bits of the input video signal. It is divided into pixels, and the data signal output circuit supplies a binary display data signal to each sub-pixel according to each bit of the video signal.

【0045】

In the above configuration, display is performed by a so-called area gradation display method in which gradation is expressed by a combination of binary states of display data signals supplied to each sub-pixel. When displaying, the binary display data signal is supplied to each sub-pixel according to each bit of the video signal, so that the data signal output circuit does not include a circuit having a large power consumption such as an amplifier. Therefore, in the power consumption of the data signal output circuit, the ratio of the power consumption associated with the supply of the video signal, the clock signal, and the like becomes large. However, as described above, since the load on the signal line is effectively reduced, the power consumption of the data signal output circuit can be reduced.

【0046】

Further, since the display data signal has two values, the influence of variations in the characteristics of the elements (transistors) constituting the data signal output circuit is less likely to appear in the display data signal.

【0047】

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) An embodiment of the present invention will be described below with reference to FIGS. 1 to 18. In the following description, the first to fifth data signal output circuits will be described as specific examples of the data signal output circuits according to the present embodiment.

【0048】

[First data signal output circuit] As shown in FIG. 1, the first data signal output circuit has n blocks BLK.₁~ BLK_nIt is divided into. Block BLK₁~ BLK_nEach has a plurality of shift register units (SR in the figure, SR) 21 ..., a drive unit (DV in the figure, DV) 22 ..., and a distribution circuit (SUD in the figure) 23 ... There is.

【0049】

As shown in FIG. 2, the shift register unit 21 includes clocked inverters 21a and 21b, inverters 21c, and NAND gate 21d. A latch is composed of clocked inverters 21a and 21b and inverters 21c. A shift register is constructed by connecting these latches in series and in multiple stages (only three stages are shown in FIG. 2).

【0050】

In this shift register, the start pulse SPS is sequentially shifted in synchronization with the clock signal CLK and its inverted signal, the clock signal / CLK. The signals output from the two adjacent latches are logically negated at the NAND gate 21d. As a result, the pulse signal SRP is transmitted from the shift register section 21 ...₁, SRP₂, SRP₃, ... is output.

【0051】

The drive unit 22 samples a digital video signal (hereinafter, simply referred to as a video signal) DIG in synchronization with the pulse signal SRP from the shift register unit 21, and from a plurality of gradation voltages based on the sampled video signal DIG. It is a circuit that selects one and outputs it as a data signal to the data signal line SL. The drive unit 22 ... is individually connected to the data signal line SL ..., and constitutes a selective output unit as a whole.

【0052】

The distribution circuit 23 as the first supply circuit selectively blocks the m-bit video signal DIG, as will be described later.₁~ BLK_nIt is a circuit to supply to. m represents the number of bits according to the number of display colors of the image. Therefore, m video signal lines are provided to supply a signal representing each bit. This also applies to the second to fifth data signal output circuits described later.

【0053】

The first data signal output circuit shown in FIG. 1 is more specifically configured as shown in FIG. In addition, here, block BLK₁~ BLK_nAny block in BLK_iWill be described.

【0054】

Block BLK_iIn, the distribution circuit 23 blocks the m-bit video signal DIG in a predetermined period of time._iBlock selection signal BKD input from the outside to supply to the drive unit 22 ..._iIs controlled by.

【0055】

As shown in FIG. 4, the distribution circuit 23 has the same number of NAND gates 23a ... and inverters 23b ... as the video signal lines. In this distribution circuit 23, the bit signal DIG constituting the video signal DIG is provided by the NAND gate 23a ...₍₁₎~ DIG_(m)Each and block selection signal BKD_iThe logical product denial is taken. Then, the output signal from the NAND gate 23a ... Is further inverted by the inverter 23b ... As a result, the block selection signal BKD_iVideo signal DIG when is active_i(DIG_{i (1)}~ DIG_{i (m)}) Is output and the block selection signal BKD_iVideo signal DIG when is inactive_iIs not output.

【0056】

The video signal DIG_iIs a block BLK_iIf not supplied to, block BLK_iThe video signal line inside is biased to a constant voltage.

【0057】

The operation of the first data signal output circuit configured as described above will be described with reference to the time chart of FIG.

【0058】

First, block BLK₁, BLK₂, BLK₃In, ..., the block selection signal BKD from each distribution circuit 23 ...₁, BKD₂, BKD₃Video signal DIG while, ... is active (high level)₁, DIG₂, DIG₃, ... is output. At this time, the video signal DIG₁, DIG₂, DIG₃Block selection signal BKD so that the beginning and end of, ... are not lost₁, BKD₂, BKD₃, ... are active for a specified period of time.

【0059】

Meanwhile, block BLK₁From the shift register section 21 ... in, the pulse signal SRP is synchronized with the clock signal CLK.₁₍₁₎, SRP₁₍₂₎, SRP₁₍₃₎, ... are output sequentially with a shift of half a clock of the clock signal CLK. Block BLK₂~ Block BLK_nSimilarly, the pulse signal SRP is output from the shift register section 21 ...

【0060】

Video signal DIG from distribution circuit 23_iIs the block selection signal BKD_iIs taken into the drive unit 22 ... in synchronization with the pulse signal SRP from the shift register unit 21 ... during the period in which is active. In the drive unit 22 ..., a plurality of gradation voltages (not shown) are video signals DIG._iIs selected based on. The selected gradation voltage is output to the data signal line SL ... as a display data signal (data signal).

【0061】

As described above, the first data signal output circuit is divided by the distribution circuit 23 ... for only the minimum necessary period.₁~ BLK_nVideo signal DIG₁~ DIG_nIs to be supplied. Specifically, the first data signal output circuit is the block BLK._iAt least the pulse signal SRP_iThe block selection signal BKD that becomes active during the period when is being output from the shift register section 21 ..._iBased on block BLK_iVideo signal DIG_iBlock selection signal BKD that supplies and becomes inactive during other periods_iVideo signal DIG based on_iDo not supply.

【0062】

As a result, the video signal DIG is sent to the drive unit 22 ..._iThe period to capture is block BLK_iRequired video signal DIG as it is determined for each_iBlock only BLK_iCan be supplied to. Thus, the block BLK_iSelectively video signal DIG_iBy supplying the above, the effective load on the video signal line can be reduced. As a result, the power consumption caused by the video signal DIG can be significantly reduced.

【0063】

In the first data signal output circuit, if the number of divisions n is increased, the effective load of the video signal line can be further reduced. On the other hand, since the number of distribution circuits 23 ... increases, the power consumption increases due to the load in the distribution circuits 23 ..., and the scale of the first data signal output circuit also increases. Therefore, it is desirable to select the optimum number of divisions in consideration of the total power consumption of the first data signal output circuit, the circuit scale, and the like.

【0064】

[Second data signal output circuit] As shown in FIG. 6, the second data signal output circuit is the block BLK, similarly to the first data signal output circuit described above.₁~ BLK_nIt is divided into blocks BLK₁~ BLK_nIs equipped with a distribution circuit 24 instead of the distribution circuit 23, and a block BLK_xIt has. Block BLK_xIs a block BLK_nIt is provided in the next stage of the above and has one shift register unit 21. This shift register section 21 is a block BLK._nIn addition to being connected in series to the shift register section 21 of the final stage in, the clock signal CLK is given.

【0065】

Also, block BLK₁~ BLK_n-1The pulse signal SRP from the shift register section 21 of the final stage in is the block BLK of the next stage, respectively.₂~ BLK_nIt is designed to be supplied to the distribution circuit 24 of. In addition, block BLK₂~ BLK_nThe pulse signal SRP from the shift register section 21 of the first stage in the above is the block BLK of the previous stage.₁~ BLK_n-1It is designed to be supplied to the distribution circuit 24 of.

【0066】

In addition, block BLK₁SPS is supplied to the distribution circuit 24 in the block BLK_nBlock BLK on the distribution circuit 24 in_xThe pulse signal SRP from the shift register section 21 of the above is supplied.

【0067】

As shown in FIG. 7, the distribution circuit 24 has NOR gates 24a and 24b, an inverter 24c, a NAND gate 24d ..., and an inverter 24e ... The NOR gates 24a and 24b form an RS flip-flop, and the RS flip-flop and the inverter 24c form a selection circuit.

【0068】

Block BLK_iIn the distribution circuit 24 in, the block BLK in the previous stage_i-1The pulse signal SRP from the shift register unit 21 in the final stage of the above is input to the NOR gate 24a as a set signal S. As a result, the output of the NOR gate 24a becomes low level, so the active block selection signal BKD is transmitted from the inverter 24c provided in the next stage._iIs output. And the video signal DIG (DIG) by the NAND gate 24d ...₍₁₎~ DIG_(m)) And block selection signal BKD_iWhen the logical product denial is taken, the video signal DIG from the NAND gate 24d ... via the inverter 24e ..._i(DIG_{i (1)}~ DIG_{i (m)}) Is output.

【0069】

Meanwhile, block BLK_iIn the distribution circuit 24 in, the subsequent block BLK_{i +}₁The pulse signal SRP from the shift register section 21 of the first stage in₁Is input to the NOR gate 24b, so the block selection signal BKD_iBecomes inactive. Therefore, the video signal DIG from the inverter 24e ..._iIs no longer output.

【0070】

The video signal DIG_iIs a block BLK_iIf not supplied to, block BLK_iThe video signal line inside is biased to a constant voltage.

【0071】

In the second data signal output circuit configured as described above, the block BLK in the previous stage_i-1By the pulse signal SRP (set signal S) from the shift register section 21 of the final stage in_iVideo signal to DIG_iSupply is started. In addition, the block BLK in the latter stage_{i + 1}Pulse signal SRP (reset signal R) from the shift register section 21 of the first stage in₁) By block BLK_iVideo signal to DIG_iSupply is stopped. Therefore, the video signal DIG_iIs at least block BLK_iBlock BLK during the period to be incorporated into the drive unit 22 ..._iIs supplied to, and is not supplied during other periods.

【0072】

In this way, the second data signal output circuit utilizes the pulse signal SRP from the shift register section 21 to block BLK._iBlock selection signal BKD inside_iIs to be generated. As a result, the block selection signal BKD_iSince it is not necessary to supply the data from the outside, the number of input terminals can be reduced as compared with the first data signal output circuit, and the configuration of the external system in which the second data signal output circuit is incorporated can be simplified. ..

【0073】

Of course, the second data signal output circuit can also reduce the effective load of the video signal line, like the first data signal output circuit. As a result, the power consumption caused by the video signal DIG can be significantly reduced.

【0074】

[Third data signal output circuit] As shown in FIG. 8, the third data signal output circuit has the same basic configuration as the first data signal output circuit described above, but the block BLK.₁~ BLK_nDistribution circuits (SUC in the figure) 25 ... are added to each. The distribution circuit 25 as the second supply circuit selectively blocks the clock signals CLK and / CLK BLK.₁~ BLK_nIt is a circuit to supply to.

【0075】

The third data signal output circuit shown in FIG. 8 is more specifically configured as shown in FIG. In addition, here, block BLK₁~ BLK_nAny block in BLK_iWill be described.

【0076】

Block BLK_iIn, the distribution circuit 25 blocks the clock signal CLK for a predetermined period of time._iBlock selection signal BKD input from the outside to supply to the shift register section 21 ..._iIs controlled by.

【0077】

As shown in FIG. 10, the distribution circuit 25 has a NAND gate 25a and inverters 25b / 25c, and the block selection signal BKD._iIs given in common with the distribution circuit 23. This distribution circuit 25 has a clock signal CLK and a block selection signal BKD at the NAND gate 25a._iSince the logical product negation with is taken, the block selection signal BKD_iClock signal CLK when is active_i / CLK_iIs output, and the block selection signal BKD_iClock signal CLK when is inactive_i / CLK_iIs not output.

【0078】

The clock signal CLK_i / CLK_iIs a block BLK_iIf not supplied to, block BLK_iThe clock signal line inside is biased to a constant voltage.

【0079】

The operation of the third data signal output circuit configured as described above will be described with reference to the time chart of FIG.

【0080】

Block BLK₁, BLK₂, BLK₃In, ..., the block selection signal BKD from each distribution circuit 25 ...₁, BKD₂, BKD₃Clock signal CLK while, ... is active (high level)₁, CLK₂, CLK₃, ... (clock signal / CLK_iIs not shown) is output. At this time, the clock signal CLK₁, CLK₂, CLK₃Block selection signal BKD so that the first and last clocks in, ... are not lost₁, BKD₂, BKD₃, ... are active for a specified period of time.

【0081】

Block BLK₁From the shift register section 21 ... in, the clock signal CLK₁Pulse signal SRP synchronized with₁₍₁₎, SRP₁₍₂₎, SRP₁₍₃₎, ... are output in sequence. Block BLK₂~ Block BLK_nSimilarly, the pulse signal SRP is output from the shift register section 21 ...

【0082】

On the other hand, the block selection signal BKD is the same as the first data signal output circuit._iDuring the period when is active, the video signal DIG_iIs output from the distribution circuit 23. And this video signal DIG_iIs taken into the drive unit 22 ... in synchronization with the pulse signal SRP, and the video signal DIG is taken by the drive unit 22 ..._iThe gradation voltage selected based on is output to the data signal line SL ...

【0083】

As described above, the third data signal output circuit shown in FIG. 9 is a divided block BLK.₁~ BLK_nIn addition, the video signal DIG by the distribution circuit 23 ...₁~ DIG_nThe clock signal CLK is supplied by the distribution circuit 25 ...₁~ CLK_nIs to be supplied. Specifically, this third data signal output circuit is the block BLK._iAt least the pulse signal SRP_iBlock selection signal BKD that becomes active during the period when is output from the shift register section 21 ... and a predetermined period before and after that period._iBased on block BLK_iVideo signal DIG_iAnd clock signal CLK_iBlock selection signal BKD that supplies and becomes inactive during other periods_iVideo signal DIG based on_iAnd clock signal CLK_iDo not supply.

【0084】

As a result, the video signal DIG is sent to the drive unit 22 ..._iClock signal CLK in the period to be taken in and the shift register section 21 ..._iThe period to supply is block BLK_iIt is determined for each. Therefore, the required video signal DIG_iAnd clock signal CLK_iBlock only BLK_iCan be supplied to. Thus, the block BLK_iSelectively video signal DIG_iAnd clock signal CLK_iBy supplying the above, the effective load of the video signal line and the clock signal line can be reduced. As a result, the power consumption caused by the video signal DIG and the clock signal CLK can be significantly reduced.

【0085】

Further, by sharing the block selection signal BKD between the distribution circuit 23 ... and the distribution circuit 25 ..., the number of signal lines does not increase. Therefore, it is possible to suppress an increase in the number of input terminals of the third data signal output circuit and simplify the configuration of the external system in which the third data signal output circuit is incorporated.

【0086】

By the way, the third data signal output circuit shown in FIG. 8 is more specifically configured as shown in FIG. Also here, block BLK₁~ BLK_nAny block in BLK_iWill be described.

【0087】

Block BLK_iIn, the distribution circuit 25 blocks the clock signal CLK for a predetermined period of time._iBlock selection signal BKC as a second block selection signal input from the outside to supply to the shift register section 21 ..._iIs controlled by.

【0088】

As shown in FIG. 13, the distribution circuit 25 has a NAND gate 25a and inverters 25b / 25c, but unlike the distribution circuit 25 shown in FIG. 10, the block selection signal BKD is attached to the NAND gate 25a._iBlock selection signal BKC instead of_iIs entered. Therefore, this distribution circuit 25 uses the block selection signal BKC._iClock signal CLK when is active_i / CLK_iIs output, and the block selection signal BKC_iClock signal CLK when is inactive_i / CLK_iIs not output.

【0089】

The operation of the third data signal output circuit configured as described above will be described with reference to the time chart of FIG.

【0090】

Block BLK₁, BLK₂, BLK₃In, ..., the block selection signal BKC from each distribution circuit 25 ...₁, BKC₂, BKC₃Clock signal CLK while, ... is active (high level)₁, CLK₂, CLK₃, ... (clock signal / CLK_iIs not shown) is output. At this time, the clock signal CLK₁, CLK₂, CLK₃Block selection signal BKC so that the first and last clocks in, ... are not lost₁, BKC₂, BKC₃, ... are activated more than once for a predetermined period of time.

【0091】

Block BLK₁From the shift register section 21 ... in, the clock signal CLK₁Pulse signal SRP synchronized with₁₍₁₎, SRP₁₍₂₎, SRP₁₍₃₎, ... are output in sequence. Block BLK₂~ Block BLK_nSimilarly, the pulse signal SRP is output from the shift register section 21 ...

【0092】

On the other hand, the video signal DIG_iIs the block selection signal BKD as the first block selection signal_iIs output from the distribution circuit 23 during the active period, and is further taken into the drive unit 22 ... in synchronization with the pulse signal SRP. And the video signal DIG by the drive unit 22 ..._iThe gradation voltage selected based on is output to the data signal line SL ... as a display data signal (data signal).

【0093】

As described above, the third data signal output circuit shown in FIG. 12 is a block BLK for only the minimum necessary period by the distribution circuit 25 ...₁~ BLK_nClock signal CLK₁~ CLK_nIs to be supplied. Specifically, this third data signal output circuit is the block BLK._iAt least the pulse signal SRP_iThe block selection signal BKC that becomes active during the period in which is output from the shift register section 21 ... and the predetermined period before and after that period._iBased on block BLK_iClock signal CLK_iBlock selection signal BKC that supplies and becomes inactive during other periods_iClock signal CLK based on_iDo not supply.

【0094】

As a result, the clock signal CLK is sent to the shift register section 21 ..._iThe video signal DIG to the drive unit 22 ..._iBlock BLK independently of the period in which it should be supplied_iIt is determined for each. Therefore, the required clock signal CLK_iBlock only BLK_iCan be supplied to. As a result, it becomes possible to set the optimum signal supply period for each of the video signal DIG and the clock signal CLK as follows.

【0095】

If the video signal DIG is input from the outside during the period when the pulse signal SRP is output from the shift register section 21 ..., the block BLK is surely blocked even if the overlapping period between the active periods of the block selection signal BKD is short. Is supplied to. However, if the active period of the block selection signal BKC is the same as the active period of the block selection signal BKD, the clock signal CLK cannot reliably transmit the rising and falling edges of the pulse signal SRP.

【0096】

In order to eliminate such inconvenience, the third data signal output circuit shown in FIG. 12 has distribution circuits 23 and 25 for the video signal DIG and the clock signal CLK, respectively, and separate block selection signals BKD and BKC. It is configured to control the signal supply. Therefore, as shown in FIG. 14, the block selection signal BKC_iBlock selection signal BKD when is changing from active to inactive_iClock signal CLK for a longer period by delaying from the same period of_iCan be supplied.

【0097】

The third data signal output circuit shown in FIG. 12 is also a block BLK like the third data signal output circuit shown in FIG._iSelectively video signal DIG_iAnd clock signal CLK_iOf course, the effective load of the video signal line and the clock signal line can be reduced by supplying the above. As a result, the power consumption caused by the video signal DIG and the clock signal CLK can be significantly reduced.

【0098】

[Fourth Data Signal Output Circuit] As shown in FIG. 15, the fourth data signal output circuit is the block BLK, similarly to the third data signal output circuit described above.₁~ BLK_nIt is divided into blocks BLK₁~ BLK_nIs equipped with distribution circuits 24 and 26, which are different from distribution circuits 23 and 25, and further blocks BLK_yIt has. Block BLK_yIs a block BLK_nIt is provided in the next stage of the above and has two shift register units 21. These shift register units 21 and 21 are block BLK._nIn addition to being connected in series to the shift register section 21 of the final stage in, the clock signal CLK is given.

【0099】

Block BLK₁~ BLK_n-1The pulse signal SRP from the shift register section 21 of the final stage in is the block BLK of the next stage, respectively.₂~ BLK_nIt is designed to be supplied to the distribution circuits 24 and 26 of. Also, block BLK₂~ BLK_nThe pulse signal SRP from the shift register section 21 of the first stage in the above is the block BLK of the previous stage.₁~ BLK_n-1It is designed to be supplied to the distribution circuit 24 of. In addition, block BLK₂~ BLK_nThe pulse signal SRP from the shift register section 21 of the second stage in the above is the block BLK of the previous stage, respectively.₁~ BLK_n-1It is designed to be supplied to the distribution circuit 26 of.

【0100】

In addition, block BLK₁SPS is supplied to the distribution circuits 24 and 26 in the above. Also, block BLK_nIn the distribution circuits 24 and 26, the block BLK_yThe pulse signals SRP from the shift register units 21 and 21 of the first stage and the second stage in the above are supplied respectively.

【0101】

As shown in FIG. 16, the distribution circuit 26 as the second supply circuit has NOR gates 26a and 26b, NAND gates 26c and 26d, and inverters 26e and 26f. The NOR gates 26a and 26b form an RS flip-flop, and the RS flip-flop and the NAND gate 26c form a second selection circuit.

【0102】

An initialization signal / INT is input to the NAND gate 26c from the outside. This initialization signal / INT is usually inactive (high level) and is a signal that becomes active when the power is turned on. Therefore, the NAND gate 26c takes the logical product denial of the output signal from the NOR gate 26a and the initialization signal / INT, so that the block selection signal BKC as the second block selection signal_iIs to be output. Also, when the power is turned on, all block selection signals BKC_iSince the internal node is initialized by outputting, malfunction can be prevented.

【0103】

Block BLK_iIn the distribution circuit 26 in, the block BLK in the previous stage_i-1The pulse signal SRP from the shift register unit 21 in the final stage of the above is input to the NOR gate 26a as a set signal S. As a result, the output of the NOR gate 26a becomes inactive, so the active block selection signal BKC from the NAND gate 26c_iIs output.

【0104】

Then, the clock signal CLK is generated by the NAND gate 26d._iAnd block selection signal BKC_iBy taking the logical product negation with, the clock signal CLK from the NAND gate 26d via the inverter 26e_iIs output. Also, the clock signal / CLK from the inverter 26e via the inverter 26f._iIs output.

【0105】

Meanwhile, block BLK_iIn the distribution circuit 26 in, the subsequent block BLK_{i +}₁The pulse signal SRP from the shift register section 21 of the first stage in₂Is input to the NOR gate 26b, so the block selection signal BKC_iBecomes inactive. Therefore, the clock signal CLK from the inverters 26e and 26f_i / CLK_iIs no longer output.

【0106】

The clock signal CLK_i / CLK_iIs a block BLK_iIf not supplied to, block BLK_iThe clock signal line inside is biased to a constant voltage.

【0107】

Block BLK_iThe distribution circuit 24 in the above is configured as shown in FIG. 7 in the same manner as the distribution circuit 24 in the second data signal output circuit. In the fourth data signal output circuit, the first selection circuit is composed of the RS flip-flops (NOR gates 24a and 24b) in the distribution circuit 24 and the inverter 24c.

【0108】

As a result, the block BLK in the previous stage_i-1When the pulse signal SRP from the shift register section 21 of the final stage in the above is input to the NOR gate 24a as the set signal S, the active block selection signal BKD_iIs output. Therefore, from the distribution circuit 24, the video signal DIG_iIs output. On the other hand, the latter block BLK_{i + 1}The pulse signal SRP from the shift register section 21 of the first stage in₁When input to the NOR gate 24b, the video signal DIG from the inverter 24e_iIs no longer output.

【0109】

The video signal DIG_iIs a block BLK_iIf not supplied to, block BLK_iThe video signal line inside is biased to a constant voltage.

【0110】

In the fourth data signal output circuit configured as described above, as shown in FIG. 14, the block BLK in the previous stage_i-1Pulse signal SRP from the shift register section 21 in the final stage of_{i-1 (n)}Block BLK by (set signal S)_iVideo signal to DIG_iSupply is started. In addition, the block BLK in the latter stage_{i + 1}Pulse signal SRP from the shift register section 21 of the first stage in_{i + 1 (1)}(Reset signal R₁) By block BLK_iVideo signal to DIG_iSupply is stopped. Therefore, the video signal DIG_iIs at least block BLK_iIt is supplied to the block during the period to be taken in by the drive unit 22 ... in, and is not supplied in other periods.

【0111】

On the other hand, the block BLK in the previous stage_i-1Pulse signal SRP from the shift register section 21 in the final stage of_{i-1 (n)}Block BLK by (set signal S)_iClock signal to CLK_i / CLK_iSupply is started. In addition, the block BLK in the latter stage_{i + 1}Pulse signal SRP from the shift register section 21 of the second stage in_{i + 1 (2)}(Reset signal R₂) By block BLK_iClock signal to CLK_i / CLK_iSupply is stopped.

【0112】

Therefore, the video signal DIG_iIs at least block BLK_iIt is supplied to the block during the period to be taken in by the drive unit 22 ... in, and is not supplied in other periods. Also, the clock signal CLK_i / CLK_iAlso, in the same way, block BLK for the required period_iIt is supplied to the shift register section 21 ... in, and is not supplied in other periods.

【0113】

As a result, the video signal DIG is sent to the drive unit 22 ..._iClock signal CLK in the period to be taken in and the shift register section 21 ..._iThe period to supply is block BLK_iIt is determined for each. Therefore, the required video signal DIG_iAnd clock signal CLK_iBlock only BLK_iCan be supplied to. Thus, the block BLK_iSelectively video signal DIG_iAnd clock signal CLK_iBy supplying the above, the effective load of the video signal line and the clock signal line can be reduced.

【0114】

As a result, the power consumption caused by the video signal DIG and the clock signal CLK can be significantly reduced.

【0115】

The fourth data signal output circuit uses the pulse signal SRP from the shift register section 21 to block BLK._iBlock selection signal BKD inside_i BKC_iIs to be generated. As a result, the block selection signal BKD_i BKC_iSince it is not necessary to supply the data from the outside, the number of input terminals can be reduced as compared with the third data signal output circuit, and the configuration of the external system in which the fourth data signal output circuit is incorporated can be simplified. ..

【0116】

In addition, the clock signal CLK_iThe period for supplying the video signal DIG_iSince it is determined independently of the period in which the data should be supplied, it is possible to set the optimum signal supply period for each of the video signal DIG and the clock signal CLK, similar to the third data signal output circuit shown in FIG. Become.

【0117】

[Fifth Data Signal Output Circuit] As shown in FIG. 17, the fifth data signal output circuit is the block BLK, similarly to the fourth data signal output circuit described above.₁~ BLK_nAs well as being divided into blocks BLK_yFeatures, but block BLK₁~ BLK_nHas a distribution circuit 28 that is different from the distribution circuits 24 and 26. The distribution circuit 28 constitutes the first and second supply circuits.

【0118】

Block BLK₁~ BLK_n-1The pulse signal SRP from the shift register section 21 of the final stage in is the block BLK of the next stage, respectively.₂~ BLK_nIt is designed to be supplied to the distribution circuit 28 of. Also, block BLK₂~ BLK_nThe pulse signal SRP from the shift register section 21 of the second stage in the above is the block BLK of the previous stage, respectively.₁~ BLK_n-1It is designed to be supplied to the distribution circuit 28 of.

【0119】

In addition, block BLK₁SPS is supplied to the distribution circuit 28 in the above. Also, block BLK_nIn the distribution circuit 28, block BLK_yThe pulse signal SRP from the shift register section 21 of the second stage in the above is supplied.

【0120】

As shown in FIG. 18, the distribution circuit 28 has NOR gates 28a / 28b, NAND gates 28c / 28d, inverters 28e / 28f, NAND gates 28g ... and inverters 28h .... The NOR gates 28a and 28b form an RS flip-flop, and the RS flip-flop and the NAND gate 28c form a selection circuit.

【0121】

The above-mentioned initialization signal / INT is input to the NAND gate 28c from the outside. Therefore, the NAND gate 28c determines the block selection signal BKD by negating the logical product of the output signal from the NOR gate 28a and the initialization signal / INT._iIs to be output. Also, when the power is turned on, as described above, all block selection signals BKD_iBy outputting, malfunction can be prevented.

【0122】

Block BLK_iIn the distribution circuit 28 in, the block BLK in the previous stage_i-1The pulse signal SRP from the shift register section 21 in the final stage of the above is input to the NOR gate 28a as a set signal S. As a result, the output of the NOR gate 28a becomes inactive, so the active block selection signal BKD from the NAND gate 28c_iIs output.

【0123】

Then, the clock signal CLK and the block selection signal BKD are generated by the NAND gate 28d._iBy taking the logical product negation with, the clock signal CLK from the NAND gate 28d via the inverter 28e_iIs output. Also, the clock signal / CLK from the inverter 28e via the inverter 28f._iIs output. Furthermore, the bit signal DIG that constitutes the video signal DIG with the NAND gate 28g ...₍₁₎~ DIG_(m)And block selection signal BKD_iBy taking the logical product denial of, the video signal DIG from the NAND gate 28g ... via the inverter 28h ..._i(DIG_{i (1)}~ DIG_{i (m)}) Is output.

【0124】

Meanwhile, block BLK_iIn the distribution circuit 28 in, the subsequent block BLK_{i +}₁The pulse signal SRP from the shift register section 21 of the second stage in₂Is input to the NOR gate 28b, so the block selection signal BKD_iBecomes inactive. Therefore, the clock signal CLK from the inverters 28e and 28f._i / CLK_iIs no longer output, and the video signal DIG from the inverter 28h ..._iIs no longer output.

【0125】

The video signal DIG_iIs a block BLK_iIf not supplied to, block BLK_iThe video signal line inside is biased to a constant voltage. Also, the clock signal CLK_iIs a block BLK_iIf not supplied to, block BLK_iThe clock signal line inside is biased to a constant voltage.

【0126】

In the fifth data signal output circuit configured as described above, as shown in FIG. 11, the block BLK in the previous stage_i-1Pulse signal SRP from the shift register section 21 in the final stage of_{i-1 (n)}Block BLK by (set signal S)_iVideo signal to DIG_iAnd clock signal CLK_i / CLK_iSupply is started. In addition, the block BLK in the latter stage_{i + 1}Pulse signal SRP from the shift register section 21 of the second stage in_{i + 1 (2)}(Reset signal R₂) By block BLK_iVideo signal to DIG_iAnd clock signal CLK_i / CLK_iSupply is stopped.

【0127】

Therefore, the video signal DIG_iIs at least block BLK_iIt is supplied to the block during the period to be taken in by the drive unit 22 ... in, and is not supplied in other periods. Also, the clock signal CLK_i / CLK_iAlso, in the same way, block BLK for the required period_iIt is supplied to the shift register section 21 ... in, and is not supplied in other periods.

【0128】

As a result, the video signal DIG is sent to the drive unit 22 ..._iClock signal CLK in the period to be taken in and the shift register section 21 ..._iThe period to supply is block BLK_iRequired video signal DIG as it is determined for each_iAnd clock signal CLK_iBlock only BLK_iCan be supplied to. Thus, the block BLK_iSelectively video signal DIG_iAnd clock signal CLK_iBy supplying the above, the effective load of the video signal line and the clock signal line can be reduced. As a result, the power consumption caused by the video signal DIG and the clock signal CLK can be significantly reduced.

【0129】

The fifth data signal output circuit uses the pulse signal SRP from the shift register section 21 to block BLK._iBlock selection signal BKD inside_iIs to be generated. As a result, the block selection signal BKD_iSince it is not necessary to supply the data from the outside, the number of input terminals can be reduced and the configuration of the external system can be simplified as in the case of the fourth data signal output circuit.

【0130】

Further, the distribution circuit 28 uses the block selection signal BKD._iTherefore, the supply of the video signal DIG and the clock signal CLK is controlled. Therefore, in the distribution circuit 28, the selection circuit including the NOR gates 28a and 28b and the NAND gate 28c can be shared between the supply unit of the video signal DIG and the supply unit of the clock signal CLK. Therefore, unlike the fourth data signal output circuit, the fifth data signal output circuit cannot independently control the supply of the video signal DIG and the clock signal CLK, but the configuration of the distribution circuit 28 is simplified. Therefore, the power consumption can be reduced as compared with the fourth data signal output circuit.

【0131】

(Embodiment 2) Other embodiments of the present invention will be described below with reference to FIGS. 19 to 26. In the following description, the first to third image display devices will be described as specific examples of the image display devices according to the present embodiment.

【0132】

[First Image Display Device] As shown in FIG. 19, the first image display device includes a pixel array 1, a scanning signal line drive circuit (hereinafter referred to as a gate driver) 2, and a data signal line drive circuit (hereinafter referred to as a gate driver). Hereinafter referred to as a source driver) 33. The pixel array 1 includes a large number of scanning signal lines GL ... and a large number of data signal lines SL ... that intersect each other, and two adjacent scanning signal lines GL / GL and two adjacent scanning signal lines GL ... Pixels (PIX in the figure) 4 ... are arranged in a matrix in the portion surrounded by the data signal lines SL and SL.

【0133】

The source driver 33 as a data signal output circuit samples the video signal DIG input in synchronization with the timing signal such as the clock signal CKS, and outputs the corresponding gradation display data to each data signal line SL. It has become like. The gate driver 2 as a write control circuit sequentially selects scanning signal lines GL ... in synchronization with a timing signal such as a clock signal CKG, and controls the opening and closing of a pixel transistor SW provided in pixel 4, which will be described later. It is designed to do. As a result, the gradation display data (gradation voltage) corresponding to the video signal output to each data signal line SL is written and held in each pixel 4.

【0134】

As shown in FIG. 20, the above pixel 4 has a pixel transistor SW and a pixel capacitance C, which are switching elements._PConsists of. Pixel capacity C_PIs the liquid crystal capacity C_LAnd auxiliary capacity C added as needed_SConsists of. In FIG. 20, the data signal line (source line) SL and the pixel capacitance C are passed through the source and drain of the transistor SW._POne electrode is connected, and the gate of the pixel transistor SW composed of a field effect transistor is connected to the scanning signal line (gate line) GL, and the pixel capacitance C_PThe other electrode is connected to a common electrode (not shown) common to all pixels 4 ... And each liquid crystal capacity C_LWhen a voltage (gradation voltage) is applied to, the transmittance or reflectance of the liquid crystal is modulated, and an image corresponding to the video signal DIG is displayed on the pixel array 1 ...

【0135】

The common electrodes are provided so as to face the pixel electrodes (not shown) of the pixels 4 ... via the liquid crystal layer.

【0136】

In an image display device such as a liquid crystal display device, it is effective to reduce the power consumption of the drive circuit in order to reduce the power consumption. On the other hand, the source driver 33 is composed of any of the first to fifth data signal output circuits. As a result, as described above, it is possible to reduce the power consumption related to the video signal and the clock signal in each data signal output circuit, so that a low power consumption image display device can be realized.

【0137】

[Second Image Display Device] As shown in FIG. 21, the second image display device includes a pixel array 1, a gate driver 2, and a source driver 33, similarly to the first image display device. Further, it includes a timing signal generation circuit (hereinafter referred to as a timing circuit) 6 and a power supply voltage generation circuit (hereinafter referred to as a power supply circuit) 7.

【0138】

In this second image display device, the gate driver 2 and the source driver 33 are formed together with the pixel array 1 on an insulating substrate, for example, a glass substrate 5. As the insulating substrate (substrate), a sapphire substrate, a quartz substrate, non-alkali glass, or the like is often used. Further, a thin film transistor is used as the pixel transistor SW, and the gate driver 2 and the source driver 33 are composed of the thin film transistor.

【0139】

The timing circuit 6 outputs a timing signal to be given to the gate driver 2, that is, a clock signal CKG, a start pulse SPG, a synchronization signal GPS, and the like. Further, the timing circuit 6 outputs timing signals such as a video signal DIG, a clock signal CKS (clock signal CLK), and a start pulse SPS to be given to the source driver 33.

【0140】

The power supply circuit 7 has a power supply voltage V on the high potential side given to the gate driver 2._GHAnd the power supply voltage V on the low potential side_GLAnd the power supply voltage V on the high potential side given to the source driver 33_SHAnd the power supply voltage V on the low potential side_SLAnd is to be output. Further, the power supply circuit 7 outputs a common potential COM given to the common electrode. Further, the power supply circuit 7 outputs a plurality of gradation voltages, which will be described later.

【0141】

Also in the second image display device configured in this way, since the source driver 33 is configured by any of the first to fifth data signal output circuits described above, it is the same as the first image display device. , Low power consumption can be realized.

【0142】

By the way, the thin film transistor is a polycrystalline silicon thin film transistor having a structure as shown in FIG. In this structure, a silicon oxide film 41 for preventing contamination is deposited on the glass substrate 5, and a field effect transistor is formed on the silicon oxide film 41.

【0143】

The thin film transistor is a polycrystalline silicon thin film 42 composed of a channel region 42a, a source region 42b and a drain region 42c formed on the silicon oxide film 41, and a gate insulating film 43 and a gate electrode 44 formed on the polycrystalline silicon thin film 42. It is composed of an interlayer insulating film 45 and metal wirings 46 and 46.

【0144】

With such a configuration, only the timing signal and the video signal from the timing circuit 6 and various voltages from the power supply circuit 7 are input from the outside of the glass substrate 5. Therefore, in the second image display device, the number of input terminals to the glass substrate 5 is smaller than that in the image display device using an external IC as a driver. As a result, it is possible to reduce the cost for mounting the component on the glass substrate 5 and the occurrence of defects due to the mounting.

【0145】

Further, the thin film transistor tends to have a large element size and a high drive voltage. Therefore, a circuit composed of such a thin film transistor generally becomes a load on a video signal line and a clock signal line in a source driver, and tends to consume a large amount of power. However, in this image display device, since the source driver 33 is composed of any of the above-mentioned first to fifth data signal output circuits, power consumption can be reduced even if a thin film transistor is used. Therefore, even in a source driver using a thin film transistor, which is difficult to reduce power consumption, the power consumption can be easily reduced.

【0146】

In this image display device, not only the structure shown in FIG. 22 but also a single crystal silicon thin film transistor, an amorphous silicon thin film transistor, or a thin film transistor made of another material can be applied.

【0147】

The thin film transistor is manufactured, for example, by the following process.

【0148】

First, the amorphous silicon thin film a-Si is deposited on the glass substrate 5 shown in FIG. 23 (a) (FIG. 23 (b)). Next, the amorphous silicon thin film a-Si is irradiated with an excimer laser to form a polycrystalline silicon thin film 42 (FIG. 23 (c)). The polycrystalline silicon thin film 42 is patterned into a desired shape (FIG. 23 (d)), and a gate insulating film 43 made of silicon dioxide is formed on the polycrystalline silicon thin film 42 (FIG. 23 (e)).

【0149】

Further, the gate electrode 44 is made of aluminum or the like (FIG. 23 (f)). After that, impurities (phosphorus in the n-type region and arsenic in the p-type region) are injected into the portions of the polycrystalline silicon thin film 42 that should be the source region 42b and the drain region 42c (Fig. 23 (g) (h)). When injecting impurities into the n-type region, mask the p-type region with resist 48 (Fig. 23 (g)), and when injecting impurities into the p-type region, mask the n-type region with resist 48. (Fig. 23 (h)).

【0150】

Then, an interlayer insulating film 45 made of silicon dioxide, silicon nitride or the like is deposited (FIG. 23 (i)), and a contact hole 45a ... Is formed in the interlayer insulating film 45 (FIG. 23 (j)). Finally, a metal wiring 46 ... such as aluminum is formed in the contact hole 45a ... (Fig. 23 (k)).

【0151】

The maximum temperature in the above process is 600 ° C or less when the gate insulating film 43 is formed. Therefore, it is not necessary to use an expensive quartz substrate having extremely high heat resistance as the insulating substrate, and an inexpensive high heat resistant glass such as 1737 glass manufactured by Corning Inc. of the United States can be used. Therefore, it becomes possible to provide a liquid crystal display device at low cost.

【0152】

In the manufacture of a liquid crystal display device, a transparent electrode (in the case of a transmissive liquid crystal display device) or a reflective electrode (reflective type) is placed on the thin film transistor produced as described above via another interlayer insulating film. In the case of a liquid crystal display device) is formed.

【0153】

By adopting the above process, a polycrystalline silicon thin film transistor can be formed on a glass substrate which is inexpensive and can have a large area. Therefore, it is possible to easily reduce the cost and increase the size of the liquid crystal display device.

【0154】

Further, such a polycrystalline silicon thin film transistor formed at a relatively low temperature has a larger element size and a higher drive voltage than a single crystal silicon transistor. Therefore, when the polycrystalline silicon thin film transistor is used as the thin film transistor constituting the source driver 33, the power consumption related to the above-mentioned video signal and clock signal becomes large. However, since the source driver 33 is composed of the first to fifth data signal output circuits, it is possible to utilize the characteristics of the polycrystalline silicon thin film transistor such as high mobility while reducing the power consumption.

【0155】

[Source Driver] A specific example of the source driver 33 used in the first or second image display device will be described with reference to FIG. 24.

【0156】

A 9-bit video signal DIG (equivalent to 512 colors) consisting of a 3-bit signal for each of the three primary colors R, G, and B is input to the source driver 33. Further, the source driver 33 is a multiplexer type digital source driver, and includes a scanning circuit 11, a latch 14, a transfer circuit 15, a decoder 16, and an analog switch 17.

【0157】

One latch 14, one transfer circuit 15, and one decoder 16 are provided for RGB. In addition, eight analog switches 17 are provided for each of RGB.

【0158】

The scanning circuit 11 is a circuit corresponding to the shift register unit 21 described above, and the start pulse SPS is sequentially shifted to the scanning circuit 11 of the next stage by the clock signal CKS. The scanning circuit 11 outputs three pulse signals for RGB.

【0159】

The latch 14 is adapted to sample a 3-bit signal for RGB from the video signal DIG in synchronization with three pulse signals output simultaneously from the scanning circuit 11. The transfer circuit 15 is a circuit that collectively transfers the video signal DIG for one horizontal scanning period within the horizontal blanking interval. The decoder 16 is a circuit that outputs eight decoded signals by performing decoding processing on each of the RGB 3-bit signals sampled by the latch 14. The decoded signals become active for different periods of time.

【0160】

Eight analog switches 17 ... for each RGB are individually connected to eight gradation power lines. Each of these analog switches 17 ... outputs the gradation voltage VGS given to the gradation power supply line by conducting one each for RGB based on the decoding signal from the decoder 16. It has become.

【0161】

A different gradation voltage VGS is given to the above-mentioned gradation power supply line by the above-mentioned power supply circuit 7.

【0162】

The above-mentioned drive unit 22 is configured by the above-mentioned latch 14, transfer circuit 15, decoder 16, analog switch 17 ... Assigned for each RGB.

【0163】

In the source driver configured as described above, the video signal DIG is sampled by the latch 14 ... in synchronization with the pulse signal from the scanning circuit 11. The sampled signals are collectively transferred to the decoder 16 within the horizontal blanking interval in synchronization with the transfer signal TRP by the transfer circuit 15 ... In the decoder 16, eight decoded signals are obtained by decoding the 3-bit signal that has passed through the latch 14 ....

【0164】

Then, one of the eight gradation voltage VGSs is selected by the analog switch 17 ... Based on the above-mentioned decoded signal. Here, by transferring the signal by the transfer circuit 15 ..., the period for outputting the gradation voltage VGS to the data signal line SL is secured for approximately one horizontal scanning period. The selected gradation voltage VGS for each RGB is output to the data signal lines SL (R), SL (G), and SL (B) via the analog switches 17 ..., respectively.

【0165】

In the source driver as described above, the video signal DIG and the clock signal CKS are selectively supplied by using any of the distribution circuits of the first to fifth data signal output circuits described above, whereby the video signal DIG and the clock signal CKS are supplied. The power consumption related to the clock signal CKS can be significantly reduced. As a result, even in an image display device provided with a multiplexer type digital source driver, power consumption can be easily reduced.

【0166】

[Third Image Display Device] The third image display device has the same configuration as the first or second image display device, but the configuration of the pixel 4 is different as shown in FIG. 25. That is, each pixel 4 is composed of three sub-pixels 4a to 4c having different areas. Separate data signal lines SL ... Are connected to the sub-pixels 4a to 4c via the pixel transistor SW .... Further, the sub-pixels 4a to 4c are driven by binary signals (gradation display data), and gradation display is performed based on their respective area ratios.

【0167】

In this display method called the area gradation display method, a binary signal is used for driving, so not only the influence of the variation in the characteristics of the pixel transistor SW ... but also the influence of noise is applied to the gradation display data. And it becomes difficult. Therefore, good display can be performed, and in particular, good display can be expected even with the source driver 33 configured by the above-mentioned thin film transistor.

【0168】

As shown in FIG. 26, the source driver 33 in the third image display device has a scanning circuit 11, a latch 14, a transfer circuit 15, and an exclusive OR circuit (FIG. 6) in order to realize the above area gradation display method. It has an XOR circuit) 18 and a buffer 19. The latch 14, the transfer circuit 15, the exclusive OR circuit 18, and the buffer 19 are provided with three each for RGB, that is, the same number as the number of bits (9) of the video signal DIG. The exclusive OR circuit 18 is a circuit that takes the exclusive OR of the inverted signal FRM that is inverted according to the period of AC drive and the signal sampled by the latch 14.

【0169】

In the source driver 33 configured as described above, similarly to the above-mentioned multiplexer type source driver, the 9-bit video signal DIG is latched 14 by 1 bit in synchronization with the pulse signal from the scanning circuit 11. Is sampled at. As for the signal from the latch 14 ..., the video signal for one horizontal scanning period is transferred by the transfer circuit 15 ... During the horizontal blanking interval.

【0170】

Then, the exclusive OR of the transferred signal and the above-mentioned inverted signal FRM is taken by the exclusive OR circuit 18 ... The output signal from the exclusive OR circuit 18 ... is buffer-amplified in buffer 19 for conversion to the voltage required for display, and then R (red) data signal line SL (R).₁) ~ SL (R)₃), G (green) data signal line SL (G)₁) ~ SL (G₃), B (blue) data signal line SL (B)₁) ~ SL (B)₃) Is output respectively.

【0171】

In the above source driver 33, the video signal DIG and the clock signal CKS are selectively supplied by using the respective distribution circuits in any of the first to fifth data signal output circuits described above, thereby supplying the video signal and the clock signal CKS. The power consumption related to the clock signal can be significantly reduced. As a result, it is possible to easily reduce the power consumption of the third image display device adapted to the area gradation display method.

【0172】

In the present embodiment, an example in which the data signal output circuit of the present invention is applied to a liquid crystal display device has been described. However, the data signal output circuit of the present invention is not limited to this, and can be applied to other image display devices for achieving the same object, or circuits and devices in other fields.

【0173】

[Effect of the invention]

As described above, the data signal output circuit according to claim 1 of the present invention is a data signal output circuit divided into a plurality of blocks, which is divided by the blocks and sequentially outputs scan signals in synchronization with the clock signal. The shift register to be used and the digital signal divided in the same manner as the shift register and input are sampled in synchronization with the scanning signal, and the data signal corresponding to the sampled digital signal is output to a plurality of output lines. A selection output unit and a first supply circuit provided in each of the above blocks and supplying a digital signal to the divided selection output unit at least during a period in which the divided selection output unit in each block should operate. It is a configuration equipped with.

【0174】

As a result, since the first supply circuit is provided in each block, the digital signal is supplied to only some blocks, but not all the blocks at all times. Therefore, the load on the signal line (digital signal line) for supplying the digital signal can be effectively reduced. Therefore, the effect is that the power consumption of the data signal output circuit can be significantly reduced.

【0175】

The data signal output circuit according to claim 2 of the present invention is the data signal output circuit according to claim 1, and the supply of the digital signal by the first supply circuit is a block selection signal input from the outside. Therefore, by appropriately setting the optimum block selection signal for each block, it is possible to minimize the number of blocks to which the digital signal is simultaneously supplied. Therefore, the load on the digital signal line can be further reduced, and the power consumption of the data signal output circuit can be further reduced.

【0176】

The data signal output circuit according to claim 3 of the present invention is the data signal output circuit according to claim 1, wherein the first supply circuit is a pulse output from a predetermined output stage in the shift register. It is configured to have a selection circuit that generates a block selection signal for controlling the supply of a digital signal based on the signal.

【0177】

As a result, if the block selection signal is set using the optimum pulse signal for each block, it is possible to minimize the number of blocks to which the digital signal is simultaneously supplied. Therefore, since it is not necessary to input the block selection signal from the outside, a signal line for inputting the block selection signal becomes unnecessary. Therefore, it is possible to further reduce the power consumption, and in addition, it is possible to simplify the configuration of the system in which the data signal output circuit is incorporated.

【0178】

The data signal output circuit according to claim 4 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least a divided shift register in each block is provided. A second supply circuit that supplies a clock signal to the divided shift register is further provided during the period in which the operation should be performed, and the supply of the digital signal and the clock signal by each of the first and second supply circuits is input from the outside. The configuration is controlled by a common block selection signal.

【0179】

As a result, the digital signal and the clock signal are supplied to only some blocks, but not all the blocks at all times. Therefore, the load on the signal line for supplying the digital signal and the clock signal can be effectively reduced. Further, in the first and second supply circuits, the signal supply is commonly controlled based on the block selection signal from the outside. Therefore, by appropriately setting the block selection signal for each block, it is possible to minimize the number of blocks to which the digital signal and the clock signal are simultaneously supplied.

【0180】

Therefore, as compared with the data signal output circuit of claim 2, the power consumption of the data signal output circuit can be further reduced.

【0181】

The data signal output circuit according to claim 5 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least a divided shift register in each block is provided. A second supply circuit that supplies a clock signal to the divided shift register is further provided during the period in which the operation should be performed, and the supply of the digital signal and the clock signal by each of the first and second supply circuits is input from the outside. The configuration is controlled independently by different block selection signals.

【0182】

As a result, similarly to the data signal output circuit according to claim 4, the load on the signal line for supplying the digital signal and the clock signal can be effectively reduced. Further, since the first and second supply circuits are independently controlled to supply signals based on different block selection signals, it is possible to optimally control the supply of digital signals and the supply of clock signals. become.

【0183】

Therefore, similar to the data signal output circuit of claim 4, the power consumption of the data signal output circuit can be reduced, and in addition, the power consumption can be reduced by optimizing the signal supply. Play.

【0184】

The data signal output circuit according to claim 6 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least a divided shift register in each block is provided. A second supply circuit that supplies a clock signal to the divided shift register during a period of operation is further provided, and the first and second supply circuits are pulse signals output from a predetermined output stage in the shift register. Based on the above, the configuration is such that a selection circuit for generating a block selection signal for controlling the supply of a digital signal and a clock signal is shared.

【0185】

As a result, if the block selection signal is set using the optimum pulse signal for each block, it is possible to minimize the number of blocks to which the digital signal and the clock signal are simultaneously supplied. Further, since it is not necessary to input the block selection signal from the outside, a signal line for inputting the block selection signal becomes unnecessary. Further, by sharing the selection circuit between the first and second supply circuits, the circuit scale of the data signal output circuit can be reduced. Therefore, similar to the data signal output circuit according to claim 4, the power consumption can be reduced, and in addition, the configuration of the system in which the data signal output circuit is incorporated can be simplified, and the data signal output circuit can be used. It has the effect of reducing power consumption as it becomes smaller.

【0186】

The data signal output circuit according to claim 7 of the present invention is the data signal output circuit according to claim 1, and is provided in each of the blocks, and at least a divided shift register in each block is provided. A second supply circuit that supplies a clock signal to the divided shift register during a period of operation is further provided, and the first supply circuit is based on a pulse signal output from a predetermined output stage in the shift register. It has a first selection circuit that generates a first block selection signal for controlling the supply of digital signals, and the second supply circuit is based on a pulse signal output from a predetermined output stage in the shift register. The configuration has a second selection circuit that generates a second block selection signal for controlling the supply of the clock signal independently of the first selection circuit.

【0187】

As a result, if the first and second block selection signals are set using the optimum pulse signal for each block, it is possible to minimize the number of blocks to which the digital signal and the clock signal are simultaneously supplied. Further, since it is not necessary to input the block selection signal from the outside, a signal line for inputting the block selection signal becomes unnecessary. Further, since the first and second selection circuits independently generate different first and second block selection signals, it is possible to optimally control the supply of the digital signal and the supply of the clock signal, respectively.

【0188】

Therefore, similar to the data signal output circuit according to claim 4, the power consumption can be reduced, and in addition, the configuration of the system in which the data signal output circuit is incorporated can be simplified and the signal supply can be optimized. This has the effect of reducing power consumption.

【0189】

The image display device according to claim 8 of the present invention receives a plurality of pixels arranged in a matrix and a digital video signal as the digital signal, and displays a data signal corresponding to the video signal in each pixel. The configuration includes the data signal output circuit according to any one of claims 1 to 7 supplied as a data signal for display, and a write control circuit for controlling writing of the data signal for display to each pixel.

【0190】

As a result, at least, as described above, the digital video signal is supplied to only some blocks, but is not always supplied to all blocks. Therefore, the load on the signal line for supplying the video signal can be effectively reduced. Further, when the data signal output circuit is the data signal output circuit according to any one of claims 4 to 7, the load on the signal line for supplying the clock signal can be effectively reduced. Therefore, the power consumption of the data signal output circuit can be significantly reduced, and the power consumption of the image display device can be reduced. In particular, as the video signal has multiple gradations, the number of signal lines for supplying the video signal increases, so that the effect becomes remarkable.

【0191】

The image display device according to claim 9 of the present invention is the image display device according to claim 8, and at least the data signal output circuit and the transistors constituting the pixels are formed on the same substrate. Since it is a thin film transistor, the power consumption tends to increase due to the thin film transistor. However, as described above, the power consumption of the data signal output circuit can be reduced by effectively reducing the load on the signal line. Therefore, in the image display device, it is possible to utilize various characteristics of the thin film transistor without causing an increase in power consumption.

【0192】

The image display device according to claim 10 of the present invention is the image display device according to claim 9, and the transistor is a polycrystalline silicon thin film transistor formed at a temperature of 600 ° C. or lower. An inexpensive glass substrate can be used as the substrate. Therefore, in the image display device, various characteristics of the thin film transistor can be utilized without increasing the power consumption, and in addition, the image display device can be provided at low cost.

【0193】

The image display device according to claim 11 of the present invention is the image display device according to any one of claims 8 to 10, and the selective output unit in the data signal output circuit has a plurality of floors from the outside. The voltage adjustment is input, and by selecting one from a plurality of gradation voltages according to the video signal of a plurality of bits, the selected gradation voltage is supplied to each pixel as a display data signal.

【0194】

As a result, the ratio of the power consumption associated with the supply of the video signal, clock signal, etc. to the power consumption of the data signal output circuit increases, but as described above, the load on the signal line is effectively reduced. The power consumption of the data signal output circuit can be reduced. Therefore, in addition to the effects of the image display devices of claims 8 to 10, it is possible to provide a low power consumption image display device in which a so-called multiplexer type drive circuit is applied to the data signal output circuit of the present invention. Play.

【0195】

The image display device according to claim 12 of the present invention is the image display device according to any one of claims 8 to 10, wherein the pixels correspond to a plurality of bits of an input video signal. It is divided into sub-pixels, and the data signal output circuit is configured to supply a binary display data signal to each sub-pixel according to each bit of the video signal.

【0196】

As a result, the display is performed by the so-called area gradation display method, and the power consumption associated with the supply of the video signal, clock signal, etc. occupies a large proportion of the power consumption of the data signal output circuit. Since the line load is effectively reduced, the power consumption of the data signal output circuit can be reduced. Further, since the display data signal has two values, the influence of variations in the characteristics of the elements (transistors) constituting the data signal output circuit is less likely to appear in the display data signal. Therefore, in addition to the effects of the image display devices of claims 8 to 10, it is possible to provide an image display device that performs better display.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the structure of the 1st data signal output circuit which concerns on one Embodiment of this invention.

[Figure 2]

It is a circuit diagram which shows the structure of the shift register part in the 1st data signal output circuit.

[Fig. 3]

It is a block diagram which shows the more specific structure of the 1st data signal output circuit.

[Fig. 4]

It is a circuit diagram which shows the structure of the distribution circuit in the 1st data signal output circuit of FIG.

[Fig. 5]

It is a time chart which shows the operation of the 1st data signal output circuit of FIG.

[Fig. 6]

It is a block diagram which shows the structure of the 2nd data signal output circuit which concerns on one Embodiment of this invention.

[Fig. 7]

It is a circuit diagram which shows the structure of the distribution circuit in the 2nd data signal output circuit.

[Fig. 8]

It is a block diagram which shows the structure of the 3rd data signal output circuit which concerns on one Embodiment of this invention.

[Fig. 9]

It is a block diagram which shows the more specific structure of the 3rd data signal output circuit.

[Fig. 10]

It is a circuit diagram which shows the structure of the distribution circuit in the 3rd data signal output circuit of FIG.

[Fig. 11]

It is a time chart which shows the operation of the 3rd data signal output circuit of FIG.

[Fig. 12]

It is a block diagram which shows other more specific configurations of the 3rd data signal output circuit.

[Fig. 13]

It is a circuit diagram which shows the structure of the distribution circuit in the 3rd data signal output circuit of FIG.

[Fig. 14]

It is a time chart which shows the operation of the 3rd data signal output circuit of FIG.

[Fig. 15]

It is a block diagram which shows the structure of the 4th data signal output circuit which concerns on one Embodiment of this invention.

[Fig. 16]

It is a circuit diagram which shows the structure of the distribution circuit in the 4th data signal output circuit.

[Fig. 17]

It is a block diagram which shows the structure of the 5th data signal output circuit which concerns on one Embodiment of this invention.

[Fig. 18]

It is a circuit diagram which shows the structure of the distribution circuit in the 5th data signal output circuit.

[Fig. 19]

It is a block diagram which shows the structure common to the 1st image display device and the conventional image display device which concerns on other embodiment of this invention.

[Fig. 20]

It is a circuit diagram which shows the composition of the pixel in the 1st image display device.

[Fig. 21]

It is a block diagram which shows the structure common to the 2nd image display device and the conventional image display device which concerns on other embodiment of this invention.

[Fig. 22]

It is sectional drawing which shows the structure of the thin film transistor used for the 2nd image display apparatus.

[Fig. 23]

It is sectional drawing which shows the manufacturing process of the thin film transistor of FIG.

[Fig. 24]

It is a block diagram which shows the structure of the source driver (data signal output circuit) commonly used for the 1st and 2nd image display apparatus and the conventional image display apparatus.

[Fig. 25]

It is a block diagram which shows the structure of the 3rd image display device which concerns on other embodiment of this invention.

[Fig. 26]

It is a block diagram which shows the structure of the source driver (data signal output circuit) used for the 3rd image display device.

[Fig. 27]

It is a block diagram which shows the structure of the analog type source driver of the conventional point sequential drive system.

[Explanation of symbols]

2 Scanning signal line drive circuit (write control circuit) 4 pixels 4a ~ 4c Sub-pixel 5 Glass substrate (board) 21 Shift register section (shift register) 22 Drive unit (selective output unit) 23/24 Distribution circuit (1st supply circuit) 24a / 24b NOR gate (selection circuit, first selection circuit) 24c Inverter (selection circuit) 25/26 distribution circuit (second supply circuit) 26a / 26b NOR gate (2nd selection circuit) 26c NAND gate (second choice circuit) 28 Distribution circuit (1st and 2nd supply circuits) 33 Data signal line drive circuit (data signal output circuit) BLK₁~ BLK_n block BKD₁~ BKD_n Block selection signal (1st block selection signal) BKC₁~ BKC_n Block selection signal (second block selection signal) CLK clock signal DIG digital video signal R reset signal S set signal SRP pulse signal VGS gradation voltage