Reception equipment

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a receiver device that can be used for receiving a digital audio broadcast signal, and more particularly to a receiver device provided with a demodulator that demodulates an orthogonal frequency division multiplexing (hereinafter, also referred to as OFDM) modulated signal. ..

【0002】

[Conventional technology]

In a receiver using a conventional demodulator of this type, as shown in Fig. 2, the OFDM-modulated reception signal input from the input terminal is supplied to the input terminal, and the reception signal is frequency-converted by the mixer 1 and A. A / D conversion is performed by the / D converter 2. The A / D converted received signal is converted into parallel data by the serial / parallel converter 3, and the output parallel data is supplied to the fast Fourier transform circuit (hereinafter referred to as FFT circuit) 4. In the FFT circuit 4, the input data is Fourier transformed, and the input time domain signal is converted into a frequency domain signal and output. The output from the FFT circuit 4 is supplied to the delay detection circuit 6 and the frequency offset detection circuit 17, and the delay detection circuit 6 delay-detects the input signal and sends out the demodulated data from the output terminal.

【0003】

The frequency offset detection circuit 17 detects the frequency offset amount based on the reference symbol for frequency offset detection in the input signal, and controls the oscillation frequency of the voltage controlled oscillator 9 acting as a local oscillator based on the detected frequency offset amount. Then, the frequency deviation is corrected, and the output from the voltage-controlled oscillator 9 in which the frequency deviation is corrected is supplied to the mixer 1 for frequency conversion.

[Problems to be Solved by the Invention]

【0004】

However, the above-mentioned conventional receiving device has a problem that a received signal delayed for a certain period of time may not be normally received due to a large frequency offset detection error in a specific multipath environment. It was.

【0005】

An object of the present invention is to provide a receiving device in which the frequency offset detection performance is prevented from being deteriorated depending on the receiving environment.

【0006】

[Means for solving problems]

The receiving device according to the present invention is a receiving device provided with a demodulator that A / D-converts the received signal, discrete-Four-converts the A / D-converted received signal, and delay-detects the discrete Fourier-converted output data. The first frequency offset detecting means for detecting the frequency offset value at the demodulator input based on the reference symbol for frequency offset detection in the Fourier transformed data, and the frequency at the demodulator input from the phase difference of the delayed detection output data. The second frequency offset detecting means for detecting the offset value and the first frequency from the start of reception until the detection frequency offset value by the first frequency offset detecting means falls within the frequency offset detection range by the second frequency offset detecting means. Provided with a selection means for selecting the detection frequency offset value by the offset detection means and then selecting the detection frequency offset value by the second frequency offset detection means, and performing automatic frequency control based on the selected detection frequency offset value. It is characterized by.

【0007】

According to the receiving device according to the present invention, the frequency offset value at the input of the demodulator is detected by the first frequency offset detecting means based on the reference symbol for frequency offset detection in the discrete Fourier transform data, and the delayed detection output. From the phase difference of the data, the frequency offset value at the input of the demodulator is detected by the second frequency offset detecting means. The selection means selects the detection frequency offset value by the first frequency offset detection means from the start of reception until the frequency offset value detected by the first frequency offset detection means falls within the frequency offset detection range by the second frequency offset detection means. Then, the detection frequency offset value by the second frequency offset detection means is selected, and automatic frequency control is performed based on the detection frequency offset value selected by the selection means.

【0008】

However, since the detection of the detection frequency offset value by the second frequency offset detection means is detected from the phase difference of the output data of the delay detector, the detection range of the detection frequency offset value is narrow, but it becomes undetectable depending on the reception environment. There is no such thing. On the other hand, since the detection of the detection frequency offset value by the first frequency offset detection means is based on the reference symbol, it is affected by the reception environment. Therefore, depending on the selection means, the detection frequency offset value by the first frequency offset detection means from the start of reception until the detection frequency offset value by the first frequency offset detection means falls within the frequency offset detection range by the second frequency offset detection means. The automatic frequency control is performed by the second frequency offset detecting means, and then the automatic frequency control is performed by the detection frequency offset value by the second frequency offset detecting means. As a result, good reception is possible regardless of the reception environment.

【0009】

Instead of the selection means, it is provided with a synthesis means for synthesizing the frequency offset value detected by the first frequency offset detection means and the frequency offset detection value by the second frequency offset detection means at a predetermined ratio, and is synthesized by the synthesis means. The same applies even if automatic frequency control is performed based on the frequency offset value. In this case, the synthesis ratio in the synthesis means may be changed based on the error correction rate obtained from the error correction means.

【0010】

BEST MODE FOR CARRYING OUT THE INVENTION

The receiving device according to the present invention will be described by embodiment. FIG. 1 is a block diagram showing a configuration of a main part of a receiving device according to an embodiment of the present invention.

【0011】

In the receiving device according to the embodiment of the present invention, the received signal is frequency-converted by the mixer 1 in cooperation with the voltage controlled oscillator 9 acting as a local oscillator and converted into an intermediate frequency signal. The intermediate frequency signal is supplied to the A / D converter 2 and converted into a digital signal. The intermediate frequency signal converted into a digital signal is supplied to the serial / parallel converter 3 and converted into parallel data, and the output parallel data is supplied to the FFT circuit 4.

【0012】

In the FFT circuit 4, windowing is performed on the input parallel data according to the number of FFT points, Fourier transform is performed in units of the windows, and the input time domain signal is converted into a frequency domain signal. And output. The output from the FFT circuit 4 is supplied to the delay detection circuit 6 for delay detection, and the delayed detection demodulation data is transmitted from the output terminal. The output from the FFT circuit 4 is also sent to the frequency offset detection circuit 7, and the delayed-detected demodulated data is also sent to the frequency offset detection circuit 8.

【0013】

In the frequency offset detection circuit 7 that receives the output from the FFT circuit 4, the frequency offset amount is detected based on the reference symbol for frequency offset detection in the input signal. The frequency offset detection circuit 8 that received the demodulated data from the delay detection circuit 6 finds the difference between the phase value obtained by finding the phase of the input demodulated data and the phase without the frequency offset, and finds the frequency. The amount of offset is detected.

【0014】

The signal based on the frequency offset amount detected by the frequency offset detection circuit 7 and the signal based on the frequency offset amount detected by the frequency offset detection circuit 8 are sent to the changeover switch circuit 10. On the other hand, the changeover switch circuit 10 selects a signal based on the frequency offset amount output from the frequency offset detection circuit 7 until the frequency offset value detected by the frequency offset detection circuit 7 falls within the frequency offset detectable range of the frequency offset detection circuit 8. Then, when the frequency offset value detected by the frequency offset detection circuit 7 falls within the frequency offset detectable range of the frequency offset detection circuit 8, a signal based on the frequency offset amount output from the frequency offset detection circuit 8 is selected by the changeover switch circuit 10. The changeover signal is sent from the frequency offset detection circuit 7 to the changeover switch circuit 10.

【0015】

A signal based on the detection frequency amount selected in the changeover switch circuit 10 is supplied to the voltage control oscillator 9 acting as a local oscillator, and the transmission frequency of the voltage control oscillator 9 is set to the detection frequency offset amount transmitted from the changeover switch circuit 10. The frequency shift is corrected by controlling based on. In this case, when the frequency control voltage of the voltage controlled oscillator 9 is an analog voltage, a signal based on the detected frequency offset amount is converted into an analog voltage by a converter (not shown) and supplied to the voltage controlled oscillator 9. As a result, the oscillation output from the voltage controlled oscillator 9 whose frequency deviation has been corrected is supplied to the mixer 1 and the input received signal is frequency-converted to perform automatic frequency control.

【0016】

Regarding the frequency offset amount detection in the frequency offset detection circuit 7 and the frequency offset detection circuit 8 in the receiving device according to the embodiment of the present invention configured as described above, in the case of the transmission mode 1 of the digital audio broadcast signal of the European standard. Will be described as an example.

【0017】

First, the frequency offset amount detection in the frequency offset detection circuit 7 will be described. In the case of a digital audio broadcast signal, the phase reference symbol (PRS), which is a reference symbol, is included in the transmitted signal. The 1536QSPK symbol used in this PRS consists of 48 blocks of 32QPSK symbols, and each block uses a differentially coded code sequence of the CAZC (Constanto Amplitude Zero Auto Correlation) code sequence, which is a phase shift. ing. The CAZAC code sequence used in all blocks is the same, and the phase to shift is every π / 2.

【0018】

The frequency offset detection circuit 7 of the receiving device detects the amount of frequency offset using this property of PRS. Upon receiving the output of the FFT circuit 4, the FFTed PRS is delayed detected between the QPSK symbols. The delayed detected QPSK symbol becomes a phase-shifted CAZAC code sequence including frequency offset and is divided into 48 blocks. After that, only 16 QPSK symbols are taken out per block to reduce interference between blocks, and the 16 × 48 QPSK symbols are phase-shifted block by block so that all blocks have the same CAZAC code sequence. After synthesizing, it correlates with the CAZAC code sequence prepared in advance.

【0019】

Here, if the position is changed when the 16QPSK symbol is taken out, it has the same effect as offsetting the frequency at the carrier frequency interval, and the autocorrelation of the CAZAC code sequence is almost the same as that of the M sequence when it is deviated by one symbol or more. There is no correlation. Utilizing this property, the frequency offset amount is detected by correlating with the CAZAC code sequence prepared in advance while shifting the position where the 16QPSK symbol is taken out, and obtaining the shift amount that maximizes the correlation coefficient. The resolution in this detection is the carrier frequency interval, which is 1 kHz.

【0020】

Therefore, the following operation is performed in order to obtain the frequency offset amount with a resolution equal to or less than the carrier frequency interval. After finding the shift amount that maximizes the correlation coefficient, find the correlation coefficient at that point and the correlation coefficient at the point where the shift amount is changed by ± 1 symbol. In addition, delayed detection between 2QPSK symbols is also performed to obtain the correlation coefficient at the point with the same shift amount and the point with one symbol changed, and the frequency offset amount is obtained from these five types of correlation coefficients.

【0021】

Next, the frequency offset detection circuit 8 estimates the frequency offset amount from the phase of the QPSK symbol after the delay detection in the delay detection circuit 6. Since the delayed detection is to obtain the phase difference per 1.246 ms (OFDM symbol length) in each QPSK symbol, when the frequency is deviated, the delayed detection output from the delayed detection circuit 6 has the phase according to the frequency deviated. The offset is included, and the frequency offset amount is detected from the phase offset amount.

【0022】

Each carrier of OFDM is π / 4-QPSK modulated. In this case, the phase of the data output from the delay detection circuit 6 has four values of ± 45 degrees and ± 135 degrees in the absence of frequency offset. In the state where there is a frequency offset, a phase shift of data occurs according to the amount of frequency offset. However, the deviation can be detected normally within the range of ± 45 degrees, and if the deviation is more than that, it will be detected as different data. Therefore, the frequency offset detection circuit 8 can detect the frequency offset amount within a narrow range.

【0023】

In the frequency offset detection circuit 7, the frequency offset amount is detected based on the FFT reference symbol for frequency offset detection, but a large error occurs in the detected value depending on the multipath state. On the other hand, the frequency offset detection in the frequency offset detection circuit 8 is limited to the frequency offset amount in a narrow range, but the detection such that the data cannot be reproduced in the multipath state within the detectable range. There is no error.

【0024】

Here, a signal based on the frequency offset amount output from the frequency offset detection circuit 7 at the start of reception is selected in the changeover switch circuit 10 by the selection signal from the frequency offset detection circuit 7, and the frequency output from the frequency offset detection circuit 7. The oscillation frequency of the voltage controlled oscillator 9 is controlled by the signal based on the offset amount.

【0025】

During this period, when the amount of frequency offset output from the frequency offset detection circuit 7 falls within the frequency offset detectable range by the frequency offset detection circuit 8, the changeover switch circuit 10 is switched by the selection signal from the frequency offset detection circuit 7 and the frequency is changed. A signal based on the frequency offset amount output from the offset detection circuit 8 is selected, and the oscillation frequency of the voltage controlled oscillator 9 is controlled by the signal based on the frequency offset amount output from the frequency offset detection circuit 8.

【0026】

As a result, once the oscillation frequency of the voltage controlled oscillator 9 is controlled by the signal based on the frequency offset amount output from the frequency offset detection circuit 8, the frequency is pulled into the reception frequency, and then the frequency offset is performed by multi-pass or the like. The amount will not be erroneously detected, the frequency offset detection performance will not deteriorate depending on the reception environment, and stable reception will be possible.

【0027】

Further, instead of the changeover switch circuit 10, a synthesis circuit for synthesizing the signal based on the frequency offset amount output from the frequency offset detection circuit 7 and the signal based on the frequency offset amount output from the frequency offset detection circuit 8 is provided. The oscillation frequency of the voltage controlled oscillator 9 may be controlled by increasing the synthesis ratio of the signal based on the frequency offset amount output from the frequency offset detection circuit 7 only for a predetermined period from the start of reception.

【0028】

In this case, the change in the synthesis ratio may be the output frequency offset amount from the frequency offset detection circuit 7 or 8, or the correction rate of the data obtained from the error correction circuit.

【0029】

[Effect of the invention]

As described above, according to the receiving device according to the present invention, it is possible to prevent the frequency offset detection performance from being deteriorated depending on the receiving environment, and it is possible to obtain an effect that normal reception can be performed.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the structure of the main part of the receiving apparatus which concerns on one Embodiment of this invention.

[Figure 2]

It is a block diagram which shows the structure of the main part of the conventional receiving apparatus.

[Explanation of symbols]

1 Mixer 2 A / D converter 3 serial / parallel converter 4 FFT circuit 5 and 15 data shift circuits 6 Delay detection circuit 7 and 8 frequency offset detection circuit 9 Voltage controlled oscillator 10 Changeover switch circuit