Selection line driver for display matrix having toggling back plane

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates generally to a drive circuit for a display device, such as a liquid crystal display (LCD), and particularly to a method of applying a line selection line signal to the line selection line of the display device.

【0002】

[Conventional technology]

A display device, such as an LCD display, consists of a matrix, or, for example, an array arranged horizontally in rows and vertically in columns. The displayed video information is applied as a luminance (grayscale) signal to the data lines individually associated with each column of pixel cells. A given data line drive circuit generates a drive signal in the corresponding data line. US Pat. No. 5,170,155, entitled "System for Applying Brightness Signals To A Display Device And Comparator Therefore," by outside Plus, is an LCD data line or An example of a column driver is shown. The rows of the pixel cell are continuously scanned or selected by a row selection signal generated by the row line conductor associated with the row of the pixel cell.

【0003】

In a working matrix display, each pixel cell includes a switch device that applies a luminance signal to the pixel cell. Generally, the switch device is a thin film transistor (TFT) that receives a luminance signal from the data line driver through the data line. This device is hereinafter referred to as a pixel TFT. The pixel TFT has a gate electrode connected to a row selection line conductor and responding to a row selection signal associated with the row of the pixel cell.

【0004】

A liquid crystal display is made of a liquid crystal material sandwiched between two electrodes. At least one, and generally both electrodes, allow light to pass through, and the surface of the electrodes adjacent to the liquid crystal material supports a pattern of transparent conductive poles arranged in a pattern that forms the individual pixel cells. Generally, one electrode of a pixel cell is at a voltage common to all pixel cells in the array. The electrodes are referred to as the backplane or common plane of the array. The other electrodes of the pixel cell far from the backplane are connected to the main current conductive electrode of the pixel TFT switch, which is referred to as the pixel electrode. The TFT generates a voltage level at the pixel electrode that is substantially the same as the voltage level of the luminance signal. The difference in voltage level between the pixel electrode and the backplane is hereinafter referred to as the pixel cell voltage.

【0005】

In order to prevent the polarization of the liquid crystal material in the pixel cell, the polarity of the pixel cell voltage must be periodically alternated so that the average value of the pixel cell voltage or the DC component is zero. One known technique for preventing the polarization of the liquid crystal material in the pixel cell is called a toggling common plane voltage technique or a toggling backplane voltage technique. In the toggle backplane voltage technique, the backplane voltage is one of the first or second voltage levels when a given row is selected. However, if the same row is selected, the backplane voltage will be one of the first or second voltage levels when updating the image information of successive image frames. The voltage level of the luminance signal that generates the pixel cell brightness in the middle range of the gray scale is referred to here as the voltage level in the middle range. In Togling backplane voltage technology, the voltage level in the middle range is the same regardless of the level of the backplane voltage.

【0006】

One of the first or second voltage levels is more positive or greater than the maximum level of the luminance signal generated by the data line driver. The other one of the first or second voltage levels is more negative or less than the minimum level of the luminance signal. The first and second levels of backplane voltage are symmetrical with respect to the level in the midrange of the luminance signal. Therefore, when the backplane voltage is at the first level, the pixel cell voltage of the pixel cell in the selected row has the opposite polarity to the voltage generated when the backplane voltage is at the second level. The result is that during a given image frame, the polarity of the pixel cell voltage is opposite to the polarity between subsequent image frames. This is called frame polarity reversal. In this way, polarization of the liquid crystal material is avoided.

【0007】

Unfortunately, the toggle backplane voltage at the frame frequency can cause flicker at frequencies that are perceptible to the eye. To reduce eye sensitivity, the backplane voltage can be toggled at higher frequencies of row selection changes. The voltage applied to the backplane changes from the first level to the second level and vice versa when the immediately following line is selected. This mode of operation is called line polarity reversal because the polarity of the pixel voltage changes from line to line. As in the case of frame polarity reversal, the polarity of the pixel cell voltage is reversed in order to avoid polarization of the liquid crystal material at each frame.

【0008】

[Problems to be Solved by the Invention]

A shift register that implements the features according to the invention, called a selection scanner, produces a row selection signal at the corresponding row selection line conductor that is suitable for the mode of row polarity reversal operation. The same voltage level occurs at the row selection conductor of the selected row, regardless of the level of backplane voltage at which the row is selected. This feature is due to the result of considering spatial uniformity and flicker. The pixel cell voltage depends on the conductivity of the pixel TFT.

【0009】

The same conduction in the pixel TFT when a row is selected when the backplane voltage is both the first and second levels to reduce flicker and reduce the difference in pixel brightness between the alternately selected rows. It is desirable to maintain sex. Maintaining the same conductivity is especially important when the luminance signal is at voltage levels in the middle range. This is because the eyes are very sensitive to changes in luminance when the luminance signal is at a voltage level in the middle range. The conductivity of a pixel TFT is determined by the voltage at the row line conductor of the selected row and the voltage level of the luminance signal. Since the voltage level in the middle range and the voltage at the row line conductor are the same regardless of the backplane voltage level, the pixel TFT advantageously retains the same conductivity.

【0010】

The selection scanner also generates a row selection deselection signal at the corresponding row selection line conductor, suitable for the mode of operation of row polarity reversal. This is achieved by generating a second toggle voltage in the row select line conductor of the deselected row that changes by the same amount as the toggle backplane voltage and at the same time during the row deselection interval. To. This feature is due to the consideration of temporary uniformity and flicker. Toggling the voltage of the row selection signal in harmony with the toggle of the backplane voltage keeps a constant difference between the backplane voltage and the voltage of the row selection line conductor during the row selection deselection interval. Therefore, the displacement current or capacitive current in the current path, including the pixel cell capacitance, is reduced or eliminated. Any displacement current can cause changes in the pixel cell voltage that can produce undesired results such as flicker or image print.

【0011】

Selection of LDC display matrix It is desirable that the line scanner is made with the toggle backplane on the same substrate and at the same time the liquid crystal display cell is made in the display matrix.

【0012】

[Means for solving problems]

A display device for embodying one aspect of the invention and applying a luminance signal to pixels arranged in multiple rows and columns of an array is given when a given row is selected. The pixel electrodes of the row pixels include multiple column drivers for generating luminance signals. The first signal source to toggle is prepared. The first signal alternates with a common electrode of pixels having first and second levels relative to a given level of the luminance signal. Multiple columns make a row selection scanner. A given column associated with a given row is for generating a row line selection signal on the corresponding row line for selecting a given row during a given row selection interval. Includes the first transistor. The second transistor connected to the row line generates a voltage in the capacitance associated with the row line according to the first signal. The capacitance connects the first signal and the row line in a capacitive manner to generate a toggle line line deselection signal in the row line level-shifted with respect to the first signal according to the capacitance voltage during the row deselection interval. ..

【0013】

BEST MODE FOR CARRYING OUT THE INVENTION

In FIG. 1, the conventional data line driver 200 for driving the data line 17 of the liquid crystal array 16 can be similar in many respects to, for example, the line driver described in the patent by outside Plus. Each data line driver 200 connects to the corresponding data line 17 through transistor MN6. The array 16 consists of a large number of pixel cells, such as a liquid crystal cell 16a, which is arranged horizontally in 560 rows and vertically in 960 columns. The liquid crystal array 16 has a data line 17 of 960 columns, one for each of the vertical columns of the liquid crystal cell 16a, and a row selection line 118 of 560 columns, one for each of the vertical columns of the liquid crystal cell 16a. including.

【0014】

The selection line scanner 60, which implements one aspect of the present invention, generates a line selection signal OUT (n) a to select a given line n of the array 16 on the corresponding selection line 118 (n). The luminance voltage VCOLUMN generated in a given data line 17 is applied to pixel cell 16a above the row during the line selection period of row n.

【0015】

The voltage VBP generated at the electrode 16d of each pixel cell 16a is common to all the pixel cells of the array 16. The electrode 16d in which a common voltage VBP is generated is referred to as an electrode of the backplane BP of the array 16. In a given pixel cell 16a, the second electrode 16e of the pixel cell 16a away from the backplane BP is coupled to the corresponding pixel TFT switch 16c. This electrode is referred to as a pixel electrode. When the corresponding row n is selected, the pixel TFT16c generates a voltage V16e at the pixel electrode 16e, which is about the same as the voltage level of the corresponding luminance voltage VCOLUMN.

【0016】

(A) and (b) of FIG. 2 show the pair of pixel cells 16a of FIG. 1 of the immediately selected rows n-1 and n generated at the backplane electrode 16d and the pixel electrode 16e, respectively. An example of the voltage waveform of each pixel cell is shown. In FIGS. 1, 2 (a) and 2 (b), similar symbols and numbers indicate similar items or functions.

【0017】

The backplane voltage VBP of FIG. 2 (a) or (b) applied to the backplane BP of matrix 16 of FIG. 1 toggles as the row selection changes. During the transition interval, while the backplane voltage VBP is toggling, each of the transistors MN6 in FIG. 1 is turned off. When the row selection signal OUT (n-1) a of FIG. 1 occurs on the row selection line 118 (n-1) of the selected row n-1, the conventional backplane of FIG. 2 (a). The backplane voltage VBP generated by driver 61 is + 6V during line time T (n-1). When the row selection signal OUT (n) a in FIG. 1 occurs on the row selection line 118 (n) of the immediately following selected row n, the backplane voltage VBP in FIG. 2 (b) is the line. During time T (n), it is -2V.

【0018】

The voltage V16e in (a) or (b) of FIG. 2 is approximately equal to the voltage VCOLUMN when the row of pixels 16a is selected. The voltage VCOLUMN generally has a voltage range that is the same for each row, between maximum + 4V and minimum 0V. Using the same voltage range facilitates the design of the dataline driver 200.

【0019】

The + 6V level of the backplane voltage VBP in (a) of FIG. 2 is even more positive than the maximum level of + 4V of the luminance voltage VCOLUMN. The level of -2V of the backplane voltage VBP is even less positive or even more negative than the minimum level of 0V of the luminance voltage VCOLUMN. The pixel cell voltage VPIXEL of the pixel cell 16a in the selected row is equal to the difference between the pixel electrode voltage V16e and the backplane voltage VBP. When the backplane voltage VBP is + 6V, the pixel cell voltage VPIXEL of the pixel cell in the selected row is negative, which is the opposite polarity to the voltage generated when the backplane voltage VBP is -2V. In the example shown, the characteristics of the pixel cell voltage VPIXEL are from the negative polarity in the selected row n-1 during the line time T (n-1) in FIG. 2 (a) to (b) in FIG. ), During the line time T (n), it changes to the positive polarity at the selected line n immediately following. In this way, the polarity of the voltage VPIXEL changes alternately on a line-by-row basis.

【0020】

For a given change in light transmission or brightness, in the selected rows n-1 and n, the direction of change in the brightness voltage VCOLUMN is opposite. If the luminance voltage VCOLUMN is at a voltage level greater than the intermediate range voltage level MRG during the line time T (n-1) in FIG. 2 (a), it is, for example, at the intermediate range voltage level MRG. Generates higher pixel light transmission or brightness. On the other hand, when the luminance voltage VCOLUMN is a voltage level higher than the voltage level MRG in the intermediate range during the line time T (n) in (b) of FIG. 2, it is the voltage level MRG in the intermediate range. Generates light transmission or brightness of pixels lower than the time. The voltage level MRG indicates a luminance level in the middle of the luminance grayscale. So, for example, in order to obtain the same light transmission in the pixels of rows n-1 and n, the difference between the voltage VCOLUMN and the voltage level MRG must be the same magnitude and opposite polarities.

【0021】

(A) and (b) of FIG. 2 show the voltage level of the voltage V16e at the pixel electrode 16e, which gives the maximum light transmission or brightness by the broken line and the minimum light transmission or brightness by the dotted line. Since the backplane voltage VBP is toggled on a row-by-row basis, the polarity of the pixel cell voltage VPIXEL also changes on a row-by-row basis.

【0022】

If a given row is selected, the backplane voltage VBP will be one of the voltage levels of + 6V or -2V when updating the image information for a given image frame. On the contrary, if the same row is selected, the backplane voltage VBP will be the other one of the + 6V or -2V voltage levels when updating the image information of the immediate image frame. The result is that during a given image frame, the polarity of the pixel cell voltage VPIXEL is opposite to the polarity that occurs during subsequent image frames. In this way, polarization of the liquid crystal material is avoided as described above. Changing the polarity of the voltage VPIXEL on a line-by-line basis reduces flicker.

【0023】

FIG. 4 shows a exemplary stage N of the selection line scanner 60 of FIG. 1 and the shift register 100 of FIG. 3 that implements the features of the present invention. Each transistor in stage N is an N-MOS TFT. To reduce the pressure that can cause threshold voltage drift, the time each transistor is conductive is shorter than the time it is non-conducting. The shift register 100 of FIG. 3 provides timing for driving the row selection line 118 of the liquid crystal display matrix 16 of FIG. In FIGS. 1, 2 (a) and 2 (b), 3 and 4, similar symbols and numbers indicate similar items or functions.

【0024】

In the shift register 100 of FIG. 3, stages N-1, N, N + 1 and N + 2 are connected to each other in a longitudinal shape. The output signal of a given stage is coupled with the input of the immediately following stage in the circuit. For example, the pulse of the output signal OUT (n-1) of the stage N-1 ahead of the circuit of the register 100 is connected to the input terminal 72 of the stage N of FIG. As an example, only the four stages N-1, N, N + 1 and N + 2 are shown in FIG. However, the total number of stages N of the circuits in register 100 is the same as the number of row selection lines, 560 in this example. The shift register 100 can also be referred to as a "walking one" shift register. This is because the true state or high level is transmitted through register 100 during the video image frame time.

【0025】

(A) to (i) of FIG. 5 show waveforms useful for explaining the circuits of FIGS. 3 and 4. In (a) and (b) of FIGS. 1 and 2, and (a) to (i) of FIGS. 3, 4 and 5, similar symbols and numbers indicate similar items or functions. The clock generator 101 of FIG. 3 generates two-phase clock signals (clock signals C1 and C2) having the waveforms shown in (b) and (c) of FIG. 5, respectively. The pulse of the output signal OUT (n-1) of FIG. 3 (a) is generated at the input terminal 72 of stage N of FIG. 4 during the pulse of the clock signal C2 of FIG. 5 (c). The pulse of the high-level output signal OUT (n-1) of FIG. 5 (a) is connected to the terminal 78a in order to generate the control signal P1 through the transistor 78 of FIG. The control signal P1 is connected to the gate electrode of the first output transistor 76.

【0026】

When the control signal P1 is generated at the gate electrode of transistor 76 in FIG. 4, the drain electrode of transistor 76 is at a negative low level of clock signal C1. The signal P1 generated at the gate of the output transistor 76 adjusts the output transistor 76 for conduction. The conductive transistor 76 creates a current path for temporarily storing a high level signal P1 in a capacitor 70 connected between the gate and the source electrode of the conductive transistor 76. The clock signal C1 is also connected to terminal 78a through the interelectrode parasitic capacitance CP of transistor 76. Therefore, the high level signal P1 is also stored in the capacitive CP. Even after the output signal OUT (n-1) of FIG. 5 (a) reaches the low level and the transistor 78 of FIG. 4 is turned off, the high level is stored in the capacitor 70 and the capacitive CP.

【0027】

The clock signal C1 of FIG. 5 (b) is generated at a high level at the drain electrode of the transistor 76 immediately after the pulse of the clock signal C2 stops or reaches a low level. The clock signal C1 of FIG. 5 (b) is connected to the output terminal 73 through the conductive transistor 76. Therefore, when high levels are reached, the voltage at terminal 78a is bootstrapped through the capacitor 70 and CP, thereby providing extra drive for the transistor 76. Such an operation is called a bootstrap operation. Therefore, the output signal OUT (n) of FIG. 5 (f) is generated at the output terminal 73 of the register N of FIG. 4 without a voltage drop from the high level of the signal C1.

【0028】

The signal P1 is also coupled to the gate electrode of the buffer output transistor 81 that implements the features according to the invention. The current drain of the transistor 81 is connected to the clock signal C1. The transistor 81 is turned on and off at the same time as the transistor 76. Whenever the transistor 81 of stage N is turned on, it generates a pulse of row selection signal OUT (n) a on the selection line 118 (n) of matrix 16 of FIG.

【0029】

According to the feature of the present invention, the signal P1 stored in the capacitor 70 after the transistor 78 is turned off is connected to the gate of the transistor 81. Thus, advantageously, the bootstrap operation is performed on both transistors 76 and 81 when the clock signal C1 is generated. The bootstrap operation causes the row selection signal OUT (n) a to achieve a high level of clock signal C1 without voltage drop. Since the transistor 76 does not need to drive a load having a relatively large capacitance on the selection line 118 (n), the transmission time of the signal OUT (n) is fast and advantageous.

【0030】

The voltage level MGR of the luminance voltage VCOLUMN that produces pixel cell brightness in the middle range does not depend on the voltage level of the backplane voltage VBP at the time the row is selected. Therefore, when row n is selected, the difference between the voltage level of the row selection signal OUT (n) in FIG. 4 and the luminance voltage VCOLUMN of the voltage level MGR in the middle range of (a) and (b) in FIG. , It is the same in both the case where the backplane voltage VBP in FIG. 2 (a) is + 6V and the case where the backplane voltage VBP in FIG. 2 (b) is -2V. Therefore, advantageously, when the luminance voltage VCOLUMN is a voltage level MGR in the middle range, the conductivity of the pixel TFT 16c in FIG. 1 is the same both when the backplane voltage is + 6V and -2V.

【0031】

It is desirable to keep the same conductivity on the TFT switch 16c when a given row is selected, both when the backplane voltage VBP is + 6V and -2V. This is because even a small difference in conductivity can cause a non-zero mean value of the pixel cell voltage VPIXEL that can cause flicker and / or image stillness. Keeping the same conductivity is when the eyes are sensitive to changes in brightness in the middle range of the grayscale, so the luminance voltage VCOLUMN is the voltage level MGR in the middle range of (a) or (b) in Figure 2. Of particular importance.

【0032】

The signal OUT (n) of stage N in FIG. 4 is applied to the input terminals of consecutive stages N + 1 in FIG. Stage N + 1 is located downstream of the signal path of register 100 and is similar to stage N to turn on the corresponding register, except that it uses a complementary clock signal C2 instead of clock signal C1. Operate. Thus, the output signal OUT (n + 1) of FIG. 5 (g) generated between the clock signal C2 of FIG. 5 (c) is from high to low of the clock signal C1 of FIG. 5 (b). Has a low-to-high level shift that immediately follows the level shift to. The low-to-high level conversion of the signal OUT (n + 1) in FIG. 5 (g) occurs at the same time as the low-to-high level conversion of the clock signal C2 in FIG. 5 (c) occurs. In this way, the selection line scanner 60 of FIG. 1 operates as a shift register.

【0033】

When the clock signal C1 in FIG. 5 (b) reaches a low level at which it does not operate, the transistors 76 and 81 in FIG. 4 remain lit until the capacitors 70 and CP are discharged. Transistor 75 is connected between terminal 78a and a constant negative supply voltage V1 of -12V. The transistor 77 is connected between the terminal 73 and the negative supply voltage V1.

【0034】

The signal OUT (n + 1) of stage N + 1 is connected back to the gate electrode of transistors 75 and 77. The signal OUT (n + 1) also implements the features of the present invention and is coupled to the gate electrode of a pull-down transistor 79 having a source and drain electrodes, each connected to a toggle voltage V2 and a selection line 118 (n) of line n. .. Thus, when the pulse of the signal OUT (n + 1) is generated, the transistors 75, 77 and 79 are turned on. When the transistors 75 and 77 are turned on, they discharge the capacitor 70 and the parasitic capacitor CP. This is because the negative supply voltage V1 of -12V is the same as the low level at which the clock signal C1 does not operate. As a result, the transistors 76 and 81 are turned off. Since the signal OUT (n + 1) occurs once per frame, which is substantially less frequent than the clock signal C1 or C2, the pressures of transistors 79, 75 and 77, which can cause threshold voltage changes in the transistors, are advantageous. ,small.

【0035】

The capacitance CSEBP is coupled between the selection line 118 (n) on line n and the backplane BP. Capacitive CSEBP is used to increase the coupling capacitance between the selection line 118 (n) at line n and the backplane BP. According to aspects of the invention, when transistor 79 is turned on, it charges the capacitive CSEBP and generates a row deselection voltage VDSEL across the capacitive CSEBP. The voltage VDSEL is equal to the difference between the toggle voltage V2 and the toggle voltage VBP. Regardless of which voltage level the voltage VBP is, the voltage VDSEL has a constant value of -10V.

【0036】

Following the falling edge of the pulse at signal OUT (n + 1) during all deselection intervals in line n, transistor 79 is non-conducting, creating a high impedance with respect to selection line 118 (n). Thus, the voltage VDSEL of -10V is kept in the capacitance CSEBP. Since the backplane BP is capacitively coupled to the selection line 118 (n) through the capacitance CSEBP, the voltage level of the signal OUT (n) of the selection line 118 (n) during the deselection interval is the backplane voltage VBP. Follow. Tracking of selection line 118 (n) advantageously does not cause the displacement currents that can occur in the current path including the pixel capacitance CPIXEL and capacitance CSP of FIG. This is because the transistor MN6 in FIG. 1 is turned off during the conversion of the toggle voltage VBP, so the data sequence is disconnected from the data scanner. Therefore, the pixel voltage VPIXEL does not change during the deselection interval of row n even if the voltage VBP toggles. (H) and (i) of FIG. 5 show the waveforms of the signals OUT (n) a and OUT (n + 1) a of FIG. 3, respectively.

【0037】

The output terminal 73 of FIG. 4 of the transistor 76 is isolated from the selection line 118 (n). Therefore, the toggle voltage of the selection line 118 (n) does not affect the voltage of the terminal 73. Therefore, the voltage of the terminal 73 connected to the stage N + 1 in FIG. 3 is constant during the deselection interval and is not affected by the toggle signal OUT (n) a. Naturally, the clock signals C1 and C2 of the stage N + 1 can be simple two-level signals without depending on the toggle voltage of the selection line 118 (n) in FIG. In this way, the design of each stage, such as stage N, is advantageously simplified.

【0038】

The reset pulse signal RESET of FIG. 5 (e) is connected to the gate electrode of any pull-down transistor 80 having a source and drain electrodes connected to the toggle voltage V2 and the source electrode of the transistor 81, respectively. The pulse signal RESET in FIG. 5 (e) is a narrow pulse that occurs each time row selection occurs with reference to each row. Transistor 80 can be used to prevent noise interference from affecting the magnitude of the voltage VDSEL during the deselection interval of line n when high impedance occurs at selection line 118 (n) a.

【0039】

During the deselection interval of line n, the clock signal C1 in FIG. 4 may have a tendency to cause charging of the capacitor 70 through the capacitive CP. Therefore, the clock signal C2 is connected to the terminal 78a through the capacitance 71, which is 20% larger than the capacitance CP. Advantageously, the capacitively coupled clock signal C2 prevents the generation of any charge on the capacitor 70 during the deselection interval of line n.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the liquid crystal display apparatus including the row selection driver which carries out the aspect of this invention.

[Figure 2]

It is a figure which shows the waveform for demonstrating the apparatus of FIG.

[Fig. 3]

It is a block diagram which shows the row selection driver of FIG. 1 which contains the shift register which contains a plurality of tandems.

[Fig. 4]

It is a system diagram which shows the shift register stage used for the shift register of FIG. 3 which carries out the aspect of this invention.

[Fig. 5]

It is a figure which shows the relative timing of an output signal, and each clock signal generated by each code of the shift register of FIG. 3 using the stage shown in FIG.

[Explanation of symbols]

16 LCD array 16a LCD cell 16c pixel TFT switch 16d electrode 16e pixel electrode 17 data line 60 selection line scanner 61 Traditional backplane driver 70 capacitors 71 capacity 72 Input terminal 73 Output terminal 75 transistors 76 transistor 77 transistor 78 transistor 78a terminal 79 transistor 80 transistors 81 transistor 100 shift register 200 data line driver 118 line selection line C1 clock signal C2 clock signal CP capacity P1 control signal MN2 transistor