Semiconductor device and manufacture therefor

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a structure for rearranging pads of a semiconductor chip and a method for manufacturing the semiconductor device.

【0002】

[Conventional technology]

The LSI chip is often mounted on a substrate by wire bonding, and the pad of the electronic device to which the wire is connected is formed of aluminum as a main component. The so-called TAB method and flip-chip method are used for mounting other LSI chips, and these are common in that the protruding electrodes are formed on the pads on the LSI chip or the wiring on the substrate.

【0003】

In the above electronic devices, pads are formed for electrical connection with external wiring, but the pad formation position differs depending on the mounting method, so the pad forming position and layout are suitable for the mounting method. It is common to predetermine the position. In other words, even when LSI chips with the same performance and basic structure are connected by wiring, it is necessary to design them separately as devices of different types due to different mounting methods. This causes a wide variety of products, complicates product management, increases costs, and eventually raises product prices.

【0004】

Therefore, if there is a technology that can be covered by the same LSI chip even if the mounting method of the LSI chip is different, product management can be simplified and it is effective in cost reduction. Therefore, the so-called pad rearrangement technique of forming the pad of the LSI chip at a predetermined position and then rearranging the pad position is described in Japanese Patent Application Laid-Open No. 2-121333 and Japanese Patent Application Laid-Open No. 5-218042.

【0005】

Specifically, the pad rearrangement is a technique of forming an lead wire on a protective insulating layer having an opening that exposes the pad, and forming another pad on the lead wire. In these two known examples, a multi-layer structure is adopted for the lead wiring, and the layer structure is a three-layer structure in which titanium (Ti), nickel (Ni), and gold (Au) are laminated in this order, or titanium. , A two-layer structure in which copper (Cu) is laminated in order is described.

【0006】

As other lead wiring, a three-layer structure of titanium, copper, and nickel is described in JP-A-60-136339, and a three-layer structure of titanium, copper, and titanium is described in JP-A-57-122542. A three-layer structure in which titanium, palladium (Pd), and titanium are formed in this order is described in Japanese Patent Application Laid-Open No. 62-183134, and a three-layer structure of aluminum (Al), vanadium (V), and aluminum and aluminum, The three-layer structure of titanium and aluminum is described in Japanese Patent Application Laid-Open No. 1-2902232.

【0007】

[Problems to be Solved by the Invention]

However, when relocating the pad, it is almost inevitable that the pad is placed on the active element region, and it is necessary to protect the active element from the load applied when connecting the pad and the external wiring. is there. In addition, the sheet resistance of the wiring must be lowered because the lead-out of the wiring may be long in consideration of the arrangement interval of the plurality of pads.

【0008】

Moreover, in preparation for connecting the bump to the pad, it is necessary to adopt a pad material having good adhesion to the bump material. Further, as the number of pads increases and the wiring width tends to become narrower as the LSI becomes more integrated, a wiring structure that can withstand electromigration of the wiring is required. For example, the wiring is made of copper, gold, or silver. The including layer needs to have a structure that can prevent the occurrence of migration.

【0009】

In response to such requirements, the wiring structure described above does not sufficiently satisfy those requirements, and a new wiring structure is required. An object of the present invention is to provide a semiconductor device or a method for manufacturing the same, which has low resistance, protects an active element, has good adhesion to bumps, and prevents electromigration.

【0010】

[Means for solving problems]

As illustrated in FIGS. 2, 4 (d) or 6 (d), the above-mentioned problems are the semiconductor element 2 formed on the semiconductor substrate 1 and the conductive material above the region surrounding the semiconductor element 2. A plurality of first pads 4 formed by the above, a first protective insulating film 5 covering the first pad 4, and the first protective insulating film 5 formed on the first protective insulating film 5 to expose the first pad 4. One end is connected to the first pad 4 through the plurality of first openings 6 and the first opening 6, and the other end is arranged in the area surrounded by the first opening 4. Of the lead wiring 7 having a main conductor layer 15 formed of copper and an uppermost layer 16 made of a material made of white metal and having good adhesion to bumps, and the upper surface of the lead wiring 7. This is solved by a semiconductor device characterized by having a second protective insulating film 8 having a second opening 9 that exposes a portion near the other end as a second pad 17.

【0011】

In the above-mentioned semiconductor device, as shown in FIG. 6D, the uppermost layer 16 is characterized in that the uppermost layer 16 is formed on the upper surface and the side surface of the main conductor layer 15. In the above-mentioned semiconductor device, the uppermost layer 16 is characterized in that it is formed of an alloy containing at least one platinum group element such as palladium, platinum, and rhodium.

【0012】

In the above-mentioned semiconductor device, the semiconductor device has a conductive protrusion 10 connected to the uppermost layer 16 of the lead wiring 7 through the second opening 9, and the uppermost layer 16 is a metal having good wettability with the protrusion 10. It is characterized in that it is composed of. The semiconductor device described above is characterized in that a base metal layer 13 having good adhesion to the main conductor layer 15 and the first protective insulating film 5 is formed under the main conductor layer 15. In this case, the base metal layer 13 is characterized in that it is formed of titanium, chromium, molybdenum, tungsten, or an alloy thereof. Further, the first protective insulating film is characterized in that it is formed of any of silicon oxide, silicon nitride or polyimide.

【0013】

As illustrated in FIGS. 2 and 4, the above-mentioned problems include a step of forming a plurality of first pads 4 with a conductive material above a region surrounding a semiconductor element 2 formed on a semiconductor substrate 1, and the above-mentioned problems. A step of forming a first protective insulating film 5 that covers the first pad 4, and a step of forming a plurality of first openings 6 that expose the first pad 4 in the first protective insulating film 6. A step of forming a resist 14 having a striped window 14a in the region including the first opening 6, and a step of forming the main conductor layer 15 of the wiring 7 from copper in the window 14a. A step of forming a gap between the resist 14 and the main conductor layer 15, and an uppermost layer 16 made of a platinum group metal in the window 14a on the upper surface and the side surface of the main conductor layer 15. A second protective insulating film having a step of forming, a step of removing the resist 14, and a second opening 9 in which a portion of the upper surface of the wiring 7 near the other end is exposed as a second pad 17. It is solved by a method for manufacturing a semiconductor device, which comprises a step of forming 8.

【0014】

In the method for manufacturing a semiconductor device described above, the gap is formed by heating and shrinking the resist 14. Next, the operation of the present invention will be described. According to the present invention, in a semiconductor device in which pads are rearranged, the main conductor layer constituting the wiring is formed of copper, and the uppermost conductive layer on the main conductor layer is formed of a hard material made of a platinum group metal. However, a part of it is used as a pad area.

【0015】

In this way, if the upper layer is formed of a material with high hardness during wiring used for pad rearrangement, the wiring will not be deformed due to the load applied during TAB and wire bonding, so the uppermost pad area will be covered. Even if a large load is applied, the load is distributed throughout the uppermost layer, the load per unit area applied to the main conductor layer is reduced, and no damage is caused by the load on the active element below it.

【0016】

In addition, since the Vickers hardness of the main conductor layer made of copper is about 30, it is relatively soft, so it can absorb the impact of the load applied to the main conductor layer to some extent, and damage to the active element below it due to the load impact. Can be suppressed. Further, by forming the uppermost layer from a material in which the protrusions (bumps) get wet, the protrusions can be easily attached when a part of the wiring is used as a pad.

【0017】

Further, since the uppermost layer of such wiring is formed on the upper surface of the main conductor layer of the wiring, electromigration is less likely to occur in the main conductor layer having low resistance, and the reliability of the semiconductor device is improved. Further, by covering at least a part of the side surface of the main conductor layer with the uppermost layer, the migration resistance is further improved.

【0018】

BEST MODE FOR CARRYING OUT THE INVENTION

Therefore, an embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 (a) shows a plane of a pad rearrangement structure in the semiconductor device according to the embodiment of the present invention, FIG. 1 (b) shows a cross section thereof, and FIG. 2 shows a cross section thereof. , A partially enlarged cross section of Fig. 1 (b) is shown.

【0019】

In the figure, a multilayer wiring structure 3 connected to a semiconductor element 2 is formed on a semiconductor substrate 1 such as silicon or a compound semiconductor. Further, a plurality of first pads 4 electrically connected to the multilayer wiring structure 3 are formed on the multilayer wiring structure 3 at intervals, and a first pad 4 is further formed on the multilayer wiring structure 3 at intervals. A protective insulating film 5 is formed.

【0020】

The first protective film 5 is formed with a first opening 6 for exposing the first pad 4. Further, a plurality of striped leader wirings 7 are formed on the first protective insulating film 5 by rearranging the pads. One end of the lead wire 7 is connected to the first pad 4 through the first opening 6. Further, the lead-out wires 7 are bypassed so as not to come into contact with each other and are pulled out into the area surrounded by the first opening 6, and the other ends of the lead-out wires 7 are arranged so as to be in different positions. Will be done.

【0021】

The lead wiring 7 is covered with a second protective insulating film 8, and the second protective insulating film 8 is formed with a second opening 9 for exposing the upper surface near the other end of each lead wiring 7. There is. A bump (projection) 10 is connected to the lead-out wiring 7 through the second opening 9, and the bump 10 is formed so as to have a larger area than the second opening 9. By increasing the diameter seen from above the bump 10, the force applied to the bump 10 per unit area is reduced.

【0022】

In FIG. 2, reference numeral 11 is a lead formed on the insulating sheet 12, 13 is the first metal layer of the lead wiring 7, 15 is the second metal layer (main conductor layer) of the lead wiring 7, and 16 is. A third metal layer (top layer) of the lead wire 7 is shown, and 17 shows a pad portion of the lead wire 7 exposed from the second opening 9. Further, in FIG. 1A, the second protective film 8 is omitted in order to clarify the planar shape of the lead wiring 7.

【0023】

The lead wiring 7, the second protective insulating film 8, the second opening 9, and the bump 10 as described above are formed according to the steps described below. Fig. 2 (a) to (d) and Fig. 3 (a) to (d) are cross-sectional views showing the pad rearrangement process, and the cross section on the left side of these figures is along the line II-II of Fig. 1. The cross sections are shown, and the right side of those figures shows the cross section along the line III-III of Fig. 1.

【0024】

First, as shown in FIG. 3A, a semiconductor substrate 1 in which a plurality of pads 4 made of aluminum are formed on the uppermost portion of the multilayer wiring structure 3 is prepared, and Si is placed on the multilayer wiring structure 3.₃N₄, SiO₂, An inorganic passivation film 5a made of an insulating material such as PSG is formed to a film thickness of about 1 μm, and an organic passivation film 5b such as polyimide is formed on the film to a film thickness of about 2 μm. The inorganic passivation film 5a or the organic passivation film 5b corresponds to the first protective insulating film 5 in FIGS. 1 (b) and 2.

【0025】

Then, the organic passivation film 5a and the inorganic passivation film 5b are patterned to form the first opening 6 on the pad 4. The size of the first opening 6 is, for example, about 70 μm × 80 μm. In this state, the pad 4 of the semiconductor device is in a state where it can be connected to an external terminal by a wire bonding method. Then, the subsequent steps are the pad rearrangement steps.

【0026】

After the formation of the first opening 6, as shown in FIG. 3 (b), the first metal layer 13 is formed in the first opening 6 and on the organic passivation film 5b by sputtering, vapor deposition, or the like. To do. The material of the first metal layer 13 may be any metal as long as it does not peel off on the organic passivation film 5b, and may be a single layer or a multilayer. Examples of the metal having good adhesion to the organic passivation film 5b include titanium, chromium (Cr), molybdenum (Mo), tangunten (W), or an alloy thereof. As the multilayer film, for example, Cr is 150 nm to 500 nm and Cu is 300 nm to 800 nm.

【0027】

After that, as shown in FIG. 3 (c), after applying the resist 14 on the first metal layer 13, the resist is exposed and developed to form the lead wiring 7 shown in FIG. 1 (a). Form a window 14a in. In this case, the portion of the window 14a existing on the pad 4 needs to be larger than the size of the first opening 6 of the organic and inorganic passivation films 5a and 5b.

【0028】

Subsequently, as shown in FIG. 3 (d), the second metal layer 15 having a film thickness of 300 nm to 800 nm is formed in the window 14a so as to have a thickness of 2 to 4 μm by electroplating, electroless plating, sputtering or vapor deposition. Form to. As the material of the second metal layer 15, a material having high conductivity such as copper, silver, and nickel is selected. When the second metal layer 15 is formed of copper, the first metal layer 13 has a multi-layer structure, and the uppermost layer thereof is copper to improve the adhesion between the second metal layer 15 and the first metal layer 13. You may.

【0029】

Further, as shown in FIG. 4A, a third metal layer 16 having a film thickness of 0.5 to 3.0 μm is formed on the second metal layer 15 by the same film forming method as that of the second metal layer 15. .. As the material for the third metal layer 16, select a metal material having a Vickers hardness greater than 70, such as an alloy containing Pd, platinum (Pt), rhodium (Rh) or any one of them. Alloy materials include nickel (Ni), cobalt (Co), copper (Cu), and gold (Au).

【0030】

After that, when the resist 14 is removed with a solvent, the state as shown in FIG. 4 (b) is obtained. When the second and third metal layers 15 and 16 are formed by sputtering and vapor deposition, those layers grown on the resist 15 are lifted off, and as a result, the second and third metal layers 15 and 16 are lifted off. The metal layers 15 and 16 of the above are left only in the window 14a, and the pattern of the second metal layer 15 and the pattern of the third metal layer 16 have the same planar shape as the window 14a.

【0031】

After this, the first metal layer 13 is removed using the second and third metal layers 15 and 16 as a mask, as shown in FIG. 4 (c), using an acid or alkaline etching solution. As a result, the first to third metal layers 13,15,16 have the same planar shape, and the first to third metal layers 13,15,16 are used as the lead wiring 7 shown in FIGS. 1 and 2. ..

【0032】

Next, as shown in Fig. 4 (d), an organic passivation film such as polyimide or an inorganic passivation film such as silicon nitride or silicon oxide is drawn out as the second protective insulating film 8 as a whole, and the wiring 7 is thicker than the wiring 7. After forming to a thickness of 4 μm, this is patterned to form a second opening 9 on the lead wire 7. The second opening 9 has a size that exposes a portion of the upper surface of the drawer wiring 7 that is separated from the pad 4 and does not expose the edge portion of the drawer wiring 7. The size of the second opening 9 is, for example, about 90 μm × 90 μm.

【0033】

Here, the area exposed from the second opening 9 of the lead wiring 7 is used as the uppermost pad 17. The pad rearrangement is completed by the above, but when the best pad 17 is connected to the external reed 11 by the TAB technology, a bump 10 made of PbSn solder is formed on the pad 17 as shown in FIG. .. In this case, since any of Pd, Pt, and Ro constituting the third metal layer 16 is exposed on the upper surface of the lead wire 7, the PbSn solder has good wettability with respect to the upper surface of the lead wire 7. become. That is, the bump 10 has good adhesion to the upper surface of the lead-out wiring 7.

【0034】

Due to the pad rearrangement as described above, the uppermost pad 17 is located above the active region of the semiconductor device. However, since the above-mentioned structure is adopted in the present embodiment, an external lead 11 may be connected to the bump 10 on the top pad 17 through the second opening 9, or a wire (wire) to the top pad 17. Even if a load on the semiconductor substrate is applied to the pad when connecting (not shown), the load is distributed by the area of the third metal layer 16 with high hardness, and the load per unit area below it is distributed. It is less. As a result, it becomes difficult to apply a load that destroys the semiconductor element 2 formed on the semiconductor substrate 1.

【0035】

That is, since the third metal layer 16 has a Vickers hardness of 70 or more, it is difficult to deform by itself, and a load locally applied to a part of the third metal layer 16 is applied to the third metal layer. It will be dispersed by the total area of 16 to reduce the load per unit area. On the contrary, when the lead wire is formed from a low hardness material such as copper and a local load is applied to the lead wire, the lead wire of the loaded portion is easily deformed locally and the semiconductor under the lead wire is easily deformed. The force applied to the element increases, causing damage to the element. The Vickers hardness of copper is about 30. When the second metal layer 15 is formed of the copper, the load dispersed by the third metal layer 16 is absorbed by the soft copper, so that the semiconductor element 2 below the copper element 2 is prevented from being destroyed.

【0036】

Further, since the third metal layer 16 is formed of a material in which the bump 11 made of PbSn solder is wet, the adhesion to the bump 11 is improved, which is most suitable for TAB. On the other hand, since the second metal layer 15 of the lead wiring 7 of the present embodiment is formed of copper, silver, nickel, or the like having high conductivity, the resistance of the lead wiring 7 is low, and the pad rearrangement of the semiconductor device causes the semiconductor device. It does not impair the circuit characteristics.

【0037】

By the way, in the above description, the first metal pattern 13 is patterned by etching the first metal pattern 13 using the patterns of the second and third metal layers 15 and 16 as a mask. .. However, as shown in FIG. 5A, the first metal layer 13 may be patterned in advance before the second metal layer 15 is formed. In this case, since the first metal layer 13 does not function as an electrode for electrolytic plating, electroless plating, sputtering or a vapor deposition method is used to form the second and third metal layers 15 and 16.

【0038】

After patterning the first metal layer 13, as shown in FIG. 5 (b), a resist 14 is applied, and the window 14b is exposed and developed to expose almost the entire first metal layer 13. To form. After that, the second protective insulating film 8 is formed as shown in FIG. 5 (c) through the steps shown in FIGS. 3 (d) and 4 (a) to 4 (d).

【0039】

Either one of the inorganic passivation membrane 5a and the organic passivation membrane 5b may be omitted. (Second Embodiment) In the first embodiment, as shown in FIG. 3 (c), the side surface of the window 14a of the resist 14 is substantially perpendicular to the upper surface of the first protective insulating film 5. I have to. Therefore, the planar shapes of the third metal layer 16 and the second metal layer 15 formed in the window 14a are substantially the same.

【0040】

In order to change such a structure and further enhance the migration resistance of the second metal layer, the following pad rearrangement process is adopted. First, a window 14a of the resist 14 is formed in the same manner as shown in FIG. 3D, and a second metal layer 15 is formed in the window 14a by electroplating or electroless plating.

【0041】

After that, as shown in FIG. 6A, a treatment is performed so that a gap g of up to about 2 μm is formed between the side wall of the window 14a of the resist 14 and the side surface of the second metal layer 15. For example, when the resist 14 is heated at 150 ° C. after the second metal layer 15 is formed by plating, the resist 14 shrinks and a gap g is formed between the resist 14 and the second metal layer 15.

【0042】

After this, as shown in FIG. 6 (b), a third metal layer 16 is formed on the second metal layer 15 by electroplating, electroless plating, sputtering or vapor deposition, and the resist 14 and the second metal layer 16 are formed. The third metal layer 16 is extended to the gap g between the metal layers 15. As a result, the pattern of the second metal layer 15 is covered not only on the upper surface but also on the side surfaces thereof by the high hardness third metal layer 16.

【0043】

After the formation of the third metal layer 16 is completed, the resist 14 is peeled off and the first metal layer 13 is patterned through the steps described in the first embodiment. The structure of the lead wire 7A as shown is obtained. After that, as shown in the sixth (d), a second protective insulating film 8 is formed, and a second opening 9 is formed.

【0044】

As described above, the upper surface and the side surface of the second metal layer 15 formed of a relatively soft metal material having a high conductivity and a Vickers hardness of about 30 are joined by the third metal layer 16 having a high hardness. By being covered, electromigration and stress migration are less likely to occur. For example, in the lead wiring having the structure shown in FIG. 4 (d), in the pressure cooker (PCT) test, when the gap between the lead wires is about 6 μm, a short circuit due to electromigration rarely occurs. On the other hand, in the lead wiring having the structure shown in Fig. 6 (d), no wiring short circuit due to migration occurred when the gap between the lead wires was 6 μm or less in the same PCT test.

【0045】

In the sample lead wire 7 used in the PCT test, the first metal layer 13 is formed of chromium, the second metal layer 15 is formed of copper having a film thickness of 2 μm, and the third metal layer 16 is formed of copper with a film thickness of 0.5. It is formed from μm palladium and uses polyimide as the second protective insulating film 8. Therefore, the lead wiring 7A obtained through the steps shown in FIGS. 6 (a) to 6 (d) has low resistance, is resistant to migration, protects the semiconductor element from the load of external wiring, and is soldered. The adhesion of the semiconductor device is also improved, and the reliability of the semiconductor device is improved.

【0046】

[Effect of the invention]

As described above, according to the present invention, since the upper layer is formed of a material having a high hardness during wiring used for pad rearrangement, there is no deformation of wiring due to the load applied during TAB and wire bonding. Therefore, even if a large load is applied to the pad region of the uppermost layer, the load is distributed by the entire uppermost layer to reduce the load per unit area applied to the main conductor layer, and further damage due to the load on the active element below it. Can be prevented.

【0047】

Further, since the main conductor layer made of copper is relatively soft, it is possible to absorb the impact of the load applied to the main conductor layer to some extent, and it is possible to suppress damage due to the load impact on the active element below the main conductor layer. Further, by forming the uppermost layer from a material in which the protrusions get wet, the protrusions can be easily attached when a part of the wiring is used as a pad.

【0048】

Further, since the uppermost layer of such wiring is formed on the upper surface and the side surface of the main conductor layer of the wiring, migration is less likely to occur in the low resistance main conductor layer, and the reliability of the semiconductor device is improved. it can.

[Simple explanation of drawings]

[Figure 1]

FIG. 1 (a) is a plan view showing a state in which the uppermost insulating film of the semiconductor device of the present invention is removed, and FIG. 1 (b) is a sectional view taken along line II of FIG. 1 (a).

[Figure 2]

FIG. 2 is an enlarged cross-sectional view of a part of FIG. 1 (b).

[Fig. 3]

3 (a) to 3 (d) are cross-sectional views (No. 1) showing a pad rearrangement step according to the first embodiment of the present invention.

[Fig. 4]

4 (a) to 4 (d) are cross-sectional views (No. 2) showing a pad rearrangement step according to the first embodiment of the present invention.

[Fig. 5]

5 (a) to 5 (c) are cross-sectional views showing a modified example of the pad rearrangement step according to the first embodiment of the present invention.

[Fig. 6]

6 (a) to 6 (d) are cross-sectional views showing a pad rearrangement step according to a second embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor substrate 2 Semiconductor element 3 Multi-layer wiring structure 4 pads 5 First protective insulating film 6 First opening 7 Drawer wiring 8 Second protective film 9 Second opening 10 bumps 11 lead 13 First metal layer 14 resist 15 Second metal layer 16 Third metal layer