High sensitivity image sensor array

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to novel pixel designs that allow the manufacture of image sensor arrays in general, and more specifically sensitive sensor arrays.

【0002】

[Conventional technology]

Large-area two-dimensional image sensor arrays are widely applied as medical imaging devices and optical scanning devices. At the heart of a typical imaging or scanning device is an array of pixels. Each pixel is generally composed of a sensor and a pass transistor. The sensor is generally a reverse biased photodiode and the path transistor is generally an amorphous silicon thin film field effect transistor (TFT). The bias line gives the sensor a reverse bias. The sensor is connected in series with a pass transistor connected to the data line. The gate electrode of the pass transistor is controlled by the gate control line. Assuming that the bias line extends horizontally and the gate control line extends vertically, then all pixels along a defined line are connected to the same data line, whereas they are defined. All gate electrodes of the pass transistor along the vertical row are connected to the same gate control line.

【0003】

Image sensors are typically configured as a two-dimensional array of rows and columns. Reading the image from the pixel array is done by a row decoder and a column decoder. The column decoder addresses one gate control line at a time, while the row decoder addresses all data lines connected to the same gate control line. The array's data line is connected to a charge-sensing readout amplifier, while the array's gate control line is connected to an external voltage switching circuit. Voltage switching circuits can independently keep their gate control lines at positive or negative voltage. Typical image sensor arrays are described in amorphous Silicon Sensor Arrays for Radiation Imaging, Street et al., Mat. Res. Soc. Symp. Proc. Vol. 192, p. 441 (1990).

【0004】

During imaging, the gateline is kept biased to turn off the pass transistor. When the light hits the sensor array, a charge corresponding to the intensity of the incident light is generated and stored in the photodiode sensor.

【0005】

During the read cycle, one gateline at a time turns on all path transitions along the gateline to a voltage that allows the charges stored in the pixels along the gateline to be read out at the same time. After the signal is read, the gate line goes low and turns off the pass transistor. This process is repeated by turning each successive gateline on and then off sequentially to read the entire 2D array to external electronics.

【0006】

In order to improve the sensitivity or dynamic range of the sensor array, it is important that the sensor array has a high signal-to-noise ratio (which allows the detection and measurement of relatively weak signals). The dynamic range of the sensor array is the smallest measurable signal (q)_min) And maximum signal (q_max). For example, for medical imaging devices, a typical target dynamic range is 4000. That is, the smallest measurable signal (q)_min) Is the maximum signal (q)_max) Will be at least 4000 times smaller. The electronic noise of the sensor array is the smallest measurable signal (q)_min) Is often the main limiting factor. If noise, or image-independent charge, corresponds to a significant portion of the pixel's charge capacitance, the sensitivity and useful dynamic range of the sensor array will be reduced.

【0007】

The noise level of the sensor array comes from many sources. The dominant noise source is the read amplifier connected to the data line. This noise is due to the input capacitance of the data line to the readout amplifier. A typical input capacitance for a data line is 50-100 picofarads. Currently, this noise source reaches about 1000-2000 electrons with high quality amplification. In contrast, the unique source associated with the array itself is generally on the order of hundreds of electrons. This noise is due to the transistor resistance and the thermal noise of the sensor capacitance (kTC noise).

【0008】

[Problems to be Solved by the Invention]

Considerable efforts have been made to reduce the capacitance of the array and redesign the readout amplifier to minimize noise in the sensor array. However, the dominant noise source that competes with the signal does not arise at the pixel level, but it arises from the amplifiers and their input lines, so techniques for improving the signal at the pixel level without increasing the noise associated with the readout electronics are The sensitivity and dynamic range of the sensor array can be increased.

【0009】

[Means for solving problems]

The present invention provides a pixel design that improves its sensitivity and dynamic range by producing a high signal-to-noise ratio in an image sensor array. This pixel design includes an intra-pixel amplifier that amplifies the signal but has a correspondingly minimal effect on the total noise of the sensor array. Specifically, this pixel design includes an intra-pixel single-transistor amplifier that increases the signal-to-noise ratio.

【0010】

The first advantage of the present invention is that it is a very efficient design in many respects. This pixel design meets many competing requirements by using two-transistor circuits. This pixel design amplifies, reads, and resets pixels with minimal negative impact on their size.

【0011】

The second advantage of this pixel design is its high pixel filling factor. The pixel fill factor represents a small area of the photosensitive array. In general, the addition of an amplifier reduces the pixel fill factor because the amplifier occupies valuable space available to the sensor. However, for efficient pixel design, the present invention reserves a very small area within the pixel occupied by the sensor.

【0012】

A third advantage is the addition of an intra-pixel amplifier at no additional gate line or bias line cost across the array. The present invention uses one gateline per pixel to perform all read and reset functions of the array. During the read cycle, a single gateline both reads pixels and resets previously read pixels.

【0013】

A fourth advantage of the present invention is that the novel pixel design is compatible with the current manufacturing process of sensor arrays. In general, adding an amplifier will deviate from the standard manufacturing process as it requires an additional process. However, this pixel design allows intra-pixel amplifiers to be made using current manufacturing processes without sacrificing array manufacturing capacity.

【0014】

The advantages and objectives of the present invention will become apparent from the following detailed description of the invention, preferred embodiments of the invention, accompanying drawings, and claims.

【0015】

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an equivalent circuit of an embodiment of the present invention that uses an intra-pixel single-transistor amplifier to increase the signal-to-noise ratio of a sensor array. The single transistor amplifier is a TFT. TFTs are easily integrated into pixels using current manufacturing technology. By this method, each pixel consists of a sensor (S) 102, a reset transistor (R) 104, a pass transistor (P) 106, and a common source amplifier transistor (A) 108. Sensor 102 is C_sA nip amorphous silicon photodiode with the relevant capacitance of. Here, "n" and "p" indicate an n-doped amorphous silicon layer and a p-doped amorphous silicon layer, respectively. The thickness of each dope layer is generally 10-100 nanometers. I is a true amorphous silicon layer with a thickness of about 1 to 2 μm. The p-doped region of sensor 102 is connected to the bias line and its negative voltage (V)._B) Gives the reverse bias necessary to operate the sensor 102. If a pin photodiode is used in this embodiment, a positive voltage will be supplied to the n-type region of the sensor instead of a negative one.

【0016】

As shown in FIG. 1, the output (point X) of the sensor 102 drives the gate of the amplifier (A) 108 to perform the desired amplification for the signal stored in the sensor 102. Since the pass transistor (P) 106 is connected in series with the amplifier (A) 108, the gate line (G)_n) 112 goes high, the pass transistor (P) 106 switches on and current flows through the amplifier (A) 108 and pass transistor (P) 106 to the data line 114. The current flowing through both transistors reflects the charge stored in the sensor 102. The gate electrode is the next gate line G_{n + 1}The reset transistor (R) 104 connected to 116 resets the sensor 102 after the read period.

【0017】

Capacitance C of sensor 102_SIs generally on the order of Pico Farad. Bias voltage V_BIs a few volts in size. The charge (q) associated with sensor 102 is its capacitance C_SAnd the voltage across the sensor (V)_S) Is the product. Generally, C_SAnd V_SProduct (maximum amount of charge that sensor 102 can store (q)_max)) Is about 1-5 picocourons. For example, if C_SAnd V_SIf the product of is 1 picofarad, q_maxIs 5x10⁶It is an electronic order. Assuming a target dynamic range of 4000, the desired minimum detectable signal (q)_min) Is about 1250 electrons (1 × 10)^-15Will be less than Coulomb). Therefore, the minimum signal (q) that can be detected by the sensor to achieve the desired sensitivity and dynamic range._min) Should be on the order of 1250 electrons at most.

【0018】

As mentioned earlier, the dominant noise source that competes with the signal does not arise at the pixel level, but from the amplifiers and their input data lines. The input capacitance of each data line is typically 50-100 picofarads, reaching noise levels of about 1000-3000 electrons, depending on the quality of the readout amplifier and associated electronics. On the other hand, the noise associated with pixel capacitance is usually on the order of hundreds of electrons. Therefore, the magnitude of the noise associated with the capacitance of the pixel is smaller than the noise associated with the readout electronics.

【0019】

The intra-pixel TFT amplifier formed by the common source amplifier (A) 108 shown in FIG. 1 increases the signal-to-noise ratio of the array because amplification occurs at the pixel level. The noise associated with the readout electronics is not amplified correspondingly. In general, the signal-to-noise ratio (S / N) is equal to the pixel signal divided by the weighted sum of noise at the pixel and read levels. That is, S / N = signal_pixel/[(noise_pixel)²+ (Noise_decode)²〕^1/2In-pixel amplifier gain G_pixelAssuming that, the signal-to-noise ratio is expressed by the following equation. S / N = G_pixel× signal_pixel/ [(G_pixel× Noise_pixel)²+ (Noise_decode)²〕^1/2= Signal_pixel/[(noise_pixel)²+ (Noise_decode/ G_pixel)²〕^1/2The above equation shows that the gain suppresses the contribution of read noise to the signal-to-noise ratio. But (noise_decode/ G_pixel) Is (noise_pixel) Much smaller, G_pixelAs the value increases, pixel noise predominates and further improvements in the signal-to-noise ratio are negligible.

【0020】

As an example, noise_pixel= 200 electrons, noise_decodeAssuming = 200 electrons and the gain of the TFT amplifier = 10, noise is amplified 10 times as well as the signal at the pixel level. The noise at the pixel level increases 10-fold from 200 to 2000 electrons, while the dominant noise associated with the amplifier increases only 1.4-fold. In other words, a 10x increase in noise at the pixel level does not result in a 10x increase in total noise. In general, a break-even point occurs when the gain of the signal is correspondingly offset by the increase in total noise. In the case of the above example, a break-even point occurs when the amplification is large as the pixel noise becomes dominant, that is, when (gain × 200)> 2000.

【0021】

The above calculation further shows that the present invention does not require an amplifier with significant gain. In fact, in the case of the above example, if the gain at the pixel level is much greater than 10, there is no further benefit.

【0022】

FIG. 2 shows a schematic diagram of the image sensor array according to the present invention. As shown in Figure 2, each gateline reads all pixels along a defined column, while each dataline carries a signal for all pixels along a defined row. The gate line is connected to an external voltage switching circuit that can apply a positive or negative bias voltage to each line. The data line is connected to a read integrator 232 that senses charge. A voltage amplifier can also be used.

【0023】

Light is sensor S_nWhen it hits 202, the voltage at the output of the sensor (point X) is the bias voltage V._BIt increases toward. Point X is V_BWhen the capacitance C associated with the sensor 102 is reached_sIs saturated. The voltage at point X is about V when the sensor is saturated, from a value close to 0 voltage when there is no illumination._BChange to.

【0024】

During imaging, all gatelines are kept low and all transistors in the array are turned off. Light is sensor S_nWhen it hits 202, an electric charge is generated and stored, and the voltage at point X is changed to V._XRaise to. After imaging, sensor S_nGateline G to read the charge stored in 202_n200 is ranked high. Transistor A_nAssuming that the threshold voltage of 206 is 0, the gate line G_nWhen 200 becomes high, amplifier transistor A_n206 and pass transistor P_nBoth 208 switch on, allowing current to flow to dataline 230. The current flowing through the data line 230 is determined by the voltage at point X and is integrated by the external integrator 232 for the selected time.

【0025】

Sensor S to read pixel n + 1_{n + 1}Gateline G so that the charge stored in 212 is read out_{n + 1}210 becomes high. Gateline G_{n + 1}When 210 becomes high, pass transistor P_{n + 1}Is turned on, and the reset transistor R of the previously read pixel_n204 is turned on and sensor S_nReset 202. In other words, Gateline G_{n + 1}210 is used to read pixels n + 1 and to reset previously read pixels.

【0026】

Figure 3 shows a schematic diagram of the pixel equivalent circuit. The equivalent circuit shows the feedthrough capacitance of the reset transistor (R) 104. As shown in Figure 3, the parasitic capacitance (C) between the source and gate regions of the reset transistor (R) 104._gs) 302 exists and the parasitic capacitance (C) between the drain and the gate area_gd) 304 exists. Due to these parasitic capacitances, Gateline G_{n + 1}When 116 is high, the reset transistor (R) 104 is not accurately reset to ground. The voltage across the source and drain contacts of the reset transistor (R) 104 is V._R(Generally called the reset voltage). Gateline G after charge transfer from sensor 102_{n + 1}When 116 goes low, the feedthrough charge generally goes from point X to a voltage V of about -0.5 volts._RReset to.

【0027】

FIG. 4 shows the current through the data line 114 of FIG. 3 (I)._F) And the voltage at point X are shown. During the read cycle, amplifier (A) 108 in FIG. 3 has its gate voltage V._GIs its drain voltage V_DSince it is lower, it generally operates within its saturated region. Assuming that amplifier (A) 108 has a threshold voltage of 0 volts, the current I through amplifier (A) 108_FIs expressed by the following equation. I_F= C_Gμ (Q_s-Q_sat)²/ C_s²W / (2L) Where C_GIs the channel capacitance of amplifier (A) 108, μ is carrier mobility, W is width, L is length, Q_sIs the amount of charge stored in the sensor, Q_satIs a saturated charge.

【0028】

As an example, 100-150 μm²1 picofarad sensor capacitance specific to pixel size, 4 W / L ratio, 5 volt gate voltage, and 5x10^-8Farad / cm²Assume the gate capacitance of. In addition, it is assumed that the capacitance associated with the gate electrode of amplifier (A) 108 and the parasitic capacitance associated with reset transistor (R) 104 and amplifier (A) 108 are negligible. For the assumed parameters, Q_sWhen is 0, the current (I)_F) Is about 2.5 μA, and if the integration time is about 20 μs, a total output charge of 50 picocourons is generated. Typical q of 5 picocourons_maxCompared to, this output charge represents a gain of about 10, which should dramatically improve the performance of amorphous silicon imaging equipment. Depending on the transistor design, the on-resistance of the reset transistor (R) 104 and pass transistor (P) 106 in the saturation region is generally about 1 MΩ.

【0029】

As shown in FIG. 4, the current through the data line 114 of FIG. 3 (I)_F) And the voltage at point X are monotonous and non-linear. Furthermore, the polarity of the signal is inverted. When the signal is large, the current in data line 114 (I)_F) Is few. In general, signal polarity reversal is not an important point in sensor array design, as software gain and offset corrections are performed on the signal on a regular basis. In addition, the pixel design is extra complex, but the signal can be more linear. If a higher source bias is applied to amplifier (A) 108, the relative change in voltage between the gate and source is reduced and the response becomes more linear. This could be achieved by adding a second bias line that can apply different bias voltages to the sensor 102 and the amplifier (A) 108. However, non-linearity may not be important in certain applications. For example, linearity is generally not important for X-ray photon counters.

【0030】

FIG. 5 shows a possible timing diagram for the array read cycle shown in FIG. This timing diagram shows the gateline G with respect to time._nShows the magnitude of the voltage above 200. Generally, the time it takes to read the gate line is called the "line time" and is on the order of 30 to 100 μs. The time required to perform a complete read of all gatelines is called the "frame time" and ranges from milliseconds to seconds. The RC time constant of the readout electronics in this array is generally 2-5 μsec.

【0031】

The readout process generally uses a double-correlation sampling technique. This sampling technique involves two consecutive measurements that remove all extra signals. Before reading pixel n in Figure 2, the previous pixel (n-1) was read, then t_{OFF (n-1)}From t_ONAll gate lines remain off during the time interval until. Gateline G_n200 is t_ONAfter becoming high in, and after the previously read pixels have been properly reset, the first measurement is t₁Is done in. Period t_ONFrom t₁During the period until, the voltage of the data line 230 in FIG. 2 is kept at the ground potential, and the integrator 232 is disabled by closing the feedback switch 231 shown in FIG. The initial reset period generally lasts 5 μs. t₁At, the integrator 232 is activated by opening the feedback switch 231 at which time the first measurement is made. T at the end of the integration time₂In, a second measurement is made before the feedback switch 231 is closed again. The difference between the two measurements is recorded. The sampling capacitor that stores the two measurements is not shown in the drawing. They are generally part of the external integrator 232 shown in Figure 2. Under that measurement method, all extra signals are removed. t₂After making the second measurement in, the sensor (S_n-1) 220 outputs (point X)_n-₁) Can be reset to a different voltage, gateline G_n200 is t_{OFF OFF}May remain high. Finally, the gate line G200 is t_{OFF OFF}When it becomes low in, the next gate line G_{n + 1}210 is t_{ON (n + 1)}At, the read cycle is repeated at that point.

【0032】

FIG. 6 shows a pixel layout of the present invention that can be produced using current manufacturing processes for amorphous silicon sensor arrays. Current manufacturing processes typically use three metal layers to form interconnect lines and an additional transparent metal film that makes surface contact with the sensor. The interconnect layer forming the gate electrode of the TFT is the "gate metal" layer 101. Above the gate metal layer 101 is another metal layer 103 that forms electrodes for the source and drain regions of the TFT. This metal layer 103 is commonly referred to as a source / drain metal or "S / D metal". Above the S / D metal layer 103 are two additional metal layers, commonly referred to as the "upper metal" layer 105 and the "InSnO" or "ITO" layer 107.

【0033】

As shown in FIG. 6, the gate electrodes of the reset transistor (R) 104, amplifier (A) 108, and pass transistor (P) were formed with the gate metal layer 101 and with the upper metal layer 105. Bias line (V_B) 110. The bias line 110 shields the gate electrode of the transistor from illumination. In the case of this embodiment, Gateline G_{n + 1}116 is connected to the gate of the reset transistor (R) 104, whereas gate line G_n112 is connected to the gate of pass transistor (P) 106. The pixel pitch is generally 100-500 μm.

【0034】

The gate electrode of the amplifier transistor (A) 108 is connected to the bottom electrode of the sensor 102 via a conductor 602. The gate electrode of the amplifier transistor (A) 108 is formed of the gate metal layer 101, whereas the bottom electrode of the sensor 102 is formed of the S / D metal layer 103. Conductor 602 provides a short circuit between the gate metal layer 101 and the S / D metal layer 103.

【0035】

The bottom electrode of the sensor 102 also forms a source region for the reset transistor (R) 104, as shown in FIG. On the other hand, the drain region of the reset transistor (R) 104 is formed by the S / D metal layer 103 and is connected to the data line 114 via the conductor 600. The conductor 600 connects the S / D metal layer 103 and the upper metal layer 105.

【0036】

The data line 114 is connected to the drain of the pass transistor (P) 106 via another conductor 606. Conductor 606 is similar to conductor 600 in that it connects the S / D metal layer 103 to the upper metal layer 105. Further, as shown in FIG. 6, a part of the S / D metal layer 103 forming the source of the pass transistor (P) 106 also forms a drain of the amplifier transistor (A) 108.

【0037】

As can be seen from FIG. 6, the sensor 102 is 150 μm.²It can occupy more than 50% of the pixel area of a cell (which indicates a reasonable sensor filling factor). In general, the larger the pixel size, the higher the fill factor can be achieved. If the sensor layer is placed on top of the TFT to form an array, it will be possible to include smaller pixel sizes, that is, more complex circuits.

【0038】

FIG. 7 shows an alternative embodiment of the present invention using the second bias line. This second bias line is formed by the gate metal layer 101. Under this technique, the source of amplifier transistor (A) 108 can be biased separately from bias to sensor 102. In addition, the lower bias (eg -2 Volts) associated with resetting the sensor output point to +5 Volts gives better linearity without a reduction in the filling factor.

【0039】

Under this technique, an additional conductor 710 is needed to provide a second bias. The source region of the amplifier transistor (A) 108 is connected to the second bias line 700 via the conductor 710. The conductor 710 connects the S / D metal layer 103 to the gate metal layer 101. Unlike the conductor 604 in FIG. 6, the conductor 712 only connects the top electrode of the sensor 102 to the bias line 110. Conductor 714 is functionally identical to conductor 600 shown in FIG.

【0040】

Although the invention has been described above for specific embodiments, it is clear from the above description that experts in the art can easily come up with many alternatives, modifications, and equivalents. Accordingly, the present invention shall include all alternatives, modifications, and equivalents that fall within the spirit of the invention and claims.

[Simple explanation of drawings]

[Figure 1]

It is a circuit diagram of the equivalent circuit of the pixel design which concerns on this invention.

[Figure 2]

It is a circuit diagram of the image sensor array which concerns on this invention.

[Fig. 3]

It is a circuit diagram of the equivalent circuit of the pixel design which shows the feedthrough capacitance of a reset transistor.

[Fig. 4]

It is a graph which shows the relationship between the voltage at the output end of a sensor in a pixel and the current on a data line.

[Fig. 5]

It is a possible timing diagram of the read cycle of an array.

[Fig. 6]

It is a figure which shows the layout of the pixel design which concerns on this invention.

[Fig. 7]

FIG. 5 shows another layout of a pixel design with an additional bias line for each column of pixels.

[Explanation of symbols]

101 Gate metal layer 102 sensor 103 S / D metal layer 104 reset transistor 105 Upper metal layer 106 pass transistor 107 ITO layer 108 Amplifier transistor 110 bias line 112 Gateline 114 data line 116 Gateline 200,210,220 Gateline 202,212,222 sensor 206,216,226 Amplifier transistor 208,218,228 pass transistor 230 data line 231 Feedback switch 232 External integrator 600,602,604,606 Conductor 700,710,712,714 Conductor