Switched capacitor filter

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a switched capacitor filter.

【0002】

[Conventional technology]

FIG. 14 shows a configuration example of a conventional switched capacitor filter. This configuration example is a first-order low-pass filter, which is composed of switched capacitor circuits 1 and 2 and an integrator 3. Each of the switched capacitor circuits 1 and 2 plays a role as a resistance element. For example, the switched capacitor circuit 1 is composed of one capacitor 10 and four analog switches 11 to 14. The same applies to the other switched capacitor circuits 2.

【0003】

Here, the analog switches 11 and 13 are brought into a conductive state by the clock φa generated at a constant cycle. When these analog switches are in a conductive state, a signal path of analog switch 11 capacitor 10 analog switch 13 grounding point is formed, and the charge corresponding to the level of the input signal is charged through this signal path to the capacitor. It is held at 10. Further, the analog switches 12 and 14 are brought into a conductive state by the clock φb generated at a constant cycle instead of the clock φa. When these analog switches are made conductive, a signal path of grounding point analog switch 12 capacitor 10 analog switch 14 integrator 3 is formed, and is held by the capacitor 10 via this signal path. The charged charge is supplied to the integrator 3.

【0004】

Since the clocks φa and φb are output alternately at regular time intervals, the operation of holding the electric charge in the capacitor 10 according to the level of the input signal and the operation of supplying this electric charge to the integrator 3 are constant. Repeated at time intervals, a current corresponding to the level of the input signal is supplied to the integrator 3. The same operation is performed in the other switched capacitor circuits 2. As a result of each switched capacitor circuit playing a role as a resistance element in this way, the circuit shown in FIG. 14 operates equivalent to an analog filter in which each of the switched capacitor circuits 1 and 2 is replaced by a resistance element. ..

【0005】

[Problems to be Solved by the Invention]

By the way, in the field of handling analog signals such as audio, it is often the case that a plurality of channels of analog signals such as stereo L channel and R channel are filtered. In such a case, since the number of filters corresponding to the number of channels has been conventionally used, there is a problem that the price of the audio device or the like becomes high.

【0006】

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a switched capacitor filter capable of filtering analog signals of a plurality of channels with a small-scale circuit configuration.

【0007】

[Means for solving problems]

The invention according to claim 1 provides a switched capacitor filter that performs filtering processing including integration processing on input analog signals of a plurality of channels by time division control. The switched capacitor filter according to the present invention has an integrating means I as illustrated in FIG._k, I_{k + 1}, ..., switch means SW, and integral value storage means M_k, M_k, ..., M_{k + 1}, M_{k + 1}, ... and have.

【0008】

The integration means sequentially executes the integration processing constituting the filter processing for each channel by time division control. When there are a plurality of integral processes that constitute the filter process, as shown in the figure, the integral means I corresponding to each integral process._k, I_{k + 1}If, ... is provided, the circuit configuration becomes simple. Further, such a configuration is preferable when high-speed operation is desired.

【0009】

The integral value storage means stores an integral value signal indicating the result of the integral processing corresponding to each channel. As shown in the figure, the integrated value storage means M corresponding to each channel._kHowever, it is not always necessary to provide the same number of channels as the number of channels, although the circuit configuration becomes simple.

【0010】

Then, each time the integration process corresponding to each channel is interrupted, the switch means stores the integral value signal indicating the result of the integral process corresponding to the channel at the time of interruption in the integral value storage means, and integrates the integral means. Initialize the processing result. Further, each time the integration process corresponding to each channel is executed, the integration value signal corresponding to the channel is supplied from the integration value storage means to the integration means, and the analog signal to be processed by the integration process is used as the integration means. Supply.

【0011】

Here, when the integration process corresponding to a plurality of channels is sequentially executed by the same integration means, the integration process corresponding to a certain channel is interrupted by another integration process. However, in the present invention, after the integration value signal at the time of interruption of the integration processing is stored in the integration value storage means via the switch means, the result of the integration processing of the integration means is initialized, and the integration processing is restarted. Since this integrated value signal is given to the integrating means when the integration is performed, the interrupted integration process is always restarted from the state before the interruption. By such control, the integration process that constitutes the filtering process is executed for each channel by sharing the integration means.

【0012】

According to the second aspect of the present invention, in the switched capacitor filter according to the first aspect, as illustrated in FIG. 2, the integrated value storage means M_kHas at least two storage units (capacitors in the figure), and the switch means SW stores the integrated value signal corresponding to the channel as the integrated value storage means each time the integration process corresponding to each channel is executed. M_kOne memory unit in MM₁Operation to be stored in and other storage units MM₂Integrate means I integrates the integrated value signal corresponding to the channel stored in_kSimultaneously execute the operations to be supplied to (solid arrow). When these operations are completed, the "integral value signal corresponding to the channel" is stored in the storage unit MM.₁It will be in the state of being stored in. Therefore, the next time the integration process for the channel is performed, the storage unit MM₁The "integral value signal corresponding to the channel" is read out from and sent to the integration means, and the integral value signal indicating the result of the integration process is stored in the storage unit MM.₂It is memorized in (dashed arrow).

【0013】

According to the present invention, since the integrated value is written and read at the same time, there is an advantage that high-speed operation is possible.

【0014】

In the invention according to claim 3, in the switched capacitor filter according to claim 1 or 2, the filter processing has a plurality of types of integration processing, and the integration means I performs each integration according to the configuration illustrated in FIG. The processing is sequentially executed by time division control.

【0015】

When the demand for high-speed operation is not strict, the number of integration means can be reduced, which is an effective configuration.

【0016】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described in order to make the present invention easier to understand. Such an embodiment shows one aspect of the present invention, does not limit the present invention, and can be arbitrarily modified within the scope of the present invention.

【0017】

A. Configuration of embodiment FIG. 4 is a block diagram showing a configuration of an embodiment of the present invention. In this embodiment, for example, a switched capacitor filter as shown in FIG. 14 is improved so that it can process two-channel analog signals Ain1 and Ain2, and the portion shown in FIG. 4 is covered. It shows the part corresponding to the integrator of the improved switched capacitor filter. Here, each analog signal to be processed is a balanced signal, the analog signal Ain1 of the first channel is composed of the positive phase signal AinP1 and the negative phase signal AinN1, and the analog signal Ain2 of the second channel is the positive phase signal AinP2 and the reverse phase signal AinP2. It consists of the phase signal AinN2.

【0018】

The clock circuit 60 is a means for controlling the operation timing of each part in the filter, and the clocks a, b, c, d, ac, bd, b1, d1, b2, d2, bb and dd required for such timing control. Is output. The waveforms of these clocks are shown in the timing chart of FIG.

【0019】

The input switched capacitor units 11 to 14 are means for outputting a current corresponding to the level of each input analog signal. Of the above-mentioned input analog signals, the positive phase signal Ain1P of the first channel goes to the input switched capacitor section 11, the positive phase signal Ain2P of the second channel goes to the input switched capacitor section 12, and the negative phase signal Ain1N of the first channel The reverse phase signal Ain2N of the second channel is supplied to the input switched capacitor unit 13, respectively, and is supplied to the input switched capacitor unit 14. The current output from the input switched capacitor units 11 and 12 is supplied to the signal line LP (hereinafter referred to as positive phase input line LP), while the current output from the input switched capacitor units 13 and 14 is It is supplied to the signal line LN (hereinafter referred to as the reverse phase input line LN).

【0020】

Explaining the configuration of each input switched capacitor unit, first, the input switched capacitor unit 11 is composed of one capacitor C4 and four analog switches S111 to S114. Here, the analog switches S111 and S113 are brought into a conductive state by the clock a. When these analog switches become conductive, a signal path of analog switch S111 capacitor C4 analog switch S113 reference power supply Vref is formed, and by passing through this signal path, it corresponds to the level of the input analog signal Ain1P. The charge is held in the capacitor C4 (sampling operation). Further, the analog switches S112 and S114 are brought into a conductive state by the clock b. When these analog switches are in a conductive state, a signal path of reference power supply Vref analog switch S112 capacitor C4 analog switch S114 positive phase input line LP is formed, and by passing through this signal path, the capacitor The charge held in C4 is inverted in polarity and supplied to the positive phase input line LP (output operation).

【0021】

The same applies to the other input switched capacitor units 12 to 13, and one capacitor for holding the input analog signal for each, the signal path for applying the input analog signal to the capacitor, and the charge held in the capacitor are output. It is composed of four analog switches to form a signal path. The name of each capacitor and the name of the clock that makes each analog switch conductive are as shown in the figure.

【0022】

In the present embodiment, the operation of each input switched capacitor unit is controlled at a different timing for each channel, and the input switched capacitor units 11 and 13 corresponding to the first channel perform sampling operation by the clock a. However, in the input switched capacitor units 12 and 14 corresponding to the second channel, the sampling operation is performed by the clock c. The sampling operation may be performed at the same timing for each channel. Further, the output operation is performed by the clock b in the input switched capacitor units 11 and 13 corresponding to the first channel, and is performed by the clock d in the input switched capacitor units 12 and 14 corresponding to the second channel.

【0023】

The integrator 40 includes a differential amplifier 41, capacitors C7, C8, C17 and C18, and analog switches S401 to S410. Here, the inverting input end of the differential amplifier 41 is connected to the positive phase input line LP, and the forward rotation input end is connected to the negative phase input line LN. Further, the forward and reverse output ends of the differential amplifier 41 are connected to signal lines MP and MN (hereinafter, referred to as positive phase output line MP and negative phase output line MN), respectively.

【0024】

The integrating capacitors C8 and C7 are inserted between the inverting input end and the normal rotation output end of the differential amplifier 41 and between the normal rotation input end and the inverting output terminal, respectively. Further, in the present embodiment, the integration operation is performed during the period when the clock bd is output. During this integration operation, the capacitor C18 is connected in parallel to the integration capacitor C8 via the analog switches S402 and S405, and the capacitor is connected. C17 is connected in parallel to the integrating capacitor C7 via analog switches S407 and S410.

【0025】

With the above configuration, the signals input to both input ends are integrated while the potentials of the forward and reverse input ends of the differential amplifier 41 are maintained at the level of the reference power supply Vref, and the positive phase input line LP is used. The total charge supplied via the integrating capacitor C8 is stored in the integrating capacitor C8, and the total charge supplied via the reverse phase input line LN is stored in the integrating capacitor C7. As a result, a voltage corresponding to the integrated value is output between the forward rotation output end and the inverting output end of the differential amplifier 41. The output voltage corresponding to this integrated value is separated into a positive phase component and a negative phase component by the positive phase output line MP and the negative phase output line MN, and is supplied to each part.

【0026】

Further, the analog switches S401, S403, S404, S406, S408 and S409 are made conductive by the clock ac, and both ends of the capacitors C7, C8, C17 and C18 are short-circuited to set the integrated value to 0 at the initial stage. Used as an analog switch.

【0027】

The integration unit 40 sequentially and repeatedly executes each integration process corresponding to the first channel and the second channel under time division control. In order to enable time-division control of such integration processing, the following means are taken in this embodiment.

【0028】

When the integrator processing being executed is interrupted, the integral value of the integrator 40 is initialized to 0, and the integrator 40 is passed to the next integrator. The initialization analog switch S described above is a means for fulfilling this role.

【0029】

b. When the above integration process is interrupted, the integrated value obtained up to the time of the interruption is stored. Then, when the integration process is restarted, the integration value is given to the integration unit 40, and the integration process is restarted from the state at the time of interruption. The means for making this possible are the first integrated value storage units 21 to 24 and the second integrated value storage units 31 to 34 in FIG.

【0030】

These integrated value storage units are means for storing signals representing integrated values for each integration process performed by the integrated unit 40. In the present embodiment, the filter processing corresponding to each channel is performed by performing each integration processing corresponding to the first channel and the second channel, and the positive phase representing the integral value of the integration processing corresponding to the first channel. Signals are stored in the first integrated value storage unit 21 and the second integrated value storage unit 31, and opposite-phase signals representing the same integrated value are stored in the first integrated value storage unit 23 and the second integrated value storage unit 33 in the second channel. The positive-phase signal representing the integrated value of the integral processing corresponding to the first integrated value storage unit 22 and the second integrated value storage unit 32, and the opposite-phase signal representing the same integrated value is the first integrated value storage unit 24 and the second integrated value storage unit 24. Each is stored in the second integrated value storage unit 34.

【0031】

Explaining the configuration of each integrated value storage unit, first, the first integrated value storage unit 21 is composed of one capacitor C6 and four analog switches S211 to S214, similarly to the input switched capacitor unit described above. There is. Here, the analog switches S211 and S213 are brought into a conductive state by being given the clock b1. When these analog switches are in a conductive state, a signal path of positive phase output line MP analog switch S211 capacitor C6 analog switch S213 reference power supply Vref is formed. Then, through this signal path, the electric charge corresponding to the positive phase component of the signal representing the integrated value is held in the capacitor C6. Further, the analog switches S212 and S214 are brought into a conductive state by the clock b2. When these analog switches are brought into a conductive state, a signal path of reference power supply Vref analog switch S212 capacitor C6 analog switch S214 positive phase input line LP is formed. Through this signal path, the electric charge held in the capacitor C6 is supplied to the positive phase input line LP in a state where the polarity is inverted. In this way, the integrated value is sampled by outputting the clock b1, and the charge equivalent to the integrated value is supplied to the positive phase input line LP in a state where the polarity is inverted by outputting the clock b2. It is.

【0032】

The second integrated value storage unit 31 also has exactly the same configuration as the first integrated value storage unit 21, and has one capacitor C5 and four analog switches. However, the roles played by the clocks b1 and b2 in the second integrated value storage unit 31 are opposite to those in the case of the first integrated value storage unit 21. Therefore, when the clock b1 is output, the voltage on the positive phase output line MP is applied to the capacitor C6 of the first integrated value storage unit 21 and at the same time held in the capacitor C5 of the second integrated value storage unit 31. The charged charge is supplied to the positive phase input line LP. Further, by outputting the clock b2, the voltage on the positive phase output line MP is applied to the capacitor C5 of the second integrated value storage unit 31 and at the same time held in the capacitor C6 of the first integrated value storage unit 21. The electric charge will be supplied to the positive phase input line LP.

【0033】

The other integrated value storage units are exactly the same as those of the first integrated value storage unit 21 and the second integrated value storage unit 31, and are composed of one capacitor and four analog switches. The name of each capacitor and the name of the clock that controls the continuity of each analog switch are as shown in the figure.

【0034】

The output unit 50 is a means for converting the output signals corresponding to each channel sequentially obtained from the integrating unit 40 into non-equilibrium signals and outputting them separately. Here, the resistors R1 to R4 and the differential amplifier 51 constitute means for amplifying the output signal of the integrating unit 40 with the amplification degree determined by the resistors R1 to R4. Further, the analog switch S501 and the capacitor C9 constitute a sample hold circuit that captures and holds the signal corresponding to the first channel among the output signals of the differential amplifier 51, and the analog switch S502 and the capacitor C10 are the second. It constitutes a sample hold circuit that captures and holds the signal corresponding to the channel. Here, the sampling operation of the sample hold circuit corresponding to the first channel is performed by the clock bb, and the sampling operation of the sample hold circuit corresponding to the second channel is performed by the clock dd. Then, the output signal of the sample hold circuit corresponding to the first channel is output as a signal OUT1 via the buffer 52, and the output signal of the sample hold circuit corresponding to the second channel is output as a signal OUT2 via the buffer 53.

【0035】

B. Operation of the embodiment Hereinafter, the operation of the present embodiment will be described with reference to the timing chart of FIG. In the present embodiment, the input analog signal is sampled at a fixed sampling cycle TS, and filtering processing for two channels is performed. A series of processes for this filter process are sequentially advanced in units of each time slot obtained by dividing each sampling period into four. Focusing on the content of the processing performed in each time slot, the same processing is repeated with eight consecutive time slots, that is, the time 2TS for two cycles converted into a sampling cycle as one unit. Therefore, in the following, two consecutive sampling cycles TS_iAnd TS_{i + 1}Assuming a period consisting of, the time slots SL1 to SL8 are obtained by dividing this period into eight, and the operation in each time slot will be explained.

【0036】

(1) Time slot SL1 Sampling period TS_iIn the time slot SL1 of, only clocks a and ac are output, and other clocks are not output. Therefore, the state of each analog switch is shown in FIG. 6 depending on the output of the clock, and the following operations are performed in each part.

【0037】

In the input switched capacitors 11 and 13, the input analog signals Ain1P and Ain1N of the first channel are sampled, and the charges corresponding to the levels of the analog signals are held in the capacitors C4 and C1, respectively.

【0038】

In the integrating unit 40, both ends of the capacitors C7, C17, C8 and C18 are short-circuited by the initialization analog switch, and the integrated value of the integrating unit 40 is initialized to 0.

【0039】

(2) Time slot SL2 In this time slot SL2, only clocks b, bd, b1 and bb are output, and other clocks are not output. Therefore, the state of each analog switch is shown in FIG. 7 depending on the output of the clock, and the following operations are performed in each part.

【0040】

In the input switched capacitor units 11 and 13, the charges held in the capacitors C4 and C1 are respectively reversed in polarity and supplied to the positive phase input line LP and the negative phase input line LN, respectively.

【0041】

In the second integrated value storage units 31 and 33, the charges held in the capacitors C5 and C2 are supplied to the positive phase input line LP and the negative phase input line LN. The holding charge of each of these capacitors is the sampling period TS._i-1It is given by the integrator 40 in the above, and corresponds to the integral value of the integral process corresponding to the first channel.

【0042】

In the integrator 40, since the initialization analog switch is opened and all of the integrator capacitors C8, C18, C7 and C18 are connected to the differential amplifier 41, the positive phase input line LP and the negative phase input The integration of each of the above and each signal supplied via the line LN is performed. As a result, the sampling period TS_i-1The sampling period TS of this time is the sum of the integrated value of the integration process corresponding to the first channel in the above and the input analog signal of the first channel captured in the time slot SL1._iIt is obtained as the integrated value of the first channel in, and the voltage corresponding to this integrated value is output from the differential amplifier 41 to the positive phase output line MP and the negative phase output line MN.

【0043】

In the first integrated value storage units 21 and 23, an operation of holding a voltage corresponding to the integrated value of the integral processing corresponding to the first channel obtained as described above is performed. That is, since a signal path from the positive phase output line MP to the reference power supply Vref is formed via the capacitor C6, the electric charge corresponding to the positive phase component of the integrated value is held in the capacitor C6 through this signal path. To. Further, since a signal path from the negative phase output line MN to the reference power supply Vref is formed via the capacitor C3, the electric charge corresponding to the negative phase component of the integrated value is held in the capacitor C3 through this signal path. The Rukoto.

【0044】

In the output unit 50, the balanced signal representing the integrated value of the first channel output between the positive phase output line MP and the negative phase output line MN is converted into a non-equilibrium signal. This non-equilibrium signal is given to the capacitor C9 by outputting the clock bb, and is output as the signal OUT1. Further, this non-equilibrium signal is held in the capacitor C9 when the clock bb falls.

【0045】

(3) Time slot SL3 In this time slot SL3, only clocks c and ac are output, and other clocks are not output. Therefore, the state of each analog switch is shown in FIG. 8 depending on the output of the clock, and the following operations are performed in each part.

【0046】

In the input switched capacitors 12 and 14, the input analog signals Ain2P and Ain2N of the second channel are sampled, and the charges corresponding to the levels of the analog signals are held in the capacitors C14 and C11, respectively.

【0047】

In the integrating unit 40, both ends of the capacitors C7, C17, C8 and C18 are short-circuited by the initialization analog switch, and the integrated value of the integrating unit 40 is initialized to 0.

【0048】

(4) Time slot SL4 In this time slot SL4, only clocks d, bd, d1 and dd are output, and other clocks are not output. Therefore, the state of each analog switch is as shown in FIG. 9 depending on the output of the clock, and the following operations are performed in each part.

【0049】

In the input switched capacitor units 12 and 14, the charges held in the capacitors C14 and C11 are respectively reversed in polarity and supplied to the positive phase input line LP and the negative phase input line LN, respectively.

【0050】

In the second integrated value storage units 32 and 34, the charges held in the capacitors C15 and C12 are supplied to the positive phase input line LP and the negative phase input line LN. The holding charge of each of these capacitors is the sampling period TS._i-1It is given by the integrator 40 in the above, and corresponds to the integral value of the integral processing corresponding to the second channel.

【0051】

In the integrator 40, since the initialization analog switch is opened and all of the integrator capacitors C8, C18, C7 and C18 are connected to the differential amplifier 41, the positive phase input line LP and the negative phase input The integration of each of the above and each signal supplied via the line LN is performed. As a result, the sampling period TS_i-1This sampling period TS is the sum of the integrated value of the integration process corresponding to the 2nd channel in the above and the input analog signal of the 2nd channel captured in the time slot SL3._iIt is obtained as the integrated value of the second channel in, and the voltage corresponding to this integrated value is output from the differential amplifier 41 to the positive phase output line MP and the negative phase output line MN.

【0052】

In the first integrated value storage units 22 and 24, an operation of holding a voltage corresponding to the integrated value of the integral processing corresponding to the second channel obtained as described above is performed. That is, since a signal path from the positive phase output line MP to the reference power supply Vref is formed via the capacitor C16, the electric charge corresponding to the positive phase component of the integrated value is held in the capacitor C16 through this signal path. To. Further, since a signal path from the negative phase output line MN to the reference power supply Vref is formed via the capacitor C13, the electric charge corresponding to the negative phase component of the integrated value is held in the capacitor C13 through this signal path. The Rukoto.

【0053】

In the output unit 50, the balanced signal representing the integrated value of the second channel output between the positive phase output line MP and the negative phase output line MN is converted into a non-equilibrium signal. This non-equilibrium signal is given to the capacitor C10 by outputting the clock dd, and is output as the signal OUT2. Further, this non-equilibrium signal is held in the capacitor C10 when the clock dd falls.

【0054】

(5) Time slot SL5 Sampling period TS_{i + 1}In the time slot SL5 of, as in the time slot SL1 described above, only the clocks a and ac are output, and the other clocks are not output. Therefore, the state of each analog switch is shown in FIG. 10 depending on the output of the clock, and the following operations are performed in each part.

【0055】

In the input switched capacitors 11 and 13, the input analog signals Ain1P and Ain1N are sampled again, and the electric charges corresponding to the levels of the analog signals are held in the capacitors C4 and C1, respectively. In the integrating unit 40, the integrated value is set to 0.

【0056】

(6) Time slot SL6 In this time slot SL6, only clocks b, bd, b2 and bb are output, and other clocks are not output. Therefore, the state of each analog switch is shown in FIG. 11 depending on the output of the clock, and the following operations are performed in each part.

【0057】

In the input switched capacitor units 11 and 13, the charges held in the capacitors C4 and C1 are respectively reversed in polarity and supplied to the positive phase input line LP and the negative phase input line LN, respectively.

【0058】

In the first integrated value storage units 21 and 23, the charges held in the capacitors C6 and C3 are supplied to the positive phase input line LP and the negative phase input line LN. The holding charge of each of these capacitors is the sampling period TS._iIt is an integral value corresponding to the first channel given by the integral unit 40 in.

【0059】

In the integrating unit 40, the above and each signals supplied via the positive phase input line LP and the negative phase input line LN are integrated. As a result, the sampling period TS_iThis sampling period TS is the sum of the integrated value of the integration process corresponding to the 1st channel in the above and the input analog signal of the 1st channel captured in the time slot SL5._{i + 1}It is obtained as the integrated value of the first channel in, and the voltage corresponding to this integrated value is output from the differential amplifier 41 to the positive phase output line MP and the negative phase output line MN.

【0060】

In the second integrated value storage units 31 and 33, the operations of holding the voltage corresponding to the integrated value of the integral processing corresponding to the first channel obtained as described above in the capacitors C5 and C2 are performed.

【0061】

In the output unit 50, the balanced signal representing the integrated value of the first channel output between the positive phase output line MP and the negative phase output line MN is converted into a non-equilibrium signal and output as a signal OUT1.

【0062】

As described above, the processing content in the time slot SL6 is the sampling period TS._iIt is substantially the same as the processing content in the time slot SL2, except that the roles played by the first integrated value storage units 21 and 23 and the second integrated value storage units 31 and 33 are interchanged.

【0063】

(7) Time slot SL7 In this time slot SL7, as in the time slot SL3 described above, only clocks c and ac are output, and other clocks are not output. Therefore, the state of each analog switch is shown in FIG. 12 depending on the output of the clock, and the following operations are performed in each part.

【0064】

In the input switched capacitors 12 and 14, the input analog signals Ain2P and Ain2N are sampled again, and the electric charges corresponding to the levels of the analog signals are held in the capacitors C14 and C11, respectively. In the integrating unit 40, the integrated value is set to 0.

【0065】

(8) Time slot SL8 In this time slot SL8, only clocks d, bd, d2 and dd are output, and other clocks are not output. Therefore, when each clock is generated, the state of each analog switch is as shown in FIG. 13, and the following operations are performed in each part.

【0066】

In the input switched capacitor units 12 and 14, the charges held in the capacitors C14 and C11 are respectively reversed in polarity and supplied to the positive phase input line LP and the negative phase input line LN, respectively.

【0067】

In the first integrated value storage units 22 and 24, the charges held in the capacitors C16 and C13 are supplied to the positive phase input line LP and the negative phase input line LN. The holding charge of each of these capacitors is the sampling period TS._iIt is the integrated value of the second channel given by the integrating unit 40 in.

【0068】

In the integrating unit 40, the above and each signals supplied via the positive phase input line LP and the negative phase input line LN are integrated. As a result, the sampling period TS_iThe sum of the integrated value of the integration process corresponding to the 2nd channel in the above and the input analog signal of the 2nd channel captured in the time slot SL7 is the sampling period TS of this time._{i + 1}It is obtained as the integrated value of the second channel in, and the voltage corresponding to this integrated value is output from the differential amplifier 41 to the positive phase output line MN and the negative phase output line MN.

【0069】

In the second integrated value storage units 32 and 34, the operations of holding the voltage corresponding to the integrated value corresponding to the second channel obtained as described above in the capacitors C15 and C12 are performed. In the output unit 50, the balanced signal representing the integrated value of the second channel output between the positive phase output line MP and the negative phase output line MN is converted into a non-equilibrium signal and output as a signal OUT2.

【0070】

In this way, the processing content in the time slot SL8 is substantially the same as the processing content in the time slot SL4, and the roles played by the first integrated value storage units 22 and 24 and the second integrated value storage units 32 and 34 are played. It's just swapped.

【0071】

After that, each process corresponding to the time slots SL1 to SL8 is repeatedly executed, the integration process corresponding to the first channel and the second channel is advanced, and the result of these integration processes is used to correspond to each channel. Each filtering process proceeds.

【0072】

C. Other embodiments In addition to those described above, various embodiments of the present invention can be considered. For example:

【0073】

(1) In the above embodiment, the analog signal is used as a balanced signal, and the analog signal is integrated by the integrator configured by the differential amplifier. However, the unbalanced analog signal is converted into a non-differential integrator. You may try to integrate.

【0074】

(2) Only one integrated value storage unit is provided for each integration process, and after the integration process by the integration unit is completed using the holding charge of this integrated value storage unit, the charge corresponding to the new integrated value is applied. It may be held in the integrated value storage unit. A time slot for holding a charge corresponding to the integrated value must be provided separately from the time slot for performing the integration process, but there is an advantage that the number of integrated value storage units can be halved.

【0075】

(3) When executing more types of integration processing than those in the above embodiment, it is sufficient to provide a corresponding number of integration value storage units.

【0076】

[Effect of the invention]

As described above, according to the present invention, under time division control, integration processing for a plurality of channels for performing filter processing corresponding to a plurality of channels can be sequentially executed by one integration means. With a small circuit configuration, it is possible to realize a switched capacitor filter that can process analog signals of multiple channels.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the structure of the invention which concerns on claim 1.

[Figure 2]

It is a figure which shows the structure of the invention which concerns on claim 2.

[Fig. 3]

It is a figure which shows the structure of the invention which concerns on claim 3.

[Fig. 4]

It is a block diagram which shows the structure of the A / D converter which is one Embodiment of this invention.

[Fig. 5]

It is a timing chart which shows the operation of the same embodiment.

[Fig. 6]

It is a figure which shows the operation state of the same embodiment.

[Fig. 7]

It is a figure which shows the operation state of the same embodiment.

[Fig. 8]

It is a figure which shows the operation state of the same embodiment.

[Fig. 9]

It is a figure which shows the operation state of the same embodiment.

[Fig. 10]

It is a figure which shows the operation state of the same embodiment.

[Fig. 11]

It is a figure which shows the operation state of the same embodiment.

[Fig. 12]

It is a figure which shows the operation state of the same embodiment.

[Fig. 13]

It is a figure which shows the operation state of the same embodiment.

[Fig. 14]

It is a block diagram which shows the structure of the conventional switched capacitor filter.

[Explanation of symbols]

I_k, I_{k + 1}...... Integral means, M_k, M_{k + 1}...... Integral value storage means, SW ...... Switch means.